Lines Matching +full:- +full:- +full:check

1 ; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s
2 ; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-pref…
3 ; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCh…
4 ; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCh…
5 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-pr…
12 ; CHECK-LABEL: @test1
13 ; CHECK: xsmuldp 1, 1, 2
14 ; CHECK: blr
16 ; CHECK-LE-LABEL: @test1
17 ; CHECK-LE: xsmuldp 1, 1, 2
18 ; CHECK-LE: blr
26 ; CHECK-LABEL: @test2
27 ; CHECK: xsdivdp 1, 1, 2
28 ; CHECK: blr
30 ; CHECK-LE-LABEL: @test2
31 ; CHECK-LE: xsdivdp 1, 1, 2
32 ; CHECK-LE: blr
40 ; CHECK-LABEL: @test3
41 ; CHECK: xsadddp 1, 1, 2
42 ; CHECK: blr
44 ; CHECK-LE-LABEL: @test3
45 ; CHECK-LE: xsadddp 1, 1, 2
46 ; CHECK-LE: blr
54 ; CHECK-LABEL: @test4
55 ; CHECK: xvadddp 34, 34, 35
56 ; CHECK: blr
58 ; CHECK-LE-LABEL: @test4
59 ; CHECK-LE: xvadddp 34, 34, 35
60 ; CHECK-LE: blr
68 ; CHECK-REG-LABEL: @test5
69 ; CHECK-REG: xxlxor 34, 34, 35
70 ; CHECK-REG: blr
72 ; CHECK-FISL-LABEL: @test5
73 ; CHECK-FISL: vor
74 ; CHECK-FISL: vor
75 ; CHECK-FISL: xxlxor
76 ; CHECK-FISL: vor 2
77 ; CHECK-FISL: blr
79 ; CHECK-LE-LABEL: @test5
80 ; CHECK-LE: xxlxor 34, 34, 35
81 ; CHECK-LE: blr
89 ; CHECK-REG-LABEL: @test6
90 ; CHECK-REG: xxlxor 34, 34, 35
91 ; CHECK-REG: blr
93 ; CHECK-FISL-LABEL: @test6
94 ; CHECK-FISL: vor 4, 2, 2
95 ; CHECK-FISL: vor 5, 3, 3
96 ; CHECK-FISL: xxlxor 36, 36, 37
97 ; CHECK-FISL: vor 2, 4, 4
98 ; CHECK-FISL: blr
100 ; CHECK-LE-LABEL: @test6
101 ; CHECK-LE: xxlxor 34, 34, 35
102 ; CHECK-LE: blr
110 ; CHECK-REG-LABEL: @test7
111 ; CHECK-REG: xxlxor 34, 34, 35
112 ; CHECK-REG: blr
114 ; CHECK-FISL-LABEL: @test7
115 ; CHECK-FISL: vor 4, 2, 2
116 ; CHECK-FISL: vor 5, 3, 3
117 ; CHECK-FISL: xxlxor 36, 36, 37
118 ; CHECK-FISL: vor 2, 4, 4
119 ; CHECK-FISL: blr
121 ; CHECK-LE-LABEL: @test7
122 ; CHECK-LE: xxlxor 34, 34, 35
123 ; CHECK-LE: blr
131 ; CHECK-REG-LABEL: @test8
132 ; CHECK-REG: xxlor 34, 34, 35
133 ; CHECK-REG: blr
135 ; CHECK-FISL-LABEL: @test8
136 ; CHECK-FISL: vor
137 ; CHECK-FISL: vor
138 ; CHECK-FISL: xxlor
139 ; CHECK-FISL: vor 2
140 ; CHECK-FISL: blr
142 ; CHECK-LE-LABEL: @test8
143 ; CHECK-LE: xxlor 34, 34, 35
144 ; CHECK-LE: blr
152 ; CHECK-REG-LABEL: @test9
153 ; CHECK-REG: xxlor 34, 34, 35
154 ; CHECK-REG: blr
156 ; CHECK-FISL-LABEL: @test9
157 ; CHECK-FISL: vor 4, 2, 2
158 ; CHECK-FISL: vor 5, 3, 3
159 ; CHECK-FISL: xxlor 36, 36, 37
160 ; CHECK-FISL: vor 2, 4, 4
161 ; CHECK-FISL: blr
163 ; CHECK-LE-LABEL: @test9
164 ; CHECK-LE: xxlor 34, 34, 35
165 ; CHECK-LE: blr
173 ; CHECK-REG-LABEL: @test10
174 ; CHECK-REG: xxlor 34, 34, 35
175 ; CHECK-REG: blr
177 ; CHECK-FISL-LABEL: @test10
178 ; CHECK-FISL: vor 4, 2, 2
179 ; CHECK-FISL: vor 5, 3, 3
180 ; CHECK-FISL: xxlor 36, 36, 37
181 ; CHECK-FISL: vor 2, 4, 4
182 ; CHECK-FISL: blr
184 ; CHECK-LE-LABEL: @test10
185 ; CHECK-LE: xxlor 34, 34, 35
186 ; CHECK-LE: blr
194 ; CHECK-REG-LABEL: @test11
195 ; CHECK-REG: xxland 34, 34, 35
196 ; CHECK-REG: blr
198 ; CHECK-FISL-LABEL: @test11
199 ; CHECK-FISL: vor
200 ; CHECK-FISL: vor
201 ; CHECK-FISL: xxland
202 ; CHECK-FISL: vor 2
203 ; CHECK-FISL: blr
205 ; CHECK-LE-LABEL: @test11
206 ; CHECK-LE: xxland 34, 34, 35
207 ; CHECK-LE: blr
215 ; CHECK-REG-LABEL: @test12
216 ; CHECK-REG: xxland 34, 34, 35
217 ; CHECK-REG: blr
219 ; CHECK-FISL-LABEL: @test12
220 ; CHECK-FISL: vor 4, 2, 2
221 ; CHECK-FISL: vor 5, 3, 3
222 ; CHECK-FISL: xxland 36, 36, 37
223 ; CHECK-FISL: vor 2, 4, 4
224 ; CHECK-FISL: blr
226 ; CHECK-LE-LABEL: @test12
227 ; CHECK-LE: xxland 34, 34, 35
228 ; CHECK-LE: blr
236 ; CHECK-REG-LABEL: @test13
237 ; CHECK-REG: xxland 34, 34, 35
238 ; CHECK-REG: blr
240 ; CHECK-FISL-LABEL: @test13
241 ; CHECK-FISL: vor 4, 2, 2
242 ; CHECK-FISL: vor 5, 3, 3
243 ; CHECK-FISL: xxland 36, 36, 37
244 ; CHECK-FISL: vor 2, 4, 4
245 ; CHECK-FISL: blr
247 ; CHECK-LE-LABEL: @test13
248 ; CHECK-LE: xxland 34, 34, 35
249 ; CHECK-LE: blr
255   %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
258 ; CHECK-REG-LABEL: @test14
259 ; CHECK-REG: xxlnor 34, 34, 35
260 ; CHECK-REG: blr
262 ; CHECK-FISL-LABEL: @test14
263 ; CHECK-FISL: vor 4, 3, 3
264 ; CHECK-FISL: vor 5, 2, 2
265 ; CHECK-FISL: xxlor 0, 37, 36
266 ; CHECK-FISL: xxlnor 36, 37, 36
267 ; CHECK-FISL: vor 2, 4, 4
268 ; CHECK-FISL: lis 0, -1
269 ; CHECK-FISL: ori 0, 0, 65520
270 ; CHECK-FISL: stxvd2x 0, 1, 0
271 ; CHECK-FISL: blr
273 ; CHECK-LE-LABEL: @test14
274 ; CHECK-LE: xxlnor 34, 34, 35
275 ; CHECK-LE: blr
281   %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
284 ; CHECK-REG-LABEL: @test15
285 ; CHECK-REG: xxlnor 34, 34, 35
286 ; CHECK-REG: blr
288 ; CHECK-FISL-LABEL: @test15
289 ; CHECK-FISL: vor 4, 2, 2
290 ; CHECK-FISL: vor 5, 3, 3
291 ; CHECK-FISL: xxlor 36, 36, 37
292 ; CHECK-FISL: vor 0, 4, 4
293 ; CHECK-FISL: vor 4, 2, 2
294 ; CHECK-FISL: vor 5, 3, 3
295 ; CHECK-FISL: xxlnor 36, 36, 37
296 ; CHECK-FISL: vor 2, 4, 4
297 ; CHECK-FISL: lis 0, -1
298 ; CHECK-FISL: ori 0, 0, 65520
299 ; CHECK-FISL: stvx 0, 1, 0
300 ; CHECK-FISL: blr
302 ; CHECK-LE-LABEL: @test15
303 ; CHECK-LE: xxlnor 34, 34, 35
304 ; CHECK-LE: blr
310 … xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i…
313 ; CHECK-REG-LABEL: @test16
314 ; CHECK-REG: xxlnor 34, 34, 35
315 ; CHECK-REG: blr
317 ; CHECK-FISL-LABEL: @test16
318 ; CHECK-FISL: vor 4, 2, 2
319 ; CHECK-FISL: vor 5, 3, 3
320 ; CHECK-FISL: xxlor 36, 36, 37
321 ; CHECK-FISL: vor 0, 4, 4
322 ; CHECK-FISL: vor 4, 2, 2
323 ; CHECK-FISL: vor 5, 3, 3
324 ; CHECK-FISL: xxlnor 36, 36, 37
325 ; CHECK-FISL: vor 2, 4, 4
326 ; CHECK-FISL: lis 0, -1
327 ; CHECK-FISL: ori 0, 0, 65520
328 ; CHECK-FISL: stvx 0, 1, 0
329 ; CHECK-FISL: blr
331 ; CHECK-LE-LABEL: @test16
332 ; CHECK-LE: xxlnor 34, 34, 35
333 ; CHECK-LE: blr
338   %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
342 ; CHECK-REG-LABEL: @test17
343 ; CHECK-REG: xxlandc 34, 34, 35
344 ; CHECK-REG: blr
346 ; CHECK-FISL-LABEL: @test17
347 ; CHECK-FISL: vor 4, 3, 3
348 ; CHECK-FISL: vor 5, 2, 2
349 ; CHECK-FISL: vspltisb 2, -1
350 ; CHECK-FISL: vor 0, 2, 2
351 ; CHECK-FISL: xxlxor 36, 36, 32
352 ; CHECK-FISL: xxland 36, 37, 36
353 ; CHECK-FISL: vor 2, 4, 4
354 ; CHECK-FISL: blr
356 ; CHECK-LE-LABEL: @test17
357 ; CHECK-LE: xxlandc 34, 34, 35
358 ; CHECK-LE: blr
363   %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
367 ; CHECK-REG-LABEL: @test18
368 ; CHECK-REG: xxlandc 34, 34, 35
369 ; CHECK-REG: blr
371 ; CHECK-FISL-LABEL: @test18
372 ; CHECK-FISL: vspltisb 4, -1
373 ; CHECK-FISL: vor 5, 3, 3
374 ; CHECK-FISL: vor 0, 4, 4
375 ; CHECK-FISL: xxlxor 37, 37, 32
376 ; CHECK-FISL: vor 4, 5, 5
377 ; CHECK-FISL: vor 5, 2, 2
378 ; CHECK-FISL: vor 0, 3, 3
379 ; CHECK-FISL: xxlandc 37, 37, 32
380 ; CHECK-FISL: vor 2, 5, 5
381 ; CHECK-FISL: lis 0, -1
382 ; CHECK-FISL: ori 0, 0, 65520
383 ; CHECK-FISL: stvx 4, 1, 0
384 ; CHECK-FISL: blr
386 ; CHECK-LE-LABEL: @test18
387 ; CHECK-LE: xxlandc 34, 34, 35
388 ; CHECK-LE: blr
393 … xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i…
397 ; CHECK-REG-LABEL: @test19
398 ; CHECK-REG: xxlandc 34, 34, 35
399 ; CHECK-REG: blr
401 ; CHECK-FISL-LABEL: @test19
402 ; CHECK-FISL: vspltisb 4, -1
403 ; CHECK-FISL: vor 5, 3, 3
404 ; CHECK-FISL: vor 0, 4, 4
405 ; CHECK-FISL: xxlxor 37, 37, 32
406 ; CHECK-FISL: vor 4, 5, 5
407 ; CHECK-FISL: vor 5, 2, 2
408 ; CHECK-FISL: vor 0, 3, 3
409 ; CHECK-FISL: xxlandc 37, 37, 32
410 ; CHECK-FISL: vor 2, 5, 5
411 ; CHECK-FISL: lis 0, -1
412 ; CHECK-FISL: ori 0, 0, 65520
413 ; CHECK-FISL: stvx 4, 1, 0
414 ; CHECK-FISL: blr
416 ; CHECK-LE-LABEL: @test19
417 ; CHECK-LE: xxlandc 34, 34, 35
418 ; CHECK-LE: blr
427 ; CHECK-REG-LABEL: @test20
428 ; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5
429 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
430 ; CHECK-REG: blr
432 ; FIXME: The fast-isel code is pretty miserable for this one.
434 ; CHECK-FISL-LABEL: @test20
435 ; CHECK-FISL: vor 0, 5, 5
436 ; CHECK-FISL: vor 1, 4, 4
437 ; CHECK-FISL: vor 6, 3, 3
438 ; CHECK-FISL: vor 7, 2, 2
439 ; CHECK-FISL: vor 2, 1, 1
440 ; CHECK-FISL: vor 3, 0, 0
441 ; CHECK-FISL: vcmpequw 2, 2, 3
442 ; CHECK-FISL: vor 0, 2, 2
443 ; CHECK-FISL: xxsel 32, 38, 39, 32
444 ; CHECK-FISL: vor 2, 0, 0
445 ; CHECK-FISL: blr
447 ; CHECK-LE-LABEL: @test20
448 ; CHECK-LE: vcmpequw {{[0-9]+}}, 4, 5
449 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
450 ; CHECK-LE: blr
459 ; CHECK-REG-LABEL: @test21
460 ; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37
461 ; CHECK-REG: xxsel 34, 35, 34, [[V1]]
462 ; CHECK-REG: blr
464 ; CHECK-FISL-LABEL: @test21
465 ; CHECK-FISL: vor 0, 5, 5
466 ; CHECK-FISL: vor 1, 4, 4
467 ; CHECK-FISL: vor 6, 3, 3
468 ; CHECK-FISL: vor 7, 2, 2
469 ; CHECK-FISL: xvcmpeqsp 32, 33, 32
470 ; CHECK-FISL: xxsel 32, 38, 39, 32
471 ; CHECK-FISL: vor 2, 0, 0
472 ; CHECK-FISL: blr
474 ; CHECK-LE-LABEL: @test21
475 ; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37
476 ; CHECK-LE: xxsel 34, 35, 34, [[V1]]
477 ; CHECK-LE: blr
486 ; CHECK-REG-LABEL: @test22
487 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
488 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
489 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
490 ; CHECK-REG-DAG: xxlnor
491 ; CHECK-REG-DAG: xxlnor
492 ; CHECK-REG-DAG: xxlor
493 ; CHECK-REG-DAG: xxlor
494 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
495 ; CHECK-REG: blr
497 ; CHECK-FISL-LABEL: @test22
498 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 32
499 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 32, 32
500 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 33
501 ; CHECK-FISL-DAG: xxlnor
502 ; CHECK-FISL-DAG: xxlnor
503 ; CHECK-FISL-DAG: xxlor
504 ; CHECK-FISL-DAG: xxlor
505 ; CHECK-FISL: xxsel 0, 38, 39, {{[0-9]+}}
506 ; CHECK-FISL: blr
508 ; CHECK-LE-LABEL: @test22
509 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
510 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
511 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
512 ; CHECK-LE-DAG: xxlnor
513 ; CHECK-LE-DAG: xxlnor
514 ; CHECK-LE-DAG: xxlor
515 ; CHECK-LE-DAG: xxlor
516 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
517 ; CHECK-LE: blr
526 ; CHECK-REG-LABEL: @test23
527 ; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5
528 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
529 ; CHECK-REG: blr
531 ; CHECK-FISL-LABEL: @test23
532 ; CHECK-FISL: vcmpequh 4, 4, 5
533 ; CHECK-FISL: vor 0, 3, 3
534 ; CHECK-FISL: vor 1, 2, 2
535 ; CHECK-FISL: vor 6, 4, 4
536 ; CHECK-FISL: xxsel 32, 32, 33, 38
537 ; CHECK-FISL: vor 2, 0, 
538 ; CHECK-FISL: blr
540 ; CHECK-LE-LABEL: @test23
541 ; CHECK-LE: vcmpequh {{[0-9]+}}, 4, 5
542 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
543 ; CHECK-LE: blr
552 ; CHECK-REG-LABEL: @test24
553 ; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5
554 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
555 ; CHECK-REG: blr
557 ; CHECK-FISL-LABEL: @test24
558 ; CHECK-FISL: vcmpequb 4, 4, 5
559 ; CHECK-FISL: vor 0, 3, 3
560 ; CHECK-FISL: vor 1, 2, 2
561 ; CHECK-FISL: vor 6, 4, 4
562 ; CHECK-FISL: xxsel 32, 32, 33, 38
563 ; CHECK-FISL: vor 2, 0, 0
564 ; CHECK-FISL: blr
566 ; CHECK-LE-LABEL: @test24
567 ; CHECK-LE: vcmpequb {{[0-9]+}}, 4, 5
568 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
569 ; CHECK-LE: blr
578 ; CHECK-LABEL: @test25
579 ; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37
580 ; CHECK: xxsel 34, 35, 34, [[V1]]
581 ; CHECK: blr
583 ; CHECK-LE-LABEL: @test25
584 ; CHECK-LE: xvcmpeqdp [[V1:[0-9]+]], 36, 37
585 ; CHECK-LE: xxsel 34, 35, 34, [[V1]]
586 ; CHECK-LE: blr
593 ; CHECK-LABEL: @test26
596 ; CHECK: stxvd2x 35,
597 ; CHECK: stxvd2x 34,
598 ; CHECK-NOT: stxvd2x
601 ; CHECK: add
602 ; CHECK: add
603 ; CHECK: blr
605 ; CHECK-LE: vaddudm 2, 2, 3
606 ; CHECK-LE: blr
613 ; CHECK-LABEL: @test27
614 ; CHECK: xxland 34, 34, 35
615 ; CHECK: blr
617 ; CHECK-LE-LABEL: @test27
618 ; CHECK-LE: xxland 34, 34, 35
619 ; CHECK-LE: blr
626 ; CHECK-LABEL: @test28
627 ; CHECK: lxvd2x 34, 0, 3
628 ; CHECK: blr
630 ; CHECK-LE-LABEL: @test28
631 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
632 ; CHECK-LE: xxswapd 34, [[V1]]
633 ; CHECK-LE: blr
640 ; CHECK-LABEL: @test29
641 ; CHECK: stxvd2x 34, 0, 3
642 ; CHECK: blr
644 ; CHECK-LE-LABEL: @test29
645 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
646 ; CHECK-LE: stxvd2x [[V1]], 0, 3
647 ; CHECK-LE: blr
654 ; CHECK-LABEL: @test28u
655 ; CHECK: lxvd2x 34, 0, 3
656 ; CHECK: blr
658 ; CHECK-LE-LABEL: @test28u
659 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
660 ; CHECK-LE: xxswapd 34, [[V1]]
661 ; CHECK-LE: blr
668 ; CHECK-LABEL: @test29u
669 ; CHECK: stxvd2x 34, 0, 3
670 ; CHECK: blr
672 ; CHECK-LE-LABEL: @test29u
673 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
674 ; CHECK-LE: stxvd2x [[V1]], 0, 3
675 ; CHECK-LE: blr
682 ; CHECK-REG-LABEL: @test30
683 ; CHECK-REG: lxvd2x 34, 0, 3
684 ; CHECK-REG: blr
686 ; CHECK-FISL-LABEL: @test30
687 ; CHECK-FISL: lxvd2x 0, 0, 3
688 ; CHECK-FISL: xxlor 34, 0, 0
689 ; CHECK-FISL: vor 3, 2, 2
690 ; CHECK-FISL: vor 2, 3, 3
691 ; CHECK-FISL: blr
693 ; CHECK-LE-LABEL: @test30
694 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
695 ; CHECK-LE: xxswapd 34, [[V1]]
696 ; CHECK-LE: blr
703 ; CHECK-LABEL: @test31
704 ; CHECK: stxvd2x 34, 0, 3
705 ; CHECK: blr
707 ; CHECK-LE-LABEL: @test31
708 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
709 ; CHECK-LE: stxvd2x [[V1]], 0, 3
710 ; CHECK-LE: blr
717 ; CHECK-REG-LABEL: @test32
718 ; CHECK-REG: lxvw4x 34, 0, 3
719 ; CHECK-REG: blr
721 ; CHECK-FISL-LABEL: @test32
722 ; CHECK-FISL: lxvw4x 0, 0, 3
723 ; CHECK-FISL: xxlor 34, 0, 0
724 ; CHECK-FISL: blr
726 ; CHECK-LE-LABEL: @test32
727 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
728 ; CHECK-LE: xxswapd 34, [[V1]]
729 ; CHECK-LE: blr
736 ; CHECK-REG-LABEL: @test33
737 ; CHECK-REG: stxvw4x 34, 0, 3
738 ; CHECK-REG: blr
740 ; CHECK-FISL-LABEL: @test33
741 ; CHECK-FISL: vor 3, 2, 2
742 ; CHECK-FISL: stxvw4x 35, 0, 3
743 ; CHECK-FISL: blr
745 ; CHECK-LE-LABEL: @test33
746 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
747 ; CHECK-LE: stxvd2x [[V1]], 0, 3
748 ; CHECK-LE: blr
755 ; CHECK-LABEL: @test32u
756 ; CHECK-DAG: lvsl
757 ; CHECK-DAG: lvx
758 ; CHECK-DAG: lvx
759 ; CHECK: vperm 2,
760 ; CHECK: blr
762 ; CHECK-LE-LABEL: @test32u
763 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
764 ; CHECK-LE: xxswapd 34, [[V1]]
765 ; CHECK-LE: blr
772 ; CHECK-REG-LABEL: @test33u
773 ; CHECK-REG: stxvw4x 34, 0, 3
774 ; CHECK-REG: blr
776 ; CHECK-FISL-LABEL: @test33u
777 ; CHECK-FISL: vor 3, 2, 2
778 ; CHECK-FISL: stxvw4x 35, 0, 3
779 ; CHECK-FISL: blr
781 ; CHECK-LE-LABEL: @test33u
782 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
783 ; CHECK-LE: stxvd2x [[V1]], 0, 3
784 ; CHECK-LE: blr
791 ; CHECK-REG-LABEL: @test34
792 ; CHECK-REG: lxvw4x 34, 0, 3
793 ; CHECK-REG: blr
795 ; CHECK-FISL-LABEL: @test34
796 ; CHECK-FISL: lxvw4x 0, 0, 3
797 ; CHECK-FISL: xxlor 34, 0, 0
798 ; CHECK-FISL: blr
800 ; CHECK-LE-LABEL: @test34
801 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
802 ; CHECK-LE: xxswapd 34, [[V1]]
803 ; CHECK-LE: blr
810 ; CHECK-REG-LABEL: @test35
811 ; CHECK-REG: stxvw4x 34, 0, 3
812 ; CHECK-REG: blr
814 ; CHECK-FISL-LABEL: @test35
815 ; CHECK-FISL: vor 3, 2, 2
816 ; CHECK-FISL: stxvw4x 35, 0, 3
817 ; CHECK-FISL: blr
819 ; CHECK-LE-LABEL: @test35
820 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
821 ; CHECK-LE: stxvd2x [[V1]], 0, 3
822 ; CHECK-LE: blr
829 ; CHECK-LABEL: @test40
830 ; CHECK: xvcvuxddp 34, 34
831 ; CHECK: blr
833 ; CHECK-LE-LABEL: @test40
834 ; CHECK-LE: xvcvuxddp 34, 34
835 ; CHECK-LE: blr
842 ; CHECK-LABEL: @test41
843 ; CHECK: xvcvsxddp 34, 34
844 ; CHECK: blr
846 ; CHECK-LE-LABEL: @test41
847 ; CHECK-LE: xvcvsxddp 34, 34
848 ; CHECK-LE: blr
855 ; CHECK-LABEL: @test42
856 ; CHECK: xvcvdpuxds 34, 34
857 ; CHECK: blr
859 ; CHECK-LE-LABEL: @test42
860 ; CHECK-LE: xvcvdpuxds 34, 34
861 ; CHECK-LE: blr
868 ; CHECK-LABEL: @test43
869 ; CHECK: xvcvdpsxds 34, 34
870 ; CHECK: blr
872 ; CHECK-LE-LABEL: @test43
873 ; CHECK-LE: xvcvdpsxds 34, 34
874 ; CHECK-LE: blr
881 ; CHECK-LABEL: @test44
883 ; CHECK: blr
890 ; CHECK-LABEL: @test45
892 ; CHECK: blr
899 ; CHECK-LABEL: @test46
901 ; CHECK: blr
908 ; CHECK-LABEL: @test47
910 ; CHECK: blr
919 ; CHECK-LABEL: @test50
920 ; CHECK: lxvdsx 34, 0, 3
921 ; CHECK: blr
923 ; CHECK-LE-LABEL: @test50
924 ; CHECK-LE: lxvdsx 34, 0, 3
925 ; CHECK-LE: blr
932 ; CHECK-LABEL: @test51
933 ; CHECK: xxspltd 34, 34, 0
934 ; CHECK: blr
936 ; CHECK-LE-LABEL: @test51
937 ; CHECK-LE: xxspltd 34, 34, 1
938 ; CHECK-LE: blr
945 ; CHECK-LABEL: @test52
946 ; CHECK: xxmrghd 34, 34, 35
947 ; CHECK: blr
949 ; CHECK-LE-LABEL: @test52
950 ; CHECK-LE: xxmrgld 34, 35, 34
951 ; CHECK-LE: blr
958 ; CHECK-LABEL: @test53
959 ; CHECK: xxmrghd 34, 35, 34
960 ; CHECK: blr
962 ; CHECK-LE-LABEL: @test53
963 ; CHECK-LE: xxmrgld 34, 34, 35
964 ; CHECK-LE: blr
971 ; CHECK-LABEL: @test54
972 ; CHECK: xxpermdi 34, 34, 35, 2
973 ; CHECK: blr
975 ; CHECK-LE-LABEL: @test54
976 ; CHECK-LE: xxpermdi 34, 35, 34, 2
977 ; CHECK-LE: blr
984 ; CHECK-LABEL: @test55
985 ; CHECK: xxmrgld 34, 34, 35
986 ; CHECK: blr
988 ; CHECK-LE-LABEL: @test55
989 ; CHECK-LE: xxmrghd 34, 35, 34
990 ; CHECK-LE: blr
997 ; CHECK-LABEL: @test56
998 ; CHECK: xxmrgld 34, 34, 35
999 ; CHECK: blr
1001 ; CHECK-LE-LABEL: @test56
1002 ; CHECK-LE: xxmrghd 34, 35, 34
1003 ; CHECK-LE: blr
1010 ; CHECK-LABEL: @test60
1012 ; CHECK: stxvd2x
1013 ; CHECK: stxvd2x
1014 ; CHECK: sld
1015 ; CHECK: sld
1016 ; CHECK: lxvd2x
1017 ; CHECK: blr
1024 ; CHECK-LABEL: @test61
1026 ; CHECK: stxvd2x
1027 ; CHECK: stxvd2x
1028 ; CHECK: srd
1029 ; CHECK: srd
1030 ; CHECK: lxvd2x
1031 ; CHECK: blr
1038 ; CHECK-LABEL: @test62
1040 ; CHECK: stxvd2x
1041 ; CHECK: stxvd2x
1042 ; CHECK: srad
1043 ; CHECK: srad
1044 ; CHECK: lxvd2x
1045 ; CHECK: blr
1052 ; CHECK-REG-LABEL: @test63
1053 ; CHECK-REG: xxlor 1, 34, 34
1054 ; CHECK-REG: blr
1056 ; CHECK-FISL-LABEL: @test63
1057 ; CHECK-FISL: xxlor 0, 34, 34
1058 ; CHECK-FISL: fmr 1, 0
1059 ; CHECK-FISL: blr
1061 ; CHECK-LE-LABEL: @test63
1062 ; CHECK-LE: xxswapd 1, 34
1063 ; CHECK-LE: blr
1070 ; CHECK-REG-LABEL: @test64
1071 ; CHECK-REG: xxswapd 1, 34
1072 ; CHECK-REG: blr
1074 ; CHECK-FISL-LABEL: @test64
1075 ; CHECK-FISL: xxswapd  34, 34
1076 ; CHECK-FISL: xxlor 0, 34, 34
1077 ; CHECK-FISL: fmr 1, 0
1078 ; CHECK-FISL: blr
1080 ; CHECK-LE-LABEL: @test64
1081 ; CHECK-LE: xxlor 1, 34, 34
1088 ; CHECK-REG-LABEL: @test65
1089 ; CHECK-REG: vcmpequw 2, 2, 3
1090 ; CHECK-REG: blr
1092 ; CHECK-FISL-LABEL: @test65
1093 ; CHECK-FISL: vor 4, 3, 3
1094 ; CHECK-FISL: vor 5, 2, 2
1095 ; CHECK-FISL: vcmpequw 4, 5, 4
1096 ; CHECK-FISL: vor 2, 4, 4
1097 ; CHECK-FISL: blr
1099 ; CHECK-LE-LABEL: @test65
1100 ; CHECK-LE: vcmpequd 2, 2, 3
1101 ; CHECK-LE: blr
1108 ; CHECK-REG-LABEL: @test66
1109 ; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3
1110 ; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
1111 ; CHECK-REG: blr
1113 ; CHECK-FISL-LABEL: @test66
1114 ; CHECK-FISL: vcmpequw {{[0-9]+}}, 5, 4
1115 ; CHECK-FISL: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
1116 ; CHECK-FISL: blr
1118 ; CHECK-LE-LABEL: @test66
1119 ; CHECK-LE: vcmpequd {{[0-9]+}}, 2, 3
1120 ; CHECK-LE: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
1121 ; CHECK-LE: blr
1128 ; CHECK-LABEL: @test67
1130 ; CHECK: stxvd2x
1131 ; CHECK: stxvd2x
1132 ; CHECK: cmpld
1133 ; CHECK: cmpld
1134 ; CHECK: lxvd2x
1135 ; CHECK: blr
1137 ; CHECK-LE-LABEL: @test67
1138 ; CHECK-LE: vcmpgtud 2, 3, 2
1139 ; CHECK-LE: blr
1146 ; CHECK-LABEL: @test68
1147 ; CHECK: xxmrghw [[V1:[0-9]+]]
1148 ; CHECK: xvcvsxwdp 34, [[V1]]
1149 ; CHECK: blr
1151 ; CHECK-LE-LABEL: @test68
1152 ; CHECK-LE: xxmrglw [[V1:[0-9]+]], 34, 34
1153 ; CHECK-LE: xvcvsxwdp 34, [[V1]]
1154 ; CHECK-LE: blr
1162 ; CHECK-LABEL: @test69
1163 ; CHECK-DAG: lfiwax
1164 ; CHECK-DAG: lfiwax
1165 ; CHECK-DAG: xscvsxddp
1166 ; CHECK-DAG: xscvsxddp
1167 ; CHECK: xxmrghd
1168 ; CHECK: blr
1170 ; CHECK-LE-LABEL: @test69
1171 ; CHECK-LE: mfvsrd
1172 ; CHECK-LE: mtvsrwa
1173 ; CHECK-LE: mtvsrwa
1174 ; CHECK-LE: xscvsxddp
1175 ; CHECK-LE: xscvsxddp
1176 ; CHECK-LE: xxspltd
1177 ; CHECK-LE: xxspltd
1178 ; CHECK-LE: xxmrgld
1179 ; CHECK-LE: blr
1187 ; CHECK-LABEL: @test70
1188 ; CHECK-DAG: lfiwax
1189 ; CHECK-DAG: lfiwax
1190 ; CHECK-DAG: xscvsxddp
1191 ; CHECK-DAG: xscvsxddp
1192 ; CHECK: xxmrghd
1193 ; CHECK: blr
1195 ; CHECK-LE-LABEL: @test70
1196 ; CHECK-LE: mfvsrd
1197 ; CHECK-LE: mtvsrwa
1198 ; CHECK-LE: mtvsrwa
1199 ; CHECK-LE: xscvsxddp
1200 ; CHECK-LE: xscvsxddp
1201 ; CHECK-LE: xxspltd
1202 ; CHECK-LE: xxspltd
1203 ; CHECK-LE: xxmrgld
1204 ; CHECK-LE: blr
1214 ; CHECK-REG-LABEL: @test80
1215 ; CHECK-REG: stw 3, -16(1)
1216 ; CHECK-REG: addi [[R1:[0-9]+]], 1, -16
1217 ; CHECK-REG: addis [[R2:[0-9]+]]
1218 ; CHECK-REG: addi [[R2]], [[R2]]
1219 ; CHECK-REG-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
1220 ; CHECK-REG-DAG: lxvw4x 35, 0, [[R2]]
1221 ; CHECK-REG: xxspltw 34, [[VS1]], 0
1222 ; CHECK-REG: vadduwm 2, 2, 3
1223 ; CHECK-REG-NOT: stxvw4x
1224 ; CHECK-REG: blr
1226 ; CHECK-FISL-LABEL: @test80
1227 ; CHECK-FISL: mr 4, 3
1228 ; CHECK-FISL: stw 4, -16(1)
1229 ; CHECK-FISL: addi [[R1:[0-9]+]], 1, -16
1230 ; CHECK-FISL-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
1231 ; CHECK-FISL-DAG: xxspltw {{[0-9]+}}, [[VS1]], 0
1232 ; CHECK-FISL: addis [[R2:[0-9]+]]
1233 ; CHECK-FISL: addi [[R2]], [[R2]]
1234 ; CHECK-FISL-DAG: lxvw4x {{[0-9]+}}, 0, [[R2]]
1235 ; CHECK-FISL: vadduwm
1236 ; CHECK-FISL-NOT: stxvw4x
1237 ; CHECK-FISL: blr
1239 ; CHECK-LE-LABEL: @test80
1240 ; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3
1241 ; CHECK-LE-DAG: xxswapd  [[V1:[0-9]+]], [[R1]]
1242 ; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI
1243 ; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]]
1244 ; CHECK-LE-DAG: xxspltw 34, [[V1]]
1245 ; CHECK-LE-DAG: xxswapd 35, [[V2]]
1246 ; CHECK-LE: vadduwm 2, 2, 3
1247 ; CHECK-LE: blr
1254 ; CHECK-LABEL: @test81
1255 ; CHECK: blr
1257 ; CHECK-LE-LABEL: @test81
1258 ; CHECK-LE: blr
1267 ; CHECK-REG-LABEL: @test82
1268 ; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4
1269 ; CHECK-REG: beqlr [[REG]]
1271 ; CHECK-FISL-LABEL: @test82
1272 ; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4
1273 ; CHECK-FISL: beq [[REG]], {{.*}}
1275 ; CHECK-LE-LABEL: @test82
1276 ; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4
1277 ; CHECK-LE: beqlr [[REG]]