Lines Matching refs:OS
77 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
79 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
81 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
88 void RegisterInfoEmitter::runEnums(raw_ostream &OS, in runEnums() argument
98 emitSourceFileHeader("Target Register Enum Values", OS); in runEnums()
100 OS << "\n#ifdef GET_REGINFO_ENUM\n"; in runEnums()
101 OS << "#undef GET_REGINFO_ENUM\n\n"; in runEnums()
103 OS << "namespace llvm {\n\n"; in runEnums()
105 OS << "class MCRegisterClass;\n" in runEnums()
110 OS << "namespace " << Namespace << " {\n"; in runEnums()
111 OS << "enum {\n NoRegister,\n"; in runEnums()
114 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
117 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; in runEnums()
118 OS << "};\n"; in runEnums()
120 OS << "} // end namespace " << Namespace << "\n"; in runEnums()
129 OS << "\n// Register classes\n\n"; in runEnums()
131 OS << "namespace " << Namespace << " {\n"; in runEnums()
132 OS << "enum {\n"; in runEnums()
134 OS << " " << RC.getName() << "RegClassID" in runEnums()
136 OS << "\n };\n"; in runEnums()
138 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
145 OS << "\n// Register alternate name indices\n\n"; in runEnums()
147 OS << "namespace " << Namespace << " {\n"; in runEnums()
148 OS << "enum {\n"; in runEnums()
150 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
151 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
152 OS << "};\n"; in runEnums()
154 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
159 OS << "\n// Subregister indices\n\n"; in runEnums()
162 OS << "namespace " << Namespace << " {\n"; in runEnums()
163 OS << "enum {\n NoSubRegister,\n"; in runEnums()
166 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
167 OS << " NUM_TARGET_SUBREGS\n};\n"; in runEnums()
169 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
172 OS << "} // end namespace llvm\n\n"; in runEnums()
173 OS << "#endif // GET_REGINFO_ENUM\n\n"; in runEnums()
176 static void printInt(raw_ostream &OS, int Val) { in printInt() argument
177 OS << Val; in printInt()
190 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
195 OS << "/// Get the weight in units of pressure for this register class.\n" in EmitRegUnitPressure()
202 OS << " {0, 0"; in EmitRegUnitPressure()
206 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
209 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
211 OS << " };\n" in EmitRegUnitPressure()
223 OS << "/// Get the weight in units of pressure for this register unit.\n" in EmitRegUnitPressure()
229 OS << " static const uint8_t RUWeightTable[] = {\n "; in EmitRegUnitPressure()
234 OS << RU.Weight << ", "; in EmitRegUnitPressure()
236 OS << "};\n" in EmitRegUnitPressure()
240 OS << " // All register units have unit weight.\n" in EmitRegUnitPressure()
243 OS << "}\n\n"; in EmitRegUnitPressure()
245 OS << "\n" in EmitRegUnitPressure()
250 OS << "// Get the name of this register unit pressure set.\n" in EmitRegUnitPressure()
258 OS << " \"" << RegUnits.Name << "\",\n"; in EmitRegUnitPressure()
260 OS << " };\n" in EmitRegUnitPressure()
264 OS << "// Get the register unit pressure limit for this dimension.\n" in EmitRegUnitPressure()
272 OS << " " << RegUnits.Weight << ", \t// " << i << ": " in EmitRegUnitPressure()
275 OS << " };\n" in EmitRegUnitPressure()
299 OS << "/// Table of pressure sets per register class or unit.\n" in EmitRegUnitPressure()
301 PSetsSeqs.emit(OS, printInt, "-1"); in EmitRegUnitPressure()
302 OS << "};\n\n"; in EmitRegUnitPressure()
304 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
309 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1) in EmitRegUnitPressure()
312 OS << PSetsSeqs.get(PSets[i]) << ","; in EmitRegUnitPressure()
314 OS << "};\n" in EmitRegUnitPressure()
318 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
325 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size()-1) in EmitRegUnitPressure()
329 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) in EmitRegUnitPressure()
332 OS << "};\n" in EmitRegUnitPressure()
338 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
366 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; in EmitRegMappingTables()
371 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
372 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
373 OS << i << "Dwarf2L[]"; in EmitRegMappingTables()
376 OS << " = {\n"; in EmitRegMappingTables()
391 OS << " { " << I->first << "U, " << getQualifiedName(I->second) in EmitRegMappingTables()
394 OS << "};\n"; in EmitRegMappingTables()
396 OS << ";\n"; in EmitRegMappingTables()
401 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
404 OS << " = array_lengthof(" << Namespace in EmitRegMappingTables()
408 OS << ";\n\n"; in EmitRegMappingTables()
426 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
427 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
428 OS << i << "L2Dwarf[]"; in EmitRegMappingTables()
430 OS << " = {\n"; in EmitRegMappingTables()
439 OS << " { " << getQualifiedName(I->first) << ", " << RegNo in EmitRegMappingTables()
442 OS << "};\n"; in EmitRegMappingTables()
444 OS << ";\n"; in EmitRegMappingTables()
449 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
452 OS << " = array_lengthof(" << Namespace in EmitRegMappingTables()
455 OS << ";\n\n"; in EmitRegMappingTables()
461 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
478 OS << " switch ("; in EmitRegMapping()
480 OS << "DwarfFlavour"; in EmitRegMapping()
482 OS << "EHFlavour"; in EmitRegMapping()
483 OS << ") {\n" in EmitRegMapping()
488 OS << " case " << i << ":\n"; in EmitRegMapping()
489 OS << " "; in EmitRegMapping()
491 OS << "RI->"; in EmitRegMapping()
496 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
498 OS << "false"; in EmitRegMapping()
500 OS << "true"; in EmitRegMapping()
501 OS << ");\n"; in EmitRegMapping()
502 OS << " break;\n"; in EmitRegMapping()
504 OS << " }\n"; in EmitRegMapping()
509 OS << " switch ("; in EmitRegMapping()
511 OS << "DwarfFlavour"; in EmitRegMapping()
513 OS << "EHFlavour"; in EmitRegMapping()
514 OS << ") {\n" in EmitRegMapping()
519 OS << " case " << i << ":\n"; in EmitRegMapping()
520 OS << " "; in EmitRegMapping()
522 OS << "RI->"; in EmitRegMapping()
527 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
529 OS << "false"; in EmitRegMapping()
531 OS << "true"; in EmitRegMapping()
532 OS << ");\n"; in EmitRegMapping()
533 OS << " break;\n"; in EmitRegMapping()
535 OS << " }\n"; in EmitRegMapping()
541 static void printBitVectorAsHex(raw_ostream &OS, in printBitVectorAsHex() argument
550 OS << format("0x%0*x, ", Digits, Value); in printBitVectorAsHex()
564 void print(raw_ostream &OS) { in print() argument
565 printBitVectorAsHex(OS, Values, 8); in print()
569 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { in printSimpleValueType() argument
570 OS << getEnumName(VT); in printSimpleValueType()
573 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { in printSubRegIndex() argument
574 OS << Idx->EnumValue; in printSubRegIndex()
617 static void printDiff16(raw_ostream &OS, uint16_t Val) { in printDiff16() argument
618 OS << Val; in printDiff16()
621 static void printMask(raw_ostream &OS, unsigned Val) { in printMask() argument
622 OS << format("0x%08X", Val); in printMask()
647 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, in emitComposeSubRegIndices() argument
651 OS << "unsigned " << ClName in emitComposeSubRegIndices()
686 OS << " static const " << getMinimalTypeForRange(Rows.size()) << " RowMap[" in emitComposeSubRegIndices()
689 OS << RowMap[i] << ", "; in emitComposeSubRegIndices()
690 OS << "\n };\n"; in emitComposeSubRegIndices()
694 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1) in emitComposeSubRegIndices()
697 OS << " { "; in emitComposeSubRegIndices()
700 OS << Rows[r][i]->EnumValue << ", "; in emitComposeSubRegIndices()
702 OS << "0, "; in emitComposeSubRegIndices()
703 OS << "},\n"; in emitComposeSubRegIndices()
705 OS << " };\n\n"; in emitComposeSubRegIndices()
707 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" in emitComposeSubRegIndices()
710 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; in emitComposeSubRegIndices()
712 OS << " return Rows[0][IdxB];\n"; in emitComposeSubRegIndices()
713 OS << "}\n\n"; in emitComposeSubRegIndices()
717 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, in emitComposeSubRegIndexLaneMask() argument
748 OS << " struct MaskRolOp {\n" in emitComposeSubRegIndexLaneMask()
755 OS << " "; in emitComposeSubRegIndexLaneMask()
759 OS << format("{ 0x%08X, %2u }, ", P.Mask, P.RotateLeft); in emitComposeSubRegIndexLaneMask()
761 OS << "{ 0, 0 }"; in emitComposeSubRegIndexLaneMask()
763 OS << ", "; in emitComposeSubRegIndexLaneMask()
764 OS << " // Sequence " << Idx << "\n"; in emitComposeSubRegIndexLaneMask()
767 OS << " };\n" in emitComposeSubRegIndexLaneMask()
770 OS << " "; in emitComposeSubRegIndexLaneMask()
772 OS << format("&LaneMaskComposeSequences[%u]", Idx); in emitComposeSubRegIndexLaneMask()
774 OS << ","; in emitComposeSubRegIndexLaneMask()
775 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
777 OS << " };\n\n"; in emitComposeSubRegIndexLaneMask()
779 OS << "LaneBitmask " << ClName in emitComposeSubRegIndexLaneMask()
794 OS << "LaneBitmask " << ClName in emitComposeSubRegIndexLaneMask()
815 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, in runMCDesc() argument
817 emitSourceFileHeader("MC Register Information", OS); in runMCDesc()
819 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; in runMCDesc()
820 OS << "#undef GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
916 OS << "namespace llvm {\n\n"; in runMCDesc()
921 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[] = {\n"; in runMCDesc()
922 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
923 OS << "};\n\n"; in runMCDesc()
926 OS << "extern const unsigned " << TargetName << "LaneMaskLists[] = {\n"; in runMCDesc()
927 LaneMaskSeqs.emit(OS, printMask, "~0u"); in runMCDesc()
928 OS << "};\n\n"; in runMCDesc()
931 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; in runMCDesc()
932 SubRegIdxSeqs.emit(OS, printSubRegIndex); in runMCDesc()
933 OS << "};\n\n"; in runMCDesc()
936 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runMCDesc()
938 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; in runMCDesc()
940 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " in runMCDesc()
943 OS << "};\n\n"; in runMCDesc()
947 OS << "extern const char " << TargetName << "RegStrings[] = {\n"; in runMCDesc()
948 RegStrings.emit(OS, printChar); in runMCDesc()
949 OS << "};\n\n"; in runMCDesc()
951 OS << "extern const MCRegisterDesc " << TargetName in runMCDesc()
953 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; in runMCDesc()
958 OS << " { " << RegStrings.get(Reg.getName()) << ", " in runMCDesc()
965 OS << "};\n\n"; // End of register descriptors... in runMCDesc()
969 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; in runMCDesc()
974 OS << " { " << getQualifiedName(Roots.front()->TheDef); in runMCDesc()
976 OS << ", " << getQualifiedName(Roots[r]->TheDef); in runMCDesc()
977 OS << " },\n"; in runMCDesc()
979 OS << "};\n\n"; in runMCDesc()
984 OS << "namespace { // Register classes...\n"; in runMCDesc()
998 OS << " // " << Name << " Register Class...\n" in runMCDesc()
1003 OS << getQualifiedName(Reg) << ", "; in runMCDesc()
1005 OS << "\n };\n\n"; in runMCDesc()
1007 OS << " // " << Name << " Bit set.\n" in runMCDesc()
1015 BVE.print(OS); in runMCDesc()
1016 OS << "\n };\n\n"; in runMCDesc()
1019 OS << "} // end anonymous namespace\n\n"; in runMCDesc()
1022 OS << "extern const char " << TargetName << "RegClassStrings[] = {\n"; in runMCDesc()
1023 RegClassStrings.emit(OS, printChar); in runMCDesc()
1024 OS << "};\n\n"; in runMCDesc()
1026 OS << "extern const MCRegisterClass " << TargetName in runMCDesc()
1036 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " in runMCDesc()
1046 OS << "};\n\n"; in runMCDesc()
1048 EmitRegMappingTables(OS, Regs, false); in runMCDesc()
1051 OS << "extern const uint16_t " << TargetName; in runMCDesc()
1052 OS << "RegEncodingTable[] = {\n"; in runMCDesc()
1054 OS << " 0,\n"; in runMCDesc()
1063 OS << " " << Value << ",\n"; in runMCDesc()
1065 OS << "};\n"; // End of HW encoding table in runMCDesc()
1068 OS << "static inline void Init" << TargetName in runMCDesc()
1082 EmitRegMapping(OS, Regs, false); in runMCDesc()
1084 OS << "}\n\n"; in runMCDesc()
1086 OS << "} // end namespace llvm\n\n"; in runMCDesc()
1087 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
1091 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, in runTargetHeader() argument
1093 emitSourceFileHeader("Register Information Header Fragment", OS); in runTargetHeader()
1095 OS << "\n#ifdef GET_REGINFO_HEADER\n"; in runTargetHeader()
1096 OS << "#undef GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1101 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n"; in runTargetHeader()
1103 OS << "namespace llvm {\n\n"; in runTargetHeader()
1105 OS << "class " << TargetName << "FrameLowering;\n\n"; in runTargetHeader()
1107 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" in runTargetHeader()
1111 OS << " unsigned composeSubRegIndicesImpl" in runTargetHeader()
1120 OS << " const RegClassWeight &getRegClassWeight(" in runTargetHeader()
1141 OS << "namespace " << RegisterClasses.front().Namespace in runTargetHeader()
1148 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; in runTargetHeader()
1150 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; in runTargetHeader()
1152 OS << "} // end namespace llvm\n\n"; in runTargetHeader()
1153 OS << "#endif // GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1160 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, in runTargetDesc() argument
1162 emitSourceFileHeader("Target Register and Register Classes Information", OS); in runTargetDesc()
1164 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1165 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1167 OS << "namespace llvm {\n\n"; in runTargetDesc()
1170 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1193 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; in runTargetDesc()
1194 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); in runTargetDesc()
1195 OS << "};\n"; in runTargetDesc()
1198 OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; in runTargetDesc()
1201 OS << Idx.getName(); in runTargetDesc()
1202 OS << "\", \""; in runTargetDesc()
1204 OS << "\" };\n\n"; in runTargetDesc()
1207 OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n"; in runTargetDesc()
1209 OS << format(" 0x%08x, // ", Idx.LaneMask) << Idx.getName() << '\n'; in runTargetDesc()
1211 OS << " };\n\n"; in runTargetDesc()
1213 OS << "\n"; in runTargetDesc()
1217 OS << "\nstatic const TargetRegisterClass *const " in runTargetDesc()
1245 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; in runTargetDesc()
1246 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1257 OS << "\n "; in runTargetDesc()
1258 printBitVectorAsHex(OS, MaskBV, 32); in runTargetDesc()
1259 OS << "// " << Idx.getName(); in runTargetDesc()
1262 OS << "\n};\n\n"; in runTargetDesc()
1265 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; in runTargetDesc()
1267 SuperRegIdxSeqs.emit(OS, printSubRegIndex); in runTargetDesc()
1268 OS << "};\n\n"; in runTargetDesc()
1278 OS << "static const TargetRegisterClass *const " in runTargetDesc()
1281 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1282 OS << " nullptr\n};\n\n"; in runTargetDesc()
1288 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1296 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; in runTargetDesc()
1298 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); in runTargetDesc()
1299 OS << " };\n"; in runTargetDesc()
1302 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1308 OS << "),\n ArrayRef<MCPhysReg>("; in runTargetDesc()
1310 OS << "),\n makeArrayRef(AltOrder" << oi; in runTargetDesc()
1311 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1318 OS << "\nnamespace " << RegisterClasses.front().Namespace in runTargetDesc()
1322 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1335 OS << "NullRegClasses,\n "; in runTargetDesc()
1337 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1339 OS << "nullptr\n"; in runTargetDesc()
1341 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1342 OS << " };\n\n"; in runTargetDesc()
1345 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; in runTargetDesc()
1348 OS << "\nnamespace {\n"; in runTargetDesc()
1349 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; in runTargetDesc()
1351 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1352 OS << " };\n"; in runTargetDesc()
1353 OS << "} // end anonymous namespace\n"; in runTargetDesc()
1357 OS << "\nstatic const TargetRegisterInfoDesc " in runTargetDesc()
1359 OS << " { 0, false },\n"; in runTargetDesc()
1363 OS << " { "; in runTargetDesc()
1364 OS << Reg.CostPerUse << ", " in runTargetDesc()
1368 OS << "};\n"; // End of register descriptors... in runTargetDesc()
1377 emitComposeSubRegIndices(OS, RegBank, ClassName); in runTargetDesc()
1378 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); in runTargetDesc()
1383 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1389 OS << " static const uint8_t Table["; in runTargetDesc()
1391 OS << " static const uint16_t Table["; in runTargetDesc()
1394 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1396 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1399 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1402 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1404 OS << " },\n"; in runTargetDesc()
1406 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1413 EmitRegUnitPressure(OS, RegBank, ClassName); in runTargetDesc()
1416 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; in runTargetDesc()
1417 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; in runTargetDesc()
1418 OS << "extern const unsigned " << TargetName << "LaneMaskLists[];\n"; in runTargetDesc()
1419 OS << "extern const char " << TargetName << "RegStrings[];\n"; in runTargetDesc()
1420 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; in runTargetDesc()
1421 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; in runTargetDesc()
1422 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; in runTargetDesc()
1423 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runTargetDesc()
1425 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; in runTargetDesc()
1427 EmitRegMappingTables(OS, Regs, true); in runTargetDesc()
1429 OS << ClassName << "::\n" << ClassName in runTargetDesc()
1434 OS.write_hex(RegBank.CoveringLanes); in runTargetDesc()
1435 OS << ") {\n" in runTargetDesc()
1450 EmitRegMapping(OS, Regs, true); in runTargetDesc()
1452 OS << "}\n\n"; in runTargetDesc()
1463 OS << "static const MCPhysReg " << CSRSet->getName() in runTargetDesc()
1466 OS << getQualifiedName((*Regs)[r]) << ", "; in runTargetDesc()
1467 OS << "0 };\n"; in runTargetDesc()
1482 OS << "static const uint32_t " << CSRSet->getName() in runTargetDesc()
1484 printBitVectorAsHex(OS, Covered, 32); in runTargetDesc()
1485 OS << "};\n"; in runTargetDesc()
1487 OS << "\n\n"; in runTargetDesc()
1489 OS << "ArrayRef<const uint32_t *> " << ClassName in runTargetDesc()
1492 OS << " static const uint32_t *const Masks[] = {\n"; in runTargetDesc()
1494 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1495 OS << " };\n"; in runTargetDesc()
1496 OS << " return makeArrayRef(Masks);\n"; in runTargetDesc()
1498 OS << " return None;\n"; in runTargetDesc()
1500 OS << "}\n\n"; in runTargetDesc()
1502 OS << "ArrayRef<const char *> " << ClassName in runTargetDesc()
1505 OS << " static const char *const Names[] = {\n"; in runTargetDesc()
1507 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1508 OS << " };\n"; in runTargetDesc()
1509 OS << " return makeArrayRef(Names);\n"; in runTargetDesc()
1511 OS << " return None;\n"; in runTargetDesc()
1513 OS << "}\n\n"; in runTargetDesc()
1515 OS << "const " << TargetName << "FrameLowering *\n" << TargetName in runTargetDesc()
1521 OS << "} // end namespace llvm\n\n"; in runTargetDesc()
1522 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1525 void RegisterInfoEmitter::run(raw_ostream &OS) { in run() argument
1530 runEnums(OS, Target, RegBank); in run()
1531 runMCDesc(OS, Target, RegBank); in run()
1532 runTargetHeader(OS, Target, RegBank); in run()
1533 runTargetDesc(OS, Target, RegBank); in run()
1538 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) { in EmitRegisterInfo() argument
1539 RegisterInfoEmitter(RK).run(OS); in EmitRegisterInfo()