Lines Matching refs:outinfo
2024 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id) in gfx10_get_ngg_info()
2218 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo; in get_vs_output_info()
2220 return &pipeline->gs_copy_shader->info.vs.outinfo; in get_vs_output_info()
2222 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo; in get_vs_output_info()
2224 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo; in get_vs_output_info()
4160 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); in radv_pipeline_generate_vgt_gs_mode() local
4177 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) { in radv_pipeline_generate_vgt_gs_mode()
4200 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); in radv_pipeline_generate_hw_vs() local
4202 clip_dist_mask = outinfo->clip_dist_mask; in radv_pipeline_generate_hw_vs()
4203 cull_dist_mask = outinfo->cull_dist_mask; in radv_pipeline_generate_hw_vs()
4205 bool misc_vec_ena = outinfo->writes_pointsize || in radv_pipeline_generate_hw_vs()
4206 outinfo->writes_layer || in radv_pipeline_generate_hw_vs()
4207 outinfo->writes_viewport_index; in radv_pipeline_generate_hw_vs()
4211 nparams = MAX2(outinfo->param_exports, 1); in radv_pipeline_generate_hw_vs()
4215 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0); in radv_pipeline_generate_hw_vs()
4222 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ? in radv_pipeline_generate_hw_vs()
4225 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ? in radv_pipeline_generate_hw_vs()
4228 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ? in radv_pipeline_generate_hw_vs()
4233 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) | in radv_pipeline_generate_hw_vs()
4234 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) | in radv_pipeline_generate_hw_vs()
4235 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) | in radv_pipeline_generate_hw_vs()
4247 outinfo->writes_viewport_index); in radv_pipeline_generate_hw_vs()
4307 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); in radv_pipeline_generate_hw_ngg() local
4309 clip_dist_mask = outinfo->clip_dist_mask; in radv_pipeline_generate_hw_ngg()
4310 cull_dist_mask = outinfo->cull_dist_mask; in radv_pipeline_generate_hw_ngg()
4312 bool misc_vec_ena = outinfo->writes_pointsize || in radv_pipeline_generate_hw_ngg()
4313 outinfo->writes_layer || in radv_pipeline_generate_hw_ngg()
4314 outinfo->writes_viewport_index; in radv_pipeline_generate_hw_ngg()
4315 bool es_enable_prim_id = outinfo->export_prim_id || in radv_pipeline_generate_hw_ngg()
4329 nparams = MAX2(outinfo->param_exports, 1); in radv_pipeline_generate_hw_ngg()
4332 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0)); in radv_pipeline_generate_hw_ngg()
4338 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ? in radv_pipeline_generate_hw_ngg()
4341 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ? in radv_pipeline_generate_hw_ngg()
4344 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ? in radv_pipeline_generate_hw_ngg()
4349 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) | in radv_pipeline_generate_hw_ngg()
4350 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) | in radv_pipeline_generate_hw_ngg()
4351 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) | in radv_pipeline_generate_hw_ngg()
4363 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id)); in radv_pipeline_generate_hw_ngg()
4718 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); in radv_pipeline_generate_ps_inputs() local
4724 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID]; in radv_pipeline_generate_ps_inputs()
4733 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER]; in radv_pipeline_generate_ps_inputs()
4742 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT]; in radv_pipeline_generate_ps_inputs()
4760 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0]; in radv_pipeline_generate_ps_inputs()
4766 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1]; in radv_pipeline_generate_ps_inputs()
4782 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i]; in radv_pipeline_generate_ps_inputs()