Lines Matching +full:freedreno +full:- +full:rules
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
9 <!-- these might be same as a5xx -->
25 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
46 <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
114 <!-- used with the Y plane of FMT6_R8_G8B8_2PLANE_420_UNORM
115 which has different UBWC compression from regular 8_UNORM format -->
153 <!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
156 <!-- Not a hw enum, used internally in driver -->
161 <!-- probably same as a5xx -->
864 <!--
880 -->
893 <doc>Allow early z-test and early-lrz (if applicable)</doc>
895 <doc>Disable early z-test and early-lrz test (if applicable)</doc>
898 A special mode that allows early-lrz test but disables
899 early-z test. Which might sound a bit funny, since
900 lrz-test happens before z-test. But as long as a couple
901 conditions are maintained this allows using lrz-test in
904 1) Disable lrz-write in cases where it is uncertain during
906 shader has-kill, writes-z, or alpha/stencil test is
907 enabled. (For correctness, lrz-write must be disabled
909 z-prepass works.
911 2) Disable lrz-write and test if a depth-test direction
916 lrz-test. But geometry which may be (or contributes to
917 blend) will pass the lrz-test.
919 This allows us to keep early-lrz-test in cases where the frag
920 shader does not write-z (ie. we know the z-value before FS)
921 and does not have side-effects (image/ssbo writes, etc), but
923 enough case that it is useful to keep early-lrz test against
985 <!-- all the threshold values seem to be in units of quad-dwords: -->
1014 <!-- total ROQ size: -->
1073 <!-- SDS == CP_SET_DRAW_STATE: -->
1077 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
1081 <!--
1084 -->
1089 <!--
1092 -->
1406 <!---
1410 -->
1412 <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
1414 <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
1416 <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
1418 <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
1420 <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
1422 <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
1424 <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
1426 <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
1428 <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
1430 <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
1768 <!-- move/rename these.. -->
1800 <!--
1803 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
1808 LIMIT is set to PITCH - 64, to make room for a bit of overflow
1809 -->
1848 <!-- always 0x03200000 ? -->
1851 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
1861 <!-- set with depthClampEnable, not clear what it does -->
1863 <!-- controls near z clip behavior (set for vulkan) -->
1865 <!-- guess based on a3xx and meaning of bits 8 and 9
1866 if the guess is right then this is related to point sprite clipping -->
1882 <!-- see also RB_RENDER_CONTROL0 -->
1884 <!-- b1 set for interpolateAtCentroid() -->
1886 <!-- b2 set instead of b0 when running in per-sample mode -->
1888 <!--
1889 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1891 -->
1894 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1902 <!-- 0x8006-0x800f invalid -->
1925 <!--
1928 -->
1938 <!-- 0x8093 invalid -->
1945 <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1961 <!-- 0x809e/0x809f invalid -->
2002 <!-- 0x80a7-0x80ae invalid -->
2020 <!-- 0x80f2-0x80ff invalid -->
2023 <!--
2026 -->
2033 <!-- set when depth-test + depth-write enabled -->
2045 <!-- TODO: fix the shr fields -->
2050 <!--
2073 // fast-clear buffer is 1bit/block:
2079 -->
2083 <!-- 0x8108 invalid -->
2093 <!-- 0x810b-0x810f invalid -->
2097 <!-- 0x8111-0x83ff invalid -->
2115 <!-- required when blitting D24S8/D24X8 -->
2117 <!-- some sort of channel mask, disabled channels are set to zero ? -->
2124 <!-- note: the low 8 bits for src coords are valid, probably fixed point
2127 -->
2139 <!-- 0x840c-0x85ff invalid -->
2141 <!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
2157 <!-- note 0x8620-0x87ff are not all invalid
2159 -->
2161 <!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
2173 <!-- always set: ?? -->
2176 <!-- set during binning pass: -->
2179 <!-- bit seems to be set whenever depth buffer enabled: -->
2181 <!-- bitmask of MRTs using UBWC flag buffer: -->
2197 <!-- 0x8807-0x8808 invalid -->
2198 <!--
2201 -->
2203 <!-- see also GRAS_CNTL -->
2205 <!-- b1 set for interpolateAtCentroid() -->
2207 <!-- b2 set instead of b0 when running in per-sample mode -->
2209 <!--
2210 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2212 -->
2215 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2221 <!-- enable bits for various FS sysvalue regs: -->
2226 <!-- b4 and b5 set in per-sample mode: -->
2264 <!-- Same as SP_SRGB_CNTL -->
2279 <!-- 0x8812-0x8817 invalid -->
2280 <!-- always 0x0 ? -->
2282 <!-- 0x8819-0x881e all 32 bits -->
2289 <!-- 0x881f invalid -->
2312 <!--
2315 -->
2318 <!--
2323 -->
2327 <!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
2343 <!-- per-mrt enable bit -->
2351 <!-- 0x8866-0x886f invalid -->
2368 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2382 <!-- 0x887a-0x887f invalid -->
2386 <!--
2391 -->
2424 <!-- 0x888a-0x888f invalid -->
2430 <!-- 0x8892-0x8897 invalid -->
2434 <!-- 0x8899-0x88bf invalid -->
2435 <!-- clamps depth value for depth test/write -->
2438 <!-- 0x88c2-0x88cf invalid-->
2445 <!-- weird to duplicate other regs from same block?? -->
2455 <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2468 <!-- array-pitch is size of layer -->
2483 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2485 …bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color resto…
2486 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2487 <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
2488 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2491 1 - depth
2492 2 - stencil
2493 3 - depth+stencil
2501 <!-- 0x88e4-0x88ef invalid -->
2502 <!-- always 0x0 ? -->
2504 <!-- could be for separate stencil? (or may not be a flag buffer at all) -->
2511 <!-- 0x88f5-0x88ff invalid -->
2517 <!-- TODO: actually part of array pitch -->
2530 <!-- 0x891b-0x8926 invalid -->
2534 <!-- 0x8929-0x89ff invalid -->
2536 <!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
2547 <!-- the rest is only for src -->
2555 <!-- 0x8c02-0x8c16 invalid -->
2556 <!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
2562 <!-- this is a guess but seems likely (for NV12/IYUV): -->
2571 <!-- this is a guess but seems likely (for NV12 with UBWC): -->
2575 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
2576 <!-- unlike a5xx, these are per channel values rather than packed -->
2581 <!-- 0x8c34-0x8dff invalid -->
2583 <!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
2585 <!-- 0x8e00-0x8e03 invalid -->
2586 <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/> <!-- TODO: valid mask 0xfffffeff -->
2588 <!-- 0x8e06 invalid -->
2590 <!-- offset into GMEM for something.
2598 -->
2600 <bitfield name="GMEM" pos="22" type="boolean"/> <!-- set for GMEM path -->
2601 <bitfield name="UNK2" pos="2" type="boolean"/> <!-- sometimes set with GMEM? -->
2606 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
2612 <!-- 0x8e09-0x8e0f invalid -->
2626 <!-- 0x8e1d-0x8e1f invalid -->
2627 <!-- 0x8e20-0x8e25 more perfcntr sel? -->
2628 <!-- 0x8e26-0x8e27 invalid -->
2630 <!-- 0x8e29-0x8e2b invalid -->
2637 <!-- 0x8e3e-0x8e4f invalid -->
2638 <!-- GMEM save/restore for preemption: -->
2640 <!-- address for GMEM save/restore? -->
2642 <!-- 0x8e53-0x8e7f invalid -->
2643 <!-- 0x8e80-0x8e83 are valid -->
2644 <!-- 0x8e84-0x90ff invalid -->
2646 <!-- 0x9000-0x90ff invalid -->
2648 <!-- something to do with geometry shader: -->
2653 <!-- there can be up to 8 total clip/cull distance outputs,
2656 -->
2674 <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
2681 <!-- 0x9109-0x91ff invalid -->
2689 <!-- always 0x0 -->
2694 <!-- one bit per varying component: -->
2699 <!--
2719 This field is auto-incremented when VPC_SO_PROG is
2721 -->
2723 <!-- clear all A_EN and B_EN bits for all DWORD's -->
2726 <!-- special register, write multiple times to load SO program (not readable) -->
2745 <reg32 offset="3" name="NCOMP" low="0" high="9"/> <!-- component count -->
2755 <!-- 0x9237-0x92ff invalid -->
2756 <!-- always 0x0 ? -->
2762 plus # of transform-feedback (streamout) varyings if using the
2771 number of views minus one when multi-position
2782 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
2790 strictly required for multi-position output,
2792 views at once, but it can be used when multi-pos
2800 <!--
2802 -->
2812 <!-- 0x9307-0x95ff invalid -->
2814 <!-- TODO: 0x9600-0x97ff range -->
2815 <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
2817 <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0"/> <!-- always 0x0 ? -->
2825 <!-- 0x960a-0x9623 invalid -->
2826 <!-- TODO: regs from 0x9624-0x963a -->
2827 <!-- 0x963b-0x97ff invalid -->
2831 <!-- always 0x0 ? -->
2856 <!-- always 0x1 ? -->
2859 <!-- probably a mirror of VFD_CONTROL_6 -->
2861 <!-- 0x980b-0x983f invalid -->
2863 <!-- 0x9840 - 0x9842 are not readable -->
2873 <!-- I think only the low bit is actually used? -->
2878 <!-- 0x9843-0x997f invalid -->
2885 <!-- which stream to send to GRAS -->
2887 <!-- discard primitives before rasterization -->
2891 <!-- 0x9982-0x9aff invalid -->
2895 <!-- maybe? b1 seems always set, so just assume it is for now: -->
2904 plus # of transform-feedback (streamout) varyings if using the
2911 <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
2925 <!-- TODO: first 16 bits are valid so something is wrong or missing here -->
2934 size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
2943 Multi-position output lets the last geometry
2954 <!-- mask of enabled views, doesn't exist on A630 -->
2956 <!-- 0x9b09-0x9bff invalid -->
2958 <!-- special register (but note first 8 bits can be written/read) -->
2962 <!-- 0x9c01-0x9dff invalid -->
2963 <!-- TODO: 0x9e00-0xa000 range incomplete -->
2970 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
2988 <!-- always 0x0 -->
2999 <!-- only used for VS in non-multi-position-output case -->
3017 <!--
3020 be passed through via fixed-function logic.
3021 -->
3031 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
3033 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
3048 <!-- IDX and byte OFFSET into VFD_FETCH -->
3066 <!-- always 0x1 ? -->
3070 <!--
3073 - used (half): 0-15 68-179 (cnt=128, max=179)
3074 …- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 12…
3078 - used (merged): 0-191 (cnt=192, max=191)
3083 -->
3086 <!-- seems to be nesting level for flow control:.. -->
3090 <!-- set when dFdxFine/dFdyFine is used -->
3097 <!--
3100 -->
3107 <!--
3110 -->
3118 <!--
3121 -->
3124 <!-- # of VS outputs including pos/psize -->
3135 <!--
3141 -->
3169 <!-- # of DS outputs including pos/psize -->
3198 <!-- size of output of previous stage -->
3201 <!--
3204 -->
3208 <!-- # of VS outputs including pos/psize -->
3256 <!--
3259 -->
3272 <!-- Same as RB_SRGB_CNTL -->
3311 <!-- unknown bits 0x7fc0 always set -->
3313 …<!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? …
3325 <!--
3327 skip pre-fetch.. TODO test texelFetch
3331 -->
3336 <!-- TODO confirm that this is actually an array -->
3346 <!-- always 0x0 ? -->
3349 <!-- set for compute shaders, always 0x41 -->
3355 64k (and has 36k of storage on A640 - reads between 36k-64k
3361 <!-- set for compute shaders, always 0x0 -->
3393 <!--
3395 -->
3400 <!-- always 0x5 ? -->
3402 <!--
3404 load a 32-bit value (so hc0.y loads the same value as c0.y)
3409 -->
3420 <!--
3423 -->
3432 <!-- looks like HW only cares about the base type of this format,
3433 which matches the ifmt? -->
3435 <!-- set when ifmt is R2D_UNORM8_SRGB -->
3437 <!-- some sort of channel mask, not sure what it is for -->
3441 <!-- always 0x0 -->
3447 <!-- always 0x3f ? -->
3450 <!--
3454 -->
3456 <!-- always 0x0 ? -->
3460 <!-- could be all the stuff below here is actually TPL1?? -->
3470 <!-- looks to work in the same way as a5xx: -->
3480 <!--
3484 -->
3505 <!-- always 0x00100000 ? -->
3508 <!-- always 0x44 ? -->
3528 <!-- always 0x7 ? -->
3532 <!-- SAMPLEID is loaded into a half-precision register: -->
3535 <!--
3539 -->
3543 <!-- register loaded with position (bary.f) -->
3556 <!-- unknown regid in low 8b -->
3562 <!-- localsize is value minus one: -->
3591 <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
3600 <!-- mirror of SP_CS_BINDLESS_BASE -->
3614 <!-- I think only the low bit is actually used? -->
3626 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
3637 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
3641 <!-- SS6_BINDLESS: one bit per bindless base -->
3654 c504-c511 in each stage. Both VS and FS shared consts
3670 <!-- mirror of SP_BINDLESS_BASE -->
3680 <!-- always 0x80 ? -->
3682 <!-- always 0x0 ? -->
3684 <!-- always 0x0 ? -->
3687 <!--
3690 - write EVENT_CMD pipe register
3691 - write CP_EVENT_START
3692 - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
3693 - write PC_EVENT_CMD with event or PC_DRAW_CMD
3694 - write HLSQ_EVENT_CMD(CONTEXT_DONE)
3695 - write PC_EVENT_CMD(CONTEXT_DONE)
3696 - write CP_EVENT_END
3698 -->
3713 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3716 <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3720 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
3722 <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3729 <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3750 … name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3753 <!-- bit 0 always set with vulkan? -->
3772 <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3780 <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3794 <!-- overlaps with MIPLVLS -->
3806 <!--
3811 …behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.bu…
3812 -->
3814 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
3822 <!--
3827 -->
3830 <!--
3834 -->
3838 <!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
3839 the address of the non-flag base buffer is determined automatically,
3841 -->
3850 <!-- pitch for plane 2 / plane 3 -->
3853 <!-- 7/8 is plane 2 address for planar formats -->
3860 <!-- 9/10 is plane 3 address for planar formats -->
3866 <!-- log2 size of the first level, required for mipmapping -->
3877 <!--
3881 -->
3884 <!--
3887 -->
3896 <!--
3899 -->
3907 <!--
3912 -->
3934 <!--
3937 -->
3948 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->