120 bool CPURegister::IsValid() const {  in IsValid()  function in vixl::aarch64::CPURegister
232   VIXL_ASSERT(reg1.IsValid());  in AreSameSizeAndType()
234   match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);  in AreSameSizeAndType()
235   match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);  in AreSameSizeAndType()
236   match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);  in AreSameSizeAndType()
237   match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);  in AreSameSizeAndType()
238   match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1);  in AreSameSizeAndType()
239   match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1);  in AreSameSizeAndType()
240   match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1);  in AreSameSizeAndType()
252   VIXL_ASSERT(reg1.IsValid());  in AreEven()
254   even &= !reg2.IsValid() || ((reg2.GetCode() % 2) == 0);  in AreEven()
255   even &= !reg3.IsValid() || ((reg3.GetCode() % 2) == 0);  in AreEven()
256   even &= !reg4.IsValid() || ((reg4.GetCode() % 2) == 0);  in AreEven()
257   even &= !reg5.IsValid() || ((reg5.GetCode() % 2) == 0);  in AreEven()
258   even &= !reg6.IsValid() || ((reg6.GetCode() % 2) == 0);  in AreEven()
259   even &= !reg7.IsValid() || ((reg7.GetCode() % 2) == 0);  in AreEven()
260   even &= !reg8.IsValid() || ((reg8.GetCode() % 2) == 0);  in AreEven()
268   VIXL_ASSERT(reg1.IsValid());  in AreConsecutive()
270   if (!reg2.IsValid()) {  in AreConsecutive()
277   if (!reg3.IsValid()) {  in AreConsecutive()
284   if (!reg4.IsValid()) {  in AreConsecutive()
298   VIXL_ASSERT(reg1.IsValid());  in AreSameFormat()
300   match &= !reg2.IsValid() || reg2.IsSameFormat(reg1);  in AreSameFormat()
301   match &= !reg3.IsValid() || reg3.IsSameFormat(reg1);  in AreSameFormat()
302   match &= !reg4.IsValid() || reg4.IsSameFormat(reg1);  in AreSameFormat()
310   VIXL_ASSERT(reg1.IsValid());  in AreSameLaneSize()
313       !reg2.IsValid() || (reg2.GetLaneSizeInBits() == reg1.GetLaneSizeInBits());  in AreSameLaneSize()
315       !reg3.IsValid() || (reg3.GetLaneSizeInBits() == reg1.GetLaneSizeInBits());  in AreSameLaneSize()
317       !reg4.IsValid() || (reg4.GetLaneSizeInBits() == reg1.GetLaneSizeInBits());  in AreSameLaneSize()