Lines Matching refs:HWC_DISPLAY_VIRTUAL

203         {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
212         {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
222         {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
231         {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
241         {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
250         {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
260         {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
269         {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
279         {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
288         {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
298         {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
307         {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
315         {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, CONSTRAINT_A0),
321         {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, CONSTRAINT_A0),
325         {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI0, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {0, 2}},
328         {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI1, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {0, 2}},
331         {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI0, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {2, 2}},
334         {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI1, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {2, 2}},