ELF@@  ;;;;  ;;;;w  2(3(4(5(6(7(8(9(de,--.R^wxU&'X()*V+,-W./ XYZ[\]^_`abc3456789:;<=NO RLMN~@,%'()*+,56-. /!0"1#2$3%4&7'8(9):*;+<,=->.?/@xyGzM{H|I}J~NKLO[\  f/ba_c0h^o!iSdj`kOglm:< ; <!=">#?4@:A;B<C%0( 1) 2* 3+ 4, 5- 6. 7/ 80 91 :2 4 5 6 7 8 9 :   GATE_PCIE_GEN4_0_APB_1GATE_PCIE_GEN4_1_SCLK_1UMUX_CLKCMU_G3AA_G3AAGATE_WDT_CL0gs101_clockUMUX_CLKCMU_IPP_BUSUMUX_CLKCMU_ITP_BUSUMUX_CLKCMU_MFC_MFCGATE_PERIC0_TOP0_S5DOUT_CLK_DNS_BUSPcould not allocate clock provider context. 3[CAL] Failed to set vclk dfs %d %lu %d GATE_GPUGATE_PCIE_GEN4_1_PCS_APBGATE_PERIC1_TOP0_USI13_USIGATE_PERIC1_TOP0_SDOUT_CLK_G3AA_BUSPGATE_DPUF_DMAUMUX_CLKCMU_MCSC_MCSCGATE_PERIC0_TOP0_I3C6DOUT_CLK_CSIS_BUSPCIS_CLK5DOUT_CLK_TPU_BUSP3Failed to disable clock %s GATE_DFTMUX_CMU_CIS_CLK2GATE_DFTMUX_CMU_CIS_CLK4GATE_PERIC0_TOP0_I3C23Failed to allocate vclk struct GATE_DFTMUX_CMU_CIS_CLK3UMUX_CLKCMU_DISP_BUSUMUX_CLKCMU_PDP_VRAUMUX_CLKCMU_PERIC0_BUSGATE_PERIC0_TOP0_S1DOUT_CLK_PDP_BUSPGATE_DFTMUX_CMU_CIS_CLK7UMUX_CLKCMU_BUS0_BUSUMUX_CLKCMU_HSI0_ALTGATE_PCIE_GEN4_0_AXI_1DOUT_CLK_HSI0_USB31DRDVDOUT_CLK_PERIC0_USI6_USIGATE_DFTMUX_CMU_CIS_CLK0GATE_PCIE_GEN4_0_PMA_APBGATE_PCIE_GEN4_1_DBG_1UMUX_CLKCMU_MCSC_ITSCGATE_PERIC1_TOP0_USI0_USIGATE_PERIC1_TOP0_USI9_USIDOUT_CLK_BUS1_BUSPUMUX_CLKCMU_EH_BUSMUX_HSI0_USB20_REFGATE_UFS_EMBD_FMPDOUT_CLK_TNR_BUSPUMUX_CLKCMU_GDC_SCSCGATE_PERIC0_TOP0_USI5_USIUMUX_CLKCMU_PERIC1_BUSVDOUT_CLK_PERIC0_USI8_USI3[CAL] Failed to set vclk rate %d %lu %d MUX_APM_FUNCGATE_UFS_EMBDUMUX_CLKCMU_MISC_SSSDOUT_CLK_MISC_BUSPDOUT_CLK_DISP_BUSPDOUT_CLK_G2D_BUSPDOUT_CLK_IPP_BUSP3Failed to get clk by register offset GATE_DFTMUX_CMU_CIS_CLK1GATE_PCIE_GEN4_0_PCS_APBUMUX_CLKCMU_HSI2_PCIEUMUX_CLKCMU_G2D_G2DMUX_HSI0_USB31DRDGATE_PCIE_GEN4_1_DBG_2GATE_PERIC0_TOP0_USI7_USIDOUT_CLK_APM_BOOSTVDOUT_CLK_PERIC0_USI1_USIVDOUT_CLK_PERIC1_USI13_USICLKOUT1UMUX_CLKCMU_HSI2_UFS_EMBDGATE_MFCGATE_PERIC0_TOP0_I3C5GATE_PERIC1_TOP0_PWMUMUX_CLKCMU_TPU_BUSDOUT_CLK_DPU_BUSPVDOUT_CLK_PERIC1_USI12_USI%s: failed to map registers MUX_APM_FUNCSRCMUX_BUS0_BUS_OPTION1GATE_JPEGUMUX_CLKCMU_HSI0_DPGTCGATE_PCIE_GEN4_1_UDBGGATE_PERIC0_TOP0_I3C7GATE_PERIC1_TOP0_USI10_USIDOUT_CLK_GDC_BUSPUFS_EMBDVDOUT_CLK_PERIC0_USI14_USI3[CAL] vclk disable failed %d %d MUX_HSI0_BUSUMUX_CLKCMU_CSIS_BUSGATE_PERIC0_TOP0_USI4_USIMUX_TPU_TPUCTLDOUT_CLK_BUS2_BUSPDOUT_CLK_EH_BUSPVDOUT_CLK_PERIC1_USI9_USICLKOUT0UMUX_CLKCMU_EH_PLL_COREGATE_DPUF_DPPGATE_PCIE_GEN4_0_AXI_2UMUX_CLKCMU_TNR_BUSGATE_PERIC0_TOP0_USI3_USIUMUX_CLKCMU_BO_BUSVDOUT_CLK_PERIC1_I3CUMUX_CLKCMU_HSI0_USB31DRDGATE_PERIC0_TOP0_USI6_USIUMUX_CLKCMU_TPU_UARTCIS_CLK1UMUX_CLKCMU_BUS1_BUSGATE_USB31DRD_SLV_LINKGATE_PCIE_GEN4_0_DBG_1GATE_PCIE_GEN4_1_APB_1UMUX_CLKCMU_GDC_GDC1GATE_PERIC0_TOP0_S7GATE_PERIC1_TOP0_USI12_USIVDOUT_CLK_PERIC0_USI7_USI3Failed to enable clock %s GATE_DPUBDOUT_CLK_APM_USI0_USIcould not allocate clock lookup table 3Failed to register lookup %s GATE_DFTMUX_CMU_CIS_CLK6UMUX_CLKCMU_G2D_MSCLUMUX_CLKCMU_HSI0_TCXOGATE_PCIE_GEN4_0_SCLK_1UMUX_CLKCMU_MISC_BUSGATE_PERIC0_TOP0_USI1_USIGATE_PERIC0_TOP0_I3C8DOUT_CLK_MCSC_BUSPCIS_CLK4VDOUT_CLK_PERIC0_USI3_USIVDOUT_CLK_PERIC0_USI5_USIDOUT_CLK_TPU_TPUCTL3Failed to register clock lookup for %s3Failed to allocate for gate_clk UMUX_CLKCMU_HSI0_BUSGATE_PCIE_GEN4_0_APB_2GATE_PCIE_GEN4_1_AXI_1UMUX_CLKCMU_GDC_GDC0GATE_PERIC0_TOP0_S2GATE_PERIC0_TOP0_S4GATE_PERIC0_TOP1_USI0_UARTUMUX_CLKCMU_TPU_TPUVDOUT_CLK_TOP_HSI0_BUSDOUT_CLK_BO_BUSPGATE_MMC_CARDGATE_PDMAGATE_PERIC0_TOP0_USI2_USIGATE_PERIC0_TOP0_USI8_USIGATE_PERIC0_TOP0_I3C1UMUX_CLKCMU_TPU_TPUCTLpwm-clock3[CAL] Failed to set vclk dfs rate switch UMUX_CLKCMU_BUS2_BUSUMUX_CLKCMU_CORE_BUSGATE_PCIE_GEN4_0_DBG_2UMUX_CLKCMU_DNS_BUSGATE_PERIC0_TOP0_S3CIS_CLK33[CAL] vclk enable failed %d %d UMUX_CLKCMU_DPU_BUSUMUX_CLKCMU_HSI1_PCIEUMUX_CLKCMU_HSI2_MMC_CARDDOUT_CLK_APM_USI1_UARTDOUT_CLK_ITP_BUSPDOUT_CLKCMU_HSI2_MMC_CARD6GS101: Clock setup completed GATE_G2DUMUX_MIF_DDRPHY2XGATE_MCTGATE_WDT_CL1GATE_PERIC0_TOP0_I3C3GATE_PERIC1_TOP0_I3C0MUX_TPU_TPUVDOUT_CLK_PERIC0_USI2_USIVDOUT_CLK_PERIC0_I3CVDOUT_CLK_PERIC1_USI0_USIgs101_clock_probe3Failed to register virtual clock %s ATCLKGATE_PERIC0_TOP0_S6CIS_CLK0CIS_CLK7VDOUT_CLK_PERIC0_USI4_USIDOUT_CLK_TPU_TPU3can not alloc for enable gate clock list fin_pllUMUX_CLKCMU_HSI2_BUSGATE_PCIE_GEN4_1_AXI_2DOUT_CLK_APM_USI0_UARTVDOUT_CLK_PERIC1_USI10_USI3Failed to register clock %s UMUX_CLKCMU_HSI0_USB20GATE_PERIC0_TOP0_S8GATE_PERIC0_TOP1_USI14_USI%s: unable to determine soc 3could not allocate usermux clk UMUX_CLKCMU_PDP_BUSUMUX_CLKCMU_PERIC0_USI0_UARTDOUT_CLK_BUS0_BUSPCIS_CLK2CIS_CLK6VDOUT_CLK_PERIC1_USI11_USIcould not register clk provider GATE_DFTMUX_CMU_CIS_CLK5GATE_PCIE_GEN4_0_UDBGGATE_PERIC1_TOP0_USI11_USIVDOUT_CLK_PERIC0_USI0_UART3can not alloc for gate clock list MUX_EH_BUSUMUX_CLKCMU_HSI1_BUSGATE_PCIE_GEN4_1_PMA_APBGATE_PCIE_GEN4_1_APB_2GATE_PERIC0_TOP0_I3C4DOUT_CLK_MFC_BUSPclock-frequencysamsung,gs101-clockgs101-clocksamsung,gs101-oscclk?#Ո҈$ȇhVT(҇Xh\;mTH҇Xh\; Ts8H@ T[hATIń(BHT葐UTGҨhhT4҈$ȇhVTrҨҰhȰT%ń(BH`Tk T( ȓT#( ȓT ?T#_( ȓ #T_$?#@9#qCT_@*?#տ#_?#{!{#_?#{ OA+*+RR@+RR@+)*K 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QX!.note.gnu.property.note.Linux.text.comment.init.plt.bss.rela.rodata.samsung_usermux_ops.rela.altinstructions__versions.rela.data.gs101_fixed_rate_ext_clks.modinfo.note.GNU-stack.llvm_addrsig.text.ftrace_trampoline.rela.text.init_module.rela.gnu.linkonce.this_module.rela__jump_table.note.gnu.build-id.shstrtab.strtab.symtab.rodata.dataof_property_read_variable_u32_arraysamsung_register_usermux__clk_get_hwclk_register_clkdevsamsung_register_of_fixed_extgate_clk_listsamsung_add_clk_gate_list__cfi_jt_startclk_hw_get_parentof_clk_src_onecell_get.cfi_jtcal_vclk_dfs_set_rate_switch.cfi_jtcal_vclk_dfs_set_rate.cfi_jtcal_vclk_set_rate.cfi_jtcal_vclk_round_rate.cfi_jtcal_vclk_dfs_sw_recalc_rate.cfi_jtcal_vclk_dfs_recalc_rate.cfi_jtcal_vclk_recalc_rate.cfi_jtcal_vclk_gate_recalc_rate.cfi_jtinit_module.cfi_jtcleanup_module.cfi_jtsamsung_usermux_disable.cfi_jtcal_vclk_disable.cfi_jtcal_vclk_qactive_disable.cfi_jtsamsung_usermux_enable.cfi_jtcal_vclk_enable.cfi_jtcal_vclk_qactive_enable.cfi_jtgs101_clock_probe.cfi_jtsamsung_usermux_is_enabled.cfi_jtcal_vclk_is_enabled.cfi_jtgs101_vclk_initsamsung_clk_initcal_qch_initof_clk_src_onecell_getsamsung_usermux_opssamsung_vclk_dfs_sw_opssamsung_vclk_dfs_opssamsung_vclk_opssamsung_vclk_qactive_opssamsung_vclk_gate_ops____versionsgs101_tpu_vclksgs101_dpu_vclksgs101_clkout_vclksgs101_dns_vclksgs101_csis_vclksgs101_tnr_vclksgs101_itp_vclksgs101_disp_vclksgs101_ipp_vclksgs101_top_vclksgs101_pdp_vclksgs101_bo_vclksgs101_apm_vclksgs101_eh_vclksgs101_tpu_hwacg_vclksgs101_dpu_hwacg_vclksgs101_dns_hwacg_vclksgs101_csis_hwacg_vclksgs101_tnr_hwacg_vclksgs101_itp_hwacg_vclksgs101_disp_hwacg_vclksgs101_ipp_hwacg_vclksgs101_top_hwacg_vclksgs101_pdp_hwacg_vclksgs101_bo_hwacg_vclksgs101_apm_hwacg_vclksgs101_eh_hwacg_vclksgs101_mif_hwacg_vclksgs101_core_hwacg_vclksgs101_g3d_hwacg_vclksgs101_g2d_hwacg_vclksgs101_misc_hwacg_vclksgs101_mcsc_hwacg_vclksgs101_mfc_hwacg_vclksgs101_gdc_hwacg_vclksgs101_g3aa_hwacg_vclksgs101_bus2_hwacg_vclksgs101_hsi2_hwacg_vclksgs101_bus1_hwacg_vclksgs101_hsi1_hwacg_vclksgs101_peric1_hwacg_vclksgs101_bus0_hwacg_vclksgs101_hsi0_hwacg_vclksgs101_peric0_hwacg_vclksgs101_g2d_vclksgs101_misc_vclksgs101_mcsc_vclksgs101_mfc_vclksgs101_gdc_vclksgs101_g3aa_vclksgs101_bus2_vclksgs101_hsi2_vclksgs101_bus1_vclksgs101_peric1_vclksgs101_bus0_vclksgs101_hsi0_vclksgs101_peric0_vclksgs101_fixed_rate_ext_clksarm64_use_ng_mappingskmalloc_cachesexynos_clock_idsclk_register_fixed_factorsamsung_register_fixed_factorgate_clk_nrgs101_clock_driverplatform_driver_unregister__platform_driver_registerclk_registergs101_clk_providerof_clk_add_providersamsung_clk_of_add_providercpu_numbersamsung_clk_alloc_reg_dumpof_iomap__ioremap__log_write_mmio__log_post_read_mmio__log_read_mmio__stack_chk_fail__cfi_check_failprintk__cpu_online_masksamsung_register_vclklock__cfi_checkcal_dfs_set_rate_switchcal_vclk_dfs_set_rate_switchext_clk_matchof_exynos_clock_matchof_find_matching_node_and_matchsamsung_clk_get_by_reg_raw_spin_lock_irqsavesamsung_clk_save__tracepoint_rwmmio_writecal_clk_setratecal_clk_getratecal_dfs_set_ratecal_vclk_dfs_set_ratecal_vclk_set_rate__tracepoint_clock_set_rate__traceiter_clock_set_ratecal_dfs_get_ratecal_dfs_cached_get_ratecal_vclk_round_rateclk_register_fixed_ratesamsung_register_fixed_ratecal_vclk_dfs_sw_recalc_ratecal_vclk_dfs_recalc_ratecal_vclk_recalc_ratecal_vclk_gate_recalc_rateclk_register_gatesamsung_register_gate_raw_spin_unlock_irqrestoresamsung_clk_restoreclk_unprepareclk_prepareclk_hw_get_name__clk_get_name__cfi_jt_init_module__this_module__cfi_jt_cleanup_module__mod_of__of_exynos_clock_match_device_tablesamsung_usermux_disablecal_vclk_disablecal_clk_disablecal_vclk_qactive_disablesamsung_usermux_enablecal_vclk_enablecal_clk_enablecal_vclk_qactive_enablekfreepreempt_schedule_notracekmem_cache_alloc_tracegs101_clock_probe__cfi_jt_endsamsung_usermux_is_enabledcal_vclk_is_enabledcal_clk_is_enabled__tracepoint_rwmmio_post_read__tracepoint_rwmmio_read__kmallocpanic__UNIQUE_ID_license399$d.199$d.99$d.189$d.89$d.179$x.79__UNIQUE_ID_alias269$d.169$x.69$d.159$x.59$d.149$d.49$d.139$x.39$x.129$x.29$d.119$x.19$x.109$x.9$d.198$x.98$d.188$x.88$d.178$d.78__UNIQUE_ID_alias268$d.168$x.68$d.158$d.58$d.148$x.48$d.138$d.38$x.128$d.28$x.118$x.18$d.108$d.8_note_7__UNIQUE_ID_license297$d.197$d.97$d.187$x.87$d.177$x.77__UNIQUE_ID_depends267$d.167$x.67$d.157$x.57$d.147$d.47$d.137$x.37$x.127$x.27$d.117$x.17$x.107$x.7$d.196$x.96$d.186$d.86$d.176$d.76__UNIQUE_ID_intree266$d.166$x.66$d.156$x.56$d.146$x.46$d.136$d.36$x.126$x.26$x.116$x.16$d.206$d.106$x.6$d.195$d.95$d.185$x.85$d.175$x.75__UNIQUE_ID_name265$d.165$x.65$d.155$d.55$d.145$d.45$d.135$x.35$x.125$x.25$d.115$d.15$d.205$x.105$x.5$d.194$x.94$d.184$d.84$d.174$d.74__UNIQUE_ID_vermagic264$d.164$x.64$d.154$x.54$d.144$x.44$d.134$d.34$x.124$x.24$x.114$x.14$d.204$d.104$x.4$d.4$d.193$d.93$d.183$x.83$d.173$x.73$d.163$x.63$d.153$d.53$d.143$d.43$d.133$x.33$x.123$x.23$d.213$d.113$x.13$d.203$x.103$x.3$d.3$d.192$x.92$d.182$d.82$d.172$x.72$d.162$d.62$d.152$x.52$d.142$x.42$d.132$d.32$x.122$x.22$d.212$x.112$d.12$d.202$x.102$x.2$d.2$d.191$d.91$d.181$x.81$d.171$x.71$d.161$x.61$d.151$d.51$d.141$x.41$d.131$x.31$x.121$x.21$x.111$x.11$d.201$d.101$x.1$d.1$d.190$x.90$d.180$d.80__UNIQUE_ID_scmversion270$d.170$x.70$d.160$d.60$d.150$x.50$d.140$d.40$x.130$d.30$x.120$x.20$d.110$d.10$d.200$x.100d@0p9a`+Y2.h  PX!4`q/aqbq@HP4@x_@@8cq>@&0Lohrr@@0uw ,$( Qx'?PgI