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A'/8*(R7)wS*R+RJ *k *,2)2-R!!!!:@* *I *A *?@RCщ*?@R**?@RZAqT2ZZC2ZZE2ZZG2ZȎH2ȎȎJ2Ȏ ȎL2uZZCuZZEuZZGuZȎHu ȎȎJu Ȏ ȎLu Ȏ ]^v@R@@ @( @?\Rb h@?h@q5*7@ HRr@:@?տ?} jRJ r}f :[dRG * h&W?;h*W??h.W?Ch@qThV? hJW?_A?z9AyNu2@2@2h@q`T cN? gN?kN?J6)6 668[R \-R Z-R 3@-R /@-R  +@R ('@R 0#@R h@R@q( @?Vu?h:J?DOh>J?@Sh:L?DOh>L?@Sh:N?DOh>N?@Sh:P?DOh>P?@Sh@qaT  ЀR*ihj-3*i( aT7*)R9R]7N)R(3 R@@@@?ըHNu2H(/C?(7[}R{q@0T R(/C?H6R?IS2rR*? U?U?U ?U ?UK@k?3KT(A@y *( R?ըNu2/C?(7Y}R9q+T R/C?H6?R*? U?U?U ?U ?UK@k?3KTA@y *h@qT RȦNiji8](*Ȧ@7@qaT@R@ qj2B9mR @@k@@,Cu *, R?i RRi_q) @_ q+ 3 @T?qT? ' @**R@@?`4q!TR@*6R@x7*Rrt) HRr(R)D) iR*O I@4 ,9!r(Q9))a9  RJ@?[Ri)h@qT(@*R C)y [4(@;R*R C)2 [* <5h@qTqRIR#** @{ O@ @>@>?h@ R !?`@?h @)R !@(5,?qHRR @?`@h"@i@ kTh?`"@h@ qTp?`@h&@i@ kTh?`&@?`@?h@ R !@aRh@ )Bq?s`TӇOB? @{èkb4*@q(R $A) (@)( @ q  H )RT @j +R`!ʚ(!Ț4?qT___QiqT ) h_qTH|S)D@?q DT_(@xJ@pH5*H*@JMSJ@QJ*(RJ @i! !) *kR) *l3LRI @JQJ!+RI *l3I @J%QJ! RI *l3I @_ qJ!KRI *l3I @%J!) *lSI @%Rk!l3i *I @kQkk!i *IxS @,m@k k Sk!k *k @L4J2K@lR!k, K+l@!( h@L@Q! *H@j@  S!  *k@%Q!h*2h_{?$q#TR @Tr*R  kѿ?՟K!˚?ik@? kTk@?Ջ4!Q? qT? qT **{_ @K ?j +RJ??j!ʚRTrKI@?? kT)@?i4IRiR* _(x qaT(R;(Qq(T @? qT@) @ @J L  )QQ?iqT)R )R*R%?uqbTIR?}qiR)5 k)R)% q#T @I )IQ?eqT*%q*?qqT*)q?yqT*-q*1q(R %? k(*_{4qcT @RTr*R) ) + kѿ?՟K!˚?hk@?kTk@?Ջ4cQ0qT0qT8&**{_ @L @? lR) * RTr?Պ!ʚIk@?5J@?_ kaT*)R* _{O@ q!T***4j @ *)i@h @i4  k@Rh@R q5qcTl@J +RJ RTrM ?խ?m!͚i i`?խ]R jT @?տ jTQ1qTRh*OA{¨_{ O@@*@5@)qT @R?,1`T @*?,1`TOB @{è_{WO@H@94@@5@)qT @R?,1`Ts @*?,1`Tt@95OBWA{è_{@5@@!@?@5*{_*_֨R @+@*A))}@ !j*Iii? 76 @*R?1 @ A)?}@I!Ri)?i( @ @ A)?}@I!jRi)KR*i( @ A) @}@@?i!)(i- @ @ A)?}@I!i)*i(@T_ @hR+@*A))}@ !j*Iii? @L@-2KA)?)yJ}@ !+,mi* @KJ@?Li+,R @M@KA)?J}@!,<S+li* @L@KA)?J}@!( i*_ֈR(qHrT @?/6?IRR* @?/6?HR_@94RJRIrR)qT,@?/6?K,@?/6?H@9H5_{ OR*Ur,qCTRrh~c*HR *q!T@?/6?HR)R* @?/6hIR?(OB @{è_{ RSrh@?76hRR?jR?hKR,R?i?j ?l??h @{¨_{ Oh@H<qTT*OB @{è_֠{#OT`J@! *`!8J@*`!`J@"R` #* 1T1`TL1 T@n<qT1T5#@1HT`h@5J@!*`4qRR*(hOE{C#@_֠{ *P @inS@I   @*{¨_{C @R+@*A))}@!h(ii?h7@ @ @ii?{_{ *+ @RL@KA)J}@)!))ij?i(7@ *j @ @?*i( @{¨_{ * @Rr+@*A))}@!h(ii? @ }SZ{¨_{ *i?qqTi? qaT`A k-lR* @iYi @ A)?}@!*Ii( @{¨_{ * @ @i @iB9 @iJ9 @iF9@h @{¨_Ԍ?܌G܌֌ߌߌߌߌߌߌߌߌ+888+ 8ߌ+ 8+ 888888+88888$ڌHٌH4H4Hnvidia,tegra20-emcnvidia,tegra20-emc-tablenvidia,tegra20-nandnvidia,tegra124-xusb-padctlnvidia,tegra210-xusb-padctlsamsung,exynos-usb-physamsung,exynos5250-usb3-physamsung,exynos-tmusamsung,exynos-mipi-dsisamsung,exynos-dwmmcjedec,spi-norsamsung,sysmmu-v3.3intel,microcodeintel,quark-mrcaltr,socfpga-stmmacaltr,socfpga-dw-mshcsnps,dwc2intel,baytrail-fspintel,baytrail-fsp-mdpintel,ivybridge-fspallwinner,sun4i-a10-nandaltr,clk-mgrpinctrl-singlealtr,socfpga-hps2fpga-bridgealtr,socfpga-lwhps2fpga-bridgealtr,socfpga-fpga2hps-bridgealtr,socfpga-fpga2sdram0-bridgealtr,socfpga-fpga2sdram1-bridgealtr,socfpga-fpga2sdram2-bridgealtr,socfpga-a10-fpga-mgraltr,socfpga-a10-nocaltr,socfpga-a10-clk-initranges### ERROR ### Please RESET the board ### #clock-cellsclock-namesassigned-clock-parentsassigned-clocksassigned-clock-ratesfixed_clockfixed_rate_raw_clockfixed-clockfixed_factor_clockfixed-factor-clockclock-divclock-multrockchip_rk3399_crurockchip_rk3399_pmucrurockchip,rk3399-crurockchip_sysresetdo not support this i2c bus %s: SPI clk-id %ld not supported rk3399_spi_get_clk%s: internal clock is UNIMPLEMENTED rk3399_gmac_set_clkrk3399_spi_set_clk%s: the frequency can't be 0 Hz pll_para_config%s: Cannot find out a supported VCO for Frequency (%uHz). %s: Failed to match output frequency %u, difference is %u Hz,exceed 4MHZ Unsupported SDRAM frequency!,%ld clock-output-namesclkin_gmacrockchip,rk3399-pmucrureg-names/clocks/firmwareroot_driverrootnopsimple_bussimple-bussimple-mfdlittle-endianbig-endiannative-endianmiscrockchip_efuserockchip,rk3399-efuseno sysreset resetting ... ramrockchip_rk3399_dmc%s: Unable to support LPDDR4 MR22 Soc ODT set_ds_odtrockchip,rk3399-dmc%s clk get failed %d rk3399_dmc_init%s clk set failed %d %s DRAM init failed %d %s: pctl timeout! read_mr%s: read mr failed with 0x%x status %s: change freq to %dMHz %d, %d lpddr4_set_ratelpddr4_set_ctl%s: channel %d training failed! Channel 1: 0: Cap error! no ddrconfig find, Cap not support! %s: sdram_init - %dMHz failed! %s: Failed to init pctl channel 0 pctl_start%s: Failed to init pctl channel 1 16bit error!!! full training error!!! rockchip,sdram-params%s: Cannot read rockchip,sdram-params %d rk3399_dmc_of_to_plat%s: regmap failed %d LPDDR2LPDDR3LPDDR4Unknown Device, MHz Col= Bk= BG= CS0 Row=/ CS1 Row= CS= Die BW= Size=MB 128B stride 512B stride 4K stride 32MB + 256B stride no stride col error row errorNo serial driver foundstdout-pathconsolereg-offsetreg-shiftreg-io-widthns16550_serialns16550ns16550aingenic,jz4780-uartnvidia,tegra20-uartsnps,dw-apb-uartKM@QRTT[\Q܌vrr)F#rr  @s7rr މ?r    b%L   b%L  85  qj@'dP   1"    m `   d   4h(      7n @@ 0Pv    P(ddP    $c111MMMMMM $c111MMMMMM @ @ @2(       (V U UU31 32   @y PP vv   v0P@ vP ?#2+ h( 4 ( ZZUUZZUUZZUUZZUU      d ee    JK41MM$1MM 1MM1MM$1MM 1MM1MM$1MM 1MM1MM$1MM 1MM d     ."    l  vP @y2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @  @@**3 3 A ??UB @@**3 3UB @@**3 3jUB@UPd"     "@@DDDDDDDDd  r&L "$"!L/  85  qj@'dP   1"    m `   d   4h(      7n @@ 0Pv    P(ddP    $c111MMMMMM $c111MMMMMM @ @ @2(       (V U UU31 32   @y PP vv   v0P@ vP ?#2+ h( 4 ( ZZUUZZUUZZUUZZUU      d ee    JK41MM$1MM 1MM1MM$1MM 1MM1MM$1MM 1MM1MM$1MM 1MM d     ."    l  vP @y2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @ 2TvUUfUUff0  @ RQ1QP1B @  @@**3 3 A ??UB @@**3 3UB @@**3 3jUB@UPd"     "@@DDDDDDDDdٌȌH00ȌٌȌ9ڌ ʌIHJOwhz axiahbdclkokayvop@ff900000rockchip,rk3399-vop-bigK>Ovhz axiahbdclkokaypinctrlrockchip,rk3399-pinctrl chosenserial2:1500000n8/mmc@fe320000/mmc@fe330000syscon@ff620000rockchip,rk3399-cicsysconKbLdfi@ff630000Kc@rockchip,rk3399-dfihydmcrockchip,rk3399-dmcOhK @ $ $"!"L $"!"L2  8 5 qj@'dP   "1   m `   d    H (     7n @@ P0v   Pd(dP   $c111MMMMMM $c111MMMMMM @  @@2(       (V UUU 133 2  y@P P v v    v0P@v P ?+2#  (H ( UUZZUUZZUUZZUUZZ      dee    KJ41MM$M1M1 MMM1$M1MM M1M1MM$M1M1 MMM1$M1MM M1M d     ".   l  vP y@vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ @ @ܺܺ**3 3 A ??U B@ @**3 3U B@ @**3 3jU B@UPd "      "@@DDDDDDDDdNsyscon@ff330000rockchip,rk3399-pmusgrfsysconK3O compatible#address-cells#size-cellsmodelserial0serial2mmc0mmc1spi1reginterruptsmax-frequencyclocksfifo-depthpower-domainsresetsreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpu-boot,spl-fifo-modephandlearasan,soc-ctl-sysconclock-output-names#clock-cellsphysphy-namesdisable-cqe-dcmdmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removablereg-shiftreg-io-widthdmasdma-namesrockchip,grf#reset-cells#phy-cellsiommusrockchip,pmurangesstdout-pathu-boot,spl-boot-orderdevfreq-eventsrockchip,sdram-params  M@@cAB8? lTTT> @_ <!{@@DբXAB8? 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R@ R r?թ@ 2* ?* @ @)@? @)-@)kii?J@?@_1qK3 i)_{ `@ @ @{¨  @{¨_{ `@ @ @{¨  @*{¨_{WOh@*6@ RVq}@y?տ? @2H}y?@ 5R? @I9Ti@)%@?!q R(?ժRi@R( yR?i@(yy)NqaT R7h@}@y?ը06Qr *T87 !!*?iRh@Or 5?h@9OEWD{B@_{ `@@ @{¨  @`A{¨_C{_WOCH@A@m@74&5е6r|@7 6_h67_1T(@5m@*tq*Z6*ODWC_B{AC_֠{_WOH@ !!* 7"B@R5J@S@ }qkT*4n56hF@c` R Z 5@ @@ @QqAT@5@5@?  @@@kT*OGWF_E{D_#D@@9h4 R*24 R*`5@@5@9@?@ @5@)2 5@I_*_@ @()@4)@ `@9)+_8 kT+_8kT)1T_(@H(@9(@9h9_@ @(9@4)@ `@9+)Rm_8 kTm_8kTm_8k@TJk1_' AT*h@hh@ _k*)7 *HEZ) 7*ySiR) *)EZHEZ? quSן uSR   Rq)} *=SI% ן@uS)  KR H9i_ |@ JI yhkT7!AT_*_* )(( y`?kTaT_{og_WOC @J@!!Pm@'@7 }Sq'iTqcT?q) D@)k ZKETAq#TR3U@)YA)@~qI @k  5~qT @q}j'H(@7`'q @)@@T 77(!@h **? 5* 7*cS*( @91!@49C?CT3( @(7@?qT@" Z"@@ R9q(T)@`' )R)!jR? j@T @)@)%@** ?@4 %qT9qT@@-@@@)@h*?7**6'@*Z@R}_(T*COEWD_CgBoA{ƨ_`A@ {OC**n~qLT@~@jq RJ@L}+! k,k@7K7 R~ RR",L}C R*! @J imJ!@7m K+ 7*ySmR!OB{A_*kl n mkEZEZ qןkuSuSR  Rqk} l=S% ןuSk  KRk R 9(!)m@%Ӛ6#*x @5_@9@% { O "Bc R*5@. `"Bc R5@#` @H 4 ,C)$M$]$o$$$$$$$$%%#%4%G%Z%k%..6 t{88888hl8,,4| 87:.= Q h   "7/7=7J7Y7o7 ~77^3v3C/|5h5P0l     +29AIMQYhl44ﾭﾭﾭﾭﾭ 22@'@B #(-27 %d__of_translate_addressmalloc_simple: %lx bytes used, %lx remain alloc space exhausted linux,phandleFDT_ERR_NOTFOUNDFDT_ERR_EXISTSFDT_ERR_NOSPACEFDT_ERR_BADOFFSETFDT_ERR_BADPATHFDT_ERR_BADPHANDLEFDT_ERR_BADSTATEFDT_ERR_TRUNCATEDFDT_ERR_BADMAGICFDT_ERR_BADVERSIONFDT_ERR_BADSTRUCTUREFDT_ERR_BADLAYOUTFDT_ERR_INTERNALFDT_ERR_BADNCELLSFDT_ERR_BADVALUEFDT_ERR_BADOVERLAYFDT_ERR_NOPHANDLESFDT_ERR_BADFLAGSFDT_ERR_ALIGNMENTpciVVVV,DDDDpcibus-range%.*s%dMissing DTB hback-porchhfront-porchhactivehsync-lenvback-porchvfront-porchvactivevsync-lenclock-frequencyvsync-activehsync-activede-activepixelclk-activeinterlaceddoublescandoubleclk/memory/reserved-memory%s@%x,%x%s@%xno-mapmatch-maskmatch-valueauto-sizeseparateboardembedenvnvidia,tegra20-emcnvidia,tegra20-emc-tablenvidia,tegra20-nandnvidia,tegra124-xusb-padctlnvidia,tegra210-xusb-padctlsamsung,exynos-usb-physamsung,exynos5250-usb3-physamsung,exynos-tmusamsung,exynos-mipi-dsisamsung,exynos-dwmmcjedec,spi-norsamsung,sysmmu-v3.3intel,microcodeintel,quark-mrcaltr,socfpga-stmmacaltr,socfpga-dw-mshcsnps,dwc2intel,baytrail-fspintel,baytrail-fsp-mdpintel,ivybridge-fspallwinner,sun4i-a10-nandaltr,clk-mgrpinctrl-singlealtr,socfpga-hps2fpga-bridgealtr,socfpga-lwhps2fpga-bridgealtr,socfpga-fpga2hps-bridgealtr,socfpga-fpga2sdram0-bridgealtr,socfpga-fpga2sdram1-bridgealtr,socfpga-fpga2sdram2-bridgealtr,socfpga-a10-fpga-mgraltr,socfpga-a10-nocaltr,socfpga-a10-clk-init### ERROR ### Please RESET the board ### %s:%dblk_partition%s: failed writing '%s' (1 blks at 0x0) write_mbr_sectorMBRDOSFATFAT32Part Start LBA End LBA Name Attributes Type GUID Partition GUID %3d 0x%08llx 0x%08llx "%s" attrs: 0x%016llx type: %pUl guid: %pUl More partitions than allowed! Partition name: %s does not match %s! Partition %s size: %llu does not match %llu! Partition %s start: %llu does not match %llu! EFIu-boot,efi-partition-entries-offset(none) IDE device %d: Device %d: unknown device %s.%sscsiusbsatahostnvmeefiloadervirtiopvblock#clock-cellsclock-namesassigned-clock-parentsassigned-clocksassigned-clock-ratesfixed_clockfixed_rate_raw_clockfixed-clockfixed_factor_clockfixed-factor-clockclock-divclock-multrockchip_rk3399_crurockchip_rk3399_pmucrurockchip,rk3399-crurockchip_sysresetdo not support this i2c bus %s: SPI clk-id %ld not supported rk3399_spi_get_clk%s: internal clock is UNIMPLEMENTED rk3399_gmac_set_clkrk3399_spi_set_clk%s: the frequency can't be 0 Hz pll_para_config%s: Cannot find out a supported VCO for Frequency (%uHz). %s: Failed to match output frequency %u, difference is %u Hz,exceed 4MHZ Unsupported SDRAM frequency!,%ld clock-output-namesclkin_gmacrockchip,rk3399-pmucrureg-names/clocks/firmwareroot_driverrootnopsimple_bussimple-bussimple-mfdlittle-endianbig-endiannative-endianmiscrockchip_efuserockchip,rk3399-efuseno sysreset resetting ... MMC legacyMMC High Speed (26MHz)SD High Speed (50MHz)MMC High Speed (52MHz)MMC DDR52 (52MHz)UHS SDR12 (25MHz)UHS SDR25 (50MHz)UHS SDR50 (100MHz)UHS DDR50 (50MHz)UHS SDR104 (208MHz)HS200 (200MHz)HS400 (200MHz)HS400ES (200MHz)Unknown modeStatus Error: 0x%08x Timeout waiting card ready MMC: block number 0x%lx exceeds max(0x%lx) Card did not respond to voltage select! : %d MMC: no card present mmc fail to send stop cmd unable to select a mode No ext_csd found! Select HS400 failed %d Select HS400ES failed %d unable to select a mode : %d %s - probe failed: %d bus-width%s %s: Invalid "bus-width" value %u! (NULLudevice *)max-frequencycap-sd-highspeedcap-mmc-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104sd-uhs-ddr50mmc-ddr-1_8vmmc-ddr-1_2vmmc-hs200-1_8vmmc-hs200-1_2vmmc-hs400-1_8vmmc-hs400-1_2vmmc-hs400-enhanced-strobenon-removablecd-invertedbroken-cdno-1-8-vMMC Device %d not found %ceMMC%s: %d (%s)mmc_blkrockchip_rk3288_dw_mshcrockchip,rk2928-dw-mshcrockchip,rk3288-dw-mshcfifo-depthu-boot,spl-fifo-modeclock-freq-min-max%s: Timeout to wait cmd & data inhibit sdhci_set_clock%s: Error while setting tap delay %s: Internal clock never stabilised. sdhci-caps-masksdhci-caps%s: Hardware doesn't specify base clock frequency sdhci_setup_cfg%s: Aligned buffer alloc failed!!! sdhci_init%s: Reset 0x%x never completed. sdhci_reset%s: MMC: %d busy sdhci_send_commandtimeout increasing to: %u ms. %s: Timeout for status update! %s: Transfer data timeout sdhci_transfer_datarockchip_sdhci_5_1arasan,sdhci-5.1rockchip,rk3568-dwcmshcphys%s Get syscon grf failedrk3399_emmc_get_phy%s: caldone timeout. rk3399_emmc_phy_power_on%s clk set rate fail! rockchip_sdhci_probe%s fail to get clk %s:Tuning failed rockchip_sdhci_execute_tuningpinconfiggpio-controllergpio-rangespinctrl-namespinctrl-%d%s %s: could not find pctldev rockchip,grfrockchip,pmurockchip,pinsbias-disablebias-bus-holdbias-pull-upbias-pull-downbias-pull-pin-defaultdrive-strengthinput-schmitt-disableinput-schmitt-enablerockchip_rk3399_pinctrlrockchip,rk3399-pinctrlgpio0gpio1gpio2gpio3gpio4rockchip_rk3399_dmcrockchip,rk3399-dmcNo serial driver foundstdout-pathconsolereg-offsetreg-shiftreg-io-widthns16550_serialns16550ns16550aingenic,jz4780-uartnvidia,tegra20-uartsnps,dw-apb-uart f|gkdlnvv.؜d(d;p=l 7 7 7 7 7   @@@5Ch H)M,(34l8c (6S7Tpxp4/B(DHF3Cxx @,eee:..d0/ lp,nX:i+pX'*W B3T]Y- b//BpC.G)M6S87TZ.t8cL.d6 l-nМ *8(d(:(,-radxa,rockpi4bradxa,rockpi4rockchip,rk3399 &Radxa ROCK Pi 4Baliases,/serial@ff1800004/serial@ff1a0000Owhz axiahbdclkokayvop@ff900000rockchip,rk3399-vop-bigK>Ovhz axiahbdclkokaypinctrlrockchip,rk3399-pinctrl chosenserial2:1500000n8/mmc@fe320000/mmc@fe330000syscon@ff620000rockchip,rk3399-cicsysconKbLdfi@ff630000Kc@rockchip,rk3399-dfihydmcrockchip,rk3399-dmcOhK @ $ $"!"L $"!"L2  8 5 qj@'dP   "1   m `   d    H (     7n @@ P0v   Pd(dP   $c111MMMMMM $c111MMMMMM @  @@2(       (V UUU 133 2  y@P P v v    v0P@v P ?+2#  (H ( UUZZUUZZUUZZUUZZ      dee    KJ41MM$M1M1 MMM1$M1MM M1M1MM$M1M1 MMM1$M1MM M1M d     ".   l  vP y@vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ vT2YfUUfUUf0  @ YQ1QR1P B @ @ @ܺܺ**3 3 A ??U B@ @**3 3U B@ @**3 3jU B@UPd "      "@@DDDDDDDDdNsyscon@ff330000rockchip,rk3399-pmusgrfsysconK3O compatible#address-cells#size-cellsmodelserial0serial2mmc0mmc1spi1reginterruptsmax-frequencyclocksfifo-depthpower-domainsresetsreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wpu-boot,spl-fifo-modephandlearasan,soc-ctl-sysconclock-output-names#clock-cellsphysphy-namesdisable-cqe-dcmdmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removablereg-shiftreg-io-widthdmasdma-namesrockchip,grf#reset-cells#phy-cellsiommusrockchip,pmurangesstdout-pathu-boot,spl-boot-orderdevfreq-eventsrockchip,sdram-params