ELF3@@*(FFFFFF""""""FFFG G Nw  2(3(4(5(6(7(8(9(deo,^{Z]&'`()*^+,-_./@1F2G3H4I5JXYZ][Y\Z^[_\uzy{vx~ !LMLMN ~:;mnopqrl.kxy~z{|}~stf-jhigl0~6, 7- 8* 9. :/ C-;=$!}"NOq;< =!>"?/@5A6B70; 1: 2< 36 47 58 64 99 A B C = @ D E    MUX_APM_FUNCGATE_DFTMUX_CMU_CIS_CLK2GATE_DFTMUX_CMU_CIS_CLK5UMUX_CLKCMU_NOCL2AA_NOCUMUX_CLKCMU_G2D_JPEGGATE_PCIE_GEN3A_1_PCS_APBUMUX_CLKCMU_RGBP_MCFPzuma_clock0x%08llx 3error writing to pad_clkout0 err=%lu 3Failed to register clock %s GATE_PCIE_GEN3A_1_APBGATE_PCIE_GEN3B_1_DBGGATE_PCIE_GEN3B_1_AXIUMUX_MIF_DDRPHY2XDOUT_CLK_DPUF0_NOCPMUX_NOCL1B_NOC_OPTION1UMUX_CLKCMU_DPUF1_NOCMUX_HSI0_USB32DRDUMUX_CLKCMU_HSI1_NOCGATE_UFS_EMBDUMUX_CLKCMU_YUVPGATE_PERIC1_TOP0_USI15_USIDOUT_CLK_NOCL1B_NOCPCLKOUT0UMUX_CLKCMU_EH_NOCGATE_MMC_CARDGATE_WDT_CL1GATE_PERIC0_TOP0_USI4_USIDOUT_CLK_APM_BOOSTVDOUT_CLK_PERIC0_USI0_UARTVDOUT_CLK_PERIC1_USI13_USIVDOUT_CLK_PERIC1_USI15_USI%s: failed to map registers 6ZUMA: Clock setup completed 3[CAL] vclk enable failed %d %d GATE_PDMA1UMUX_CLKCMU_PERIC0_NOCDOUT_CLK_G2D_NOCPVDOUT_CLK_HSI0_USI3_USIzuma_clock_probeGATE_DFTMUX_CMU_CIS_CLK6UMUX_CLKCMU_NOCL1B_NOCUMUX_CLKCMU_NOCL2AB_NOCGATE_HSI0_USI2_USIUMUX_CLKCMU_TNR_MERGEUMUX_CLKCMU_GDC_GDC0DOUT_CLK_APM_USI0_USIVDOUT_CLK_HSI0_USI2_USIVDOUT_CLK_TOP_HSI0_NOCDOUT_CLK_RGBP_NOCPDOUT_CLK_GDC_NOCPVDOUT_CLK_PERIC1_USI0_USIGATE_HSI0_USI0_USIGATE_PERIC0_TOP0_USI2_USIclock-frequency3Failed to disable clock %s UMUX_CLKCMU_HSI0_TCXOMUX_HSI0_USB20_REFUMUX_CLKCMU_HSI0_ALTMUX_HSI0_NOCUMUX_CLKCMU_TPU_TPUVDOUT_CLK_HSI0_USI0_USIVDOUT_CLK_HSI0_USI4_USIVDOUT_CLK_PERIC1_USI9_USI3[CAL] Failed to set vclk rate %d %lu %d GATE_DFTMUX_CMU_CIS_CLK1UMUX_CLKCMU_RGBP_RGBPUMUX_CLKCMU_TNR_ALIGN0x%16llx UMUX_CLKCMU_HSI2_NOCUMUX_CLKCMU_MCSCMUX_TPU_TPUDOUT_CLK_DPUB_NOCPVDOUT_CLK_PERIC0_USI4_USIUMUX_CLKCMU_HSI0_NOCGATE_HSI0_USI1_USIGATE_PCIE_GEN3A_1_AXIDOUT_CLK_GSE_NOCPDOUT_CLK_MFC_NOCP3Failed to allocate for gate_clk fin_pllGATE_MFCGATE_PERIC0_TOP0_USI5_USIGATE_PERIC0_TOP0_USI6_USIUMUX_CLKCMU_HSI0_DPOSC_USERDOUT_CLK_MCSC_NOCPCIS_CLK1CIS_CLK7VDOUT_CLK_PERIC0_USI14_USIVDOUT_CLK_PERIC1_USI10_USIDOUT_CLK_TPU_NOCPcould not register clk provider GATE_HSI0_USI3_USIGATE_PERIC0_TOP0_USI1_USIDOUT_CLK_NOCL2AB_NOCPinclude/trace/events/power.hUMUX_CLKCMU_HSI2_PCIEGATE_PCIE_GEN3B_1_APBUMUX_CLKCMU_MFC_MFCUMUX_CLKCMU_MISC_SCVDOUT_CLK_PERIC0_USI3_USIpwm-clockpad_clkout0pad_clkout1clkout_addr3Failed to enable clock %s 3Failed to allocate vclk struct UMUX_CLKCMU_NOCL1_NOCGATE_PCIE_GEN3_0_PMA_APBGATE_PCIE_GEN3A_1_PMA_APBGATE_PCIE_GEN3B_1_PCS_APBUMUX_CLKCMU_TPU_NOCDOUT_CLK_TPU_TPUcould not allocate clock lookup table &ctx->lock3Failed to get clk by register offset GATE_DFTMUX_CMU_CIS_CLK0UMUX_CLKCMU_DPUF0_NOCUMUX_CLKCMU_HSI1_PCIEGATE_PCIE_GEN3_0_APBGATE_PCIE_GEN3_0_PCS_APBUMUX_CLKCMU_GSEDOUT_CLK_MISC_NOCPGATE_PERIC1_TOP0_USI9_USIDOUT_CLK_EH_NOCPDOUT_CLK_DPUF1_NOCPCIS_CLK0GATE_G2DGATE_JPEGGATE_PCIE_GEN3_0_AXIGATE_PCIE_GEN3A_1_DBGDOUT_CLK_NOCL2AA_NOCPDOUT_CLKCMU_HSI2_MMC_CARDUMUX_CLKCMU_G2D_G2DUMUX_CLKCMU_HSI0_USB32DRDUMUX_CLKCMU_HSI2_UFS_EMBDGATE_UFS_EMBD_FMPUMUX_CLKCMU_GDC_LMEGATE_MCTVDOUT_CLK_HSI0_USI1_USI3Failed to register lookup %s GATE_DPUBGATE_USB32DRD_LINKGATE_PDMA0DOUT_CLK_HSI0_USB32DRDVDOUT_CLK_PERIC1_USI11_USIDOUT_CLK_BW_NOCPxclkoutcould not allocate clock provider context. 3[CAL] vclk disable failed %d %d GATE_DFTMUX_CMU_CIS_CLK7UMUX_CLKCMU_PERIC0_USI0_UARTCLKOUT1GATE_DFTMUX_CMU_CIS_CLK3UMUX_CLKCMU_NOCL0_NOCCIS_CLK5VDOUT_CLK_PERIC0_USI5_USI3error writing to pad_clkout1 err=%lu UMUX_CLKCMU_HSI0_USB20GATE_PERIC1_TOP0_USI12_USICIS_CLK2CIS_CLK3VDOUT_CLK_PERIC1_USI12_USIGATE_PERIC0_TOP0_USI14_USIMUX_TPU_TPUCTLDOUT_CLK_ISPFE_NOCP3Failed to register clock lookup for %sGATE_PCIE_GEN3_0_UDBGUMUX_CLKCMU_TPU_TPUCTLCIS_CLK4VDOUT_CLK_PERIC0_USI6_USI%s: unable to allocate context. clkout_valUMUX_CLKCMU_HSI2_MMC_CARDUMUX_CLKCMU_ISPFEGATE_PERIC0_TOP0_USI3_USIGATE_PERIC0_TOP1_USI0_UARTGATE_PERIC1_TOP0_USI10_USIDOUT_CLK_APM_USI0_UARTVDOUT_CLK_PERIC0_USI2_USIGATE_DFTMUX_CMU_CIS_CLK4GATE_GPUGATE_PCIE_GEN3B_1_PMA_APBDOUT_CLK_NOCL1A_NOCP3error address not found 3Failed to register virtual clock %s lockMUX_APM_FUNCSRCDOUT_CLK_TNR_NOCPVDOUT_CLK_PERIC0_USI1_USI%s: unable to determine soc 3can not alloc for gate clock list UMUX_CLKCMU_MISC_NOCGATE_WDT_CL0GATE_PERIC1_TOP0_USI13_USI3can not alloc for enable gate clock list 3[CAL] Failed to set vclk dfs %d %lu %d 3[CAL] Failed to set vclk dfs rate switch UMUX_CLKCMU_DPUB_NOCUMUX_CLKCMU_HSI0_DPGTCUMUX_CLKCMU_PERIC1_NOCGATE_PERIC1_TOP0_USI11_USIUMUX_CLKCMU_BW_NOCCIS_CLK6DOUT_CLK_TPU_TPUCTL3could not allocate usermux clk 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.note.gnu.property.note.Linux.rela.exit.text.rela.init.text.hyp.text.comment.init.plt.hyp.bss.rela.rodata.samsung_usermux_ops.rela.altinstructions__versions.modinfo.rela.text.__cfi_check_fail.rela.data.lock.note.GNU-stack.llvm_addrsig.text.ftrace_trampoline.rela.gnu.linkonce.this_module.rela__jump_table.rela__bug_table.note.gnu.build-id.shstrtab.strtab.symtab.hyp.rodata.rela.exit.data.rela.init.data.hyp.datasamsung_clk_init.__keyof_property_read_variable_u32_arraysamsung_register_usermux__clk_get_hwclk_register_clkdevsamsung_register_of_fixed_extgate_clk_listsamsung_add_clk_gate_list__ubsan_handle_cfi_check_fail_abortclk_hw_get_parentclkout_addr_set.cfi_jtclkout_val_set.cfi_jtpad_clkout1_set.cfi_jtpad_clkout0_set.cfi_jtclkout_addr_get.cfi_jtof_clk_src_onecell_get.cfi_jtclkout_val_get.cfi_jtpad_clkout1_get.cfi_jtpad_clkout0_get.cfi_jtclkout_addr_fops_open.cfi_jtclkout_val_fops_open.cfi_jtpad_clkout1_fops_open.cfi_jtpad_clkout0_fops_open.cfi_jtno_llseek.cfi_jtcal_vclk_dfs_set_rate_switch.cfi_jtdebugfs_attr_write.cfi_jtcal_vclk_dfs_set_rate.cfi_jtcal_vclk_set_rate.cfi_jtcal_vclk_round_rate.cfi_jtcal_vclk_dfs_sw_recalc_rate.cfi_jtcal_vclk_dfs_recalc_rate.cfi_jtcal_vclk_recalc_rate.cfi_jtcal_vclk_gate_recalc_rate.cfi_jtsimple_attr_release.cfi_jtinit_module.cfi_jtcleanup_module.cfi_jtsamsung_usermux_disable.cfi_jtcal_vclk_disable.cfi_jtcal_vclk_qactive_disable.cfi_jtsamsung_usermux_enable.cfi_jtcal_vclk_enable.cfi_jtcal_vclk_qactive_enable.cfi_jtzuma_clock_probe.cfi_jtsamsung_usermux_is_enabled.cfi_jtcal_vclk_is_enabled.cfi_jtdebugfs_attr_read.cfi_jtsamsung_clk_init__raw_spin_lock_initcal_qch_initclkout_addr_setclkout_val_setpad_clkout1_setpad_clkout0_setclkout_addr_getof_clk_src_onecell_getclkout_val_getpad_clkout1_getpad_clkout0_getclkout_addr_fopsclkout_val_fopspad_clkout1_fopspad_clkout0_fopssamsung_usermux_opssamsung_vclk_dfs_sw_opssamsung_vclk_dfs_opssamsung_vclk_opssamsung_vclk_qactive_opssamsung_vclk_gate_ops____versionszuma_bw_vclkszuma_tpu_vclkszuma_clkout_vclkszuma_tnr_vclkszuma_yuvp_vclkszuma_top_vclkszuma_rgbp_vclkszuma_apm_vclkszuma_eh_vclkszuma_bw_hwacg_vclkszuma_tpu_hwacg_vclkszuma_tnr_hwacg_vclkszuma_yuvp_hwacg_vclkszuma_top_hwacg_vclkszuma_rgbp_hwacg_vclkszuma_apm_hwacg_vclkszuma_eh_hwacg_vclkszuma_dpuf_hwacg_vclkszuma_mif_hwacg_vclkszuma_gse_hwacg_vclkszuma_ispfe_hwacg_vclkszuma_g3d_hwacg_vclkszuma_g2d_hwacg_vclkszuma_misc_hwacg_vclkszuma_mcsc_hwacg_vclkszuma_mfc_hwacg_vclkszuma_gdc_hwacg_vclkszuma_dpub_hwacg_vclkszuma_nocl1b_hwacg_vclkszuma_nocl2a_hwacg_vclkszuma_nocl1a_hwacg_vclkszuma_hsi2_hwacg_vclkszuma_hsi1_hwacg_vclkszuma_peric1_hwacg_vclkszuma_nocl0_hwacg_vclkszuma_hsi0_hwacg_vclkszuma_peric0_hwacg_vclkszuma_dpuf_vclkszuma_gse_vclkszuma_ispfe_vclkszuma_g2d_vclkszuma_misc_vclkszuma_mcsc_vclkszuma_mfc_vclkszuma_gdc_vclkszuma_dpub_vclkszuma_nocl1b_vclkszuma_nocl2a_vclkszuma_nocl1a_vclkszuma_hsi2_vclkszuma_peric1_vclkszuma_hsi0_vclkszuma_peric0_vclkszuma_fixed_rate_ext_clksarm64_use_ng_mappingsclkout_addresseskmalloc_cachesexynos_clock_idsclk_register_fixed_factorsamsung_register_fixed_factorgate_clk_nrdebugfs_create_dirzuma_clock_driverplatform_driver_unregister__platform_driver_registerclk_registerzuma_clk_providerof_clk_add_providersamsung_clk_of_add_providercpu_numbersamsung_clk_alloc_reg_dumpof_iomapiounmap__ioremapclkout_addr_fops_openclkout_val_fops_openpad_clkout1_fops_openpad_clkout0_fops_opensimple_attr_open__stack_chk_fail__cfi_check_fail_printk__cpu_online_masksamsung_register_vclkno_llseeklock__cfi_checkcal_dfs_set_rate_switchcal_vclk_dfs_set_rate_switchext_clk_matchof_exynos_clock_matchof_find_matching_node_and_matchrcu_is_watchingsamsung_clk_get_by_reg_raw_spin_lock_irqsavesamsung_clk_savedebugfs_attr_writecal_clk_setratecal_clk_getratecal_dfs_set_ratecal_vclk_dfs_set_ratecal_vclk_set_rate__tracepoint_clock_set_rate__traceiter_clock_set_ratecal_dfs_get_ratecal_dfs_cached_get_ratecal_vclk_round_rateclk_register_fixed_ratesamsung_register_fixed_ratecal_vclk_dfs_sw_recalc_ratecal_vclk_dfs_recalc_ratecal_vclk_recalc_ratecal_vclk_gate_recalc_rateclk_register_gatesamsung_register_gatesimple_attr_release_raw_spin_unlock_irqrestoresamsung_clk_restoreclk_unprepareclk_prepareclk_hw_get_name__clk_get_name__cfi_jt_init_module__this_module__cfi_jt_cleanup_moduledebugfs_create_file__mod_of__of_exynos_clock_match_device_tablesamsung_usermux_disablecal_vclk_disablecal_clk_disablecal_vclk_qactive_disablesamsung_usermux_enablecal_vclk_enablecal_clk_enablecal_vclk_qactive_enablekfreepreempt_schedule_notracekmem_cache_alloc_tracezuma_clock_probesamsung_usermux_is_enabledcal_vclk_is_enabledcal_clk_is_enableddebugfs_attr_read__kmalloc__arm_smccc_smcpanic_note_9$x.99$d.189$x.89$d.179$x.79$d.169$x.69$d.159$x.59$d.149$d.49__UNIQUE_ID_license439$d.139$x.39$d.129$x.29$d.119$x.19$x.109$x.9_note_8$d.198$x.98$d.188$x.88$d.178$d.78$d.168$d.68$d.158$d.58$d.148$x.48$d.138$x.38$d.128$d.28$d.118$d.18$x.108$x.8$d.8$d.197$x.97$d.187$x.87$d.177$x.77$d.167$x.67$d.157$x.57$d.147$d.47$d.137$x.37$d.127$x.27$d.117$x.17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