// Copyright 2020 The ChromiumOS Authors
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

// This list of MSRs comes from HAXM here:
// https://github.com/intel/haxm/blob/v7.6.1/core/include/ia32_defs.h#L99

pub const IA32_P5_MC_ADDR: u32 = 0x0;
pub const IA32_P5_MC_TYPE: u32 = 0x1;
pub const IA32_TSC: u32 = 0x10;
pub const IA32_PLATFORM_ID: u32 = 0x17;
pub const IA32_APIC_BASE: u32 = 0x1b;
pub const IA32_EBC_HARD_POWERON: u32 = 0x2a;
pub const IA32_EBC_SOFT_POWERON: u32 = 0x2b;
pub const IA32_EBC_FREQUENCY_ID: u32 = 0x2c;
pub const IA32_FEATURE_CONTROL: u32 = 0x3a;
pub const IA32_THERM_DIODE_OFFSET: u32 = 0x3f;
pub const IA32_BIOS_UPDT_TRIG: u32 = 0x79;
pub const IA32_BIOS_SIGN_ID: u32 = 0x8b;
pub const IA32_SMM_MONITOR_CTL: u32 = 0x9b;
pub const IA32_PMC0: u32 = 0xc1;
pub const IA32_PMC1: u32 = 0xc2;
pub const IA32_PMC2: u32 = 0xc3;
pub const IA32_PMC3: u32 = 0xc4;
pub const IA32_FSB_FREQ: u32 = 0xcd;
pub const IA32_MPERF: u32 = 0xe7;
pub const IA32_APERF: u32 = 0xe8;
pub const IA32_TEMP_TARGET: u32 = 0xee;
pub const IA32_MTRRCAP: u32 = 0xfe;
pub const IA32_BBL_CR_CTL3: u32 = 0x11e;
pub const IA32_SYSENTER_CS: u32 = 0x174;
pub const IA32_SYSENTER_ESP: u32 = 0x175;
pub const IA32_SYSENTER_EIP: u32 = 0x176;
pub const IA32_MCG_CAP: u32 = 0x179;
pub const IA32_MCG_STATUS: u32 = 0x17a;
pub const IA32_MCG_CTL: u32 = 0x17b;
pub const IA32_PERFEVTSEL0: u32 = 0x186;
pub const IA32_PERFEVTSEL1: u32 = 0x187;
pub const IA32_PERFEVTSEL2: u32 = 0x188;
pub const IA32_PERFEVTSEL3: u32 = 0x189;
pub const IA32_PERF_CTL: u32 = 0x199;
pub const IA32_MISC_ENABLE: u32 = 0x1a0;
pub const IA32_DEBUGCTL: u32 = 0x1d9;
pub const IA32_MTRR_PHYSBASE0: u32 = 0x200;
pub const IA32_MTRR_PHYSMASK0: u32 = 0x201;
pub const IA32_MTRR_PHYSBASE1: u32 = 0x202;
pub const IA32_MTRR_PHYSMASK1: u32 = 0x203;
pub const IA32_MTRR_PHYSBASE2: u32 = 0x204;
pub const IA32_MTRR_PHYSMASK2: u32 = 0x205;
pub const IA32_MTRR_PHYSBASE3: u32 = 0x206;
pub const IA32_MTRR_PHYSMASK3: u32 = 0x207;
pub const IA32_MTRR_PHYSBASE4: u32 = 0x208;
pub const IA32_MTRR_PHYSMASK4: u32 = 0x209;
pub const IA32_MTRR_PHYSBASE5: u32 = 0x20a;
pub const IA32_MTRR_PHYSMASK5: u32 = 0x20b;
pub const IA32_MTRR_PHYSBASE6: u32 = 0x20c;
pub const IA32_MTRR_PHYSMASK6: u32 = 0x20d;
pub const IA32_MTRR_PHYSBASE7: u32 = 0x20e;
pub const IA32_MTRR_PHYSMASK7: u32 = 0x20f;
pub const IA32_MTRR_PHYSBASE8: u32 = 0x210;
pub const IA32_MTRR_PHYSMASK8: u32 = 0x211;
pub const IA32_MTRR_PHYSBASE9: u32 = 0x212;
pub const IA32_MTRR_PHYSMASK9: u32 = 0x213;
pub const MTRRFIX64K_00000: u32 = 0x250;
pub const MTRRFIX16K_80000: u32 = 0x258;
pub const MTRRFIX16K_A0000: u32 = 0x259;
pub const MTRRFIX4K_C0000: u32 = 0x268;
pub const MTRRFIX4K_F8000: u32 = 0x26f;
pub const IA32_CR_PAT: u32 = 0x277;
pub const IA32_MC0_CTL2: u32 = 0x280;
pub const IA32_MC1_CTL2: u32 = 0x281;
pub const IA32_MC2_CTL2: u32 = 0x282;
pub const IA32_MC3_CTL2: u32 = 0x283;
pub const IA32_MC4_CTL2: u32 = 0x284;
pub const IA32_MC5_CTL2: u32 = 0x285;
pub const IA32_MC6_CTL2: u32 = 0x286;
pub const IA32_MC7_CTL2: u32 = 0x287;
pub const IA32_MC8_CTL2: u32 = 0x288;
pub const IA32_MTRR_DEF_TYPE: u32 = 0x2ff;
pub const MSR_BPU_COUNTER0: u32 = 0x300;
pub const IA32_FIXED_CTR0: u32 = 0x309;
pub const IA32_FIXED_CTR1: u32 = 0x30a;
pub const IA32_FIXED_CTR2: u32 = 0x30b;
pub const IA32_PERF_CAPABILITIES: u32 = 0x345;
pub const MSR_PEBS_MATRIX_VERT: u32 = 0x3f2;
pub const IA32_FIXED_CTR_CTRL: u32 = 0x38d;
pub const IA32_PERF_GLOBAL_STATUS: u32 = 0x38e;
pub const IA32_PERF_GLOBAL_CTRL: u32 = 0x38f;
pub const IA32_PERF_GLOBAL_OVF_CTRL: u32 = 0x390;
pub const IA32_MC0_CTL: u32 = 0x400;
pub const IA32_MC0_STATUS: u32 = 0x401;
pub const IA32_MC0_ADDR: u32 = 0x402;
pub const IA32_MC0_MISC: u32 = 0x403;
pub const IA32_CPUID_FEATURE_MASK: u32 = 0x478;
pub const IA32_VMX_BASIC: u32 = 0x480;
pub const IA32_VMX_PINBASED_CTLS: u32 = 0x481;
pub const IA32_VMX_PROCBASED_CTLS: u32 = 0x482;
pub const IA32_VMX_EXIT_CTLS: u32 = 0x483;
pub const IA32_VMX_ENTRY_CTLS: u32 = 0x484;
pub const IA32_VMX_MISC: u32 = 0x485;
pub const IA32_VMX_CR0_FIXED0: u32 = 0x486;
pub const IA32_VMX_CR0_FIXED1: u32 = 0x487;
pub const IA32_VMX_CR4_FIXED0: u32 = 0x488;
pub const IA32_VMX_CR4_FIXED1: u32 = 0x489;
pub const IA32_VMX_VMCS_ENUM: u32 = 0x48a;
pub const IA32_VMX_SECONDARY_CTLS: u32 = 0x48b;
pub const IA32_VMX_EPT_VPID_CAP: u32 = 0x48c;
pub const IA32_VMX_TRUE_PINBASED_CTLS: u32 = 0x48d;
pub const IA32_VMX_TRUE_PROCBASED_CTLS: u32 = 0x48e;
pub const IA32_VMX_TRUE_EXIT_CTLS: u32 = 0x48f;
pub const IA32_VMX_TRUE_ENTRY_CTLS: u32 = 0x490;
pub const IA32_EFER: u32 = 0xc0000080;
pub const IA32_STAR: u32 = 0xc0000081;
pub const IA32_LSTAR: u32 = 0xc0000082;
pub const IA32_CSTAR: u32 = 0xc0000083;
pub const IA32_SF_MASK: u32 = 0xc0000084;
pub const IA32_FS_BASE: u32 = 0xc0000100;
pub const IA32_GS_BASE: u32 = 0xc0000101;
pub const IA32_KERNEL_GS_BASE: u32 = 0xc0000102;
pub const IA32_TSC_AUX: u32 = 0xc0000103;