1 /* 2 * Copyright (c) 2020-2022 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_EXPERIMENTAL_TYPES_H 25 #define ARM_COMPUTE_EXPERIMENTAL_TYPES_H 26 27 #include "arm_compute/core/ITensorPack.h" 28 #include "arm_compute/core/TensorShape.h" 29 30 #include <vector> 31 32 namespace arm_compute 33 { 34 // Forward declaration 35 class ITensor; 36 37 /** Memory type */ 38 enum TensorType : int32_t 39 { 40 ACL_UNKNOWN = -1, 41 ACL_SRC_DST = 0, 42 43 // Src 44 ACL_SRC = 0, 45 ACL_SRC_0 = 0, 46 ACL_SRC_1 = 1, 47 ACL_SRC_2 = 2, 48 ACL_SRC_3 = 3, 49 ACL_SRC_4 = 4, 50 ACL_SRC_5 = 5, 51 ACL_SRC_6 = 6, 52 ACL_SRC_END = 6, 53 54 // Dst 55 ACL_DST = 30, 56 ACL_DST_0 = 30, 57 ACL_DST_1 = 31, 58 ACL_DST_2 = 32, 59 ACL_DST_END = 32, 60 61 // Aux 62 ACL_INT = 50, 63 ACL_INT_0 = 50, 64 ACL_INT_1 = 51, 65 ACL_INT_2 = 52, 66 ACL_INT_3 = 53, 67 ACL_INT_4 = 54, 68 ACL_SRC_VEC = 256, 69 ACL_DST_VEC = 512, 70 ACL_INT_VEC = 1024, 71 72 // Aliasing Types 73 // Conv etc 74 ACL_BIAS = ACL_SRC_2, 75 76 // Gemm 77 ACL_VEC_ROW_SUM = ACL_SRC_3, 78 ACL_VEC_COL_SUM = ACL_SRC_4, 79 ACL_SHIFTS = ACL_SRC_5, 80 ACL_MULTIPLIERS = ACL_SRC_6, 81 82 // (EXPERIMENTAL_POST_OPS) Post ops arguments begin after everything else 83 EXPERIMENTAL_ACL_POST_OP_ARG = 2048, 84 EXPERIMENTAL_ACL_POST_OP_ARG_FIRST = EXPERIMENTAL_ACL_POST_OP_ARG, 85 EXPERIMENTAL_ACL_POST_OP_ARG_LAST = EXPERIMENTAL_ACL_POST_OP_ARG_FIRST + 1024, // Max number of post op arguments 86 }; 87 88 namespace experimental 89 { 90 enum class MemoryLifetime 91 { 92 Temporary = 0, 93 Persistent = 1, 94 Prepare = 2, 95 }; 96 struct MemoryInfo 97 { 98 MemoryInfo() = default; 99 100 MemoryInfo(int slot, size_t size, size_t alignment = 0) noexcept slotMemoryInfo101 : slot(slot), 102 size(size), 103 alignment(alignment) 104 { 105 } 106 107 MemoryInfo(int slot, MemoryLifetime lifetime, size_t size, size_t alignment = 0) noexcept slotMemoryInfo108 : slot(slot), 109 lifetime(lifetime), 110 size(size), 111 alignment(alignment) 112 { 113 } 114 115 bool merge(int slot, size_t new_size, size_t new_alignment = 0) noexcept 116 { 117 if(slot != this->slot) 118 { 119 return false; 120 } 121 122 size = std::max(size, new_size); 123 alignment = std::max(alignment, new_alignment); 124 125 return true; 126 } 127 128 int slot{ ACL_UNKNOWN }; 129 MemoryLifetime lifetime{ MemoryLifetime::Temporary }; 130 size_t size{ 0 }; 131 size_t alignment{ 64 }; 132 }; 133 134 using MemoryRequirements = std::vector<MemoryInfo>; 135 } // namespace experimental 136 } // namespace arm_compute 137 #endif /* ARM_COMPUTE_EXPERIMENTAL_TYPES_H */ 138