1 // Copyright 2020 The ChromiumOS Authors 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 // These cpuid bit definitions come from HAXM here: 6 // https://github.com/intel/haxm/blob/v7.6.1/core/include/cpuid.h#L97 7 8 use bitflags::bitflags; 9 feature_bit(bit: u32) -> u3210const fn feature_bit(bit: u32) -> u32 { 11 1 << bit 12 } 13 14 /* 15 * Intel SDM Vol. 2A: Table 3-10. 16 * Feature Information Returned in the ECX Register 17 * Features for CPUID with EAX=01h stored in ECX 18 */ 19 bitflags! { 20 pub struct Feature1Ecx: u32 { 21 const SSE3 = feature_bit(0); /* 0x00000001 Streaming SIMD Extensions 3 */ 22 const PCLMULQDQ = feature_bit(1); /* 0x00000002 PCLMULQDQ Instruction */ 23 const DTES64 = feature_bit(2); /* 0x00000004 64-bit DS Area */ 24 const MONITOR = feature_bit(3); /* 0x00000008 MONITOR/MWAIT Instructions */ 25 const DS_CPL = feature_bit(4); /* 0x00000010 CPL Qualified Debug Store */ 26 const VMX = feature_bit(5); /* 0x00000020 Virtual Machine Extensions */ 27 const SMX = feature_bit(6); /* 0x00000040 Safer Mode Extensions */ 28 const EIST = feature_bit(7); /* 0x00000080 Enhanced Intel SpeedStep technology */ 29 const TM2 = feature_bit(8); /* 0x00000100 Thermal Monitor 2 */ 30 const SSSE3 = feature_bit(9); /* 0x00000200 Supplemental Streaming SIMD Extensions 3 */ 31 const CNXT_ID = feature_bit(10); /* 0x00000400 L1 Context ID */ 32 const SDBG = feature_bit(11); /* 0x00000800 Silicon Debug Interface */ 33 const FMA = feature_bit(12); /* 0x00001000 Fused Multiply-Add */ 34 const CMPXCHG16B = feature_bit(13); /* 0x00002000 CMPXCHG16B Instruction */ 35 const XTPR_UPDATE = feature_bit(14); /* 0x00004000 xTPR Update Control */ 36 const PDCM = feature_bit(15); /* 0x00008000 Perfmon and Debug Capability */ 37 const PCID = feature_bit(17); /* 0x00020000 Process-context identifiers */ 38 const DCA = feature_bit(18); /* 0x00040000 Direct cache access for DMA writes */ 39 const SSE41 = feature_bit(19); /* 0x00080000 Streaming SIMD Extensions 4.1 */ 40 const SSE42 = feature_bit(20); /* 0x00100000 Streaming SIMD Extensions 4.2 */ 41 const X2APIC = feature_bit(21); /* 0x00200000 x2APIC support */ 42 const MOVBE = feature_bit(22); /* 0x00400000 MOVBE Instruction */ 43 const POPCNT = feature_bit(23); /* 0x00800000 POPCNT Instruction */ 44 const TSC_DEADLINE = feature_bit(24); /* 0x01000000 APIC supports one-shot operation using TSC deadline */ 45 const AESNI = feature_bit(25); /* 0x02000000 AESNI Extension */ 46 const XSAVE = feature_bit(26); /* 0x04000000 XSAVE/XRSTOR/XSETBV/XGETBV Instructions and XCR0 */ 47 const OSXSAVE = feature_bit(27); /* 0x08000000 XSAVE enabled by OS */ 48 const AVX = feature_bit(28); /* 0x10000000 Advanced Vector Extensions */ 49 const F16C = feature_bit(29); /* 0x20000000 16-bit Floating-Point Instructions */ 50 const RDRAND = feature_bit(30); /* 0x40000000 RDRAND Instruction */ 51 const HYPERVISOR = feature_bit(31); /* 0x80000000 Hypervisor Running */ 52 } 53 } 54 55 /* 56 * Intel SDM Vol. 2A: Table 3-11. 57 * More on Feature Information Returned in the EDX Register 58 * Features for CPUID with EAX=01h stored in EDX 59 */ 60 bitflags! { 61 pub struct Feature1Edx: u32 { 62 const FPU = feature_bit(0); /* 0x00000001 Floating Point Unit On-Chip */ 63 const VME = feature_bit(1); /* 0x00000002 Virtual 8086 Mode Enhancements */ 64 const DE = feature_bit(2); /* 0x00000004 Debugging Extensions */ 65 const PSE = feature_bit(3); /* 0x00000008 Page Size Extension */ 66 const TSC = feature_bit(4); /* 0x00000010 Time Stamp Counter */ 67 const MSR = feature_bit(5); /* 0x00000020 RDMSR/WRMSR Instructions */ 68 const PAE = feature_bit(6); /* 0x00000040 Physical Address Extension */ 69 const MCE = feature_bit(7); /* 0x00000080 Machine Check Exception */ 70 const CX8 = feature_bit(8); /* 0x00000100 CMPXCHG8B Instruction */ 71 const APIC = feature_bit(9); /* 0x00000200 APIC On-Chip */ 72 const SEP = feature_bit(11); /* 0x00000800 SYSENTER/SYSEXIT Instructions */ 73 const MTRR = feature_bit(12); /* 0x00001000 Memory Type Range Registers */ 74 const PGE = feature_bit(13); /* 0x00002000 Page Global Bit */ 75 const MCA = feature_bit(14); /* 0x00004000 Machine Check Architecture */ 76 const CMOV = feature_bit(15); /* 0x00008000 Conditional Move Instructions */ 77 const PAT = feature_bit(16); /* 0x00010000 Page Attribute Table */ 78 const PSE36 = feature_bit(17); /* 0x00020000 36-Bit Page Size Extension */ 79 const PSN = feature_bit(18); /* 0x00040000 Processor Serial Number */ 80 const CLFSH = feature_bit(19); /* 0x00080000 CLFLUSH Instruction */ 81 const DS = feature_bit(21); /* 0x00200000 Debug Store */ 82 const ACPI = feature_bit(22); /* 0x00400000 Thermal Monitor and Software Controlled Clock Facilities */ 83 const MMX = feature_bit(23); /* 0x00800000 Intel MMX Technology */ 84 const FXSR = feature_bit(24); /* 0x01000000 FXSAVE and FXRSTOR Instructions */ 85 const SSE = feature_bit(25); /* 0x02000000 Streaming SIMD Extensions */ 86 const SSE2 = feature_bit(26); /* 0x04000000 Streaming SIMD Extensions 2 */ 87 const SS = feature_bit(27); /* 0x08000000 Self Snoop */ 88 const HTT = feature_bit(28); /* 0x10000000 Max APIC IDs reserved field is Valid */ 89 const TM = feature_bit(29); /* 0x20000000 Thermal Monitor */ 90 const PBE = feature_bit(31); /* 0x80000000 Pending Break Enable */ 91 } 92 } 93 /* 94 * Intel SDM Vol. 2A: Table 3-8. Information Returned by CPUID Instruction 95 * Extended Function CPUID Information 96 * Features for CPUID with EAX=80000001h stored in ECX 97 */ 98 bitflags! { 99 pub struct Feature80000001Ecx: u32 { 100 const LAHF = feature_bit(0); /* 0x00000001 LAHF/SAHF Instructions */ 101 const ABM = feature_bit(5); /* 0x00000020 Advanced bit manipulation (lzcnt and popcnt) */ 102 const PREFETCHW = feature_bit(8); /* 0x00000100 PREFETCH/PREFETCHW instructions */ 103 } 104 } 105 106 /* 107 * Intel SDM Vol. 2A: Table 3-8. Information Returned by CPUID Instruction 108 * Extended Function CPUID Information 109 * Features for CPUID with EAX=80000001h stored in EDX 110 */ 111 bitflags! { 112 pub struct Feature80000001Edx: u32 { 113 const SYSCALL = feature_bit(11); /* 0x00000800 SYSCALL/SYSRET Instructions */ 114 const NX = feature_bit(20); /* 0x00100000 No-Execute Bit */ 115 const PDPE1GB = feature_bit(26); /* 0x04000000 Gibibyte pages */ 116 const RDTSCP = feature_bit(27); /* 0x08000000 RDTSCP Instruction */ 117 const EM64T = feature_bit(29); /* 0x20000000 Long Mode */ 118 } 119 } 120