1 /* 2 * Copyright (c) 2019, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CLOCKMANAGER_H 8 #define CLOCKMANAGER_H 9 10 #include "socfpga_handoff.h" 11 12 /* Clock Manager Registers */ 13 #define CLKMGR_OFFSET 0xffd10000 14 15 #define CLKMGR_CTRL 0x0 16 #define CLKMGR_STAT 0x4 17 #define CLKMGR_INTRCLR 0x14 18 19 /* Main PLL Group */ 20 #define CLKMGR_MAINPLL 0xffd10024 21 #define CLKMGR_MAINPLL_EN 0x0 22 #define CLKMGR_MAINPLL_BYPASS 0xc 23 #define CLKMGR_MAINPLL_MPUCLK 0x18 24 #define CLKMGR_MAINPLL_NOCCLK 0x1c 25 #define CLKMGR_MAINPLL_NOCDIV 0x20 26 #define CLKMGR_MAINPLL_PLLGLOB 0x24 27 #define CLKMGR_MAINPLL_FDBCK 0x28 28 #define CLKMGR_MAINPLL_MEM 0x2c 29 #define CLKMGR_MAINPLL_MEMSTAT 0x30 30 #define CLKMGR_MAINPLL_PLLC0 0x34 31 #define CLKMGR_MAINPLL_PLLC1 0x38 32 #define CLKMGR_MAINPLL_VCOCALIB 0x3c 33 #define CLKMGR_MAINPLL_PLLC2 0x40 34 #define CLKMGR_MAINPLL_PLLC3 0x44 35 #define CLKMGR_MAINPLL_PLLM 0x48 36 #define CLKMGR_MAINPLL_LOSTLOCK 0x54 37 38 /* Peripheral PLL Group */ 39 #define CLKMGR_PERPLL 0xffd1007c 40 #define CLKMGR_PERPLL_EN 0x0 41 #define CLKMGR_PERPLL_BYPASS 0xc 42 #define CLKMGR_PERPLL_EMACCTL 0x18 43 #define CLKMGR_PERPLL_GPIODIV 0x1c 44 #define CLKMGR_PERPLL_PLLGLOB 0x20 45 #define CLKMGR_PERPLL_FDBCK 0x24 46 #define CLKMGR_PERPLL_MEM 0x28 47 #define CLKMGR_PERPLL_MEMSTAT 0x2c 48 #define CLKMGR_PERPLL_PLLC0 0x30 49 #define CLKMGR_PERPLL_PLLC1 0x34 50 #define CLKMGR_PERPLL_VCOCALIB 0x38 51 #define CLKMGR_PERPLL_PLLC2 0x3c 52 #define CLKMGR_PERPLL_PLLC3 0x40 53 #define CLKMGR_PERPLL_PLLM 0x44 54 #define CLKMGR_PERPLL_LOSTLOCK 0x50 55 56 /* Altera Group */ 57 #define CLKMGR_ALTERA 0xffd100d0 58 #define CLKMGR_ALTERA_JTAG 0x0 59 #define CLKMGR_ALTERA_EMACACTR 0x4 60 #define CLKMGR_ALTERA_EMACBCTR 0x8 61 #define CLKMGR_ALTERA_EMACPTPCTR 0xc 62 #define CLKMGR_ALTERA_GPIODBCTR 0x10 63 #define CLKMGR_ALTERA_SDMMCCTR 0x14 64 #define CLKMGR_ALTERA_S2FUSER0CTR 0x18 65 #define CLKMGR_ALTERA_S2FUSER1CTR 0x1c 66 #define CLKMGR_ALTERA_PSIREFCTR 0x20 67 #define CLKMGR_ALTERA_EXTCNTRST 0x24 68 69 /* Membus */ 70 #define CLKMGR_MEM_REQ BIT(24) 71 #define CLKMGR_MEM_WR BIT(25) 72 #define CLKMGR_MEM_ERR BIT(26) 73 #define CLKMGR_MEM_WDAT_OFFSET 16 74 #define CLKMGR_MEM_ADDR 0x4027 75 #define CLKMGR_MEM_WDAT 0x80 76 77 /* Clock Manager Macros */ 78 #define CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001 79 #define CLKMGR_STAT_BUSY_E_BUSY 0x1 80 #define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) 81 #define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) 82 #define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16) 83 #define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004 84 #define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008 85 #define CLKMGR_INTOSC_HZ 460000000 86 87 /* Main PLL Macros */ 88 #define CLKMGR_MAINPLL_EN_RESET 0x000000ff 89 90 /* Peripheral PLL Macros */ 91 #define CLKMGR_PERPLL_EN_RESET 0x00000fff 92 #define CLKMGR_PERPLL_EN_SDMMCCLK BIT(5) 93 #define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) 94 95 /* Altera Macros */ 96 #define CLKMGR_ALTERA_EXTCNTRST_RESET 0xff 97 98 /* Shared Macros */ 99 #define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) 100 #define CLKMGR_PSRC_MAIN 0 101 #define CLKMGR_PSRC_PER 1 102 103 #define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0 104 #define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1 105 #define CLKMGR_PLLGLOB_PSRC_F2S 0x2 106 107 #define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff) 108 #define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001 109 #define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002 110 111 #define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) 112 #define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) 113 #define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) 114 115 #define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) 116 #define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00ff0000) 117 118 #define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000 119 120 typedef struct { 121 uint32_t clk_freq_of_eosc1; 122 uint32_t clk_freq_of_f2h_free; 123 uint32_t clk_freq_of_cb_intosc_ls; 124 } CLOCK_SOURCE_CONFIG; 125 126 void config_clkmgr_handoff(handoff *hoff_ptr); 127 uint32_t get_wdt_clk(void); 128 uint32_t get_uart_clk(void); 129 uint32_t get_mmc_clk(void); 130 131 #endif 132