• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /**
2   ******************************************************************************
3   * @file    stm32l4a6xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS STM32L4A6xx Device Peripheral Access Layer Header File.
6   *
7   *          This file contains:
8   *           - Data structures and the address mapping for all peripherals
9   *           - Peripheral's registers declarations and bits definition
10   *           - Macros to access peripheral�s registers hardware
11   *
12   ******************************************************************************
13   * @attention
14   *
15   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16   *
17   * Redistribution and use in source and binary forms, with or without modification,
18   * are permitted provided that the following conditions are met:
19   *   1. Redistributions of source code must retain the above copyright notice,
20   *      this list of conditions and the following disclaimer.
21   *   2. Redistributions in binary form must reproduce the above copyright notice,
22   *      this list of conditions and the following disclaimer in the documentation
23   *      and/or other materials provided with the distribution.
24   *   3. Neither the name of STMicroelectronics nor the names of its contributors
25   *      may be used to endorse or promote products derived from this software
26   *      without specific prior written permission.
27   *
28   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38   *
39   ******************************************************************************
40   */
41 
42 /** @addtogroup CMSIS_Device
43   * @{
44   */
45 
46 /** @addtogroup stm32l4a6xx
47   * @{
48   */
49 
50 #ifndef __STM32L4A6xx_H
51 #define __STM32L4A6xx_H
52 
53 #ifdef __cplusplus
54  extern "C" {
55 #endif /* __cplusplus */
56 
57 /** @addtogroup Configuration_section_for_CMSIS
58   * @{
59   */
60 
61 /**
62   * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63    */
64 #define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
65 #define __MPU_PRESENT             1       /*!< STM32L4XX provides an MPU                     */
66 #define __NVIC_PRIO_BITS          4       /*!< STM32L4XX uses 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
68 #define __FPU_PRESENT             1       /*!< FPU present                                   */
69 
70 /**
71   * @}
72   */
73 
74 /** @addtogroup Peripheral_interrupt_number_definition
75   * @{
76   */
77 
78 /**
79  * @brief STM32L4XX Interrupt Number Definition, according to the selected device
80  *        in @ref Library_configuration_section
81  */
82 typedef enum
83 {
84 /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85   NonMaskableInt_IRQn         = -14,    /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
86   HardFault_IRQn              = -13,    /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
87   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
88   BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
89   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
90   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
91   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
92   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
93   SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
94 /******  STM32 specific Interrupt Numbers **********************************************************************/
95   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
96   PVD_PVM_IRQn                = 1,      /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts    */
97   TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
98   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
99   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
100   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
101   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
102   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
103   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
104   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
105   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
106   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                                   */
107   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                                   */
108   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                                   */
109   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                                   */
110   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                                   */
111   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                                   */
112   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                                   */
113   ADC1_2_IRQn                 = 18,     /*!< ADC1, ADC2 SAR global Interrupts                                  */
114   CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
115   CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
116   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
117   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
118   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
119   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break interrupt and TIM15 global interrupt                   */
120   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM16 global interrupt                  */
121   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
122   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
123   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
124   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
125   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
126   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
127   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
128   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
129   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
130   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
131   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
132   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
133   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
134   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
135   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
136   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
137   DFSDM1_FLT3_IRQn            = 42,     /*!< DFSDM1 Filter 3 global Interrupt                                  */
138   TIM8_BRK_IRQn               = 43,     /*!< TIM8 Break Interrupt                                              */
139   TIM8_UP_IRQn                = 44,     /*!< TIM8 Update Interrupt                                             */
140   TIM8_TRG_COM_IRQn           = 45,     /*!< TIM8 Trigger and Commutation Interrupt                            */
141   TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
142   ADC3_IRQn                   = 47,     /*!< ADC3 global  Interrupt                                            */
143   FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
144   SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
145   TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
146   SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
147   UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
148   UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
149   TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
150   TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
151   DMA2_Channel1_IRQn          = 56,     /*!< DMA2 Channel 1 global Interrupt                                   */
152   DMA2_Channel2_IRQn          = 57,     /*!< DMA2 Channel 2 global Interrupt                                   */
153   DMA2_Channel3_IRQn          = 58,     /*!< DMA2 Channel 3 global Interrupt                                   */
154   DMA2_Channel4_IRQn          = 59,     /*!< DMA2 Channel 4 global Interrupt                                   */
155   DMA2_Channel5_IRQn          = 60,     /*!< DMA2 Channel 5 global Interrupt                                   */
156   DFSDM1_FLT0_IRQn            = 61,     /*!< DFSDM1 Filter 0 global Interrupt                                  */
157   DFSDM1_FLT1_IRQn            = 62,     /*!< DFSDM1 Filter 1 global Interrupt                                  */
158   DFSDM1_FLT2_IRQn            = 63,     /*!< DFSDM1 Filter 2 global Interrupt                                  */
159   COMP_IRQn                   = 64,     /*!< COMP1 and COMP2 Interrupts                                        */
160   LPTIM1_IRQn                 = 65,     /*!< LP TIM1 interrupt                                                 */
161   LPTIM2_IRQn                 = 66,     /*!< LP TIM2 interrupt                                                 */
162   OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
163   DMA2_Channel6_IRQn          = 68,     /*!< DMA2 Channel 6 global interrupt                                   */
164   DMA2_Channel7_IRQn          = 69,     /*!< DMA2 Channel 7 global interrupt                                   */
165   LPUART1_IRQn                = 70,     /*!< LP UART1 interrupt                                                */
166   QUADSPI_IRQn                = 71,     /*!< Quad SPI global interrupt                                         */
167   I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
168   I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
169   SAI1_IRQn                   = 74,     /*!< Serial Audio Interface 1 global interrupt                         */
170   SAI2_IRQn                   = 75,     /*!< Serial Audio Interface 2 global interrupt                         */
171   SWPMI1_IRQn                 = 76,     /*!< Serial Wire Interface 1 global interrupt                          */
172   TSC_IRQn                    = 77,     /*!< Touch Sense Controller global interrupt                           */
173   LCD_IRQn                    = 78,     /*!< LCD global interrupt                                              */
174   AES_IRQn                    = 79,     /*!< AES global interrupt                                              */
175   HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */
176   FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
177   CRS_IRQn                    = 82,     /*!< CRS global interrupt                                              */
178   I2C4_EV_IRQn                = 83,     /*!< I2C4 Event interrupt                                              */
179   I2C4_ER_IRQn                = 84,     /*!< I2C4 Error interrupt                                              */
180   DCMI_IRQn                   = 85,     /*!< DCMI global interrupt                                             */
181   CAN2_TX_IRQn                = 86,     /*!< CAN2 TX interrupt                                                 */
182   CAN2_RX0_IRQn               = 87,     /*!< CAN2 RX0 interrupt                                                */
183   CAN2_RX1_IRQn               = 88,     /*!< CAN2 RX1 interrupt                                                */
184   CAN2_SCE_IRQn               = 89,     /*!< CAN2 SCE interrupt                                                */
185   DMA2D_IRQn                  = 90      /*!< DMA2D global interrupt                                            */
186 } IRQn_Type;
187 
188 /**
189   * @}
190   */
191 
192 #include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
193 #include "system_stm32l4xx.h"
194 #include <stdint.h>
195 
196 /** @addtogroup Peripheral_registers_structures
197   * @{
198   */
199 
200 /**
201   * @brief Analog to Digital Converter
202   */
203 
204 typedef struct
205 {
206   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
207   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
208   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
209   __IO uint32_t CFGR;         /*!< ADC configuration register 1,                  Address offset: 0x0C */
210   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
211   __IO uint32_t SMPR1;        /*!< ADC sampling time register 1,                  Address offset: 0x14 */
212   __IO uint32_t SMPR2;        /*!< ADC sampling time register 2,                  Address offset: 0x18 */
213        uint32_t RESERVED1;    /*!< Reserved,                                                      0x1C */
214   __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
215   __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
216   __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x28 */
217        uint32_t RESERVED2;    /*!< Reserved,                                                      0x2C */
218   __IO uint32_t SQR1;         /*!< ADC group regular sequencer register 1,        Address offset: 0x30 */
219   __IO uint32_t SQR2;         /*!< ADC group regular sequencer register 2,        Address offset: 0x34 */
220   __IO uint32_t SQR3;         /*!< ADC group regular sequencer register 3,        Address offset: 0x38 */
221   __IO uint32_t SQR4;         /*!< ADC group regular sequencer register 4,        Address offset: 0x3C */
222   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
223        uint32_t RESERVED3;    /*!< Reserved,                                                      0x44 */
224        uint32_t RESERVED4;    /*!< Reserved,                                                      0x48 */
225   __IO uint32_t JSQR;         /*!< ADC group injected sequencer register,         Address offset: 0x4C */
226        uint32_t RESERVED5[4]; /*!< Reserved,                                               0x50 - 0x5C */
227   __IO uint32_t OFR1;         /*!< ADC offset register 1,                         Address offset: 0x60 */
228   __IO uint32_t OFR2;         /*!< ADC offset register 2,                         Address offset: 0x64 */
229   __IO uint32_t OFR3;         /*!< ADC offset register 3,                         Address offset: 0x68 */
230   __IO uint32_t OFR4;         /*!< ADC offset register 4,                         Address offset: 0x6C */
231        uint32_t RESERVED6[4]; /*!< Reserved,                                               0x70 - 0x7C */
232   __IO uint32_t JDR1;         /*!< ADC group injected rank 1 data register,       Address offset: 0x80 */
233   __IO uint32_t JDR2;         /*!< ADC group injected rank 2 data register,       Address offset: 0x84 */
234   __IO uint32_t JDR3;         /*!< ADC group injected rank 3 data register,       Address offset: 0x88 */
235   __IO uint32_t JDR4;         /*!< ADC group injected rank 4 data register,       Address offset: 0x8C */
236        uint32_t RESERVED7[4]; /*!< Reserved,                                             0x090 - 0x09C */
237   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 1 configuration register,  Address offset: 0xA0 */
238   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 Configuration Register,  Address offset: 0xA4 */
239        uint32_t RESERVED8;    /*!< Reserved,                                                     0x0A8 */
240        uint32_t RESERVED9;    /*!< Reserved,                                                     0x0AC */
241   __IO uint32_t DIFSEL;       /*!< ADC differential mode selection register,      Address offset: 0xB0 */
242   __IO uint32_t CALFACT;      /*!< ADC calibration factors,                       Address offset: 0xB4 */
243 
244 } ADC_TypeDef;
245 
246 typedef struct
247 {
248   __IO uint32_t CSR;          /*!< ADC common status register,                    Address offset: ADC1 base address + 0x300 */
249   uint32_t      RESERVED;     /*!< Reserved,                                      Address offset: ADC1 base address + 0x304 */
250   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
251   __IO uint32_t CDR;          /*!< ADC common group regular data register         Address offset: ADC1 base address + 0x30C */
252 } ADC_Common_TypeDef;
253 
254 /**
255   * @brief DCMI
256   */
257 
258 typedef struct
259 {
260   __IO uint32_t CR;       /*!< DCMI control register,                         Address offset: 0x00 */
261   __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
262   __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
263   __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
264   __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
265   __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
266   __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
267   __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
268   __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
269   __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
270   __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
271 } DCMI_TypeDef;
272 
273 /**
274   * @brief Controller Area Network TxMailBox
275   */
276 
277 typedef struct
278 {
279   __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
280   __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
281   __IO uint32_t TDLR; /*!< CAN mailbox data low register */
282   __IO uint32_t TDHR; /*!< CAN mailbox data high register */
283 } CAN_TxMailBox_TypeDef;
284 
285 /**
286   * @brief Controller Area Network FIFOMailBox
287   */
288 
289 typedef struct
290 {
291   __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
292   __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
293   __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
294   __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
295 } CAN_FIFOMailBox_TypeDef;
296 
297 /**
298   * @brief Controller Area Network FilterRegister
299   */
300 
301 typedef struct
302 {
303   __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
304   __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
305 } CAN_FilterRegister_TypeDef;
306 
307 /**
308   * @brief Controller Area Network
309   */
310 
311 typedef struct
312 {
313   __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
314   __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
315   __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
316   __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
317   __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
318   __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
319   __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
320   __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
321   uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
322   CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
323   CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
324   uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
325   __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
326   __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
327   uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
328   __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
329   uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
330   __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
331   uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
332   __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
333   uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */
334   CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
335 } CAN_TypeDef;
336 
337 
338 /**
339   * @brief Comparator
340   */
341 
342 typedef struct
343 {
344   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
345 } COMP_TypeDef;
346 
347 typedef struct
348 {
349   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
350 } COMP_Common_TypeDef;
351 
352 /**
353   * @brief CRC calculation unit
354   */
355 
356 typedef struct
357 {
358   __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
359   __IO uint8_t  IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
360   uint8_t       RESERVED0;   /*!< Reserved,                                                    0x05 */
361   uint16_t      RESERVED1;   /*!< Reserved,                                                    0x06 */
362   __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
363   uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
364   __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
365   __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
366 } CRC_TypeDef;
367 
368 /**
369   * @brief Clock Recovery System
370   */
371 typedef struct
372 {
373 __IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
374 __IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
375 __IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
376 __IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
377 } CRS_TypeDef;
378 
379 /**
380   * @brief Digital to Analog Converter
381   */
382 
383 typedef struct
384 {
385   __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
386   __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
387   __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
388   __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
389   __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
390   __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
391   __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
392   __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
393   __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
394   __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
395   __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
396   __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
397   __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
398   __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
399   __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
400   __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
401   __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
402   __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
403   __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
404   __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
405 } DAC_TypeDef;
406 
407 /**
408   * @brief DFSDM module registers
409   */
410 typedef struct
411 {
412   __IO uint32_t FLTCR1;      /*!< DFSDM control register1,                          Address offset: 0x100 */
413   __IO uint32_t FLTCR2;      /*!< DFSDM control register2,                          Address offset: 0x104 */
414   __IO uint32_t FLTISR;      /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
415   __IO uint32_t FLTICR;      /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
416   __IO uint32_t FLTJCHGR;    /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
417   __IO uint32_t FLTFCR;      /*!< DFSDM filter control register,                    Address offset: 0x114 */
418   __IO uint32_t FLTJDATAR;   /*!< DFSDM data register for injected group,           Address offset: 0x118 */
419   __IO uint32_t FLTRDATAR;   /*!< DFSDM data register for regular group,            Address offset: 0x11C */
420   __IO uint32_t FLTAWHTR;    /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
421   __IO uint32_t FLTAWLTR;    /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
422   __IO uint32_t FLTAWSR;     /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
423   __IO uint32_t FLTAWCFR;    /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
424   __IO uint32_t FLTEXMAX;    /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
425   __IO uint32_t FLTEXMIN;    /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
426   __IO uint32_t FLTCNVTIMR;  /*!< DFSDM conversion timer,                           Address offset: 0x138 */
427 } DFSDM_Filter_TypeDef;
428 
429 /**
430   * @brief DFSDM channel configuration registers
431   */
432 typedef struct
433 {
434   __IO uint32_t CHCFGR1;     /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
435   __IO uint32_t CHCFGR2;     /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
436   __IO uint32_t CHAWSCDR;    /*!< DFSDM channel analog watchdog and
437                                   short circuit detector register,                  Address offset: 0x08 */
438   __IO uint32_t CHWDATAR;    /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
439   __IO uint32_t CHDATINR;    /*!< DFSDM channel data input register,                Address offset: 0x10 */
440 } DFSDM_Channel_TypeDef;
441 
442 /**
443   * @brief Debug MCU
444   */
445 
446 typedef struct
447 {
448   __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
449   __IO uint32_t CR;          /*!< Debug MCU configuration register,   Address offset: 0x04 */
450   __IO uint32_t APB1FZR1;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
451   __IO uint32_t APB1FZR2;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
452   __IO uint32_t APB2FZ;      /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
453 } DBGMCU_TypeDef;
454 
455 
456 /**
457   * @brief DMA Controller
458   */
459 
460 typedef struct
461 {
462   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
463   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
464   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
465   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
466 } DMA_Channel_TypeDef;
467 
468 typedef struct
469 {
470   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
471   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
472 } DMA_TypeDef;
473 
474 typedef struct
475 {
476   __IO uint32_t CSELR;       /*!< DMA channel selection register              */
477 } DMA_Request_TypeDef;
478 
479 /* Legacy define */
480 #define DMA_request_TypeDef  DMA_Request_TypeDef
481 
482 
483 /**
484   * @brief DMA2D Controller
485   */
486 
487 typedef struct
488 {
489   __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
490   __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
491   __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
492   __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
493   __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
494   __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
495   __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
496   __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
497   __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
498   __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
499   __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
500   __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
501   __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
502   __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
503   __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
504   __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
505   __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
506   __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
507   __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
508   __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
509   uint32_t      RESERVED[236]; /*!< Reserved,                                 Address offset: 0x50-0x3FF */
510   __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                    Address offset:0x400-0x7FF */
511   __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                    Address offset:0x800-0xBFF */
512 } DMA2D_TypeDef;
513 
514 /**
515   * @brief External Interrupt/Event Controller
516   */
517 
518 typedef struct
519 {
520   __IO uint32_t IMR1;        /*!< EXTI Interrupt mask register 1,             Address offset: 0x00 */
521   __IO uint32_t EMR1;        /*!< EXTI Event mask register 1,                 Address offset: 0x04 */
522   __IO uint32_t RTSR1;       /*!< EXTI Rising trigger selection register 1,   Address offset: 0x08 */
523   __IO uint32_t FTSR1;       /*!< EXTI Falling trigger selection register 1,  Address offset: 0x0C */
524   __IO uint32_t SWIER1;      /*!< EXTI Software interrupt event register 1,   Address offset: 0x10 */
525   __IO uint32_t PR1;         /*!< EXTI Pending register 1,                    Address offset: 0x14 */
526   uint32_t      RESERVED1;   /*!< Reserved, 0x18                                                   */
527   uint32_t      RESERVED2;   /*!< Reserved, 0x1C                                                   */
528   __IO uint32_t IMR2;        /*!< EXTI Interrupt mask register 2,             Address offset: 0x20 */
529   __IO uint32_t EMR2;        /*!< EXTI Event mask register 2,                 Address offset: 0x24 */
530   __IO uint32_t RTSR2;       /*!< EXTI Rising trigger selection register 2,   Address offset: 0x28 */
531   __IO uint32_t FTSR2;       /*!< EXTI Falling trigger selection register 2,  Address offset: 0x2C */
532   __IO uint32_t SWIER2;      /*!< EXTI Software interrupt event register 2,   Address offset: 0x30 */
533   __IO uint32_t PR2;         /*!< EXTI Pending register 2,                    Address offset: 0x34 */
534 } EXTI_TypeDef;
535 
536 
537 /**
538   * @brief Firewall
539   */
540 
541 typedef struct
542 {
543   __IO uint32_t CSSA;        /*!< Code Segment Start Address register,              Address offset: 0x00 */
544   __IO uint32_t CSL;         /*!< Code Segment Length register,                      Address offset: 0x04 */
545   __IO uint32_t NVDSSA;      /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
546   __IO uint32_t NVDSL;       /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
547   __IO uint32_t VDSSA ;      /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
548   __IO uint32_t VDSL ;       /*!< Volatile data Segment Length register,             Address offset: 0x14 */
549   uint32_t      RESERVED1;   /*!< Reserved1,                                         Address offset: 0x18 */
550   uint32_t      RESERVED2;   /*!< Reserved2,                                         Address offset: 0x1C */
551   __IO uint32_t CR ;         /*!< Configuration  register,                           Address offset: 0x20 */
552 } FIREWALL_TypeDef;
553 
554 
555 /**
556   * @brief FLASH Registers
557   */
558 
559 typedef struct
560 {
561   __IO uint32_t ACR;              /*!< FLASH access control register,            Address offset: 0x00 */
562   __IO uint32_t PDKEYR;           /*!< FLASH power down key register,            Address offset: 0x04 */
563   __IO uint32_t KEYR;             /*!< FLASH key register,                       Address offset: 0x08 */
564   __IO uint32_t OPTKEYR;          /*!< FLASH option key register,                Address offset: 0x0C */
565   __IO uint32_t SR;               /*!< FLASH status register,                    Address offset: 0x10 */
566   __IO uint32_t CR;               /*!< FLASH control register,                   Address offset: 0x14 */
567   __IO uint32_t ECCR;             /*!< FLASH ECC register,                       Address offset: 0x18 */
568   __IO uint32_t RESERVED1;        /*!< Reserved1,                                Address offset: 0x1C */
569   __IO uint32_t OPTR;             /*!< FLASH option register,                    Address offset: 0x20 */
570   __IO uint32_t PCROP1SR;         /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
571   __IO uint32_t PCROP1ER;         /*!< FLASH bank1 PCROP end address register,   Address offset: 0x28 */
572   __IO uint32_t WRP1AR;           /*!< FLASH bank1 WRP area A address register,  Address offset: 0x2C */
573   __IO uint32_t WRP1BR;           /*!< FLASH bank1 WRP area B address register,  Address offset: 0x30 */
574        uint32_t RESERVED2[4];     /*!< Reserved2,                           Address offset: 0x34-0x40 */
575   __IO uint32_t PCROP2SR;         /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
576   __IO uint32_t PCROP2ER;         /*!< FLASH bank2 PCROP end address register,   Address offset: 0x48 */
577   __IO uint32_t WRP2AR;           /*!< FLASH bank2 WRP area A address register,  Address offset: 0x4C */
578   __IO uint32_t WRP2BR;           /*!< FLASH bank2 WRP area B address register,  Address offset: 0x50 */
579 } FLASH_TypeDef;
580 
581 
582 /**
583   * @brief Flexible Memory Controller
584   */
585 
586 typedef struct
587 {
588   __IO uint32_t BTCR[8];     /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
589 } FMC_Bank1_TypeDef;
590 
591 /**
592   * @brief Flexible Memory Controller Bank1E
593   */
594 
595 typedef struct
596 {
597   __IO uint32_t BWTR[7];     /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
598 } FMC_Bank1E_TypeDef;
599 
600 /**
601   * @brief Flexible Memory Controller Bank3
602   */
603 
604 typedef struct
605 {
606   __IO uint32_t PCR;        /*!< NAND Flash control register,                       Address offset: 0x80 */
607   __IO uint32_t SR;         /*!< NAND Flash FIFO status and interrupt register,     Address offset: 0x84 */
608   __IO uint32_t PMEM;       /*!< NAND Flash Common memory space timing register,    Address offset: 0x88 */
609   __IO uint32_t PATT;       /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
610   uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
611   __IO uint32_t ECCR;       /*!< NAND Flash ECC result registers,                   Address offset: 0x94 */
612 } FMC_Bank3_TypeDef;
613 
614 /**
615   * @brief General Purpose I/O
616   */
617 
618 typedef struct
619 {
620   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
621   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
622   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
623   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
624   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
625   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
626   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
627   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
628   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
629   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
630 
631 } GPIO_TypeDef;
632 
633 
634 /**
635   * @brief Inter-integrated Circuit Interface
636   */
637 
638 typedef struct
639 {
640   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
641   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
642   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
643   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
644   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
645   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
646   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
647   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
648   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
649   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
650   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
651 } I2C_TypeDef;
652 
653 /**
654   * @brief Independent WATCHDOG
655   */
656 
657 typedef struct
658 {
659   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
660   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
661   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
662   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
663   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
664 } IWDG_TypeDef;
665 
666 /**
667   * @brief LCD
668   */
669 
670 typedef struct
671 {
672   __IO uint32_t CR;          /*!< LCD control register,              Address offset: 0x00 */
673   __IO uint32_t FCR;         /*!< LCD frame control register,        Address offset: 0x04 */
674   __IO uint32_t SR;          /*!< LCD status register,               Address offset: 0x08 */
675   __IO uint32_t CLR;         /*!< LCD clear register,                Address offset: 0x0C */
676   uint32_t RESERVED;         /*!< Reserved,                          Address offset: 0x10 */
677   __IO uint32_t RAM[16];     /*!< LCD display memory,           Address offset: 0x14-0x50 */
678 } LCD_TypeDef;
679 
680 /**
681   * @brief LPTIMER
682   */
683 typedef struct
684 {
685   __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
686   __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
687   __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
688   __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
689   __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
690   __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
691   __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
692   __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
693   __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
694 } LPTIM_TypeDef;
695 
696 /**
697   * @brief Operational Amplifier (OPAMP)
698   */
699 
700 typedef struct
701 {
702   __IO uint32_t CSR;         /*!< OPAMP control/status register,                     Address offset: 0x00 */
703   __IO uint32_t OTR;         /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
704   __IO uint32_t LPOTR;       /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
705 } OPAMP_TypeDef;
706 
707 typedef struct
708 {
709   __IO uint32_t CSR;         /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
710 } OPAMP_Common_TypeDef;
711 
712 /**
713   * @brief Power Control
714   */
715 
716 typedef struct
717 {
718   __IO uint32_t CR1;   /*!< PWR power control register 1,        Address offset: 0x00 */
719   __IO uint32_t CR2;   /*!< PWR power control register 2,        Address offset: 0x04 */
720   __IO uint32_t CR3;   /*!< PWR power control register 3,        Address offset: 0x08 */
721   __IO uint32_t CR4;   /*!< PWR power control register 4,        Address offset: 0x0C */
722   __IO uint32_t SR1;   /*!< PWR power status register 1,         Address offset: 0x10 */
723   __IO uint32_t SR2;   /*!< PWR power status register 2,         Address offset: 0x14 */
724   __IO uint32_t SCR;   /*!< PWR power status reset register,     Address offset: 0x18 */
725   uint32_t RESERVED;   /*!< Reserved,                            Address offset: 0x1C */
726   __IO uint32_t PUCRA; /*!< Pull_up control register of portA,   Address offset: 0x20 */
727   __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
728   __IO uint32_t PUCRB; /*!< Pull_up control register of portB,   Address offset: 0x28 */
729   __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
730   __IO uint32_t PUCRC; /*!< Pull_up control register of portC,   Address offset: 0x30 */
731   __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
732   __IO uint32_t PUCRD; /*!< Pull_up control register of portD,   Address offset: 0x38 */
733   __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
734   __IO uint32_t PUCRE; /*!< Pull_up control register of portE,   Address offset: 0x40 */
735   __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
736   __IO uint32_t PUCRF; /*!< Pull_up control register of portF,   Address offset: 0x48 */
737   __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
738   __IO uint32_t PUCRG; /*!< Pull_up control register of portG,   Address offset: 0x50 */
739   __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
740   __IO uint32_t PUCRH; /*!< Pull_up control register of portH,   Address offset: 0x58 */
741   __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
742   __IO uint32_t PUCRI; /*!< Pull_up control register of portI,   Address offset: 0x60 */
743   __IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */
744 } PWR_TypeDef;
745 
746 
747 /**
748   * @brief QUAD Serial Peripheral Interface
749   */
750 
751 typedef struct
752 {
753   __IO uint32_t CR;          /*!< QUADSPI Control register,                           Address offset: 0x00 */
754   __IO uint32_t DCR;         /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
755   __IO uint32_t SR;          /*!< QUADSPI Status register,                            Address offset: 0x08 */
756   __IO uint32_t FCR;         /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
757   __IO uint32_t DLR;         /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
758   __IO uint32_t CCR;         /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
759   __IO uint32_t AR;          /*!< QUADSPI Address register,                           Address offset: 0x18 */
760   __IO uint32_t ABR;         /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
761   __IO uint32_t DR;          /*!< QUADSPI Data register,                              Address offset: 0x20 */
762   __IO uint32_t PSMKR;       /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
763   __IO uint32_t PSMAR;       /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
764   __IO uint32_t PIR;         /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
765   __IO uint32_t LPTR;        /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
766 } QUADSPI_TypeDef;
767 
768 
769 /**
770   * @brief Reset and Clock Control
771   */
772 
773 typedef struct
774 {
775   __IO uint32_t CR;          /*!< RCC clock control register,                                              Address offset: 0x00 */
776   __IO uint32_t ICSCR;       /*!< RCC internal clock sources calibration register,                         Address offset: 0x04 */
777   __IO uint32_t CFGR;        /*!< RCC clock configuration register,                                        Address offset: 0x08 */
778   __IO uint32_t PLLCFGR;     /*!< RCC system PLL configuration register,                                   Address offset: 0x0C */
779   __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register,                                     Address offset: 0x10 */
780   __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register,                                     Address offset: 0x14 */
781   __IO uint32_t CIER;        /*!< RCC clock interrupt enable register,                                     Address offset: 0x18 */
782   __IO uint32_t CIFR;        /*!< RCC clock interrupt flag register,                                       Address offset: 0x1C */
783   __IO uint32_t CICR;        /*!< RCC clock interrupt clear register,                                      Address offset: 0x20 */
784   uint32_t      RESERVED0;   /*!< Reserved,                                                                Address offset: 0x24 */
785   __IO uint32_t AHB1RSTR;    /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x28 */
786   __IO uint32_t AHB2RSTR;    /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x2C */
787   __IO uint32_t AHB3RSTR;    /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x30 */
788   uint32_t      RESERVED1;   /*!< Reserved,                                                                Address offset: 0x34 */
789   __IO uint32_t APB1RSTR1;   /*!< RCC APB1 peripheral reset register 1,                                    Address offset: 0x38 */
790   __IO uint32_t APB1RSTR2;   /*!< RCC APB1 peripheral reset register 2,                                    Address offset: 0x3C */
791   __IO uint32_t APB2RSTR;    /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x40 */
792   uint32_t      RESERVED2;   /*!< Reserved,                                                                Address offset: 0x44 */
793   __IO uint32_t AHB1ENR;     /*!< RCC AHB1 peripheral clocks enable register,                              Address offset: 0x48 */
794   __IO uint32_t AHB2ENR;     /*!< RCC AHB2 peripheral clocks enable register,                              Address offset: 0x4C */
795   __IO uint32_t AHB3ENR;     /*!< RCC AHB3 peripheral clocks enable register,                              Address offset: 0x50 */
796   uint32_t      RESERVED3;   /*!< Reserved,                                                                Address offset: 0x54 */
797   __IO uint32_t APB1ENR1;    /*!< RCC APB1 peripheral clocks enable register 1,                            Address offset: 0x58 */
798   __IO uint32_t APB1ENR2;    /*!< RCC APB1 peripheral clocks enable register 2,                            Address offset: 0x5C */
799   __IO uint32_t APB2ENR;     /*!< RCC APB2 peripheral clocks enable register,                              Address offset: 0x60 */
800   uint32_t      RESERVED4;   /*!< Reserved,                                                                Address offset: 0x64 */
801   __IO uint32_t AHB1SMENR;   /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x68 */
802   __IO uint32_t AHB2SMENR;   /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x6C */
803   __IO uint32_t AHB3SMENR;   /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
804   uint32_t      RESERVED5;   /*!< Reserved,                                                                Address offset: 0x74 */
805   __IO uint32_t APB1SMENR1;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
806   __IO uint32_t APB1SMENR2;  /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
807   __IO uint32_t APB2SMENR;   /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
808   uint32_t      RESERVED6;   /*!< Reserved,                                                                Address offset: 0x84 */
809   __IO uint32_t CCIPR;       /*!< RCC peripherals independent clock configuration register,                Address offset: 0x88 */
810   uint32_t      RESERVED7;   /*!< Reserved,                                                                Address offset: 0x8C */
811   __IO uint32_t BDCR;        /*!< RCC backup domain control register,                                      Address offset: 0x90 */
812   __IO uint32_t CSR;         /*!< RCC clock control & status register,                                     Address offset: 0x94 */
813   __IO uint32_t CRRCR;       /*!< RCC clock recovery RC register,                                          Address offset: 0x98 */
814   __IO uint32_t CCIPR2;      /*!< RCC peripherals independent clock configuration register 2,              Address offset: 0x9C */
815 } RCC_TypeDef;
816 
817 /**
818   * @brief Real-Time Clock
819   */
820 
821 typedef struct
822 {
823   __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
824   __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
825   __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x08 */
826   __IO uint32_t ISR;         /*!< RTC initialization and status register,                    Address offset: 0x0C */
827   __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
828   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
829        uint32_t reserved;    /*!< Reserved  */
830   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x1C */
831   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x20 */
832   __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
833   __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x28 */
834   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
835   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
836   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
837   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
838   __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x3C */
839   __IO uint32_t TAMPCR;      /*!< RTC tamper configuration register,                         Address offset: 0x40 */
840   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
841   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
842   __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x4C */
843   __IO uint32_t BKP0R;       /*!< RTC backup register 0,                                     Address offset: 0x50 */
844   __IO uint32_t BKP1R;       /*!< RTC backup register 1,                                     Address offset: 0x54 */
845   __IO uint32_t BKP2R;       /*!< RTC backup register 2,                                     Address offset: 0x58 */
846   __IO uint32_t BKP3R;       /*!< RTC backup register 3,                                     Address offset: 0x5C */
847   __IO uint32_t BKP4R;       /*!< RTC backup register 4,                                     Address offset: 0x60 */
848   __IO uint32_t BKP5R;       /*!< RTC backup register 5,                                     Address offset: 0x64 */
849   __IO uint32_t BKP6R;       /*!< RTC backup register 6,                                     Address offset: 0x68 */
850   __IO uint32_t BKP7R;       /*!< RTC backup register 7,                                     Address offset: 0x6C */
851   __IO uint32_t BKP8R;       /*!< RTC backup register 8,                                     Address offset: 0x70 */
852   __IO uint32_t BKP9R;       /*!< RTC backup register 9,                                     Address offset: 0x74 */
853   __IO uint32_t BKP10R;      /*!< RTC backup register 10,                                    Address offset: 0x78 */
854   __IO uint32_t BKP11R;      /*!< RTC backup register 11,                                    Address offset: 0x7C */
855   __IO uint32_t BKP12R;      /*!< RTC backup register 12,                                    Address offset: 0x80 */
856   __IO uint32_t BKP13R;      /*!< RTC backup register 13,                                    Address offset: 0x84 */
857   __IO uint32_t BKP14R;      /*!< RTC backup register 14,                                    Address offset: 0x88 */
858   __IO uint32_t BKP15R;      /*!< RTC backup register 15,                                    Address offset: 0x8C */
859   __IO uint32_t BKP16R;      /*!< RTC backup register 16,                                    Address offset: 0x90 */
860   __IO uint32_t BKP17R;      /*!< RTC backup register 17,                                    Address offset: 0x94 */
861   __IO uint32_t BKP18R;      /*!< RTC backup register 18,                                    Address offset: 0x98 */
862   __IO uint32_t BKP19R;      /*!< RTC backup register 19,                                    Address offset: 0x9C */
863   __IO uint32_t BKP20R;      /*!< RTC backup register 20,                                    Address offset: 0xA0 */
864   __IO uint32_t BKP21R;      /*!< RTC backup register 21,                                    Address offset: 0xA4 */
865   __IO uint32_t BKP22R;      /*!< RTC backup register 22,                                    Address offset: 0xA8 */
866   __IO uint32_t BKP23R;      /*!< RTC backup register 23,                                    Address offset: 0xAC */
867   __IO uint32_t BKP24R;      /*!< RTC backup register 24,                                    Address offset: 0xB0 */
868   __IO uint32_t BKP25R;      /*!< RTC backup register 25,                                    Address offset: 0xB4 */
869   __IO uint32_t BKP26R;      /*!< RTC backup register 26,                                    Address offset: 0xB8 */
870   __IO uint32_t BKP27R;      /*!< RTC backup register 27,                                    Address offset: 0xBC */
871   __IO uint32_t BKP28R;      /*!< RTC backup register 28,                                    Address offset: 0xC0 */
872   __IO uint32_t BKP29R;      /*!< RTC backup register 29,                                    Address offset: 0xC4 */
873   __IO uint32_t BKP30R;      /*!< RTC backup register 30,                                    Address offset: 0xC8 */
874   __IO uint32_t BKP31R;      /*!< RTC backup register 31,                                    Address offset: 0xCC */
875 } RTC_TypeDef;
876 
877 
878 /**
879   * @brief Serial Audio Interface
880   */
881 
882 typedef struct
883 {
884   __IO uint32_t GCR;         /*!< SAI global configuration register,        Address offset: 0x00 */
885 } SAI_TypeDef;
886 
887 typedef struct
888 {
889   __IO uint32_t CR1;         /*!< SAI block x configuration register 1,     Address offset: 0x04 */
890   __IO uint32_t CR2;         /*!< SAI block x configuration register 2,     Address offset: 0x08 */
891   __IO uint32_t FRCR;        /*!< SAI block x frame configuration register, Address offset: 0x0C */
892   __IO uint32_t SLOTR;       /*!< SAI block x slot register,                Address offset: 0x10 */
893   __IO uint32_t IMR;         /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
894   __IO uint32_t SR;          /*!< SAI block x status register,              Address offset: 0x18 */
895   __IO uint32_t CLRFR;       /*!< SAI block x clear flag register,          Address offset: 0x1C */
896   __IO uint32_t DR;          /*!< SAI block x data register,                Address offset: 0x20 */
897 } SAI_Block_TypeDef;
898 
899 
900 /**
901   * @brief Secure digital input/output Interface
902   */
903 
904 typedef struct
905 {
906   __IO uint32_t POWER;          /*!< SDMMC power control register,    Address offset: 0x00 */
907   __IO uint32_t CLKCR;          /*!< SDMMC clock control register,    Address offset: 0x04 */
908   __IO uint32_t ARG;            /*!< SDMMC argument register,         Address offset: 0x08 */
909   __IO uint32_t CMD;            /*!< SDMMC command register,          Address offset: 0x0C */
910   __I uint32_t  RESPCMD;        /*!< SDMMC command response register, Address offset: 0x10 */
911   __I uint32_t  RESP1;          /*!< SDMMC response 1 register,       Address offset: 0x14 */
912   __I uint32_t  RESP2;          /*!< SDMMC response 2 register,       Address offset: 0x18 */
913   __I uint32_t  RESP3;          /*!< SDMMC response 3 register,       Address offset: 0x1C */
914   __I uint32_t  RESP4;          /*!< SDMMC response 4 register,       Address offset: 0x20 */
915   __IO uint32_t DTIMER;         /*!< SDMMC data timer register,       Address offset: 0x24 */
916   __IO uint32_t DLEN;           /*!< SDMMC data length register,      Address offset: 0x28 */
917   __IO uint32_t DCTRL;          /*!< SDMMC data control register,     Address offset: 0x2C */
918   __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,     Address offset: 0x30 */
919   __I uint32_t  STA;            /*!< SDMMC status register,           Address offset: 0x34 */
920   __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,  Address offset: 0x38 */
921   __IO uint32_t MASK;           /*!< SDMMC mask register,             Address offset: 0x3C */
922   uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
923   __I uint32_t  FIFOCNT;        /*!< SDMMC FIFO counter register,     Address offset: 0x48 */
924   uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
925   __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,        Address offset: 0x80 */
926 } SDMMC_TypeDef;
927 
928 
929 /**
930   * @brief Serial Peripheral Interface
931   */
932 
933 typedef struct
934 {
935   __IO uint32_t CR1;         /*!< SPI Control register 1,                              Address offset: 0x00 */
936   __IO uint32_t CR2;         /*!< SPI Control register 2,                              Address offset: 0x04 */
937   __IO uint32_t SR;          /*!< SPI Status register,                                 Address offset: 0x08 */
938   __IO uint32_t DR;          /*!< SPI data register,                                   Address offset: 0x0C */
939   __IO uint32_t CRCPR;       /*!< SPI CRC polynomial register,                         Address offset: 0x10 */
940   __IO uint32_t RXCRCR;      /*!< SPI Rx CRC register,                                 Address offset: 0x14 */
941   __IO uint32_t TXCRCR;      /*!< SPI Tx CRC register,                                 Address offset: 0x18 */
942 } SPI_TypeDef;
943 
944 
945 /**
946   * @brief Single Wire Protocol Master Interface SPWMI
947   */
948 
949 typedef struct
950 {
951   __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
952   __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
953     uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
954   __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
955   __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
956   __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
957   __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
958   __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
959   __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
960   __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
961 } SWPMI_TypeDef;
962 
963 
964 /**
965   * @brief System configuration controller
966   */
967 
968 typedef struct
969 {
970   __IO uint32_t MEMRMP;      /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
971   __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                   Address offset: 0x04      */
972   __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
973   __IO uint32_t SCSR;        /*!< SYSCFG SRAM2 control and status register,          Address offset: 0x18      */
974   __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                   Address offset: 0x1C      */
975   __IO uint32_t SWPR;        /*!< SYSCFG SRAM2 write protection register,            Address offset: 0x20      */
976   __IO uint32_t SKR;         /*!< SYSCFG SRAM2 key register,                         Address offset: 0x24      */
977   __IO uint32_t SWPR2;       /*!< SYSCFG SRAM2 write protection register 2,          Address offset: 0x28      */
978 } SYSCFG_TypeDef;
979 
980 
981 /**
982   * @brief TIM
983   */
984 
985 typedef struct
986 {
987   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
988   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
989   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
990   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
991   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
992   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
993   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
994   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
995   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
996   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
997   __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
998   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
999   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
1000   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
1001   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
1002   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
1003   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
1004   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
1005   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
1006   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
1007   __IO uint32_t OR1;         /*!< TIM option register 1,                    Address offset: 0x50 */
1008   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
1009   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
1010   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
1011   __IO uint32_t OR2;         /*!< TIM option register 2,                    Address offset: 0x60 */
1012   __IO uint32_t OR3;         /*!< TIM option register 3,                    Address offset: 0x64 */
1013 } TIM_TypeDef;
1014 
1015 
1016 /**
1017   * @brief Touch Sensing Controller (TSC)
1018   */
1019 
1020 typedef struct
1021 {
1022   __IO uint32_t CR;            /*!< TSC control register,                                     Address offset: 0x00 */
1023   __IO uint32_t IER;           /*!< TSC interrupt enable register,                            Address offset: 0x04 */
1024   __IO uint32_t ICR;           /*!< TSC interrupt clear register,                             Address offset: 0x08 */
1025   __IO uint32_t ISR;           /*!< TSC interrupt status register,                            Address offset: 0x0C */
1026   __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
1027   uint32_t      RESERVED1;     /*!< Reserved,                                                 Address offset: 0x14 */
1028   __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
1029   uint32_t      RESERVED2;     /*!< Reserved,                                                 Address offset: 0x1C */
1030   __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
1031   uint32_t      RESERVED3;     /*!< Reserved,                                                 Address offset: 0x24 */
1032   __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,                         Address offset: 0x28 */
1033   uint32_t      RESERVED4;     /*!< Reserved,                                                 Address offset: 0x2C */
1034   __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,                    Address offset: 0x30 */
1035   __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,                         Address offset: 0x34-50 */
1036 } TSC_TypeDef;
1037 
1038 /**
1039   * @brief Universal Synchronous Asynchronous Receiver Transmitter
1040   */
1041 
1042 typedef struct
1043 {
1044   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00 */
1045   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04 */
1046   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08 */
1047   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C */
1048   __IO uint16_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
1049   uint16_t  RESERVED2;       /*!< Reserved, 0x12                                                 */
1050   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14 */
1051   __IO uint16_t RQR;         /*!< USART Request register,                   Address offset: 0x18 */
1052   uint16_t  RESERVED3;       /*!< Reserved, 0x1A                                                 */
1053   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C */
1054   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
1055   __IO uint16_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24 */
1056   uint16_t  RESERVED4;       /*!< Reserved, 0x26                                                 */
1057   __IO uint16_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28 */
1058   uint16_t  RESERVED5;       /*!< Reserved, 0x2A                                                 */
1059 } USART_TypeDef;
1060 
1061 /**
1062   * @brief VREFBUF
1063   */
1064 
1065 typedef struct
1066 {
1067   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
1068   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
1069 } VREFBUF_TypeDef;
1070 
1071 /**
1072   * @brief Window WATCHDOG
1073   */
1074 
1075 typedef struct
1076 {
1077   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
1078   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
1079   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
1080 } WWDG_TypeDef;
1081 
1082 /**
1083   * @brief AES hardware accelerator
1084   */
1085 
1086 typedef struct
1087 {
1088   __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
1089   __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
1090   __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
1091   __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
1092   __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
1093   __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
1094   __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
1095   __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
1096   __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
1097   __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
1098   __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
1099   __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
1100   __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
1101   __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
1102   __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
1103   __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
1104   __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
1105   __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
1106   __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
1107   __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
1108   __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
1109   __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
1110   __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
1111   __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x6C */
1112 } AES_TypeDef;
1113 
1114 /**
1115   * @brief HASH
1116   */
1117 
1118 typedef struct
1119 {
1120   __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */
1121   __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */
1122   __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */
1123   __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
1124   __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */
1125   __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */
1126        uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */
1127   __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */
1128 } HASH_TypeDef;
1129 
1130 /**
1131   * @brief HASH_DIGEST
1132   */
1133 
1134 typedef struct
1135 {
1136   __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */
1137 } HASH_DIGEST_TypeDef;
1138 
1139 /**
1140   * @brief RNG
1141   */
1142 
1143 typedef struct
1144 {
1145   __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
1146   __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
1147   __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
1148 } RNG_TypeDef;
1149 
1150 /**
1151   * @brief USB_OTG_Core_register
1152   */
1153 typedef struct
1154 {
1155   __IO uint32_t GOTGCTL;              /*!<  USB_OTG Control and Status Register          000h*/
1156   __IO uint32_t GOTGINT;              /*!<  USB_OTG Interrupt Register                   004h*/
1157   __IO uint32_t GAHBCFG;              /*!<  Core AHB Configuration Register              008h*/
1158   __IO uint32_t GUSBCFG;              /*!<  Core USB Configuration Register              00Ch*/
1159   __IO uint32_t GRSTCTL;              /*!<  Core Reset Register                          010h*/
1160   __IO uint32_t GINTSTS;              /*!<  Core Interrupt Register                      014h*/
1161   __IO uint32_t GINTMSK;              /*!<  Core Interrupt Mask Register                 018h*/
1162   __IO uint32_t GRXSTSR;              /*!<  Receive Sts Q Read Register                  01Ch*/
1163   __IO uint32_t GRXSTSP;              /*!<  Receive Sts Q Read & POP Register            020h*/
1164   __IO uint32_t GRXFSIZ;              /* Receive FIFO Size Register                      024h*/
1165   __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!<  EP0 / Non Periodic Tx FIFO Size Register     028h*/
1166   __IO uint32_t HNPTXSTS;             /*!<  Non Periodic Tx FIFO/Queue Sts reg           02Ch*/
1167   uint32_t Reserved30[2];             /* Reserved                                        030h*/
1168   __IO uint32_t GCCFG;                /* General Purpose IO Register                     038h*/
1169   __IO uint32_t CID;                  /* User ID Register                                03Ch*/
1170   __IO uint32_t GSNPSID;              /* USB_OTG core ID                                 040h*/
1171   __IO uint32_t GHWCFG1;              /* User HW config1                                 044h*/
1172   __IO uint32_t GHWCFG2;              /* User HW config2                                 048h*/
1173   __IO uint32_t GHWCFG3;              /* User HW config3                                 04Ch*/
1174   uint32_t  Reserved6;                /* Reserved                                        050h*/
1175   __IO uint32_t GLPMCFG;              /* LPM Register                                    054h*/
1176   __IO uint32_t GPWRDN;               /* Power Down Register                             058h*/
1177   __IO uint32_t GDFIFOCFG;            /* DFIFO Software Config Register                  05Ch*/
1178    __IO uint32_t GADPCTL;             /* ADP Timer, Control and Status Register          60Ch*/
1179     uint32_t  Reserved43[39];         /* Reserved                                        058h-0FFh*/
1180   __IO uint32_t HPTXFSIZ;             /* Host Periodic Tx FIFO Size Reg                  100h*/
1181   __IO uint32_t DIEPTXF[0x0F];        /* dev Periodic Transmit FIFO */
1182 } USB_OTG_GlobalTypeDef;
1183 
1184 /**
1185   * @brief USB_OTG_device_Registers
1186   */
1187 typedef struct
1188 {
1189   __IO uint32_t DCFG;        /* dev Configuration Register   800h*/
1190   __IO uint32_t DCTL;        /* dev Control Register         804h*/
1191   __IO uint32_t DSTS;        /* dev Status Register (RO)     808h*/
1192   uint32_t Reserved0C;       /* Reserved                     80Ch*/
1193   __IO uint32_t DIEPMSK;     /* dev IN Endpoint Mask         810h*/
1194   __IO uint32_t DOEPMSK;     /* dev OUT Endpoint Mask        814h*/
1195   __IO uint32_t DAINT;       /* dev All Endpoints Itr Reg    818h*/
1196   __IO uint32_t DAINTMSK;    /* dev All Endpoints Itr Mask   81Ch*/
1197   uint32_t  Reserved20;      /* Reserved                     820h*/
1198   uint32_t Reserved9;        /* Reserved                     824h*/
1199   __IO uint32_t DVBUSDIS;    /* dev VBUS discharge Register  828h*/
1200   __IO uint32_t DVBUSPULSE;  /* dev VBUS Pulse Register      82Ch*/
1201   __IO uint32_t DTHRCTL;     /* dev thr                      830h*/
1202   __IO uint32_t DIEPEMPMSK;  /* dev empty msk             834h*/
1203   __IO uint32_t DEACHINT;    /* dedicated EP interrupt       838h*/
1204   __IO uint32_t DEACHMSK;    /* dedicated EP msk             83Ch*/
1205   uint32_t Reserved40;       /* dedicated EP mask           840h*/
1206   __IO uint32_t DINEP1MSK;   /* dedicated EP mask           844h*/
1207   uint32_t  Reserved44[15];  /* Reserved                 844-87Ch*/
1208   __IO uint32_t DOUTEP1MSK;  /* dedicated EP msk            884h*/
1209 } USB_OTG_DeviceTypeDef;
1210 
1211 /**
1212   * @brief USB_OTG_IN_Endpoint-Specific_Register
1213   */
1214 typedef struct
1215 {
1216   __IO uint32_t DIEPCTL;     /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
1217   uint32_t Reserved04;       /* Reserved                       900h + (ep_num * 20h) + 04h*/
1218   __IO uint32_t DIEPINT;     /* dev IN Endpoint Itr Reg     900h + (ep_num * 20h) + 08h*/
1219   uint32_t Reserved0C;       /* Reserved                       900h + (ep_num * 20h) + 0Ch*/
1220   __IO uint32_t DIEPTSIZ;    /* IN Endpoint Txfer Size   900h + (ep_num * 20h) + 10h*/
1221   __IO uint32_t DIEPDMA;     /* IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h*/
1222   __IO uint32_t DTXFSTS;     /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
1223   uint32_t Reserved18;       /* Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
1224 } USB_OTG_INEndpointTypeDef;
1225 
1226 /**
1227   * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1228   */
1229 typedef struct
1230 {
1231   __IO uint32_t DOEPCTL;     /* dev OUT Endpoint Control Reg  B00h + (ep_num * 20h) + 00h*/
1232   uint32_t Reserved04;       /* Reserved                      B00h + (ep_num * 20h) + 04h*/
1233   __IO uint32_t DOEPINT;     /* dev OUT Endpoint Itr Reg      B00h + (ep_num * 20h) + 08h*/
1234   uint32_t Reserved0C;       /* Reserved                      B00h + (ep_num * 20h) + 0Ch*/
1235   __IO uint32_t DOEPTSIZ;    /* dev OUT Endpoint Txfer Size   B00h + (ep_num * 20h) + 10h*/
1236   __IO uint32_t DOEPDMA;     /* dev OUT Endpoint DMA Address  B00h + (ep_num * 20h) + 14h*/
1237   uint32_t Reserved18[2];    /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
1238 } USB_OTG_OUTEndpointTypeDef;
1239 
1240 /**
1241   * @brief USB_OTG_Host_Mode_Register_Structures
1242   */
1243 typedef struct
1244 {
1245   __IO uint32_t HCFG;        /* Host Configuration Register    400h*/
1246   __IO uint32_t HFIR;        /* Host Frame Interval Register   404h*/
1247   __IO uint32_t HFNUM;       /* Host Frame Nbr/Frame Remaining 408h*/
1248   uint32_t Reserved40C;      /* Reserved                       40Ch*/
1249   __IO uint32_t HPTXSTS;     /* Host Periodic Tx FIFO/ Queue Status 410h*/
1250   __IO uint32_t HAINT;       /* Host All Channels Interrupt Register 414h*/
1251   __IO uint32_t HAINTMSK;    /* Host All Channels Interrupt Mask 418h*/
1252 } USB_OTG_HostTypeDef;
1253 
1254 /**
1255   * @brief USB_OTG_Host_Channel_Specific_Registers
1256   */
1257 typedef struct
1258 {
1259   __IO uint32_t HCCHAR;
1260   __IO uint32_t HCSPLT;
1261   __IO uint32_t HCINT;
1262   __IO uint32_t HCINTMSK;
1263   __IO uint32_t HCTSIZ;
1264   __IO uint32_t HCDMA;
1265   uint32_t Reserved[2];
1266 } USB_OTG_HostChannelTypeDef;
1267 
1268 /**
1269   * @}
1270   */
1271 
1272 /** @addtogroup Peripheral_memory_map
1273   * @{
1274   */
1275 #define FLASH_BASE            ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */
1276 #define SRAM1_BASE            ((uint32_t)0x20000000U) /*!< SRAM1(up to 256 KB) base address */
1277 #define SRAM2_BASE            ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */
1278 #define PERIPH_BASE           ((uint32_t)0x40000000U) /*!< Peripheral base address */
1279 #define FMC_BASE              ((uint32_t)0x60000000U) /*!< FMC base address */
1280 #define QSPI_BASE             ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */
1281 
1282 #define FMC_R_BASE            ((uint32_t)0xA0000000U) /*!< FMC  control registers base address */
1283 #define QSPI_R_BASE           ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */
1284 #define SRAM1_BB_BASE         ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */
1285 #define PERIPH_BB_BASE        ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
1286 
1287 /* Legacy defines */
1288 #define SRAM_BASE             SRAM1_BASE
1289 #define SRAM_BB_BASE          SRAM1_BB_BASE
1290 
1291 #define SRAM1_SIZE_MAX        ((uint32_t)0x00040000U) /*!< maximum SRAM1 size (up to 256 KBytes) */
1292 #define SRAM2_SIZE            ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */
1293 
1294 /*!< Peripheral memory map */
1295 #define APB1PERIPH_BASE        PERIPH_BASE
1296 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
1297 #define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000U)
1298 #define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000U)
1299 
1300 #define FMC_BANK1             FMC_BASE
1301 #define FMC_BANK1_1           FMC_BANK1
1302 #define FMC_BANK1_2           (FMC_BANK1 + 0x04000000U)
1303 #define FMC_BANK1_3           (FMC_BANK1 + 0x08000000U)
1304 #define FMC_BANK1_4           (FMC_BANK1 + 0x0C000000U)
1305 #define FMC_BANK3             (FMC_BASE  + 0x20000000U)
1306 
1307 /*!< APB1 peripherals */
1308 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000U)
1309 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400U)
1310 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800U)
1311 #define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00U)
1312 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000U)
1313 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400U)
1314 #define LCD_BASE              (APB1PERIPH_BASE + 0x2400U)
1315 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800U)
1316 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00U)
1317 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000U)
1318 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800U)
1319 #define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00U)
1320 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400U)
1321 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800U)
1322 #define UART4_BASE            (APB1PERIPH_BASE + 0x4C00U)
1323 #define UART5_BASE            (APB1PERIPH_BASE + 0x5000U)
1324 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400U)
1325 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800U)
1326 #define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00U)
1327 #define CRS_BASE              (APB1PERIPH_BASE + 0x6000U)
1328 #define CAN1_BASE             (APB1PERIPH_BASE + 0x6400U)
1329 #define CAN2_BASE             (APB1PERIPH_BASE + 0x6800U)
1330 #define I2C4_BASE             (APB1PERIPH_BASE + 0x8400U)
1331 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000U)
1332 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400U)
1333 #define DAC1_BASE             (APB1PERIPH_BASE + 0x7400U)
1334 #define OPAMP_BASE            (APB1PERIPH_BASE + 0x7800U)
1335 #define OPAMP1_BASE           (APB1PERIPH_BASE + 0x7800U)
1336 #define OPAMP2_BASE           (APB1PERIPH_BASE + 0x7810U)
1337 #define LPTIM1_BASE           (APB1PERIPH_BASE + 0x7C00U)
1338 #define LPUART1_BASE          (APB1PERIPH_BASE + 0x8000U)
1339 #define SWPMI1_BASE           (APB1PERIPH_BASE + 0x8800U)
1340 #define LPTIM2_BASE           (APB1PERIPH_BASE + 0x9400U)
1341 
1342 
1343 /*!< APB2 peripherals */
1344 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x0000U)
1345 #define VREFBUF_BASE          (APB2PERIPH_BASE + 0x0030U)
1346 #define COMP1_BASE            (APB2PERIPH_BASE + 0x0200U)
1347 #define COMP2_BASE            (APB2PERIPH_BASE + 0x0204U)
1348 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400U)
1349 #define FIREWALL_BASE         (APB2PERIPH_BASE + 0x1C00U)
1350 #define SDMMC1_BASE           (APB2PERIPH_BASE + 0x2800U)
1351 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00U)
1352 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000U)
1353 #define TIM8_BASE             (APB2PERIPH_BASE + 0x3400U)
1354 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800U)
1355 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000U)
1356 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400U)
1357 #define TIM17_BASE            (APB2PERIPH_BASE + 0x4800U)
1358 #define SAI1_BASE             (APB2PERIPH_BASE + 0x5400U)
1359 #define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)
1360 #define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)
1361 #define SAI2_BASE             (APB2PERIPH_BASE + 0x5800U)
1362 #define SAI2_Block_A_BASE     (SAI2_BASE + 0x004)
1363 #define SAI2_Block_B_BASE     (SAI2_BASE + 0x024)
1364 #define DFSDM1_BASE           (APB2PERIPH_BASE + 0x6000U)
1365 #define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00)
1366 #define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20)
1367 #define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40)
1368 #define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60)
1369 #define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80)
1370 #define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0)
1371 #define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0)
1372 #define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0)
1373 #define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100)
1374 #define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180)
1375 #define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200)
1376 #define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280)
1377 
1378 /*!< AHB1 peripherals */
1379 #define DMA1_BASE             (AHB1PERIPH_BASE)
1380 #define DMA2_BASE             (AHB1PERIPH_BASE + 0x0400U)
1381 #define RCC_BASE              (AHB1PERIPH_BASE + 0x1000U)
1382 #define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x2000U)
1383 #define CRC_BASE              (AHB1PERIPH_BASE + 0x3000U)
1384 #define TSC_BASE              (AHB1PERIPH_BASE + 0x4000U)
1385 #define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000U)
1386 
1387 
1388 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x0008U)
1389 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x001CU)
1390 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x0030U)
1391 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x0044U)
1392 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x0058U)
1393 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x006CU)
1394 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x0080U)
1395 #define DMA1_CSELR_BASE       (DMA1_BASE + 0x00A8U)
1396 
1397 
1398 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x0008U)
1399 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x001CU)
1400 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x0030U)
1401 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x0044U)
1402 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x0058U)
1403 #define DMA2_Channel6_BASE    (DMA2_BASE + 0x006CU)
1404 #define DMA2_Channel7_BASE    (DMA2_BASE + 0x0080U)
1405 #define DMA2_CSELR_BASE       (DMA2_BASE + 0x00A8U)
1406 
1407 
1408 /*!< AHB2 peripherals */
1409 #define GPIOA_BASE            (AHB2PERIPH_BASE + 0x0000U)
1410 #define GPIOB_BASE            (AHB2PERIPH_BASE + 0x0400U)
1411 #define GPIOC_BASE            (AHB2PERIPH_BASE + 0x0800U)
1412 #define GPIOD_BASE            (AHB2PERIPH_BASE + 0x0C00U)
1413 #define GPIOE_BASE            (AHB2PERIPH_BASE + 0x1000U)
1414 #define GPIOF_BASE            (AHB2PERIPH_BASE + 0x1400U)
1415 #define GPIOG_BASE            (AHB2PERIPH_BASE + 0x1800U)
1416 #define GPIOH_BASE            (AHB2PERIPH_BASE + 0x1C00U)
1417 #define GPIOI_BASE            (AHB2PERIPH_BASE + 0x2000U)
1418 
1419 #define USBOTG_BASE           (AHB2PERIPH_BASE + 0x08000000U)
1420 
1421 #define ADC1_BASE             (AHB2PERIPH_BASE + 0x08040000U)
1422 #define ADC2_BASE             (AHB2PERIPH_BASE + 0x08040100U)
1423 #define ADC3_BASE             (AHB2PERIPH_BASE + 0x08040200U)
1424 #define ADC123_COMMON_BASE    (AHB2PERIPH_BASE + 0x08040300U)
1425 
1426 #define DCMI_BASE             (AHB2PERIPH_BASE + 0x08050000U)
1427 
1428 #define AES_BASE              (AHB2PERIPH_BASE + 0x08060000U)
1429 #define HASH_BASE             (AHB2PERIPH_BASE + 0x08060400U)
1430 #define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x08060710U)
1431 #define RNG_BASE              (AHB2PERIPH_BASE + 0x08060800U)
1432 
1433 
1434 /*!< FMC Banks registers base  address */
1435 #define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000U)
1436 #define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104U)
1437 #define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080U)
1438 
1439 /* Debug MCU registers base address */
1440 #define DBGMCU_BASE           ((uint32_t)0xE0042000U)
1441 
1442 /*!< USB registers base address */
1443 #define USB_OTG_FS_PERIPH_BASE               ((uint32_t)0x50000000U)
1444 
1445 #define USB_OTG_GLOBAL_BASE                  ((uint32_t)0x00000000U)
1446 #define USB_OTG_DEVICE_BASE                  ((uint32_t)0x00000800U)
1447 #define USB_OTG_IN_ENDPOINT_BASE             ((uint32_t)0x00000900U)
1448 #define USB_OTG_OUT_ENDPOINT_BASE            ((uint32_t)0x00000B00U)
1449 #define USB_OTG_EP_REG_SIZE                  ((uint32_t)0x00000020U)
1450 #define USB_OTG_HOST_BASE                    ((uint32_t)0x00000400U)
1451 #define USB_OTG_HOST_PORT_BASE               ((uint32_t)0x00000440U)
1452 #define USB_OTG_HOST_CHANNEL_BASE            ((uint32_t)0x00000500U)
1453 #define USB_OTG_HOST_CHANNEL_SIZE            ((uint32_t)0x00000020U)
1454 #define USB_OTG_PCGCCTL_BASE                 ((uint32_t)0x00000E00U)
1455 #define USB_OTG_FIFO_BASE                    ((uint32_t)0x00001000U)
1456 #define USB_OTG_FIFO_SIZE                    ((uint32_t)0x00001000U)
1457 
1458 
1459 #define PACKAGE_BASE          ((uint32_t)0x1FFF7500U)        /*!< Package data register base address     */
1460 #define UID_BASE              ((uint32_t)0x1FFF7590U)        /*!< Unique device ID register base address */
1461 #define FLASHSIZE_BASE        ((uint32_t)0x1FFF75E0U)        /*!< Flash size data register base address  */
1462 /**
1463   * @}
1464   */
1465 
1466 /** @addtogroup Peripheral_declaration
1467   * @{
1468   */
1469 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
1470 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
1471 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
1472 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
1473 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
1474 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
1475 #define LCD                 ((LCD_TypeDef *) LCD_BASE)
1476 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
1477 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
1478 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
1479 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
1480 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
1481 #define USART2              ((USART_TypeDef *) USART2_BASE)
1482 #define USART3              ((USART_TypeDef *) USART3_BASE)
1483 #define UART4               ((USART_TypeDef *) UART4_BASE)
1484 #define UART5               ((USART_TypeDef *) UART5_BASE)
1485 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
1486 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
1487 #define I2C3                ((I2C_TypeDef *) I2C3_BASE)
1488 #define CRS                 ((CRS_TypeDef *) CRS_BASE)
1489 #define CAN                 ((CAN_TypeDef *) CAN1_BASE)
1490 #define CAN1                ((CAN_TypeDef *) CAN1_BASE)
1491 #define CAN2                ((CAN_TypeDef *) CAN2_BASE)
1492 #define I2C4                ((I2C_TypeDef *) I2C4_BASE)
1493 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
1494 #define DAC                 ((DAC_TypeDef *) DAC1_BASE)
1495 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
1496 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
1497 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
1498 #define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
1499 #define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
1500 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
1501 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
1502 #define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
1503 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
1504 
1505 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
1506 #define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
1507 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
1508 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
1509 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
1510 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
1511 #define FIREWALL            ((FIREWALL_TypeDef *) FIREWALL_BASE)
1512 #define SDMMC1              ((SDMMC_TypeDef *) SDMMC1_BASE)
1513 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
1514 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
1515 #define TIM8                ((TIM_TypeDef *) TIM8_BASE)
1516 #define USART1              ((USART_TypeDef *) USART1_BASE)
1517 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
1518 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
1519 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
1520 #define SAI1                ((SAI_TypeDef *) SAI1_BASE)
1521 #define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1522 #define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1523 #define SAI2                ((SAI_TypeDef *) SAI2_BASE)
1524 #define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1525 #define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1526 #define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
1527 #define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
1528 #define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
1529 #define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
1530 #define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
1531 #define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
1532 #define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
1533 #define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
1534 #define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
1535 #define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
1536 #define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
1537 #define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
1538 /* Aliases to keep compatibility after DFSDM renaming */
1539 #define DFSDM_Channel0      DFSDM1_Channel0
1540 #define DFSDM_Channel1      DFSDM1_Channel1
1541 #define DFSDM_Channel2      DFSDM1_Channel2
1542 #define DFSDM_Channel3      DFSDM1_Channel3
1543 #define DFSDM_Channel4      DFSDM1_Channel4
1544 #define DFSDM_Channel5      DFSDM1_Channel5
1545 #define DFSDM_Channel6      DFSDM1_Channel6
1546 #define DFSDM_Channel7      DFSDM1_Channel7
1547 #define DFSDM_Filter0       DFSDM1_Filter0
1548 #define DFSDM_Filter1       DFSDM1_Filter1
1549 #define DFSDM_Filter2       DFSDM1_Filter2
1550 #define DFSDM_Filter3       DFSDM1_Filter3
1551 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
1552 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
1553 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
1554 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
1555 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
1556 #define TSC                 ((TSC_TypeDef *) TSC_BASE)
1557 
1558 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
1559 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
1560 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
1561 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
1562 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
1563 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
1564 #define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
1565 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
1566 #define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
1567 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
1568 #define ADC2                ((ADC_TypeDef *) ADC2_BASE)
1569 #define ADC3                ((ADC_TypeDef *) ADC3_BASE)
1570 #define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1571 #define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
1572 #define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)
1573 #define HASH                ((HASH_TypeDef *) HASH_BASE)
1574 #define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
1575 #define AES                 ((AES_TypeDef *) AES_BASE)
1576 #define RNG                 ((RNG_TypeDef *) RNG_BASE)
1577 
1578 
1579 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
1580 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
1581 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
1582 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
1583 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
1584 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
1585 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
1586 #define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
1587 
1588 
1589 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
1590 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
1591 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
1592 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
1593 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
1594 #define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
1595 #define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
1596 #define DMA2_CSELR          ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
1597 
1598 
1599 #define FMC_Bank1_R         ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1600 #define FMC_Bank1E_R        ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1601 #define FMC_Bank3_R         ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1602 
1603 #define QUADSPI             ((QUADSPI_TypeDef *) QSPI_R_BASE)
1604 
1605 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
1606 
1607 #define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1608 /**
1609   * @}
1610   */
1611 
1612 /** @addtogroup Exported_constants
1613   * @{
1614   */
1615 
1616 /** @addtogroup Peripheral_Registers_Bits_Definition
1617   * @{
1618   */
1619 
1620 /******************************************************************************/
1621 /*                         Peripheral Registers_Bits_Definition               */
1622 /******************************************************************************/
1623 
1624 /******************************************************************************/
1625 /*                                                                            */
1626 /*                        Analog to Digital Converter                         */
1627 /*                                                                            */
1628 /******************************************************************************/
1629 
1630 /*
1631  * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
1632  */
1633 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
1634 
1635 /********************  Bit definition for ADC_ISR register  *******************/
1636 #define ADC_ISR_ADRDY_Pos              (0U)
1637 #define ADC_ISR_ADRDY_Msk              (0x1U << ADC_ISR_ADRDY_Pos)             /*!< 0x00000001 */
1638 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
1639 #define ADC_ISR_EOSMP_Pos              (1U)
1640 #define ADC_ISR_EOSMP_Msk              (0x1U << ADC_ISR_EOSMP_Pos)             /*!< 0x00000002 */
1641 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
1642 #define ADC_ISR_EOC_Pos                (2U)
1643 #define ADC_ISR_EOC_Msk                (0x1U << ADC_ISR_EOC_Pos)               /*!< 0x00000004 */
1644 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
1645 #define ADC_ISR_EOS_Pos                (3U)
1646 #define ADC_ISR_EOS_Msk                (0x1U << ADC_ISR_EOS_Pos)               /*!< 0x00000008 */
1647 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
1648 #define ADC_ISR_OVR_Pos                (4U)
1649 #define ADC_ISR_OVR_Msk                (0x1U << ADC_ISR_OVR_Pos)               /*!< 0x00000010 */
1650 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
1651 #define ADC_ISR_JEOC_Pos               (5U)
1652 #define ADC_ISR_JEOC_Msk               (0x1U << ADC_ISR_JEOC_Pos)              /*!< 0x00000020 */
1653 #define ADC_ISR_JEOC                   ADC_ISR_JEOC_Msk                        /*!< ADC group injected end of unitary conversion flag */
1654 #define ADC_ISR_JEOS_Pos               (6U)
1655 #define ADC_ISR_JEOS_Msk               (0x1U << ADC_ISR_JEOS_Pos)              /*!< 0x00000040 */
1656 #define ADC_ISR_JEOS                   ADC_ISR_JEOS_Msk                        /*!< ADC group injected end of sequence conversions flag */
1657 #define ADC_ISR_AWD1_Pos               (7U)
1658 #define ADC_ISR_AWD1_Msk               (0x1U << ADC_ISR_AWD1_Pos)              /*!< 0x00000080 */
1659 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
1660 #define ADC_ISR_AWD2_Pos               (8U)
1661 #define ADC_ISR_AWD2_Msk               (0x1U << ADC_ISR_AWD2_Pos)              /*!< 0x00000100 */
1662 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
1663 #define ADC_ISR_AWD3_Pos               (9U)
1664 #define ADC_ISR_AWD3_Msk               (0x1U << ADC_ISR_AWD3_Pos)              /*!< 0x00000200 */
1665 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
1666 #define ADC_ISR_JQOVF_Pos              (10U)
1667 #define ADC_ISR_JQOVF_Msk              (0x1U << ADC_ISR_JQOVF_Pos)             /*!< 0x00000400 */
1668 #define ADC_ISR_JQOVF                  ADC_ISR_JQOVF_Msk                       /*!< ADC group injected contexts queue overflow flag */
1669 
1670 /********************  Bit definition for ADC_IER register  *******************/
1671 #define ADC_IER_ADRDYIE_Pos            (0U)
1672 #define ADC_IER_ADRDYIE_Msk            (0x1U << ADC_IER_ADRDYIE_Pos)           /*!< 0x00000001 */
1673 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
1674 #define ADC_IER_EOSMPIE_Pos            (1U)
1675 #define ADC_IER_EOSMPIE_Msk            (0x1U << ADC_IER_EOSMPIE_Pos)           /*!< 0x00000002 */
1676 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
1677 #define ADC_IER_EOCIE_Pos              (2U)
1678 #define ADC_IER_EOCIE_Msk              (0x1U << ADC_IER_EOCIE_Pos)             /*!< 0x00000004 */
1679 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
1680 #define ADC_IER_EOSIE_Pos              (3U)
1681 #define ADC_IER_EOSIE_Msk              (0x1U << ADC_IER_EOSIE_Pos)             /*!< 0x00000008 */
1682 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
1683 #define ADC_IER_OVRIE_Pos              (4U)
1684 #define ADC_IER_OVRIE_Msk              (0x1U << ADC_IER_OVRIE_Pos)             /*!< 0x00000010 */
1685 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
1686 #define ADC_IER_JEOCIE_Pos             (5U)
1687 #define ADC_IER_JEOCIE_Msk             (0x1U << ADC_IER_JEOCIE_Pos)            /*!< 0x00000020 */
1688 #define ADC_IER_JEOCIE                 ADC_IER_JEOCIE_Msk                      /*!< ADC group injected end of unitary conversion interrupt */
1689 #define ADC_IER_JEOSIE_Pos             (6U)
1690 #define ADC_IER_JEOSIE_Msk             (0x1U << ADC_IER_JEOSIE_Pos)            /*!< 0x00000040 */
1691 #define ADC_IER_JEOSIE                 ADC_IER_JEOSIE_Msk                      /*!< ADC group injected end of sequence conversions interrupt */
1692 #define ADC_IER_AWD1IE_Pos             (7U)
1693 #define ADC_IER_AWD1IE_Msk             (0x1U << ADC_IER_AWD1IE_Pos)            /*!< 0x00000080 */
1694 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
1695 #define ADC_IER_AWD2IE_Pos             (8U)
1696 #define ADC_IER_AWD2IE_Msk             (0x1U << ADC_IER_AWD2IE_Pos)            /*!< 0x00000100 */
1697 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
1698 #define ADC_IER_AWD3IE_Pos             (9U)
1699 #define ADC_IER_AWD3IE_Msk             (0x1U << ADC_IER_AWD3IE_Pos)            /*!< 0x00000200 */
1700 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
1701 #define ADC_IER_JQOVFIE_Pos            (10U)
1702 #define ADC_IER_JQOVFIE_Msk            (0x1U << ADC_IER_JQOVFIE_Pos)           /*!< 0x00000400 */
1703 #define ADC_IER_JQOVFIE                ADC_IER_JQOVFIE_Msk                     /*!< ADC group injected contexts queue overflow interrupt */
1704 
1705 /* Legacy defines */
1706 #define ADC_IER_ADRDY           (ADC_IER_ADRDYIE)
1707 #define ADC_IER_EOSMP           (ADC_IER_EOSMPIE)
1708 #define ADC_IER_EOC             (ADC_IER_EOCIE)
1709 #define ADC_IER_EOS             (ADC_IER_EOSIE)
1710 #define ADC_IER_OVR             (ADC_IER_OVRIE)
1711 #define ADC_IER_JEOC            (ADC_IER_JEOCIE)
1712 #define ADC_IER_JEOS            (ADC_IER_JEOSIE)
1713 #define ADC_IER_AWD1            (ADC_IER_AWD1IE)
1714 #define ADC_IER_AWD2            (ADC_IER_AWD2IE)
1715 #define ADC_IER_AWD3            (ADC_IER_AWD3IE)
1716 #define ADC_IER_JQOVF           (ADC_IER_JQOVFIE)
1717 
1718 /********************  Bit definition for ADC_CR register  ********************/
1719 #define ADC_CR_ADEN_Pos                (0U)
1720 #define ADC_CR_ADEN_Msk                (0x1U << ADC_CR_ADEN_Pos)               /*!< 0x00000001 */
1721 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
1722 #define ADC_CR_ADDIS_Pos               (1U)
1723 #define ADC_CR_ADDIS_Msk               (0x1U << ADC_CR_ADDIS_Pos)              /*!< 0x00000002 */
1724 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
1725 #define ADC_CR_ADSTART_Pos             (2U)
1726 #define ADC_CR_ADSTART_Msk             (0x1U << ADC_CR_ADSTART_Pos)            /*!< 0x00000004 */
1727 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
1728 #define ADC_CR_JADSTART_Pos            (3U)
1729 #define ADC_CR_JADSTART_Msk            (0x1U << ADC_CR_JADSTART_Pos)           /*!< 0x00000008 */
1730 #define ADC_CR_JADSTART                ADC_CR_JADSTART_Msk                     /*!< ADC group injected conversion start */
1731 #define ADC_CR_ADSTP_Pos               (4U)
1732 #define ADC_CR_ADSTP_Msk               (0x1U << ADC_CR_ADSTP_Pos)              /*!< 0x00000010 */
1733 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
1734 #define ADC_CR_JADSTP_Pos              (5U)
1735 #define ADC_CR_JADSTP_Msk              (0x1U << ADC_CR_JADSTP_Pos)             /*!< 0x00000020 */
1736 #define ADC_CR_JADSTP                  ADC_CR_JADSTP_Msk                       /*!< ADC group injected conversion stop */
1737 #define ADC_CR_ADVREGEN_Pos            (28U)
1738 #define ADC_CR_ADVREGEN_Msk            (0x1U << ADC_CR_ADVREGEN_Pos)           /*!< 0x10000000 */
1739 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
1740 #define ADC_CR_DEEPPWD_Pos             (29U)
1741 #define ADC_CR_DEEPPWD_Msk             (0x1U << ADC_CR_DEEPPWD_Pos)            /*!< 0x20000000 */
1742 #define ADC_CR_DEEPPWD                 ADC_CR_DEEPPWD_Msk                      /*!< ADC deep power down enable */
1743 #define ADC_CR_ADCALDIF_Pos            (30U)
1744 #define ADC_CR_ADCALDIF_Msk            (0x1U << ADC_CR_ADCALDIF_Pos)           /*!< 0x40000000 */
1745 #define ADC_CR_ADCALDIF                ADC_CR_ADCALDIF_Msk                     /*!< ADC differential mode for calibration */
1746 #define ADC_CR_ADCAL_Pos               (31U)
1747 #define ADC_CR_ADCAL_Msk               (0x1U << ADC_CR_ADCAL_Pos)              /*!< 0x80000000 */
1748 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
1749 
1750 /********************  Bit definition for ADC_CFGR register  ******************/
1751 #define ADC_CFGR_DMAEN_Pos             (0U)
1752 #define ADC_CFGR_DMAEN_Msk             (0x1U << ADC_CFGR_DMAEN_Pos)            /*!< 0x00000001 */
1753 #define ADC_CFGR_DMAEN                 ADC_CFGR_DMAEN_Msk                      /*!< ADC DMA transfer enable */
1754 #define ADC_CFGR_DMACFG_Pos            (1U)
1755 #define ADC_CFGR_DMACFG_Msk            (0x1U << ADC_CFGR_DMACFG_Pos)           /*!< 0x00000002 */
1756 #define ADC_CFGR_DMACFG                ADC_CFGR_DMACFG_Msk                     /*!< ADC DMA transfer configuration */
1757 
1758 #define ADC_CFGR_DFSDMCFG_Pos          (2U)
1759 #define ADC_CFGR_DFSDMCFG_Msk          (0x1U << ADC_CFGR_DFSDMCFG_Pos)         /*!< 0x00000004 */
1760 #define ADC_CFGR_DFSDMCFG              ADC_CFGR_DFSDMCFG_Msk                   /*!< ADC DFSDM mode configuration */
1761 
1762 #define ADC_CFGR_RES_Pos               (3U)
1763 #define ADC_CFGR_RES_Msk               (0x3U << ADC_CFGR_RES_Pos)              /*!< 0x00000018 */
1764 #define ADC_CFGR_RES                   ADC_CFGR_RES_Msk                        /*!< ADC data resolution */
1765 #define ADC_CFGR_RES_0                 (0x1U << ADC_CFGR_RES_Pos)              /*!< 0x00000008 */
1766 #define ADC_CFGR_RES_1                 (0x2U << ADC_CFGR_RES_Pos)              /*!< 0x00000010 */
1767 
1768 #define ADC_CFGR_ALIGN_Pos             (5U)
1769 #define ADC_CFGR_ALIGN_Msk             (0x1U << ADC_CFGR_ALIGN_Pos)            /*!< 0x00000020 */
1770 #define ADC_CFGR_ALIGN                 ADC_CFGR_ALIGN_Msk                      /*!< ADC data alignement */
1771 
1772 #define ADC_CFGR_EXTSEL_Pos            (6U)
1773 #define ADC_CFGR_EXTSEL_Msk            (0xFU << ADC_CFGR_EXTSEL_Pos)           /*!< 0x000003C0 */
1774 #define ADC_CFGR_EXTSEL                ADC_CFGR_EXTSEL_Msk                     /*!< ADC group regular external trigger source */
1775 #define ADC_CFGR_EXTSEL_0              (0x1U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000040 */
1776 #define ADC_CFGR_EXTSEL_1              (0x2U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000080 */
1777 #define ADC_CFGR_EXTSEL_2              (0x4U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000100 */
1778 #define ADC_CFGR_EXTSEL_3              (0x8U << ADC_CFGR_EXTSEL_Pos)           /*!< 0x00000200 */
1779 
1780 #define ADC_CFGR_EXTEN_Pos             (10U)
1781 #define ADC_CFGR_EXTEN_Msk             (0x3U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000C00 */
1782 #define ADC_CFGR_EXTEN                 ADC_CFGR_EXTEN_Msk                      /*!< ADC group regular external trigger polarity */
1783 #define ADC_CFGR_EXTEN_0               (0x1U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000400 */
1784 #define ADC_CFGR_EXTEN_1               (0x2U << ADC_CFGR_EXTEN_Pos)            /*!< 0x00000800 */
1785 
1786 #define ADC_CFGR_OVRMOD_Pos            (12U)
1787 #define ADC_CFGR_OVRMOD_Msk            (0x1U << ADC_CFGR_OVRMOD_Pos)           /*!< 0x00001000 */
1788 #define ADC_CFGR_OVRMOD                ADC_CFGR_OVRMOD_Msk                     /*!< ADC group regular overrun configuration */
1789 #define ADC_CFGR_CONT_Pos              (13U)
1790 #define ADC_CFGR_CONT_Msk              (0x1U << ADC_CFGR_CONT_Pos)             /*!< 0x00002000 */
1791 #define ADC_CFGR_CONT                  ADC_CFGR_CONT_Msk                       /*!< ADC group regular continuous conversion mode */
1792 #define ADC_CFGR_AUTDLY_Pos            (14U)
1793 #define ADC_CFGR_AUTDLY_Msk            (0x1U << ADC_CFGR_AUTDLY_Pos)           /*!< 0x00004000 */
1794 #define ADC_CFGR_AUTDLY                ADC_CFGR_AUTDLY_Msk                     /*!< ADC low power auto wait */
1795 
1796 #define ADC_CFGR_DISCEN_Pos            (16U)
1797 #define ADC_CFGR_DISCEN_Msk            (0x1U << ADC_CFGR_DISCEN_Pos)           /*!< 0x00010000 */
1798 #define ADC_CFGR_DISCEN                ADC_CFGR_DISCEN_Msk                     /*!< ADC group regular sequencer discontinuous mode */
1799 
1800 #define ADC_CFGR_DISCNUM_Pos           (17U)
1801 #define ADC_CFGR_DISCNUM_Msk           (0x7U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x000E0000 */
1802 #define ADC_CFGR_DISCNUM               ADC_CFGR_DISCNUM_Msk                    /*!< ADC group regular sequencer discontinuous number of ranks */
1803 #define ADC_CFGR_DISCNUM_0             (0x1U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00020000 */
1804 #define ADC_CFGR_DISCNUM_1             (0x2U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00040000 */
1805 #define ADC_CFGR_DISCNUM_2             (0x4U << ADC_CFGR_DISCNUM_Pos)          /*!< 0x00080000 */
1806 
1807 #define ADC_CFGR_JDISCEN_Pos           (20U)
1808 #define ADC_CFGR_JDISCEN_Msk           (0x1U << ADC_CFGR_JDISCEN_Pos)          /*!< 0x00100000 */
1809 #define ADC_CFGR_JDISCEN               ADC_CFGR_JDISCEN_Msk                    /*!< ADC group injected sequencer discontinuous mode */
1810 #define ADC_CFGR_JQM_Pos               (21U)
1811 #define ADC_CFGR_JQM_Msk               (0x1U << ADC_CFGR_JQM_Pos)              /*!< 0x00200000 */
1812 #define ADC_CFGR_JQM                   ADC_CFGR_JQM_Msk                        /*!< ADC group injected contexts queue mode */
1813 #define ADC_CFGR_AWD1SGL_Pos           (22U)
1814 #define ADC_CFGR_AWD1SGL_Msk           (0x1U << ADC_CFGR_AWD1SGL_Pos)          /*!< 0x00400000 */
1815 #define ADC_CFGR_AWD1SGL               ADC_CFGR_AWD1SGL_Msk                    /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
1816 #define ADC_CFGR_AWD1EN_Pos            (23U)
1817 #define ADC_CFGR_AWD1EN_Msk            (0x1U << ADC_CFGR_AWD1EN_Pos)           /*!< 0x00800000 */
1818 #define ADC_CFGR_AWD1EN                ADC_CFGR_AWD1EN_Msk                     /*!< ADC analog watchdog 1 enable on scope ADC group regular */
1819 #define ADC_CFGR_JAWD1EN_Pos           (24U)
1820 #define ADC_CFGR_JAWD1EN_Msk           (0x1U << ADC_CFGR_JAWD1EN_Pos)          /*!< 0x01000000 */
1821 #define ADC_CFGR_JAWD1EN               ADC_CFGR_JAWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group injected */
1822 #define ADC_CFGR_JAUTO_Pos             (25U)
1823 #define ADC_CFGR_JAUTO_Msk             (0x1U << ADC_CFGR_JAUTO_Pos)            /*!< 0x02000000 */
1824 #define ADC_CFGR_JAUTO                 ADC_CFGR_JAUTO_Msk                      /*!< ADC group injected automatic trigger mode */
1825 
1826 #define ADC_CFGR_AWD1CH_Pos            (26U)
1827 #define ADC_CFGR_AWD1CH_Msk            (0x1FU << ADC_CFGR_AWD1CH_Pos)          /*!< 0x7C000000 */
1828 #define ADC_CFGR_AWD1CH                ADC_CFGR_AWD1CH_Msk                     /*!< ADC analog watchdog 1 monitored channel selection */
1829 #define ADC_CFGR_AWD1CH_0              (0x01U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x04000000 */
1830 #define ADC_CFGR_AWD1CH_1              (0x02U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x08000000 */
1831 #define ADC_CFGR_AWD1CH_2              (0x04U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x10000000 */
1832 #define ADC_CFGR_AWD1CH_3              (0x08U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x20000000 */
1833 #define ADC_CFGR_AWD1CH_4              (0x10U << ADC_CFGR_AWD1CH_Pos)          /*!< 0x40000000 */
1834 
1835 #define ADC_CFGR_JQDIS_Pos             (31U)
1836 #define ADC_CFGR_JQDIS_Msk             (0x1U << ADC_CFGR_JQDIS_Pos)            /*!< 0x80000000 */
1837 #define ADC_CFGR_JQDIS                 ADC_CFGR_JQDIS_Msk                      /*!< ADC group injected contexts queue disable */
1838 
1839 /********************  Bit definition for ADC_CFGR2 register  *****************/
1840 #define ADC_CFGR2_ROVSE_Pos            (0U)
1841 #define ADC_CFGR2_ROVSE_Msk            (0x1U << ADC_CFGR2_ROVSE_Pos)           /*!< 0x00000001 */
1842 #define ADC_CFGR2_ROVSE                ADC_CFGR2_ROVSE_Msk                     /*!< ADC oversampler enable on scope ADC group regular */
1843 #define ADC_CFGR2_JOVSE_Pos            (1U)
1844 #define ADC_CFGR2_JOVSE_Msk            (0x1U << ADC_CFGR2_JOVSE_Pos)           /*!< 0x00000002 */
1845 #define ADC_CFGR2_JOVSE                ADC_CFGR2_JOVSE_Msk                     /*!< ADC oversampler enable on scope ADC group injected */
1846 
1847 #define ADC_CFGR2_OVSR_Pos             (2U)
1848 #define ADC_CFGR2_OVSR_Msk             (0x7U << ADC_CFGR2_OVSR_Pos)            /*!< 0x0000001C */
1849 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1850 #define ADC_CFGR2_OVSR_0               (0x1U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000004 */
1851 #define ADC_CFGR2_OVSR_1               (0x2U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000008 */
1852 #define ADC_CFGR2_OVSR_2               (0x4U << ADC_CFGR2_OVSR_Pos)            /*!< 0x00000010 */
1853 
1854 #define ADC_CFGR2_OVSS_Pos             (5U)
1855 #define ADC_CFGR2_OVSS_Msk             (0xFU << ADC_CFGR2_OVSS_Pos)            /*!< 0x000001E0 */
1856 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1857 #define ADC_CFGR2_OVSS_0               (0x1U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000020 */
1858 #define ADC_CFGR2_OVSS_1               (0x2U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000040 */
1859 #define ADC_CFGR2_OVSS_2               (0x4U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000080 */
1860 #define ADC_CFGR2_OVSS_3               (0x8U << ADC_CFGR2_OVSS_Pos)            /*!< 0x00000100 */
1861 
1862 #define ADC_CFGR2_TROVS_Pos            (9U)
1863 #define ADC_CFGR2_TROVS_Msk            (0x1U << ADC_CFGR2_TROVS_Pos)           /*!< 0x00000200 */
1864 #define ADC_CFGR2_TROVS                ADC_CFGR2_TROVS_Msk                     /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1865 #define ADC_CFGR2_ROVSM_Pos            (10U)
1866 #define ADC_CFGR2_ROVSM_Msk            (0x1U << ADC_CFGR2_ROVSM_Pos)           /*!< 0x00000400 */
1867 #define ADC_CFGR2_ROVSM                ADC_CFGR2_ROVSM_Msk                     /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
1868 
1869 /********************  Bit definition for ADC_SMPR1 register  *****************/
1870 #define ADC_SMPR1_SMP0_Pos             (0U)
1871 #define ADC_SMPR1_SMP0_Msk             (0x7U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000007 */
1872 #define ADC_SMPR1_SMP0                 ADC_SMPR1_SMP0_Msk                      /*!< ADC channel 0 sampling time selection  */
1873 #define ADC_SMPR1_SMP0_0               (0x1U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000001 */
1874 #define ADC_SMPR1_SMP0_1               (0x2U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000002 */
1875 #define ADC_SMPR1_SMP0_2               (0x4U << ADC_SMPR1_SMP0_Pos)            /*!< 0x00000004 */
1876 
1877 #define ADC_SMPR1_SMP1_Pos             (3U)
1878 #define ADC_SMPR1_SMP1_Msk             (0x7U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000038 */
1879 #define ADC_SMPR1_SMP1                 ADC_SMPR1_SMP1_Msk                      /*!< ADC channel 1 sampling time selection  */
1880 #define ADC_SMPR1_SMP1_0               (0x1U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000008 */
1881 #define ADC_SMPR1_SMP1_1               (0x2U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000010 */
1882 #define ADC_SMPR1_SMP1_2               (0x4U << ADC_SMPR1_SMP1_Pos)            /*!< 0x00000020 */
1883 
1884 #define ADC_SMPR1_SMP2_Pos             (6U)
1885 #define ADC_SMPR1_SMP2_Msk             (0x7U << ADC_SMPR1_SMP2_Pos)            /*!< 0x000001C0 */
1886 #define ADC_SMPR1_SMP2                 ADC_SMPR1_SMP2_Msk                      /*!< ADC channel 2 sampling time selection  */
1887 #define ADC_SMPR1_SMP2_0               (0x1U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000040 */
1888 #define ADC_SMPR1_SMP2_1               (0x2U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000080 */
1889 #define ADC_SMPR1_SMP2_2               (0x4U << ADC_SMPR1_SMP2_Pos)            /*!< 0x00000100 */
1890 
1891 #define ADC_SMPR1_SMP3_Pos             (9U)
1892 #define ADC_SMPR1_SMP3_Msk             (0x7U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000E00 */
1893 #define ADC_SMPR1_SMP3                 ADC_SMPR1_SMP3_Msk                      /*!< ADC channel 3 sampling time selection  */
1894 #define ADC_SMPR1_SMP3_0               (0x1U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000200 */
1895 #define ADC_SMPR1_SMP3_1               (0x2U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000400 */
1896 #define ADC_SMPR1_SMP3_2               (0x4U << ADC_SMPR1_SMP3_Pos)            /*!< 0x00000800 */
1897 
1898 #define ADC_SMPR1_SMP4_Pos             (12U)
1899 #define ADC_SMPR1_SMP4_Msk             (0x7U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00007000 */
1900 #define ADC_SMPR1_SMP4                 ADC_SMPR1_SMP4_Msk                      /*!< ADC channel 4 sampling time selection  */
1901 #define ADC_SMPR1_SMP4_0               (0x1U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00001000 */
1902 #define ADC_SMPR1_SMP4_1               (0x2U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00002000 */
1903 #define ADC_SMPR1_SMP4_2               (0x4U << ADC_SMPR1_SMP4_Pos)            /*!< 0x00004000 */
1904 
1905 #define ADC_SMPR1_SMP5_Pos             (15U)
1906 #define ADC_SMPR1_SMP5_Msk             (0x7U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00038000 */
1907 #define ADC_SMPR1_SMP5                 ADC_SMPR1_SMP5_Msk                      /*!< ADC channel 5 sampling time selection  */
1908 #define ADC_SMPR1_SMP5_0               (0x1U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00008000 */
1909 #define ADC_SMPR1_SMP5_1               (0x2U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00010000 */
1910 #define ADC_SMPR1_SMP5_2               (0x4U << ADC_SMPR1_SMP5_Pos)            /*!< 0x00020000 */
1911 
1912 #define ADC_SMPR1_SMP6_Pos             (18U)
1913 #define ADC_SMPR1_SMP6_Msk             (0x7U << ADC_SMPR1_SMP6_Pos)            /*!< 0x001C0000 */
1914 #define ADC_SMPR1_SMP6                 ADC_SMPR1_SMP6_Msk                      /*!< ADC channel 6 sampling time selection  */
1915 #define ADC_SMPR1_SMP6_0               (0x1U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00040000 */
1916 #define ADC_SMPR1_SMP6_1               (0x2U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00080000 */
1917 #define ADC_SMPR1_SMP6_2               (0x4U << ADC_SMPR1_SMP6_Pos)            /*!< 0x00100000 */
1918 
1919 #define ADC_SMPR1_SMP7_Pos             (21U)
1920 #define ADC_SMPR1_SMP7_Msk             (0x7U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00E00000 */
1921 #define ADC_SMPR1_SMP7                 ADC_SMPR1_SMP7_Msk                      /*!< ADC channel 7 sampling time selection  */
1922 #define ADC_SMPR1_SMP7_0               (0x1U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00200000 */
1923 #define ADC_SMPR1_SMP7_1               (0x2U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00400000 */
1924 #define ADC_SMPR1_SMP7_2               (0x4U << ADC_SMPR1_SMP7_Pos)            /*!< 0x00800000 */
1925 
1926 #define ADC_SMPR1_SMP8_Pos             (24U)
1927 #define ADC_SMPR1_SMP8_Msk             (0x7U << ADC_SMPR1_SMP8_Pos)            /*!< 0x07000000 */
1928 #define ADC_SMPR1_SMP8                 ADC_SMPR1_SMP8_Msk                      /*!< ADC channel 8 sampling time selection  */
1929 #define ADC_SMPR1_SMP8_0               (0x1U << ADC_SMPR1_SMP8_Pos)            /*!< 0x01000000 */
1930 #define ADC_SMPR1_SMP8_1               (0x2U << ADC_SMPR1_SMP8_Pos)            /*!< 0x02000000 */
1931 #define ADC_SMPR1_SMP8_2               (0x4U << ADC_SMPR1_SMP8_Pos)            /*!< 0x04000000 */
1932 
1933 #define ADC_SMPR1_SMP9_Pos             (27U)
1934 #define ADC_SMPR1_SMP9_Msk             (0x7U << ADC_SMPR1_SMP9_Pos)            /*!< 0x38000000 */
1935 #define ADC_SMPR1_SMP9                 ADC_SMPR1_SMP9_Msk                      /*!< ADC channel 9 sampling time selection  */
1936 #define ADC_SMPR1_SMP9_0               (0x1U << ADC_SMPR1_SMP9_Pos)            /*!< 0x08000000 */
1937 #define ADC_SMPR1_SMP9_1               (0x2U << ADC_SMPR1_SMP9_Pos)            /*!< 0x10000000 */
1938 #define ADC_SMPR1_SMP9_2               (0x4U << ADC_SMPR1_SMP9_Pos)            /*!< 0x20000000 */
1939 
1940 #define ADC_SMPR1_SMPPLUS_Pos          (31U)
1941 #define ADC_SMPR1_SMPPLUS_Msk          (0x1U << ADC_SMPR1_SMPPLUS_Pos)         /*!< 0x80000000 */
1942 #define ADC_SMPR1_SMPPLUS              ADC_SMPR1_SMPPLUS_Msk                   /*!< ADC channels sampling time additional setting */
1943 
1944 /********************  Bit definition for ADC_SMPR2 register  *****************/
1945 #define ADC_SMPR2_SMP10_Pos            (0U)
1946 #define ADC_SMPR2_SMP10_Msk            (0x7U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000007 */
1947 #define ADC_SMPR2_SMP10                ADC_SMPR2_SMP10_Msk                     /*!< ADC channel 10 sampling time selection  */
1948 #define ADC_SMPR2_SMP10_0              (0x1U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000001 */
1949 #define ADC_SMPR2_SMP10_1              (0x2U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000002 */
1950 #define ADC_SMPR2_SMP10_2              (0x4U << ADC_SMPR2_SMP10_Pos)           /*!< 0x00000004 */
1951 
1952 #define ADC_SMPR2_SMP11_Pos            (3U)
1953 #define ADC_SMPR2_SMP11_Msk            (0x7U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000038 */
1954 #define ADC_SMPR2_SMP11                ADC_SMPR2_SMP11_Msk                     /*!< ADC channel 11 sampling time selection  */
1955 #define ADC_SMPR2_SMP11_0              (0x1U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000008 */
1956 #define ADC_SMPR2_SMP11_1              (0x2U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000010 */
1957 #define ADC_SMPR2_SMP11_2              (0x4U << ADC_SMPR2_SMP11_Pos)           /*!< 0x00000020 */
1958 
1959 #define ADC_SMPR2_SMP12_Pos            (6U)
1960 #define ADC_SMPR2_SMP12_Msk            (0x7U << ADC_SMPR2_SMP12_Pos)           /*!< 0x000001C0 */
1961 #define ADC_SMPR2_SMP12                ADC_SMPR2_SMP12_Msk                     /*!< ADC channel 12 sampling time selection  */
1962 #define ADC_SMPR2_SMP12_0              (0x1U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000040 */
1963 #define ADC_SMPR2_SMP12_1              (0x2U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000080 */
1964 #define ADC_SMPR2_SMP12_2              (0x4U << ADC_SMPR2_SMP12_Pos)           /*!< 0x00000100 */
1965 
1966 #define ADC_SMPR2_SMP13_Pos            (9U)
1967 #define ADC_SMPR2_SMP13_Msk            (0x7U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000E00 */
1968 #define ADC_SMPR2_SMP13                ADC_SMPR2_SMP13_Msk                     /*!< ADC channel 13 sampling time selection  */
1969 #define ADC_SMPR2_SMP13_0              (0x1U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000200 */
1970 #define ADC_SMPR2_SMP13_1              (0x2U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000400 */
1971 #define ADC_SMPR2_SMP13_2              (0x4U << ADC_SMPR2_SMP13_Pos)           /*!< 0x00000800 */
1972 
1973 #define ADC_SMPR2_SMP14_Pos            (12U)
1974 #define ADC_SMPR2_SMP14_Msk            (0x7U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00007000 */
1975 #define ADC_SMPR2_SMP14                ADC_SMPR2_SMP14_Msk                     /*!< ADC channel 14 sampling time selection  */
1976 #define ADC_SMPR2_SMP14_0              (0x1U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00001000 */
1977 #define ADC_SMPR2_SMP14_1              (0x2U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00002000 */
1978 #define ADC_SMPR2_SMP14_2              (0x4U << ADC_SMPR2_SMP14_Pos)           /*!< 0x00004000 */
1979 
1980 #define ADC_SMPR2_SMP15_Pos            (15U)
1981 #define ADC_SMPR2_SMP15_Msk            (0x7U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00038000 */
1982 #define ADC_SMPR2_SMP15                ADC_SMPR2_SMP15_Msk                     /*!< ADC channel 15 sampling time selection  */
1983 #define ADC_SMPR2_SMP15_0              (0x1U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00008000 */
1984 #define ADC_SMPR2_SMP15_1              (0x2U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00010000 */
1985 #define ADC_SMPR2_SMP15_2              (0x4U << ADC_SMPR2_SMP15_Pos)           /*!< 0x00020000 */
1986 
1987 #define ADC_SMPR2_SMP16_Pos            (18U)
1988 #define ADC_SMPR2_SMP16_Msk            (0x7U << ADC_SMPR2_SMP16_Pos)           /*!< 0x001C0000 */
1989 #define ADC_SMPR2_SMP16                ADC_SMPR2_SMP16_Msk                     /*!< ADC channel 16 sampling time selection  */
1990 #define ADC_SMPR2_SMP16_0              (0x1U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00040000 */
1991 #define ADC_SMPR2_SMP16_1              (0x2U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00080000 */
1992 #define ADC_SMPR2_SMP16_2              (0x4U << ADC_SMPR2_SMP16_Pos)           /*!< 0x00100000 */
1993 
1994 #define ADC_SMPR2_SMP17_Pos            (21U)
1995 #define ADC_SMPR2_SMP17_Msk            (0x7U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00E00000 */
1996 #define ADC_SMPR2_SMP17                ADC_SMPR2_SMP17_Msk                     /*!< ADC channel 17 sampling time selection  */
1997 #define ADC_SMPR2_SMP17_0              (0x1U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00200000 */
1998 #define ADC_SMPR2_SMP17_1              (0x2U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00400000 */
1999 #define ADC_SMPR2_SMP17_2              (0x4U << ADC_SMPR2_SMP17_Pos)           /*!< 0x00800000 */
2000 
2001 #define ADC_SMPR2_SMP18_Pos            (24U)
2002 #define ADC_SMPR2_SMP18_Msk            (0x7U << ADC_SMPR2_SMP18_Pos)           /*!< 0x07000000 */
2003 #define ADC_SMPR2_SMP18                ADC_SMPR2_SMP18_Msk                     /*!< ADC channel 18 sampling time selection  */
2004 #define ADC_SMPR2_SMP18_0              (0x1U << ADC_SMPR2_SMP18_Pos)           /*!< 0x01000000 */
2005 #define ADC_SMPR2_SMP18_1              (0x2U << ADC_SMPR2_SMP18_Pos)           /*!< 0x02000000 */
2006 #define ADC_SMPR2_SMP18_2              (0x4U << ADC_SMPR2_SMP18_Pos)           /*!< 0x04000000 */
2007 
2008 /********************  Bit definition for ADC_TR1 register  *******************/
2009 #define ADC_TR1_LT1_Pos                (0U)
2010 #define ADC_TR1_LT1_Msk                (0xFFFU << ADC_TR1_LT1_Pos)             /*!< 0x00000FFF */
2011 #define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
2012 #define ADC_TR1_LT1_0                  (0x001U << ADC_TR1_LT1_Pos)             /*!< 0x00000001 */
2013 #define ADC_TR1_LT1_1                  (0x002U << ADC_TR1_LT1_Pos)             /*!< 0x00000002 */
2014 #define ADC_TR1_LT1_2                  (0x004U << ADC_TR1_LT1_Pos)             /*!< 0x00000004 */
2015 #define ADC_TR1_LT1_3                  (0x008U << ADC_TR1_LT1_Pos)             /*!< 0x00000008 */
2016 #define ADC_TR1_LT1_4                  (0x010U << ADC_TR1_LT1_Pos)             /*!< 0x00000010 */
2017 #define ADC_TR1_LT1_5                  (0x020U << ADC_TR1_LT1_Pos)             /*!< 0x00000020 */
2018 #define ADC_TR1_LT1_6                  (0x040U << ADC_TR1_LT1_Pos)             /*!< 0x00000040 */
2019 #define ADC_TR1_LT1_7                  (0x080U << ADC_TR1_LT1_Pos)             /*!< 0x00000080 */
2020 #define ADC_TR1_LT1_8                  (0x100U << ADC_TR1_LT1_Pos)             /*!< 0x00000100 */
2021 #define ADC_TR1_LT1_9                  (0x200U << ADC_TR1_LT1_Pos)             /*!< 0x00000200 */
2022 #define ADC_TR1_LT1_10                 (0x400U << ADC_TR1_LT1_Pos)             /*!< 0x00000400 */
2023 #define ADC_TR1_LT1_11                 (0x800U << ADC_TR1_LT1_Pos)             /*!< 0x00000800 */
2024 
2025 #define ADC_TR1_HT1_Pos                (16U)
2026 #define ADC_TR1_HT1_Msk                (0xFFFU << ADC_TR1_HT1_Pos)             /*!< 0x0FFF0000 */
2027 #define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
2028 #define ADC_TR1_HT1_0                  (0x001U << ADC_TR1_HT1_Pos)             /*!< 0x00010000 */
2029 #define ADC_TR1_HT1_1                  (0x002U << ADC_TR1_HT1_Pos)             /*!< 0x00020000 */
2030 #define ADC_TR1_HT1_2                  (0x004U << ADC_TR1_HT1_Pos)             /*!< 0x00040000 */
2031 #define ADC_TR1_HT1_3                  (0x008U << ADC_TR1_HT1_Pos)             /*!< 0x00080000 */
2032 #define ADC_TR1_HT1_4                  (0x010U << ADC_TR1_HT1_Pos)             /*!< 0x00100000 */
2033 #define ADC_TR1_HT1_5                  (0x020U << ADC_TR1_HT1_Pos)             /*!< 0x00200000 */
2034 #define ADC_TR1_HT1_6                  (0x040U << ADC_TR1_HT1_Pos)             /*!< 0x00400000 */
2035 #define ADC_TR1_HT1_7                  (0x080U << ADC_TR1_HT1_Pos)             /*!< 0x00800000 */
2036 #define ADC_TR1_HT1_8                  (0x100U << ADC_TR1_HT1_Pos)             /*!< 0x01000000 */
2037 #define ADC_TR1_HT1_9                  (0x200U << ADC_TR1_HT1_Pos)             /*!< 0x02000000 */
2038 #define ADC_TR1_HT1_10                 (0x400U << ADC_TR1_HT1_Pos)             /*!< 0x04000000 */
2039 #define ADC_TR1_HT1_11                 (0x800U << ADC_TR1_HT1_Pos)             /*!< 0x08000000 */
2040 
2041 /********************  Bit definition for ADC_TR2 register  *******************/
2042 #define ADC_TR2_LT2_Pos                (0U)
2043 #define ADC_TR2_LT2_Msk                (0xFFU << ADC_TR2_LT2_Pos)              /*!< 0x000000FF */
2044 #define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
2045 #define ADC_TR2_LT2_0                  (0x01U << ADC_TR2_LT2_Pos)              /*!< 0x00000001 */
2046 #define ADC_TR2_LT2_1                  (0x02U << ADC_TR2_LT2_Pos)              /*!< 0x00000002 */
2047 #define ADC_TR2_LT2_2                  (0x04U << ADC_TR2_LT2_Pos)              /*!< 0x00000004 */
2048 #define ADC_TR2_LT2_3                  (0x08U << ADC_TR2_LT2_Pos)              /*!< 0x00000008 */
2049 #define ADC_TR2_LT2_4                  (0x10U << ADC_TR2_LT2_Pos)              /*!< 0x00000010 */
2050 #define ADC_TR2_LT2_5                  (0x20U << ADC_TR2_LT2_Pos)              /*!< 0x00000020 */
2051 #define ADC_TR2_LT2_6                  (0x40U << ADC_TR2_LT2_Pos)              /*!< 0x00000040 */
2052 #define ADC_TR2_LT2_7                  (0x80U << ADC_TR2_LT2_Pos)              /*!< 0x00000080 */
2053 
2054 #define ADC_TR2_HT2_Pos                (16U)
2055 #define ADC_TR2_HT2_Msk                (0xFFU << ADC_TR2_HT2_Pos)              /*!< 0x00FF0000 */
2056 #define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
2057 #define ADC_TR2_HT2_0                  (0x01U << ADC_TR2_HT2_Pos)              /*!< 0x00010000 */
2058 #define ADC_TR2_HT2_1                  (0x02U << ADC_TR2_HT2_Pos)              /*!< 0x00020000 */
2059 #define ADC_TR2_HT2_2                  (0x04U << ADC_TR2_HT2_Pos)              /*!< 0x00040000 */
2060 #define ADC_TR2_HT2_3                  (0x08U << ADC_TR2_HT2_Pos)              /*!< 0x00080000 */
2061 #define ADC_TR2_HT2_4                  (0x10U << ADC_TR2_HT2_Pos)              /*!< 0x00100000 */
2062 #define ADC_TR2_HT2_5                  (0x20U << ADC_TR2_HT2_Pos)              /*!< 0x00200000 */
2063 #define ADC_TR2_HT2_6                  (0x40U << ADC_TR2_HT2_Pos)              /*!< 0x00400000 */
2064 #define ADC_TR2_HT2_7                  (0x80U << ADC_TR2_HT2_Pos)              /*!< 0x00800000 */
2065 
2066 /********************  Bit definition for ADC_TR3 register  *******************/
2067 #define ADC_TR3_LT3_Pos                (0U)
2068 #define ADC_TR3_LT3_Msk                (0xFFU << ADC_TR3_LT3_Pos)              /*!< 0x000000FF */
2069 #define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
2070 #define ADC_TR3_LT3_0                  (0x01U << ADC_TR3_LT3_Pos)              /*!< 0x00000001 */
2071 #define ADC_TR3_LT3_1                  (0x02U << ADC_TR3_LT3_Pos)              /*!< 0x00000002 */
2072 #define ADC_TR3_LT3_2                  (0x04U << ADC_TR3_LT3_Pos)              /*!< 0x00000004 */
2073 #define ADC_TR3_LT3_3                  (0x08U << ADC_TR3_LT3_Pos)              /*!< 0x00000008 */
2074 #define ADC_TR3_LT3_4                  (0x10U << ADC_TR3_LT3_Pos)              /*!< 0x00000010 */
2075 #define ADC_TR3_LT3_5                  (0x20U << ADC_TR3_LT3_Pos)              /*!< 0x00000020 */
2076 #define ADC_TR3_LT3_6                  (0x40U << ADC_TR3_LT3_Pos)              /*!< 0x00000040 */
2077 #define ADC_TR3_LT3_7                  (0x80U << ADC_TR3_LT3_Pos)              /*!< 0x00000080 */
2078 
2079 #define ADC_TR3_HT3_Pos                (16U)
2080 #define ADC_TR3_HT3_Msk                (0xFFU << ADC_TR3_HT3_Pos)              /*!< 0x00FF0000 */
2081 #define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
2082 #define ADC_TR3_HT3_0                  (0x01U << ADC_TR3_HT3_Pos)              /*!< 0x00010000 */
2083 #define ADC_TR3_HT3_1                  (0x02U << ADC_TR3_HT3_Pos)              /*!< 0x00020000 */
2084 #define ADC_TR3_HT3_2                  (0x04U << ADC_TR3_HT3_Pos)              /*!< 0x00040000 */
2085 #define ADC_TR3_HT3_3                  (0x08U << ADC_TR3_HT3_Pos)              /*!< 0x00080000 */
2086 #define ADC_TR3_HT3_4                  (0x10U << ADC_TR3_HT3_Pos)              /*!< 0x00100000 */
2087 #define ADC_TR3_HT3_5                  (0x20U << ADC_TR3_HT3_Pos)              /*!< 0x00200000 */
2088 #define ADC_TR3_HT3_6                  (0x40U << ADC_TR3_HT3_Pos)              /*!< 0x00400000 */
2089 #define ADC_TR3_HT3_7                  (0x80U << ADC_TR3_HT3_Pos)              /*!< 0x00800000 */
2090 
2091 /********************  Bit definition for ADC_SQR1 register  ******************/
2092 #define ADC_SQR1_L_Pos                 (0U)
2093 #define ADC_SQR1_L_Msk                 (0xFU << ADC_SQR1_L_Pos)                /*!< 0x0000000F */
2094 #define ADC_SQR1_L                     ADC_SQR1_L_Msk                          /*!< ADC group regular sequencer scan length */
2095 #define ADC_SQR1_L_0                   (0x1U << ADC_SQR1_L_Pos)                /*!< 0x00000001 */
2096 #define ADC_SQR1_L_1                   (0x2U << ADC_SQR1_L_Pos)                /*!< 0x00000002 */
2097 #define ADC_SQR1_L_2                   (0x4U << ADC_SQR1_L_Pos)                /*!< 0x00000004 */
2098 #define ADC_SQR1_L_3                   (0x8U << ADC_SQR1_L_Pos)                /*!< 0x00000008 */
2099 
2100 #define ADC_SQR1_SQ1_Pos               (6U)
2101 #define ADC_SQR1_SQ1_Msk               (0x1FU << ADC_SQR1_SQ1_Pos)             /*!< 0x000007C0 */
2102 #define ADC_SQR1_SQ1                   ADC_SQR1_SQ1_Msk                        /*!< ADC group regular sequencer rank 1 */
2103 #define ADC_SQR1_SQ1_0                 (0x01U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000040 */
2104 #define ADC_SQR1_SQ1_1                 (0x02U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000080 */
2105 #define ADC_SQR1_SQ1_2                 (0x04U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000100 */
2106 #define ADC_SQR1_SQ1_3                 (0x08U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000200 */
2107 #define ADC_SQR1_SQ1_4                 (0x10U << ADC_SQR1_SQ1_Pos)             /*!< 0x00000400 */
2108 
2109 #define ADC_SQR1_SQ2_Pos               (12U)
2110 #define ADC_SQR1_SQ2_Msk               (0x1FU << ADC_SQR1_SQ2_Pos)             /*!< 0x0001F000 */
2111 #define ADC_SQR1_SQ2                   ADC_SQR1_SQ2_Msk                        /*!< ADC group regular sequencer rank 2 */
2112 #define ADC_SQR1_SQ2_0                 (0x01U << ADC_SQR1_SQ2_Pos)             /*!< 0x00001000 */
2113 #define ADC_SQR1_SQ2_1                 (0x02U << ADC_SQR1_SQ2_Pos)             /*!< 0x00002000 */
2114 #define ADC_SQR1_SQ2_2                 (0x04U << ADC_SQR1_SQ2_Pos)             /*!< 0x00004000 */
2115 #define ADC_SQR1_SQ2_3                 (0x08U << ADC_SQR1_SQ2_Pos)             /*!< 0x00008000 */
2116 #define ADC_SQR1_SQ2_4                 (0x10U << ADC_SQR1_SQ2_Pos)             /*!< 0x00010000 */
2117 
2118 #define ADC_SQR1_SQ3_Pos               (18U)
2119 #define ADC_SQR1_SQ3_Msk               (0x1FU << ADC_SQR1_SQ3_Pos)             /*!< 0x007C0000 */
2120 #define ADC_SQR1_SQ3                   ADC_SQR1_SQ3_Msk                        /*!< ADC group regular sequencer rank 3 */
2121 #define ADC_SQR1_SQ3_0                 (0x01U << ADC_SQR1_SQ3_Pos)             /*!< 0x00040000 */
2122 #define ADC_SQR1_SQ3_1                 (0x02U << ADC_SQR1_SQ3_Pos)             /*!< 0x00080000 */
2123 #define ADC_SQR1_SQ3_2                 (0x04U << ADC_SQR1_SQ3_Pos)             /*!< 0x00100000 */
2124 #define ADC_SQR1_SQ3_3                 (0x08U << ADC_SQR1_SQ3_Pos)             /*!< 0x00200000 */
2125 #define ADC_SQR1_SQ3_4                 (0x10U << ADC_SQR1_SQ3_Pos)             /*!< 0x00400000 */
2126 
2127 #define ADC_SQR1_SQ4_Pos               (24U)
2128 #define ADC_SQR1_SQ4_Msk               (0x1FU << ADC_SQR1_SQ4_Pos)             /*!< 0x1F000000 */
2129 #define ADC_SQR1_SQ4                   ADC_SQR1_SQ4_Msk                        /*!< ADC group regular sequencer rank 4 */
2130 #define ADC_SQR1_SQ4_0                 (0x01U << ADC_SQR1_SQ4_Pos)             /*!< 0x01000000 */
2131 #define ADC_SQR1_SQ4_1                 (0x02U << ADC_SQR1_SQ4_Pos)             /*!< 0x02000000 */
2132 #define ADC_SQR1_SQ4_2                 (0x04U << ADC_SQR1_SQ4_Pos)             /*!< 0x04000000 */
2133 #define ADC_SQR1_SQ4_3                 (0x08U << ADC_SQR1_SQ4_Pos)             /*!< 0x08000000 */
2134 #define ADC_SQR1_SQ4_4                 (0x10U << ADC_SQR1_SQ4_Pos)             /*!< 0x10000000 */
2135 
2136 /********************  Bit definition for ADC_SQR2 register  ******************/
2137 #define ADC_SQR2_SQ5_Pos               (0U)
2138 #define ADC_SQR2_SQ5_Msk               (0x1FU << ADC_SQR2_SQ5_Pos)             /*!< 0x0000001F */
2139 #define ADC_SQR2_SQ5                   ADC_SQR2_SQ5_Msk                        /*!< ADC group regular sequencer rank 5 */
2140 #define ADC_SQR2_SQ5_0                 (0x01U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000001 */
2141 #define ADC_SQR2_SQ5_1                 (0x02U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000002 */
2142 #define ADC_SQR2_SQ5_2                 (0x04U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000004 */
2143 #define ADC_SQR2_SQ5_3                 (0x08U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000008 */
2144 #define ADC_SQR2_SQ5_4                 (0x10U << ADC_SQR2_SQ5_Pos)             /*!< 0x00000010 */
2145 
2146 #define ADC_SQR2_SQ6_Pos               (6U)
2147 #define ADC_SQR2_SQ6_Msk               (0x1FU << ADC_SQR2_SQ6_Pos)             /*!< 0x000007C0 */
2148 #define ADC_SQR2_SQ6                   ADC_SQR2_SQ6_Msk                        /*!< ADC group regular sequencer rank 6 */
2149 #define ADC_SQR2_SQ6_0                 (0x01U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000040 */
2150 #define ADC_SQR2_SQ6_1                 (0x02U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000080 */
2151 #define ADC_SQR2_SQ6_2                 (0x04U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000100 */
2152 #define ADC_SQR2_SQ6_3                 (0x08U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000200 */
2153 #define ADC_SQR2_SQ6_4                 (0x10U << ADC_SQR2_SQ6_Pos)             /*!< 0x00000400 */
2154 
2155 #define ADC_SQR2_SQ7_Pos               (12U)
2156 #define ADC_SQR2_SQ7_Msk               (0x1FU << ADC_SQR2_SQ7_Pos)             /*!< 0x0001F000 */
2157 #define ADC_SQR2_SQ7                   ADC_SQR2_SQ7_Msk                        /*!< ADC group regular sequencer rank 7 */
2158 #define ADC_SQR2_SQ7_0                 (0x01U << ADC_SQR2_SQ7_Pos)             /*!< 0x00001000 */
2159 #define ADC_SQR2_SQ7_1                 (0x02U << ADC_SQR2_SQ7_Pos)             /*!< 0x00002000 */
2160 #define ADC_SQR2_SQ7_2                 (0x04U << ADC_SQR2_SQ7_Pos)             /*!< 0x00004000 */
2161 #define ADC_SQR2_SQ7_3                 (0x08U << ADC_SQR2_SQ7_Pos)             /*!< 0x00008000 */
2162 #define ADC_SQR2_SQ7_4                 (0x10U << ADC_SQR2_SQ7_Pos)             /*!< 0x00010000 */
2163 
2164 #define ADC_SQR2_SQ8_Pos               (18U)
2165 #define ADC_SQR2_SQ8_Msk               (0x1FU << ADC_SQR2_SQ8_Pos)             /*!< 0x007C0000 */
2166 #define ADC_SQR2_SQ8                   ADC_SQR2_SQ8_Msk                        /*!< ADC group regular sequencer rank 8 */
2167 #define ADC_SQR2_SQ8_0                 (0x01U << ADC_SQR2_SQ8_Pos)             /*!< 0x00040000 */
2168 #define ADC_SQR2_SQ8_1                 (0x02U << ADC_SQR2_SQ8_Pos)             /*!< 0x00080000 */
2169 #define ADC_SQR2_SQ8_2                 (0x04U << ADC_SQR2_SQ8_Pos)             /*!< 0x00100000 */
2170 #define ADC_SQR2_SQ8_3                 (0x08U << ADC_SQR2_SQ8_Pos)             /*!< 0x00200000 */
2171 #define ADC_SQR2_SQ8_4                 (0x10U << ADC_SQR2_SQ8_Pos)             /*!< 0x00400000 */
2172 
2173 #define ADC_SQR2_SQ9_Pos               (24U)
2174 #define ADC_SQR2_SQ9_Msk               (0x1FU << ADC_SQR2_SQ9_Pos)             /*!< 0x1F000000 */
2175 #define ADC_SQR2_SQ9                   ADC_SQR2_SQ9_Msk                        /*!< ADC group regular sequencer rank 9 */
2176 #define ADC_SQR2_SQ9_0                 (0x01U << ADC_SQR2_SQ9_Pos)             /*!< 0x01000000 */
2177 #define ADC_SQR2_SQ9_1                 (0x02U << ADC_SQR2_SQ9_Pos)             /*!< 0x02000000 */
2178 #define ADC_SQR2_SQ9_2                 (0x04U << ADC_SQR2_SQ9_Pos)             /*!< 0x04000000 */
2179 #define ADC_SQR2_SQ9_3                 (0x08U << ADC_SQR2_SQ9_Pos)             /*!< 0x08000000 */
2180 #define ADC_SQR2_SQ9_4                 (0x10U << ADC_SQR2_SQ9_Pos)             /*!< 0x10000000 */
2181 
2182 /********************  Bit definition for ADC_SQR3 register  ******************/
2183 #define ADC_SQR3_SQ10_Pos              (0U)
2184 #define ADC_SQR3_SQ10_Msk              (0x1FU << ADC_SQR3_SQ10_Pos)            /*!< 0x0000001F */
2185 #define ADC_SQR3_SQ10                  ADC_SQR3_SQ10_Msk                       /*!< ADC group regular sequencer rank 10 */
2186 #define ADC_SQR3_SQ10_0                (0x01U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000001 */
2187 #define ADC_SQR3_SQ10_1                (0x02U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000002 */
2188 #define ADC_SQR3_SQ10_2                (0x04U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000004 */
2189 #define ADC_SQR3_SQ10_3                (0x08U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000008 */
2190 #define ADC_SQR3_SQ10_4                (0x10U << ADC_SQR3_SQ10_Pos)            /*!< 0x00000010 */
2191 
2192 #define ADC_SQR3_SQ11_Pos              (6U)
2193 #define ADC_SQR3_SQ11_Msk              (0x1FU << ADC_SQR3_SQ11_Pos)            /*!< 0x000007C0 */
2194 #define ADC_SQR3_SQ11                  ADC_SQR3_SQ11_Msk                       /*!< ADC group regular sequencer rank 11 */
2195 #define ADC_SQR3_SQ11_0                (0x01U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000040 */
2196 #define ADC_SQR3_SQ11_1                (0x02U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000080 */
2197 #define ADC_SQR3_SQ11_2                (0x04U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000100 */
2198 #define ADC_SQR3_SQ11_3                (0x08U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000200 */
2199 #define ADC_SQR3_SQ11_4                (0x10U << ADC_SQR3_SQ11_Pos)            /*!< 0x00000400 */
2200 
2201 #define ADC_SQR3_SQ12_Pos              (12U)
2202 #define ADC_SQR3_SQ12_Msk              (0x1FU << ADC_SQR3_SQ12_Pos)            /*!< 0x0001F000 */
2203 #define ADC_SQR3_SQ12                  ADC_SQR3_SQ12_Msk                       /*!< ADC group regular sequencer rank 12 */
2204 #define ADC_SQR3_SQ12_0                (0x01U << ADC_SQR3_SQ12_Pos)            /*!< 0x00001000 */
2205 #define ADC_SQR3_SQ12_1                (0x02U << ADC_SQR3_SQ12_Pos)            /*!< 0x00002000 */
2206 #define ADC_SQR3_SQ12_2                (0x04U << ADC_SQR3_SQ12_Pos)            /*!< 0x00004000 */
2207 #define ADC_SQR3_SQ12_3                (0x08U << ADC_SQR3_SQ12_Pos)            /*!< 0x00008000 */
2208 #define ADC_SQR3_SQ12_4                (0x10U << ADC_SQR3_SQ12_Pos)            /*!< 0x00010000 */
2209 
2210 #define ADC_SQR3_SQ13_Pos              (18U)
2211 #define ADC_SQR3_SQ13_Msk              (0x1FU << ADC_SQR3_SQ13_Pos)            /*!< 0x007C0000 */
2212 #define ADC_SQR3_SQ13                  ADC_SQR3_SQ13_Msk                       /*!< ADC group regular sequencer rank 13 */
2213 #define ADC_SQR3_SQ13_0                (0x01U << ADC_SQR3_SQ13_Pos)            /*!< 0x00040000 */
2214 #define ADC_SQR3_SQ13_1                (0x02U << ADC_SQR3_SQ13_Pos)            /*!< 0x00080000 */
2215 #define ADC_SQR3_SQ13_2                (0x04U << ADC_SQR3_SQ13_Pos)            /*!< 0x00100000 */
2216 #define ADC_SQR3_SQ13_3                (0x08U << ADC_SQR3_SQ13_Pos)            /*!< 0x00200000 */
2217 #define ADC_SQR3_SQ13_4                (0x10U << ADC_SQR3_SQ13_Pos)            /*!< 0x00400000 */
2218 
2219 #define ADC_SQR3_SQ14_Pos              (24U)
2220 #define ADC_SQR3_SQ14_Msk              (0x1FU << ADC_SQR3_SQ14_Pos)            /*!< 0x1F000000 */
2221 #define ADC_SQR3_SQ14                  ADC_SQR3_SQ14_Msk                       /*!< ADC group regular sequencer rank 14 */
2222 #define ADC_SQR3_SQ14_0                (0x01U << ADC_SQR3_SQ14_Pos)            /*!< 0x01000000 */
2223 #define ADC_SQR3_SQ14_1                (0x02U << ADC_SQR3_SQ14_Pos)            /*!< 0x02000000 */
2224 #define ADC_SQR3_SQ14_2                (0x04U << ADC_SQR3_SQ14_Pos)            /*!< 0x04000000 */
2225 #define ADC_SQR3_SQ14_3                (0x08U << ADC_SQR3_SQ14_Pos)            /*!< 0x08000000 */
2226 #define ADC_SQR3_SQ14_4                (0x10U << ADC_SQR3_SQ14_Pos)            /*!< 0x10000000 */
2227 
2228 /********************  Bit definition for ADC_SQR4 register  ******************/
2229 #define ADC_SQR4_SQ15_Pos              (0U)
2230 #define ADC_SQR4_SQ15_Msk              (0x1FU << ADC_SQR4_SQ15_Pos)            /*!< 0x0000001F */
2231 #define ADC_SQR4_SQ15                  ADC_SQR4_SQ15_Msk                       /*!< ADC group regular sequencer rank 15 */
2232 #define ADC_SQR4_SQ15_0                (0x01U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000001 */
2233 #define ADC_SQR4_SQ15_1                (0x02U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000002 */
2234 #define ADC_SQR4_SQ15_2                (0x04U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000004 */
2235 #define ADC_SQR4_SQ15_3                (0x08U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000008 */
2236 #define ADC_SQR4_SQ15_4                (0x10U << ADC_SQR4_SQ15_Pos)            /*!< 0x00000010 */
2237 
2238 #define ADC_SQR4_SQ16_Pos              (6U)
2239 #define ADC_SQR4_SQ16_Msk              (0x1FU << ADC_SQR4_SQ16_Pos)            /*!< 0x000007C0 */
2240 #define ADC_SQR4_SQ16                  ADC_SQR4_SQ16_Msk                       /*!< ADC group regular sequencer rank 16 */
2241 #define ADC_SQR4_SQ16_0                (0x01U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000040 */
2242 #define ADC_SQR4_SQ16_1                (0x02U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000080 */
2243 #define ADC_SQR4_SQ16_2                (0x04U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000100 */
2244 #define ADC_SQR4_SQ16_3                (0x08U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000200 */
2245 #define ADC_SQR4_SQ16_4                (0x10U << ADC_SQR4_SQ16_Pos)            /*!< 0x00000400 */
2246 
2247 /********************  Bit definition for ADC_DR register  ********************/
2248 #define ADC_DR_RDATA_Pos               (0U)
2249 #define ADC_DR_RDATA_Msk               (0xFFFFU << ADC_DR_RDATA_Pos)           /*!< 0x0000FFFF */
2250 #define ADC_DR_RDATA                   ADC_DR_RDATA_Msk                        /*!< ADC group regular conversion data */
2251 #define ADC_DR_RDATA_0                 (0x0001U << ADC_DR_RDATA_Pos)           /*!< 0x00000001 */
2252 #define ADC_DR_RDATA_1                 (0x0002U << ADC_DR_RDATA_Pos)           /*!< 0x00000002 */
2253 #define ADC_DR_RDATA_2                 (0x0004U << ADC_DR_RDATA_Pos)           /*!< 0x00000004 */
2254 #define ADC_DR_RDATA_3                 (0x0008U << ADC_DR_RDATA_Pos)           /*!< 0x00000008 */
2255 #define ADC_DR_RDATA_4                 (0x0010U << ADC_DR_RDATA_Pos)           /*!< 0x00000010 */
2256 #define ADC_DR_RDATA_5                 (0x0020U << ADC_DR_RDATA_Pos)           /*!< 0x00000020 */
2257 #define ADC_DR_RDATA_6                 (0x0040U << ADC_DR_RDATA_Pos)           /*!< 0x00000040 */
2258 #define ADC_DR_RDATA_7                 (0x0080U << ADC_DR_RDATA_Pos)           /*!< 0x00000080 */
2259 #define ADC_DR_RDATA_8                 (0x0100U << ADC_DR_RDATA_Pos)           /*!< 0x00000100 */
2260 #define ADC_DR_RDATA_9                 (0x0200U << ADC_DR_RDATA_Pos)           /*!< 0x00000200 */
2261 #define ADC_DR_RDATA_10                (0x0400U << ADC_DR_RDATA_Pos)           /*!< 0x00000400 */
2262 #define ADC_DR_RDATA_11                (0x0800U << ADC_DR_RDATA_Pos)           /*!< 0x00000800 */
2263 #define ADC_DR_RDATA_12                (0x1000U << ADC_DR_RDATA_Pos)           /*!< 0x00001000 */
2264 #define ADC_DR_RDATA_13                (0x2000U << ADC_DR_RDATA_Pos)           /*!< 0x00002000 */
2265 #define ADC_DR_RDATA_14                (0x4000U << ADC_DR_RDATA_Pos)           /*!< 0x00004000 */
2266 #define ADC_DR_RDATA_15                (0x8000U << ADC_DR_RDATA_Pos)           /*!< 0x00008000 */
2267 
2268 /********************  Bit definition for ADC_JSQR register  ******************/
2269 #define ADC_JSQR_JL_Pos                (0U)
2270 #define ADC_JSQR_JL_Msk                (0x3U << ADC_JSQR_JL_Pos)               /*!< 0x00000003 */
2271 #define ADC_JSQR_JL                    ADC_JSQR_JL_Msk                         /*!< ADC group injected sequencer scan length */
2272 #define ADC_JSQR_JL_0                  (0x1U << ADC_JSQR_JL_Pos)               /*!< 0x00000001 */
2273 #define ADC_JSQR_JL_1                  (0x2U << ADC_JSQR_JL_Pos)               /*!< 0x00000002 */
2274 
2275 #define ADC_JSQR_JEXTSEL_Pos           (2U)
2276 #define ADC_JSQR_JEXTSEL_Msk           (0xFU << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x0000003C */
2277 #define ADC_JSQR_JEXTSEL               ADC_JSQR_JEXTSEL_Msk                    /*!< ADC group injected external trigger source */
2278 #define ADC_JSQR_JEXTSEL_0             (0x1U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000004 */
2279 #define ADC_JSQR_JEXTSEL_1             (0x2U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000008 */
2280 #define ADC_JSQR_JEXTSEL_2             (0x4U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000010 */
2281 #define ADC_JSQR_JEXTSEL_3             (0x8U << ADC_JSQR_JEXTSEL_Pos)          /*!< 0x00000020 */
2282 
2283 #define ADC_JSQR_JEXTEN_Pos            (6U)
2284 #define ADC_JSQR_JEXTEN_Msk            (0x3U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x000000C0 */
2285 #define ADC_JSQR_JEXTEN                ADC_JSQR_JEXTEN_Msk                     /*!< ADC group injected external trigger polarity */
2286 #define ADC_JSQR_JEXTEN_0              (0x1U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000040 */
2287 #define ADC_JSQR_JEXTEN_1              (0x2U << ADC_JSQR_JEXTEN_Pos)           /*!< 0x00000080 */
2288 
2289 #define ADC_JSQR_JSQ1_Pos              (8U)
2290 #define ADC_JSQR_JSQ1_Msk              (0x1FU << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001F00 */
2291 #define ADC_JSQR_JSQ1                  ADC_JSQR_JSQ1_Msk                       /*!< ADC group injected sequencer rank 1 */
2292 #define ADC_JSQR_JSQ1_0                (0x01U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000100 */
2293 #define ADC_JSQR_JSQ1_1                (0x02U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000200 */
2294 #define ADC_JSQR_JSQ1_2                (0x04U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000400 */
2295 #define ADC_JSQR_JSQ1_3                (0x08U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00000800 */
2296 #define ADC_JSQR_JSQ1_4                (0x10U << ADC_JSQR_JSQ1_Pos)            /*!< 0x00001000 */
2297 
2298 #define ADC_JSQR_JSQ2_Pos              (14U)
2299 #define ADC_JSQR_JSQ2_Msk              (0x1FU << ADC_JSQR_JSQ2_Pos)            /*!< 0x0007C000 */
2300 #define ADC_JSQR_JSQ2                  ADC_JSQR_JSQ2_Msk                       /*!< ADC group injected sequencer rank 2 */
2301 #define ADC_JSQR_JSQ2_0                (0x01U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00004000 */
2302 #define ADC_JSQR_JSQ2_1                (0x02U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00008000 */
2303 #define ADC_JSQR_JSQ2_2                (0x04U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00010000 */
2304 #define ADC_JSQR_JSQ2_3                (0x08U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00020000 */
2305 #define ADC_JSQR_JSQ2_4                (0x10U << ADC_JSQR_JSQ2_Pos)            /*!< 0x00040000 */
2306 
2307 #define ADC_JSQR_JSQ3_Pos              (20U)
2308 #define ADC_JSQR_JSQ3_Msk              (0x1FU << ADC_JSQR_JSQ3_Pos)            /*!< 0x01F00000 */
2309 #define ADC_JSQR_JSQ3                  ADC_JSQR_JSQ3_Msk                       /*!< ADC group injected sequencer rank 3 */
2310 #define ADC_JSQR_JSQ3_0                (0x01U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00100000 */
2311 #define ADC_JSQR_JSQ3_1                (0x02U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00200000 */
2312 #define ADC_JSQR_JSQ3_2                (0x04U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00400000 */
2313 #define ADC_JSQR_JSQ3_3                (0x08U << ADC_JSQR_JSQ3_Pos)            /*!< 0x00800000 */
2314 #define ADC_JSQR_JSQ3_4                (0x10U << ADC_JSQR_JSQ3_Pos)            /*!< 0x01000000 */
2315 
2316 #define ADC_JSQR_JSQ4_Pos              (26U)
2317 #define ADC_JSQR_JSQ4_Msk              (0x1FU << ADC_JSQR_JSQ4_Pos)            /*!< 0x7C000000 */
2318 #define ADC_JSQR_JSQ4                  ADC_JSQR_JSQ4_Msk                       /*!< ADC group injected sequencer rank 4 */
2319 #define ADC_JSQR_JSQ4_0                (0x01U << ADC_JSQR_JSQ4_Pos)            /*!< 0x04000000 */
2320 #define ADC_JSQR_JSQ4_1                (0x02U << ADC_JSQR_JSQ4_Pos)            /*!< 0x08000000 */
2321 #define ADC_JSQR_JSQ4_2                (0x04U << ADC_JSQR_JSQ4_Pos)            /*!< 0x10000000 */
2322 #define ADC_JSQR_JSQ4_3                (0x08U << ADC_JSQR_JSQ4_Pos)            /*!< 0x20000000 */
2323 #define ADC_JSQR_JSQ4_4                (0x10U << ADC_JSQR_JSQ4_Pos)            /*!< 0x40000000 */
2324 
2325 /********************  Bit definition for ADC_OFR1 register  ******************/
2326 #define ADC_OFR1_OFFSET1_Pos           (0U)
2327 #define ADC_OFR1_OFFSET1_Msk           (0xFFFU << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000FFF */
2328 #define ADC_OFR1_OFFSET1               ADC_OFR1_OFFSET1_Msk                    /*!< ADC offset number 1 offset level */
2329 #define ADC_OFR1_OFFSET1_0             (0x001U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000001 */
2330 #define ADC_OFR1_OFFSET1_1             (0x002U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000002 */
2331 #define ADC_OFR1_OFFSET1_2             (0x004U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000004 */
2332 #define ADC_OFR1_OFFSET1_3             (0x008U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000008 */
2333 #define ADC_OFR1_OFFSET1_4             (0x010U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000010 */
2334 #define ADC_OFR1_OFFSET1_5             (0x020U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000020 */
2335 #define ADC_OFR1_OFFSET1_6             (0x040U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000040 */
2336 #define ADC_OFR1_OFFSET1_7             (0x080U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000080 */
2337 #define ADC_OFR1_OFFSET1_8             (0x100U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000100 */
2338 #define ADC_OFR1_OFFSET1_9             (0x200U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000200 */
2339 #define ADC_OFR1_OFFSET1_10            (0x400U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000400 */
2340 #define ADC_OFR1_OFFSET1_11            (0x800U << ADC_OFR1_OFFSET1_Pos)        /*!< 0x00000800 */
2341 
2342 #define ADC_OFR1_OFFSET1_CH_Pos        (26U)
2343 #define ADC_OFR1_OFFSET1_CH_Msk        (0x1FU << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x7C000000 */
2344 #define ADC_OFR1_OFFSET1_CH            ADC_OFR1_OFFSET1_CH_Msk                 /*!< ADC offset number 1 channel selection */
2345 #define ADC_OFR1_OFFSET1_CH_0          (0x01U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x04000000 */
2346 #define ADC_OFR1_OFFSET1_CH_1          (0x02U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x08000000 */
2347 #define ADC_OFR1_OFFSET1_CH_2          (0x04U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x10000000 */
2348 #define ADC_OFR1_OFFSET1_CH_3          (0x08U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x20000000 */
2349 #define ADC_OFR1_OFFSET1_CH_4          (0x10U << ADC_OFR1_OFFSET1_CH_Pos)      /*!< 0x40000000 */
2350 
2351 #define ADC_OFR1_OFFSET1_EN_Pos        (31U)
2352 #define ADC_OFR1_OFFSET1_EN_Msk        (0x1U << ADC_OFR1_OFFSET1_EN_Pos)       /*!< 0x80000000 */
2353 #define ADC_OFR1_OFFSET1_EN            ADC_OFR1_OFFSET1_EN_Msk                 /*!< ADC offset number 1 enable */
2354 
2355 /********************  Bit definition for ADC_OFR2 register  ******************/
2356 #define ADC_OFR2_OFFSET2_Pos           (0U)
2357 #define ADC_OFR2_OFFSET2_Msk           (0xFFFU << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000FFF */
2358 #define ADC_OFR2_OFFSET2               ADC_OFR2_OFFSET2_Msk                    /*!< ADC offset number 2 offset level */
2359 #define ADC_OFR2_OFFSET2_0             (0x001U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000001 */
2360 #define ADC_OFR2_OFFSET2_1             (0x002U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000002 */
2361 #define ADC_OFR2_OFFSET2_2             (0x004U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000004 */
2362 #define ADC_OFR2_OFFSET2_3             (0x008U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000008 */
2363 #define ADC_OFR2_OFFSET2_4             (0x010U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000010 */
2364 #define ADC_OFR2_OFFSET2_5             (0x020U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000020 */
2365 #define ADC_OFR2_OFFSET2_6             (0x040U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000040 */
2366 #define ADC_OFR2_OFFSET2_7             (0x080U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000080 */
2367 #define ADC_OFR2_OFFSET2_8             (0x100U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000100 */
2368 #define ADC_OFR2_OFFSET2_9             (0x200U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000200 */
2369 #define ADC_OFR2_OFFSET2_10            (0x400U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000400 */
2370 #define ADC_OFR2_OFFSET2_11            (0x800U << ADC_OFR2_OFFSET2_Pos)        /*!< 0x00000800 */
2371 
2372 #define ADC_OFR2_OFFSET2_CH_Pos        (26U)
2373 #define ADC_OFR2_OFFSET2_CH_Msk        (0x1FU << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x7C000000 */
2374 #define ADC_OFR2_OFFSET2_CH            ADC_OFR2_OFFSET2_CH_Msk                 /*!< ADC offset number 2 channel selection */
2375 #define ADC_OFR2_OFFSET2_CH_0          (0x01U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x04000000 */
2376 #define ADC_OFR2_OFFSET2_CH_1          (0x02U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x08000000 */
2377 #define ADC_OFR2_OFFSET2_CH_2          (0x04U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x10000000 */
2378 #define ADC_OFR2_OFFSET2_CH_3          (0x08U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x20000000 */
2379 #define ADC_OFR2_OFFSET2_CH_4          (0x10U << ADC_OFR2_OFFSET2_CH_Pos)      /*!< 0x40000000 */
2380 
2381 #define ADC_OFR2_OFFSET2_EN_Pos        (31U)
2382 #define ADC_OFR2_OFFSET2_EN_Msk        (0x1U << ADC_OFR2_OFFSET2_EN_Pos)       /*!< 0x80000000 */
2383 #define ADC_OFR2_OFFSET2_EN            ADC_OFR2_OFFSET2_EN_Msk                 /*!< ADC offset number 2 enable */
2384 
2385 /********************  Bit definition for ADC_OFR3 register  ******************/
2386 #define ADC_OFR3_OFFSET3_Pos           (0U)
2387 #define ADC_OFR3_OFFSET3_Msk           (0xFFFU << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000FFF */
2388 #define ADC_OFR3_OFFSET3               ADC_OFR3_OFFSET3_Msk                    /*!< ADC offset number 3 offset level */
2389 #define ADC_OFR3_OFFSET3_0             (0x001U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000001 */
2390 #define ADC_OFR3_OFFSET3_1             (0x002U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000002 */
2391 #define ADC_OFR3_OFFSET3_2             (0x004U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000004 */
2392 #define ADC_OFR3_OFFSET3_3             (0x008U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000008 */
2393 #define ADC_OFR3_OFFSET3_4             (0x010U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000010 */
2394 #define ADC_OFR3_OFFSET3_5             (0x020U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000020 */
2395 #define ADC_OFR3_OFFSET3_6             (0x040U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000040 */
2396 #define ADC_OFR3_OFFSET3_7             (0x080U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000080 */
2397 #define ADC_OFR3_OFFSET3_8             (0x100U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000100 */
2398 #define ADC_OFR3_OFFSET3_9             (0x200U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000200 */
2399 #define ADC_OFR3_OFFSET3_10            (0x400U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000400 */
2400 #define ADC_OFR3_OFFSET3_11            (0x800U << ADC_OFR3_OFFSET3_Pos)        /*!< 0x00000800 */
2401 
2402 #define ADC_OFR3_OFFSET3_CH_Pos        (26U)
2403 #define ADC_OFR3_OFFSET3_CH_Msk        (0x1FU << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x7C000000 */
2404 #define ADC_OFR3_OFFSET3_CH            ADC_OFR3_OFFSET3_CH_Msk                 /*!< ADC offset number 3 channel selection */
2405 #define ADC_OFR3_OFFSET3_CH_0          (0x01U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x04000000 */
2406 #define ADC_OFR3_OFFSET3_CH_1          (0x02U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x08000000 */
2407 #define ADC_OFR3_OFFSET3_CH_2          (0x04U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x10000000 */
2408 #define ADC_OFR3_OFFSET3_CH_3          (0x08U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x20000000 */
2409 #define ADC_OFR3_OFFSET3_CH_4          (0x10U << ADC_OFR3_OFFSET3_CH_Pos)      /*!< 0x40000000 */
2410 
2411 #define ADC_OFR3_OFFSET3_EN_Pos        (31U)
2412 #define ADC_OFR3_OFFSET3_EN_Msk        (0x1U << ADC_OFR3_OFFSET3_EN_Pos)       /*!< 0x80000000 */
2413 #define ADC_OFR3_OFFSET3_EN            ADC_OFR3_OFFSET3_EN_Msk                 /*!< ADC offset number 3 enable */
2414 
2415 /********************  Bit definition for ADC_OFR4 register  ******************/
2416 #define ADC_OFR4_OFFSET4_Pos           (0U)
2417 #define ADC_OFR4_OFFSET4_Msk           (0xFFFU << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000FFF */
2418 #define ADC_OFR4_OFFSET4               ADC_OFR4_OFFSET4_Msk                    /*!< ADC offset number 4 offset level */
2419 #define ADC_OFR4_OFFSET4_0             (0x001U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000001 */
2420 #define ADC_OFR4_OFFSET4_1             (0x002U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000002 */
2421 #define ADC_OFR4_OFFSET4_2             (0x004U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000004 */
2422 #define ADC_OFR4_OFFSET4_3             (0x008U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000008 */
2423 #define ADC_OFR4_OFFSET4_4             (0x010U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000010 */
2424 #define ADC_OFR4_OFFSET4_5             (0x020U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000020 */
2425 #define ADC_OFR4_OFFSET4_6             (0x040U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000040 */
2426 #define ADC_OFR4_OFFSET4_7             (0x080U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000080 */
2427 #define ADC_OFR4_OFFSET4_8             (0x100U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000100 */
2428 #define ADC_OFR4_OFFSET4_9             (0x200U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000200 */
2429 #define ADC_OFR4_OFFSET4_10            (0x400U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000400 */
2430 #define ADC_OFR4_OFFSET4_11            (0x800U << ADC_OFR4_OFFSET4_Pos)        /*!< 0x00000800 */
2431 
2432 #define ADC_OFR4_OFFSET4_CH_Pos        (26U)
2433 #define ADC_OFR4_OFFSET4_CH_Msk        (0x1FU << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x7C000000 */
2434 #define ADC_OFR4_OFFSET4_CH            ADC_OFR4_OFFSET4_CH_Msk                 /*!< ADC offset number 4 channel selection */
2435 #define ADC_OFR4_OFFSET4_CH_0          (0x01U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x04000000 */
2436 #define ADC_OFR4_OFFSET4_CH_1          (0x02U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x08000000 */
2437 #define ADC_OFR4_OFFSET4_CH_2          (0x04U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x10000000 */
2438 #define ADC_OFR4_OFFSET4_CH_3          (0x08U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x20000000 */
2439 #define ADC_OFR4_OFFSET4_CH_4          (0x10U << ADC_OFR4_OFFSET4_CH_Pos)      /*!< 0x40000000 */
2440 
2441 #define ADC_OFR4_OFFSET4_EN_Pos        (31U)
2442 #define ADC_OFR4_OFFSET4_EN_Msk        (0x1U << ADC_OFR4_OFFSET4_EN_Pos)       /*!< 0x80000000 */
2443 #define ADC_OFR4_OFFSET4_EN            ADC_OFR4_OFFSET4_EN_Msk                 /*!< ADC offset number 4 enable */
2444 
2445 /********************  Bit definition for ADC_JDR1 register  ******************/
2446 #define ADC_JDR1_JDATA_Pos             (0U)
2447 #define ADC_JDR1_JDATA_Msk             (0xFFFFU << ADC_JDR1_JDATA_Pos)         /*!< 0x0000FFFF */
2448 #define ADC_JDR1_JDATA                 ADC_JDR1_JDATA_Msk                      /*!< ADC group injected sequencer rank 1 conversion data */
2449 #define ADC_JDR1_JDATA_0               (0x0001U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000001 */
2450 #define ADC_JDR1_JDATA_1               (0x0002U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000002 */
2451 #define ADC_JDR1_JDATA_2               (0x0004U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000004 */
2452 #define ADC_JDR1_JDATA_3               (0x0008U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000008 */
2453 #define ADC_JDR1_JDATA_4               (0x0010U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000010 */
2454 #define ADC_JDR1_JDATA_5               (0x0020U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000020 */
2455 #define ADC_JDR1_JDATA_6               (0x0040U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000040 */
2456 #define ADC_JDR1_JDATA_7               (0x0080U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000080 */
2457 #define ADC_JDR1_JDATA_8               (0x0100U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000100 */
2458 #define ADC_JDR1_JDATA_9               (0x0200U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000200 */
2459 #define ADC_JDR1_JDATA_10              (0x0400U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000400 */
2460 #define ADC_JDR1_JDATA_11              (0x0800U << ADC_JDR1_JDATA_Pos)         /*!< 0x00000800 */
2461 #define ADC_JDR1_JDATA_12              (0x1000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00001000 */
2462 #define ADC_JDR1_JDATA_13              (0x2000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00002000 */
2463 #define ADC_JDR1_JDATA_14              (0x4000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00004000 */
2464 #define ADC_JDR1_JDATA_15              (0x8000U << ADC_JDR1_JDATA_Pos)         /*!< 0x00008000 */
2465 
2466 /********************  Bit definition for ADC_JDR2 register  ******************/
2467 #define ADC_JDR2_JDATA_Pos             (0U)
2468 #define ADC_JDR2_JDATA_Msk             (0xFFFFU << ADC_JDR2_JDATA_Pos)         /*!< 0x0000FFFF */
2469 #define ADC_JDR2_JDATA                 ADC_JDR2_JDATA_Msk                      /*!< ADC group injected sequencer rank 2 conversion data */
2470 #define ADC_JDR2_JDATA_0               (0x0001U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000001 */
2471 #define ADC_JDR2_JDATA_1               (0x0002U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000002 */
2472 #define ADC_JDR2_JDATA_2               (0x0004U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000004 */
2473 #define ADC_JDR2_JDATA_3               (0x0008U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000008 */
2474 #define ADC_JDR2_JDATA_4               (0x0010U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000010 */
2475 #define ADC_JDR2_JDATA_5               (0x0020U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000020 */
2476 #define ADC_JDR2_JDATA_6               (0x0040U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000040 */
2477 #define ADC_JDR2_JDATA_7               (0x0080U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000080 */
2478 #define ADC_JDR2_JDATA_8               (0x0100U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000100 */
2479 #define ADC_JDR2_JDATA_9               (0x0200U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000200 */
2480 #define ADC_JDR2_JDATA_10              (0x0400U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000400 */
2481 #define ADC_JDR2_JDATA_11              (0x0800U << ADC_JDR2_JDATA_Pos)         /*!< 0x00000800 */
2482 #define ADC_JDR2_JDATA_12              (0x1000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00001000 */
2483 #define ADC_JDR2_JDATA_13              (0x2000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00002000 */
2484 #define ADC_JDR2_JDATA_14              (0x4000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00004000 */
2485 #define ADC_JDR2_JDATA_15              (0x8000U << ADC_JDR2_JDATA_Pos)         /*!< 0x00008000 */
2486 
2487 /********************  Bit definition for ADC_JDR3 register  ******************/
2488 #define ADC_JDR3_JDATA_Pos             (0U)
2489 #define ADC_JDR3_JDATA_Msk             (0xFFFFU << ADC_JDR3_JDATA_Pos)         /*!< 0x0000FFFF */
2490 #define ADC_JDR3_JDATA                 ADC_JDR3_JDATA_Msk                      /*!< ADC group injected sequencer rank 3 conversion data */
2491 #define ADC_JDR3_JDATA_0               (0x0001U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000001 */
2492 #define ADC_JDR3_JDATA_1               (0x0002U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000002 */
2493 #define ADC_JDR3_JDATA_2               (0x0004U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000004 */
2494 #define ADC_JDR3_JDATA_3               (0x0008U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000008 */
2495 #define ADC_JDR3_JDATA_4               (0x0010U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000010 */
2496 #define ADC_JDR3_JDATA_5               (0x0020U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000020 */
2497 #define ADC_JDR3_JDATA_6               (0x0040U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000040 */
2498 #define ADC_JDR3_JDATA_7               (0x0080U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000080 */
2499 #define ADC_JDR3_JDATA_8               (0x0100U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000100 */
2500 #define ADC_JDR3_JDATA_9               (0x0200U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000200 */
2501 #define ADC_JDR3_JDATA_10              (0x0400U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000400 */
2502 #define ADC_JDR3_JDATA_11              (0x0800U << ADC_JDR3_JDATA_Pos)         /*!< 0x00000800 */
2503 #define ADC_JDR3_JDATA_12              (0x1000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00001000 */
2504 #define ADC_JDR3_JDATA_13              (0x2000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00002000 */
2505 #define ADC_JDR3_JDATA_14              (0x4000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00004000 */
2506 #define ADC_JDR3_JDATA_15              (0x8000U << ADC_JDR3_JDATA_Pos)         /*!< 0x00008000 */
2507 
2508 /********************  Bit definition for ADC_JDR4 register  ******************/
2509 #define ADC_JDR4_JDATA_Pos             (0U)
2510 #define ADC_JDR4_JDATA_Msk             (0xFFFFU << ADC_JDR4_JDATA_Pos)         /*!< 0x0000FFFF */
2511 #define ADC_JDR4_JDATA                 ADC_JDR4_JDATA_Msk                      /*!< ADC group injected sequencer rank 4 conversion data */
2512 #define ADC_JDR4_JDATA_0               (0x0001U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000001 */
2513 #define ADC_JDR4_JDATA_1               (0x0002U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000002 */
2514 #define ADC_JDR4_JDATA_2               (0x0004U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000004 */
2515 #define ADC_JDR4_JDATA_3               (0x0008U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000008 */
2516 #define ADC_JDR4_JDATA_4               (0x0010U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000010 */
2517 #define ADC_JDR4_JDATA_5               (0x0020U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000020 */
2518 #define ADC_JDR4_JDATA_6               (0x0040U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000040 */
2519 #define ADC_JDR4_JDATA_7               (0x0080U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000080 */
2520 #define ADC_JDR4_JDATA_8               (0x0100U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000100 */
2521 #define ADC_JDR4_JDATA_9               (0x0200U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000200 */
2522 #define ADC_JDR4_JDATA_10              (0x0400U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000400 */
2523 #define ADC_JDR4_JDATA_11              (0x0800U << ADC_JDR4_JDATA_Pos)         /*!< 0x00000800 */
2524 #define ADC_JDR4_JDATA_12              (0x1000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00001000 */
2525 #define ADC_JDR4_JDATA_13              (0x2000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00002000 */
2526 #define ADC_JDR4_JDATA_14              (0x4000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00004000 */
2527 #define ADC_JDR4_JDATA_15              (0x8000U << ADC_JDR4_JDATA_Pos)         /*!< 0x00008000 */
2528 
2529 /********************  Bit definition for ADC_AWD2CR register  ****************/
2530 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
2531 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x0007FFFF */
2532 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
2533 #define ADC_AWD2CR_AWD2CH_0            (0x00001U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000001 */
2534 #define ADC_AWD2CR_AWD2CH_1            (0x00002U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000002 */
2535 #define ADC_AWD2CR_AWD2CH_2            (0x00004U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000004 */
2536 #define ADC_AWD2CR_AWD2CH_3            (0x00008U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000008 */
2537 #define ADC_AWD2CR_AWD2CH_4            (0x00010U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000010 */
2538 #define ADC_AWD2CR_AWD2CH_5            (0x00020U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000020 */
2539 #define ADC_AWD2CR_AWD2CH_6            (0x00040U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000040 */
2540 #define ADC_AWD2CR_AWD2CH_7            (0x00080U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000080 */
2541 #define ADC_AWD2CR_AWD2CH_8            (0x00100U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000100 */
2542 #define ADC_AWD2CR_AWD2CH_9            (0x00200U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000200 */
2543 #define ADC_AWD2CR_AWD2CH_10           (0x00400U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000400 */
2544 #define ADC_AWD2CR_AWD2CH_11           (0x00800U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00000800 */
2545 #define ADC_AWD2CR_AWD2CH_12           (0x01000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00001000 */
2546 #define ADC_AWD2CR_AWD2CH_13           (0x02000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00002000 */
2547 #define ADC_AWD2CR_AWD2CH_14           (0x04000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00004000 */
2548 #define ADC_AWD2CR_AWD2CH_15           (0x08000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00008000 */
2549 #define ADC_AWD2CR_AWD2CH_16           (0x10000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00010000 */
2550 #define ADC_AWD2CR_AWD2CH_17           (0x20000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00020000 */
2551 #define ADC_AWD2CR_AWD2CH_18           (0x40000U << ADC_AWD2CR_AWD2CH_Pos)     /*!< 0x00040000 */
2552 
2553 /********************  Bit definition for ADC_AWD3CR register  ****************/
2554 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
2555 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x0007FFFF */
2556 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
2557 #define ADC_AWD3CR_AWD3CH_0            (0x00001U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000001 */
2558 #define ADC_AWD3CR_AWD3CH_1            (0x00002U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000002 */
2559 #define ADC_AWD3CR_AWD3CH_2            (0x00004U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000004 */
2560 #define ADC_AWD3CR_AWD3CH_3            (0x00008U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000008 */
2561 #define ADC_AWD3CR_AWD3CH_4            (0x00010U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000010 */
2562 #define ADC_AWD3CR_AWD3CH_5            (0x00020U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000020 */
2563 #define ADC_AWD3CR_AWD3CH_6            (0x00040U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000040 */
2564 #define ADC_AWD3CR_AWD3CH_7            (0x00080U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000080 */
2565 #define ADC_AWD3CR_AWD3CH_8            (0x00100U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000100 */
2566 #define ADC_AWD3CR_AWD3CH_9            (0x00200U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000200 */
2567 #define ADC_AWD3CR_AWD3CH_10           (0x00400U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000400 */
2568 #define ADC_AWD3CR_AWD3CH_11           (0x00800U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00000800 */
2569 #define ADC_AWD3CR_AWD3CH_12           (0x01000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00001000 */
2570 #define ADC_AWD3CR_AWD3CH_13           (0x02000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00002000 */
2571 #define ADC_AWD3CR_AWD3CH_14           (0x04000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00004000 */
2572 #define ADC_AWD3CR_AWD3CH_15           (0x08000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00008000 */
2573 #define ADC_AWD3CR_AWD3CH_16           (0x10000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00010000 */
2574 #define ADC_AWD3CR_AWD3CH_17           (0x20000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00020000 */
2575 #define ADC_AWD3CR_AWD3CH_18           (0x40000U << ADC_AWD3CR_AWD3CH_Pos)     /*!< 0x00040000 */
2576 
2577 /********************  Bit definition for ADC_DIFSEL register  ****************/
2578 #define ADC_DIFSEL_DIFSEL_Pos          (0U)
2579 #define ADC_DIFSEL_DIFSEL_Msk          (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x0007FFFF */
2580 #define ADC_DIFSEL_DIFSEL              ADC_DIFSEL_DIFSEL_Msk                   /*!< ADC channel differential or single-ended mode */
2581 #define ADC_DIFSEL_DIFSEL_0            (0x00001U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000001 */
2582 #define ADC_DIFSEL_DIFSEL_1            (0x00002U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000002 */
2583 #define ADC_DIFSEL_DIFSEL_2            (0x00004U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000004 */
2584 #define ADC_DIFSEL_DIFSEL_3            (0x00008U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000008 */
2585 #define ADC_DIFSEL_DIFSEL_4            (0x00010U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000010 */
2586 #define ADC_DIFSEL_DIFSEL_5            (0x00020U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000020 */
2587 #define ADC_DIFSEL_DIFSEL_6            (0x00040U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000040 */
2588 #define ADC_DIFSEL_DIFSEL_7            (0x00080U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000080 */
2589 #define ADC_DIFSEL_DIFSEL_8            (0x00100U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000100 */
2590 #define ADC_DIFSEL_DIFSEL_9            (0x00200U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000200 */
2591 #define ADC_DIFSEL_DIFSEL_10           (0x00400U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000400 */
2592 #define ADC_DIFSEL_DIFSEL_11           (0x00800U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00000800 */
2593 #define ADC_DIFSEL_DIFSEL_12           (0x01000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00001000 */
2594 #define ADC_DIFSEL_DIFSEL_13           (0x02000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00002000 */
2595 #define ADC_DIFSEL_DIFSEL_14           (0x04000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00004000 */
2596 #define ADC_DIFSEL_DIFSEL_15           (0x08000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00008000 */
2597 #define ADC_DIFSEL_DIFSEL_16           (0x10000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00010000 */
2598 #define ADC_DIFSEL_DIFSEL_17           (0x20000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00020000 */
2599 #define ADC_DIFSEL_DIFSEL_18           (0x40000U << ADC_DIFSEL_DIFSEL_Pos)     /*!< 0x00040000 */
2600 
2601 /********************  Bit definition for ADC_CALFACT register  ***************/
2602 #define ADC_CALFACT_CALFACT_S_Pos      (0U)
2603 #define ADC_CALFACT_CALFACT_S_Msk      (0x7FU << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x0000007F */
2604 #define ADC_CALFACT_CALFACT_S          ADC_CALFACT_CALFACT_S_Msk               /*!< ADC calibration factor in single-ended mode */
2605 #define ADC_CALFACT_CALFACT_S_0        (0x01U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000001 */
2606 #define ADC_CALFACT_CALFACT_S_1        (0x02U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000002 */
2607 #define ADC_CALFACT_CALFACT_S_2        (0x04U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000004 */
2608 #define ADC_CALFACT_CALFACT_S_3        (0x08U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000008 */
2609 #define ADC_CALFACT_CALFACT_S_4        (0x10U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000010 */
2610 #define ADC_CALFACT_CALFACT_S_5        (0x20U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000020 */
2611 #define ADC_CALFACT_CALFACT_S_6        (0x40U << ADC_CALFACT_CALFACT_S_Pos)    /*!< 0x00000040 */
2612 
2613 #define ADC_CALFACT_CALFACT_D_Pos      (16U)
2614 #define ADC_CALFACT_CALFACT_D_Msk      (0x7FU << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x007F0000 */
2615 #define ADC_CALFACT_CALFACT_D          ADC_CALFACT_CALFACT_D_Msk               /*!< ADC calibration factor in differential mode */
2616 #define ADC_CALFACT_CALFACT_D_0        (0x01U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00010000 */
2617 #define ADC_CALFACT_CALFACT_D_1        (0x02U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00020000 */
2618 #define ADC_CALFACT_CALFACT_D_2        (0x04U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00040000 */
2619 #define ADC_CALFACT_CALFACT_D_3        (0x08U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00080000 */
2620 #define ADC_CALFACT_CALFACT_D_4        (0x10U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00100000 */
2621 #define ADC_CALFACT_CALFACT_D_5        (0x20U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00200000 */
2622 #define ADC_CALFACT_CALFACT_D_6        (0x40U << ADC_CALFACT_CALFACT_D_Pos)    /*!< 0x00400000 */
2623 
2624 /*************************  ADC Common registers  *****************************/
2625 /********************  Bit definition for ADC_CSR register  *******************/
2626 #define ADC_CSR_ADRDY_MST_Pos          (0U)
2627 #define ADC_CSR_ADRDY_MST_Msk          (0x1U << ADC_CSR_ADRDY_MST_Pos)         /*!< 0x00000001 */
2628 #define ADC_CSR_ADRDY_MST              ADC_CSR_ADRDY_MST_Msk                   /*!< ADC multimode master ready flag */
2629 #define ADC_CSR_EOSMP_MST_Pos          (1U)
2630 #define ADC_CSR_EOSMP_MST_Msk          (0x1U << ADC_CSR_EOSMP_MST_Pos)         /*!< 0x00000002 */
2631 #define ADC_CSR_EOSMP_MST              ADC_CSR_EOSMP_MST_Msk                   /*!< ADC multimode master group regular end of sampling flag */
2632 #define ADC_CSR_EOC_MST_Pos            (2U)
2633 #define ADC_CSR_EOC_MST_Msk            (0x1U << ADC_CSR_EOC_MST_Pos)           /*!< 0x00000004 */
2634 #define ADC_CSR_EOC_MST                ADC_CSR_EOC_MST_Msk                     /*!< ADC multimode master group regular end of unitary conversion flag */
2635 #define ADC_CSR_EOS_MST_Pos            (3U)
2636 #define ADC_CSR_EOS_MST_Msk            (0x1U << ADC_CSR_EOS_MST_Pos)           /*!< 0x00000008 */
2637 #define ADC_CSR_EOS_MST                ADC_CSR_EOS_MST_Msk                     /*!< ADC multimode master group regular end of sequence conversions flag */
2638 #define ADC_CSR_OVR_MST_Pos            (4U)
2639 #define ADC_CSR_OVR_MST_Msk            (0x1U << ADC_CSR_OVR_MST_Pos)           /*!< 0x00000010 */
2640 #define ADC_CSR_OVR_MST                ADC_CSR_OVR_MST_Msk                     /*!< ADC multimode master group regular overrun flag */
2641 #define ADC_CSR_JEOC_MST_Pos           (5U)
2642 #define ADC_CSR_JEOC_MST_Msk           (0x1U << ADC_CSR_JEOC_MST_Pos)          /*!< 0x00000020 */
2643 #define ADC_CSR_JEOC_MST               ADC_CSR_JEOC_MST_Msk                    /*!< ADC multimode master group injected end of unitary conversion flag */
2644 #define ADC_CSR_JEOS_MST_Pos           (6U)
2645 #define ADC_CSR_JEOS_MST_Msk           (0x1U << ADC_CSR_JEOS_MST_Pos)          /*!< 0x00000040 */
2646 #define ADC_CSR_JEOS_MST               ADC_CSR_JEOS_MST_Msk                    /*!< ADC multimode master group injected end of sequence conversions flag */
2647 #define ADC_CSR_AWD1_MST_Pos           (7U)
2648 #define ADC_CSR_AWD1_MST_Msk           (0x1U << ADC_CSR_AWD1_MST_Pos)          /*!< 0x00000080 */
2649 #define ADC_CSR_AWD1_MST               ADC_CSR_AWD1_MST_Msk                    /*!< ADC multimode master analog watchdog 1 flag */
2650 #define ADC_CSR_AWD2_MST_Pos           (8U)
2651 #define ADC_CSR_AWD2_MST_Msk           (0x1U << ADC_CSR_AWD2_MST_Pos)          /*!< 0x00000100 */
2652 #define ADC_CSR_AWD2_MST               ADC_CSR_AWD2_MST_Msk                    /*!< ADC multimode master analog watchdog 2 flag */
2653 #define ADC_CSR_AWD3_MST_Pos           (9U)
2654 #define ADC_CSR_AWD3_MST_Msk           (0x1U << ADC_CSR_AWD3_MST_Pos)          /*!< 0x00000200 */
2655 #define ADC_CSR_AWD3_MST               ADC_CSR_AWD3_MST_Msk                    /*!< ADC multimode master analog watchdog 3 flag */
2656 #define ADC_CSR_JQOVF_MST_Pos          (10U)
2657 #define ADC_CSR_JQOVF_MST_Msk          (0x1U << ADC_CSR_JQOVF_MST_Pos)         /*!< 0x00000400 */
2658 #define ADC_CSR_JQOVF_MST              ADC_CSR_JQOVF_MST_Msk                   /*!< ADC multimode master group injected contexts queue overflow flag */
2659 
2660 #define ADC_CSR_ADRDY_SLV_Pos          (16U)
2661 #define ADC_CSR_ADRDY_SLV_Msk          (0x1U << ADC_CSR_ADRDY_SLV_Pos)         /*!< 0x00010000 */
2662 #define ADC_CSR_ADRDY_SLV              ADC_CSR_ADRDY_SLV_Msk                   /*!< ADC multimode slave ready flag */
2663 #define ADC_CSR_EOSMP_SLV_Pos          (17U)
2664 #define ADC_CSR_EOSMP_SLV_Msk          (0x1U << ADC_CSR_EOSMP_SLV_Pos)         /*!< 0x00020000 */
2665 #define ADC_CSR_EOSMP_SLV              ADC_CSR_EOSMP_SLV_Msk                   /*!< ADC multimode slave group regular end of sampling flag */
2666 #define ADC_CSR_EOC_SLV_Pos            (18U)
2667 #define ADC_CSR_EOC_SLV_Msk            (0x1U << ADC_CSR_EOC_SLV_Pos)           /*!< 0x00040000 */
2668 #define ADC_CSR_EOC_SLV                ADC_CSR_EOC_SLV_Msk                     /*!< ADC multimode slave group regular end of unitary conversion flag */
2669 #define ADC_CSR_EOS_SLV_Pos            (19U)
2670 #define ADC_CSR_EOS_SLV_Msk            (0x1U << ADC_CSR_EOS_SLV_Pos)           /*!< 0x00080000 */
2671 #define ADC_CSR_EOS_SLV                ADC_CSR_EOS_SLV_Msk                     /*!< ADC multimode slave group regular end of sequence conversions flag */
2672 #define ADC_CSR_OVR_SLV_Pos            (20U)
2673 #define ADC_CSR_OVR_SLV_Msk            (0x1U << ADC_CSR_OVR_SLV_Pos)           /*!< 0x00100000 */
2674 #define ADC_CSR_OVR_SLV                ADC_CSR_OVR_SLV_Msk                     /*!< ADC multimode slave group regular overrun flag */
2675 #define ADC_CSR_JEOC_SLV_Pos           (21U)
2676 #define ADC_CSR_JEOC_SLV_Msk           (0x1U << ADC_CSR_JEOC_SLV_Pos)          /*!< 0x00200000 */
2677 #define ADC_CSR_JEOC_SLV               ADC_CSR_JEOC_SLV_Msk                    /*!< ADC multimode slave group injected end of unitary conversion flag */
2678 #define ADC_CSR_JEOS_SLV_Pos           (22U)
2679 #define ADC_CSR_JEOS_SLV_Msk           (0x1U << ADC_CSR_JEOS_SLV_Pos)          /*!< 0x00400000 */
2680 #define ADC_CSR_JEOS_SLV               ADC_CSR_JEOS_SLV_Msk                    /*!< ADC multimode slave group injected end of sequence conversions flag */
2681 #define ADC_CSR_AWD1_SLV_Pos           (23U)
2682 #define ADC_CSR_AWD1_SLV_Msk           (0x1U << ADC_CSR_AWD1_SLV_Pos)          /*!< 0x00800000 */
2683 #define ADC_CSR_AWD1_SLV               ADC_CSR_AWD1_SLV_Msk                    /*!< ADC multimode slave analog watchdog 1 flag */
2684 #define ADC_CSR_AWD2_SLV_Pos           (24U)
2685 #define ADC_CSR_AWD2_SLV_Msk           (0x1U << ADC_CSR_AWD2_SLV_Pos)          /*!< 0x01000000 */
2686 #define ADC_CSR_AWD2_SLV               ADC_CSR_AWD2_SLV_Msk                    /*!< ADC multimode slave analog watchdog 2 flag */
2687 #define ADC_CSR_AWD3_SLV_Pos           (25U)
2688 #define ADC_CSR_AWD3_SLV_Msk           (0x1U << ADC_CSR_AWD3_SLV_Pos)          /*!< 0x02000000 */
2689 #define ADC_CSR_AWD3_SLV               ADC_CSR_AWD3_SLV_Msk                    /*!< ADC multimode slave analog watchdog 3 flag */
2690 #define ADC_CSR_JQOVF_SLV_Pos          (26U)
2691 #define ADC_CSR_JQOVF_SLV_Msk          (0x1U << ADC_CSR_JQOVF_SLV_Pos)         /*!< 0x04000000 */
2692 #define ADC_CSR_JQOVF_SLV              ADC_CSR_JQOVF_SLV_Msk                   /*!< ADC multimode slave group injected contexts queue overflow flag */
2693 
2694 /********************  Bit definition for ADC_CCR register  *******************/
2695 #define ADC_CCR_DUAL_Pos               (0U)
2696 #define ADC_CCR_DUAL_Msk               (0x1FU << ADC_CCR_DUAL_Pos)             /*!< 0x0000001F */
2697 #define ADC_CCR_DUAL                   ADC_CCR_DUAL_Msk                        /*!< ADC multimode mode selection */
2698 #define ADC_CCR_DUAL_0                 (0x01U << ADC_CCR_DUAL_Pos)             /*!< 0x00000001 */
2699 #define ADC_CCR_DUAL_1                 (0x02U << ADC_CCR_DUAL_Pos)             /*!< 0x00000002 */
2700 #define ADC_CCR_DUAL_2                 (0x04U << ADC_CCR_DUAL_Pos)             /*!< 0x00000004 */
2701 #define ADC_CCR_DUAL_3                 (0x08U << ADC_CCR_DUAL_Pos)             /*!< 0x00000008 */
2702 #define ADC_CCR_DUAL_4                 (0x10U << ADC_CCR_DUAL_Pos)             /*!< 0x00000010 */
2703 
2704 #define ADC_CCR_DELAY_Pos              (8U)
2705 #define ADC_CCR_DELAY_Msk              (0xFU << ADC_CCR_DELAY_Pos)             /*!< 0x00000F00 */
2706 #define ADC_CCR_DELAY                  ADC_CCR_DELAY_Msk                       /*!< ADC multimode delay between 2 sampling phases */
2707 #define ADC_CCR_DELAY_0                (0x1U << ADC_CCR_DELAY_Pos)             /*!< 0x00000100 */
2708 #define ADC_CCR_DELAY_1                (0x2U << ADC_CCR_DELAY_Pos)             /*!< 0x00000200 */
2709 #define ADC_CCR_DELAY_2                (0x4U << ADC_CCR_DELAY_Pos)             /*!< 0x00000400 */
2710 #define ADC_CCR_DELAY_3                (0x8U << ADC_CCR_DELAY_Pos)             /*!< 0x00000800 */
2711 
2712 #define ADC_CCR_DMACFG_Pos             (13U)
2713 #define ADC_CCR_DMACFG_Msk             (0x1U << ADC_CCR_DMACFG_Pos)            /*!< 0x00002000 */
2714 #define ADC_CCR_DMACFG                 ADC_CCR_DMACFG_Msk                      /*!< ADC multimode DMA transfer configuration */
2715 
2716 #define ADC_CCR_MDMA_Pos               (14U)
2717 #define ADC_CCR_MDMA_Msk               (0x3U << ADC_CCR_MDMA_Pos)              /*!< 0x0000C000 */
2718 #define ADC_CCR_MDMA                   ADC_CCR_MDMA_Msk                        /*!< ADC multimode DMA transfer enable */
2719 #define ADC_CCR_MDMA_0                 (0x1U << ADC_CCR_MDMA_Pos)              /*!< 0x00004000 */
2720 #define ADC_CCR_MDMA_1                 (0x2U << ADC_CCR_MDMA_Pos)              /*!< 0x00008000 */
2721 
2722 #define ADC_CCR_CKMODE_Pos             (16U)
2723 #define ADC_CCR_CKMODE_Msk             (0x3U << ADC_CCR_CKMODE_Pos)            /*!< 0x00030000 */
2724 #define ADC_CCR_CKMODE                 ADC_CCR_CKMODE_Msk                      /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
2725 #define ADC_CCR_CKMODE_0               (0x1U << ADC_CCR_CKMODE_Pos)            /*!< 0x00010000 */
2726 #define ADC_CCR_CKMODE_1               (0x2U << ADC_CCR_CKMODE_Pos)            /*!< 0x00020000 */
2727 
2728 #define ADC_CCR_PRESC_Pos              (18U)
2729 #define ADC_CCR_PRESC_Msk              (0xFU << ADC_CCR_PRESC_Pos)             /*!< 0x003C0000 */
2730 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
2731 #define ADC_CCR_PRESC_0                (0x1U << ADC_CCR_PRESC_Pos)             /*!< 0x00040000 */
2732 #define ADC_CCR_PRESC_1                (0x2U << ADC_CCR_PRESC_Pos)             /*!< 0x00080000 */
2733 #define ADC_CCR_PRESC_2                (0x4U << ADC_CCR_PRESC_Pos)             /*!< 0x00100000 */
2734 #define ADC_CCR_PRESC_3                (0x8U << ADC_CCR_PRESC_Pos)             /*!< 0x00200000 */
2735 
2736 #define ADC_CCR_VREFEN_Pos             (22U)
2737 #define ADC_CCR_VREFEN_Msk             (0x1U << ADC_CCR_VREFEN_Pos)            /*!< 0x00400000 */
2738 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
2739 #define ADC_CCR_TSEN_Pos               (23U)
2740 #define ADC_CCR_TSEN_Msk               (0x1U << ADC_CCR_TSEN_Pos)              /*!< 0x00800000 */
2741 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
2742 #define ADC_CCR_VBATEN_Pos             (24U)
2743 #define ADC_CCR_VBATEN_Msk             (0x1U << ADC_CCR_VBATEN_Pos)            /*!< 0x01000000 */
2744 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
2745 
2746 /********************  Bit definition for ADC_CDR register  *******************/
2747 #define ADC_CDR_RDATA_MST_Pos          (0U)
2748 #define ADC_CDR_RDATA_MST_Msk          (0xFFFFU << ADC_CDR_RDATA_MST_Pos)      /*!< 0x0000FFFF */
2749 #define ADC_CDR_RDATA_MST              ADC_CDR_RDATA_MST_Msk                   /*!< ADC multimode master group regular conversion data */
2750 #define ADC_CDR_RDATA_MST_0            (0x0001U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000001 */
2751 #define ADC_CDR_RDATA_MST_1            (0x0002U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000002 */
2752 #define ADC_CDR_RDATA_MST_2            (0x0004U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000004 */
2753 #define ADC_CDR_RDATA_MST_3            (0x0008U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000008 */
2754 #define ADC_CDR_RDATA_MST_4            (0x0010U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000010 */
2755 #define ADC_CDR_RDATA_MST_5            (0x0020U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000020 */
2756 #define ADC_CDR_RDATA_MST_6            (0x0040U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000040 */
2757 #define ADC_CDR_RDATA_MST_7            (0x0080U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000080 */
2758 #define ADC_CDR_RDATA_MST_8            (0x0100U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000100 */
2759 #define ADC_CDR_RDATA_MST_9            (0x0200U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000200 */
2760 #define ADC_CDR_RDATA_MST_10           (0x0400U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000400 */
2761 #define ADC_CDR_RDATA_MST_11           (0x0800U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00000800 */
2762 #define ADC_CDR_RDATA_MST_12           (0x1000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00001000 */
2763 #define ADC_CDR_RDATA_MST_13           (0x2000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00002000 */
2764 #define ADC_CDR_RDATA_MST_14           (0x4000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00004000 */
2765 #define ADC_CDR_RDATA_MST_15           (0x8000U << ADC_CDR_RDATA_MST_Pos)      /*!< 0x00008000 */
2766 
2767 #define ADC_CDR_RDATA_SLV_Pos          (16U)
2768 #define ADC_CDR_RDATA_SLV_Msk          (0xFFFFU << ADC_CDR_RDATA_SLV_Pos)      /*!< 0xFFFF0000 */
2769 #define ADC_CDR_RDATA_SLV              ADC_CDR_RDATA_SLV_Msk                   /*!< ADC multimode slave group regular conversion data */
2770 #define ADC_CDR_RDATA_SLV_0            (0x0001U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00010000 */
2771 #define ADC_CDR_RDATA_SLV_1            (0x0002U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00020000 */
2772 #define ADC_CDR_RDATA_SLV_2            (0x0004U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00040000 */
2773 #define ADC_CDR_RDATA_SLV_3            (0x0008U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00080000 */
2774 #define ADC_CDR_RDATA_SLV_4            (0x0010U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00100000 */
2775 #define ADC_CDR_RDATA_SLV_5            (0x0020U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00200000 */
2776 #define ADC_CDR_RDATA_SLV_6            (0x0040U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00400000 */
2777 #define ADC_CDR_RDATA_SLV_7            (0x0080U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x00800000 */
2778 #define ADC_CDR_RDATA_SLV_8            (0x0100U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x01000000 */
2779 #define ADC_CDR_RDATA_SLV_9            (0x0200U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x02000000 */
2780 #define ADC_CDR_RDATA_SLV_10           (0x0400U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x04000000 */
2781 #define ADC_CDR_RDATA_SLV_11           (0x0800U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x08000000 */
2782 #define ADC_CDR_RDATA_SLV_12           (0x1000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x10000000 */
2783 #define ADC_CDR_RDATA_SLV_13           (0x2000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x20000000 */
2784 #define ADC_CDR_RDATA_SLV_14           (0x4000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x40000000 */
2785 #define ADC_CDR_RDATA_SLV_15           (0x8000U << ADC_CDR_RDATA_SLV_Pos)      /*!< 0x80000000 */
2786 
2787 /******************************************************************************/
2788 /*                                                                            */
2789 /*                         Controller Area Network                            */
2790 /*                                                                            */
2791 /******************************************************************************/
2792 /*!<CAN control and status registers */
2793 /*******************  Bit definition for CAN_MCR register  ********************/
2794 #define CAN_MCR_INRQ_Pos       (0U)
2795 #define CAN_MCR_INRQ_Msk       (0x1U << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
2796 #define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
2797 #define CAN_MCR_SLEEP_Pos      (1U)
2798 #define CAN_MCR_SLEEP_Msk      (0x1U << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
2799 #define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
2800 #define CAN_MCR_TXFP_Pos       (2U)
2801 #define CAN_MCR_TXFP_Msk       (0x1U << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
2802 #define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
2803 #define CAN_MCR_RFLM_Pos       (3U)
2804 #define CAN_MCR_RFLM_Msk       (0x1U << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
2805 #define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
2806 #define CAN_MCR_NART_Pos       (4U)
2807 #define CAN_MCR_NART_Msk       (0x1U << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
2808 #define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
2809 #define CAN_MCR_AWUM_Pos       (5U)
2810 #define CAN_MCR_AWUM_Msk       (0x1U << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
2811 #define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
2812 #define CAN_MCR_ABOM_Pos       (6U)
2813 #define CAN_MCR_ABOM_Msk       (0x1U << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
2814 #define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
2815 #define CAN_MCR_TTCM_Pos       (7U)
2816 #define CAN_MCR_TTCM_Msk       (0x1U << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
2817 #define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
2818 #define CAN_MCR_RESET_Pos      (15U)
2819 #define CAN_MCR_RESET_Msk      (0x1U << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
2820 #define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
2821 
2822 /*******************  Bit definition for CAN_MSR register  ********************/
2823 #define CAN_MSR_INAK_Pos       (0U)
2824 #define CAN_MSR_INAK_Msk       (0x1U << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
2825 #define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
2826 #define CAN_MSR_SLAK_Pos       (1U)
2827 #define CAN_MSR_SLAK_Msk       (0x1U << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
2828 #define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
2829 #define CAN_MSR_ERRI_Pos       (2U)
2830 #define CAN_MSR_ERRI_Msk       (0x1U << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
2831 #define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
2832 #define CAN_MSR_WKUI_Pos       (3U)
2833 #define CAN_MSR_WKUI_Msk       (0x1U << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
2834 #define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
2835 #define CAN_MSR_SLAKI_Pos      (4U)
2836 #define CAN_MSR_SLAKI_Msk      (0x1U << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
2837 #define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
2838 #define CAN_MSR_TXM_Pos        (8U)
2839 #define CAN_MSR_TXM_Msk        (0x1U << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
2840 #define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
2841 #define CAN_MSR_RXM_Pos        (9U)
2842 #define CAN_MSR_RXM_Msk        (0x1U << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
2843 #define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
2844 #define CAN_MSR_SAMP_Pos       (10U)
2845 #define CAN_MSR_SAMP_Msk       (0x1U << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
2846 #define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
2847 #define CAN_MSR_RX_Pos         (11U)
2848 #define CAN_MSR_RX_Msk         (0x1U << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
2849 #define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
2850 
2851 /*******************  Bit definition for CAN_TSR register  ********************/
2852 #define CAN_TSR_RQCP0_Pos      (0U)
2853 #define CAN_TSR_RQCP0_Msk      (0x1U << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
2854 #define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
2855 #define CAN_TSR_TXOK0_Pos      (1U)
2856 #define CAN_TSR_TXOK0_Msk      (0x1U << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
2857 #define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
2858 #define CAN_TSR_ALST0_Pos      (2U)
2859 #define CAN_TSR_ALST0_Msk      (0x1U << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
2860 #define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
2861 #define CAN_TSR_TERR0_Pos      (3U)
2862 #define CAN_TSR_TERR0_Msk      (0x1U << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
2863 #define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
2864 #define CAN_TSR_ABRQ0_Pos      (7U)
2865 #define CAN_TSR_ABRQ0_Msk      (0x1U << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
2866 #define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
2867 #define CAN_TSR_RQCP1_Pos      (8U)
2868 #define CAN_TSR_RQCP1_Msk      (0x1U << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
2869 #define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
2870 #define CAN_TSR_TXOK1_Pos      (9U)
2871 #define CAN_TSR_TXOK1_Msk      (0x1U << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
2872 #define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
2873 #define CAN_TSR_ALST1_Pos      (10U)
2874 #define CAN_TSR_ALST1_Msk      (0x1U << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
2875 #define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
2876 #define CAN_TSR_TERR1_Pos      (11U)
2877 #define CAN_TSR_TERR1_Msk      (0x1U << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
2878 #define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
2879 #define CAN_TSR_ABRQ1_Pos      (15U)
2880 #define CAN_TSR_ABRQ1_Msk      (0x1U << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
2881 #define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
2882 #define CAN_TSR_RQCP2_Pos      (16U)
2883 #define CAN_TSR_RQCP2_Msk      (0x1U << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
2884 #define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
2885 #define CAN_TSR_TXOK2_Pos      (17U)
2886 #define CAN_TSR_TXOK2_Msk      (0x1U << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
2887 #define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
2888 #define CAN_TSR_ALST2_Pos      (18U)
2889 #define CAN_TSR_ALST2_Msk      (0x1U << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
2890 #define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
2891 #define CAN_TSR_TERR2_Pos      (19U)
2892 #define CAN_TSR_TERR2_Msk      (0x1U << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
2893 #define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
2894 #define CAN_TSR_ABRQ2_Pos      (23U)
2895 #define CAN_TSR_ABRQ2_Msk      (0x1U << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
2896 #define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
2897 #define CAN_TSR_CODE_Pos       (24U)
2898 #define CAN_TSR_CODE_Msk       (0x3U << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
2899 #define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
2900 
2901 #define CAN_TSR_TME_Pos        (26U)
2902 #define CAN_TSR_TME_Msk        (0x7U << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
2903 #define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
2904 #define CAN_TSR_TME0_Pos       (26U)
2905 #define CAN_TSR_TME0_Msk       (0x1U << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
2906 #define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
2907 #define CAN_TSR_TME1_Pos       (27U)
2908 #define CAN_TSR_TME1_Msk       (0x1U << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
2909 #define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
2910 #define CAN_TSR_TME2_Pos       (28U)
2911 #define CAN_TSR_TME2_Msk       (0x1U << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
2912 #define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
2913 
2914 #define CAN_TSR_LOW_Pos        (29U)
2915 #define CAN_TSR_LOW_Msk        (0x7U << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
2916 #define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
2917 #define CAN_TSR_LOW0_Pos       (29U)
2918 #define CAN_TSR_LOW0_Msk       (0x1U << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
2919 #define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
2920 #define CAN_TSR_LOW1_Pos       (30U)
2921 #define CAN_TSR_LOW1_Msk       (0x1U << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
2922 #define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
2923 #define CAN_TSR_LOW2_Pos       (31U)
2924 #define CAN_TSR_LOW2_Msk       (0x1U << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
2925 #define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
2926 
2927 /*******************  Bit definition for CAN_RF0R register  *******************/
2928 #define CAN_RF0R_FMP0_Pos      (0U)
2929 #define CAN_RF0R_FMP0_Msk      (0x3U << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
2930 #define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
2931 #define CAN_RF0R_FULL0_Pos     (3U)
2932 #define CAN_RF0R_FULL0_Msk     (0x1U << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
2933 #define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
2934 #define CAN_RF0R_FOVR0_Pos     (4U)
2935 #define CAN_RF0R_FOVR0_Msk     (0x1U << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
2936 #define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
2937 #define CAN_RF0R_RFOM0_Pos     (5U)
2938 #define CAN_RF0R_RFOM0_Msk     (0x1U << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
2939 #define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
2940 
2941 /*******************  Bit definition for CAN_RF1R register  *******************/
2942 #define CAN_RF1R_FMP1_Pos      (0U)
2943 #define CAN_RF1R_FMP1_Msk      (0x3U << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
2944 #define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
2945 #define CAN_RF1R_FULL1_Pos     (3U)
2946 #define CAN_RF1R_FULL1_Msk     (0x1U << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
2947 #define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
2948 #define CAN_RF1R_FOVR1_Pos     (4U)
2949 #define CAN_RF1R_FOVR1_Msk     (0x1U << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
2950 #define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
2951 #define CAN_RF1R_RFOM1_Pos     (5U)
2952 #define CAN_RF1R_RFOM1_Msk     (0x1U << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
2953 #define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
2954 
2955 /********************  Bit definition for CAN_IER register  *******************/
2956 #define CAN_IER_TMEIE_Pos      (0U)
2957 #define CAN_IER_TMEIE_Msk      (0x1U << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
2958 #define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
2959 #define CAN_IER_FMPIE0_Pos     (1U)
2960 #define CAN_IER_FMPIE0_Msk     (0x1U << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
2961 #define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2962 #define CAN_IER_FFIE0_Pos      (2U)
2963 #define CAN_IER_FFIE0_Msk      (0x1U << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
2964 #define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
2965 #define CAN_IER_FOVIE0_Pos     (3U)
2966 #define CAN_IER_FOVIE0_Msk     (0x1U << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
2967 #define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
2968 #define CAN_IER_FMPIE1_Pos     (4U)
2969 #define CAN_IER_FMPIE1_Msk     (0x1U << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
2970 #define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
2971 #define CAN_IER_FFIE1_Pos      (5U)
2972 #define CAN_IER_FFIE1_Msk      (0x1U << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
2973 #define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
2974 #define CAN_IER_FOVIE1_Pos     (6U)
2975 #define CAN_IER_FOVIE1_Msk     (0x1U << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
2976 #define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
2977 #define CAN_IER_EWGIE_Pos      (8U)
2978 #define CAN_IER_EWGIE_Msk      (0x1U << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
2979 #define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
2980 #define CAN_IER_EPVIE_Pos      (9U)
2981 #define CAN_IER_EPVIE_Msk      (0x1U << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
2982 #define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
2983 #define CAN_IER_BOFIE_Pos      (10U)
2984 #define CAN_IER_BOFIE_Msk      (0x1U << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
2985 #define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
2986 #define CAN_IER_LECIE_Pos      (11U)
2987 #define CAN_IER_LECIE_Msk      (0x1U << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
2988 #define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
2989 #define CAN_IER_ERRIE_Pos      (15U)
2990 #define CAN_IER_ERRIE_Msk      (0x1U << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
2991 #define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
2992 #define CAN_IER_WKUIE_Pos      (16U)
2993 #define CAN_IER_WKUIE_Msk      (0x1U << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
2994 #define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
2995 #define CAN_IER_SLKIE_Pos      (17U)
2996 #define CAN_IER_SLKIE_Msk      (0x1U << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
2997 #define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
2998 
2999 /********************  Bit definition for CAN_ESR register  *******************/
3000 #define CAN_ESR_EWGF_Pos       (0U)
3001 #define CAN_ESR_EWGF_Msk       (0x1U << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
3002 #define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
3003 #define CAN_ESR_EPVF_Pos       (1U)
3004 #define CAN_ESR_EPVF_Msk       (0x1U << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
3005 #define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
3006 #define CAN_ESR_BOFF_Pos       (2U)
3007 #define CAN_ESR_BOFF_Msk       (0x1U << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
3008 #define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
3009 
3010 #define CAN_ESR_LEC_Pos        (4U)
3011 #define CAN_ESR_LEC_Msk        (0x7U << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
3012 #define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
3013 #define CAN_ESR_LEC_0          (0x1U << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
3014 #define CAN_ESR_LEC_1          (0x2U << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
3015 #define CAN_ESR_LEC_2          (0x4U << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
3016 
3017 #define CAN_ESR_TEC_Pos        (16U)
3018 #define CAN_ESR_TEC_Msk        (0xFFU << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
3019 #define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
3020 #define CAN_ESR_REC_Pos        (24U)
3021 #define CAN_ESR_REC_Msk        (0xFFU << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
3022 #define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
3023 
3024 /*******************  Bit definition for CAN_BTR register  ********************/
3025 #define CAN_BTR_BRP_Pos        (0U)
3026 #define CAN_BTR_BRP_Msk        (0x3FFU << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
3027 #define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
3028 #define CAN_BTR_TS1_Pos        (16U)
3029 #define CAN_BTR_TS1_Msk        (0xFU << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
3030 #define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
3031 #define CAN_BTR_TS1_0          (0x1U << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
3032 #define CAN_BTR_TS1_1          (0x2U << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
3033 #define CAN_BTR_TS1_2          (0x4U << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
3034 #define CAN_BTR_TS1_3          (0x8U << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
3035 #define CAN_BTR_TS2_Pos        (20U)
3036 #define CAN_BTR_TS2_Msk        (0x7U << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
3037 #define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
3038 #define CAN_BTR_TS2_0          (0x1U << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
3039 #define CAN_BTR_TS2_1          (0x2U << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
3040 #define CAN_BTR_TS2_2          (0x4U << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
3041 #define CAN_BTR_SJW_Pos        (24U)
3042 #define CAN_BTR_SJW_Msk        (0x3U << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
3043 #define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
3044 #define CAN_BTR_SJW_0          (0x1U << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
3045 #define CAN_BTR_SJW_1          (0x2U << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
3046 #define CAN_BTR_LBKM_Pos       (30U)
3047 #define CAN_BTR_LBKM_Msk       (0x1U << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
3048 #define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
3049 #define CAN_BTR_SILM_Pos       (31U)
3050 #define CAN_BTR_SILM_Msk       (0x1U << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
3051 #define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
3052 
3053 /*!<Mailbox registers */
3054 /******************  Bit definition for CAN_TI0R register  ********************/
3055 #define CAN_TI0R_TXRQ_Pos      (0U)
3056 #define CAN_TI0R_TXRQ_Msk      (0x1U << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
3057 #define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
3058 #define CAN_TI0R_RTR_Pos       (1U)
3059 #define CAN_TI0R_RTR_Msk       (0x1U << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
3060 #define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
3061 #define CAN_TI0R_IDE_Pos       (2U)
3062 #define CAN_TI0R_IDE_Msk       (0x1U << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
3063 #define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
3064 #define CAN_TI0R_EXID_Pos      (3U)
3065 #define CAN_TI0R_EXID_Msk      (0x3FFFFU << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
3066 #define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
3067 #define CAN_TI0R_STID_Pos      (21U)
3068 #define CAN_TI0R_STID_Msk      (0x7FFU << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
3069 #define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3070 
3071 /******************  Bit definition for CAN_TDT0R register  *******************/
3072 #define CAN_TDT0R_DLC_Pos      (0U)
3073 #define CAN_TDT0R_DLC_Msk      (0xFU << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
3074 #define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
3075 #define CAN_TDT0R_TGT_Pos      (8U)
3076 #define CAN_TDT0R_TGT_Msk      (0x1U << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
3077 #define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
3078 #define CAN_TDT0R_TIME_Pos     (16U)
3079 #define CAN_TDT0R_TIME_Msk     (0xFFFFU << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
3080 #define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
3081 
3082 /******************  Bit definition for CAN_TDL0R register  *******************/
3083 #define CAN_TDL0R_DATA0_Pos    (0U)
3084 #define CAN_TDL0R_DATA0_Msk    (0xFFU << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
3085 #define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
3086 #define CAN_TDL0R_DATA1_Pos    (8U)
3087 #define CAN_TDL0R_DATA1_Msk    (0xFFU << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
3088 #define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
3089 #define CAN_TDL0R_DATA2_Pos    (16U)
3090 #define CAN_TDL0R_DATA2_Msk    (0xFFU << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
3091 #define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
3092 #define CAN_TDL0R_DATA3_Pos    (24U)
3093 #define CAN_TDL0R_DATA3_Msk    (0xFFU << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
3094 #define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
3095 
3096 /******************  Bit definition for CAN_TDH0R register  *******************/
3097 #define CAN_TDH0R_DATA4_Pos    (0U)
3098 #define CAN_TDH0R_DATA4_Msk    (0xFFU << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
3099 #define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
3100 #define CAN_TDH0R_DATA5_Pos    (8U)
3101 #define CAN_TDH0R_DATA5_Msk    (0xFFU << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
3102 #define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
3103 #define CAN_TDH0R_DATA6_Pos    (16U)
3104 #define CAN_TDH0R_DATA6_Msk    (0xFFU << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
3105 #define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
3106 #define CAN_TDH0R_DATA7_Pos    (24U)
3107 #define CAN_TDH0R_DATA7_Msk    (0xFFU << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
3108 #define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
3109 
3110 /*******************  Bit definition for CAN_TI1R register  *******************/
3111 #define CAN_TI1R_TXRQ_Pos      (0U)
3112 #define CAN_TI1R_TXRQ_Msk      (0x1U << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
3113 #define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
3114 #define CAN_TI1R_RTR_Pos       (1U)
3115 #define CAN_TI1R_RTR_Msk       (0x1U << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
3116 #define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
3117 #define CAN_TI1R_IDE_Pos       (2U)
3118 #define CAN_TI1R_IDE_Msk       (0x1U << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
3119 #define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
3120 #define CAN_TI1R_EXID_Pos      (3U)
3121 #define CAN_TI1R_EXID_Msk      (0x3FFFFU << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
3122 #define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
3123 #define CAN_TI1R_STID_Pos      (21U)
3124 #define CAN_TI1R_STID_Msk      (0x7FFU << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
3125 #define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3126 
3127 /*******************  Bit definition for CAN_TDT1R register  ******************/
3128 #define CAN_TDT1R_DLC_Pos      (0U)
3129 #define CAN_TDT1R_DLC_Msk      (0xFU << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
3130 #define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
3131 #define CAN_TDT1R_TGT_Pos      (8U)
3132 #define CAN_TDT1R_TGT_Msk      (0x1U << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
3133 #define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
3134 #define CAN_TDT1R_TIME_Pos     (16U)
3135 #define CAN_TDT1R_TIME_Msk     (0xFFFFU << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
3136 #define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
3137 
3138 /*******************  Bit definition for CAN_TDL1R register  ******************/
3139 #define CAN_TDL1R_DATA0_Pos    (0U)
3140 #define CAN_TDL1R_DATA0_Msk    (0xFFU << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
3141 #define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
3142 #define CAN_TDL1R_DATA1_Pos    (8U)
3143 #define CAN_TDL1R_DATA1_Msk    (0xFFU << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
3144 #define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
3145 #define CAN_TDL1R_DATA2_Pos    (16U)
3146 #define CAN_TDL1R_DATA2_Msk    (0xFFU << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
3147 #define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
3148 #define CAN_TDL1R_DATA3_Pos    (24U)
3149 #define CAN_TDL1R_DATA3_Msk    (0xFFU << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
3150 #define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
3151 
3152 /*******************  Bit definition for CAN_TDH1R register  ******************/
3153 #define CAN_TDH1R_DATA4_Pos    (0U)
3154 #define CAN_TDH1R_DATA4_Msk    (0xFFU << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
3155 #define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
3156 #define CAN_TDH1R_DATA5_Pos    (8U)
3157 #define CAN_TDH1R_DATA5_Msk    (0xFFU << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
3158 #define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
3159 #define CAN_TDH1R_DATA6_Pos    (16U)
3160 #define CAN_TDH1R_DATA6_Msk    (0xFFU << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
3161 #define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
3162 #define CAN_TDH1R_DATA7_Pos    (24U)
3163 #define CAN_TDH1R_DATA7_Msk    (0xFFU << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
3164 #define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
3165 
3166 /*******************  Bit definition for CAN_TI2R register  *******************/
3167 #define CAN_TI2R_TXRQ_Pos      (0U)
3168 #define CAN_TI2R_TXRQ_Msk      (0x1U << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
3169 #define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
3170 #define CAN_TI2R_RTR_Pos       (1U)
3171 #define CAN_TI2R_RTR_Msk       (0x1U << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
3172 #define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
3173 #define CAN_TI2R_IDE_Pos       (2U)
3174 #define CAN_TI2R_IDE_Msk       (0x1U << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
3175 #define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
3176 #define CAN_TI2R_EXID_Pos      (3U)
3177 #define CAN_TI2R_EXID_Msk      (0x3FFFFU << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
3178 #define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
3179 #define CAN_TI2R_STID_Pos      (21U)
3180 #define CAN_TI2R_STID_Msk      (0x7FFU << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
3181 #define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3182 
3183 /*******************  Bit definition for CAN_TDT2R register  ******************/
3184 #define CAN_TDT2R_DLC_Pos      (0U)
3185 #define CAN_TDT2R_DLC_Msk      (0xFU << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
3186 #define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
3187 #define CAN_TDT2R_TGT_Pos      (8U)
3188 #define CAN_TDT2R_TGT_Msk      (0x1U << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
3189 #define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
3190 #define CAN_TDT2R_TIME_Pos     (16U)
3191 #define CAN_TDT2R_TIME_Msk     (0xFFFFU << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
3192 #define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
3193 
3194 /*******************  Bit definition for CAN_TDL2R register  ******************/
3195 #define CAN_TDL2R_DATA0_Pos    (0U)
3196 #define CAN_TDL2R_DATA0_Msk    (0xFFU << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
3197 #define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
3198 #define CAN_TDL2R_DATA1_Pos    (8U)
3199 #define CAN_TDL2R_DATA1_Msk    (0xFFU << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
3200 #define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
3201 #define CAN_TDL2R_DATA2_Pos    (16U)
3202 #define CAN_TDL2R_DATA2_Msk    (0xFFU << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
3203 #define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
3204 #define CAN_TDL2R_DATA3_Pos    (24U)
3205 #define CAN_TDL2R_DATA3_Msk    (0xFFU << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
3206 #define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
3207 
3208 /*******************  Bit definition for CAN_TDH2R register  ******************/
3209 #define CAN_TDH2R_DATA4_Pos    (0U)
3210 #define CAN_TDH2R_DATA4_Msk    (0xFFU << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
3211 #define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
3212 #define CAN_TDH2R_DATA5_Pos    (8U)
3213 #define CAN_TDH2R_DATA5_Msk    (0xFFU << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
3214 #define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
3215 #define CAN_TDH2R_DATA6_Pos    (16U)
3216 #define CAN_TDH2R_DATA6_Msk    (0xFFU << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
3217 #define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
3218 #define CAN_TDH2R_DATA7_Pos    (24U)
3219 #define CAN_TDH2R_DATA7_Msk    (0xFFU << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
3220 #define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
3221 
3222 /*******************  Bit definition for CAN_RI0R register  *******************/
3223 #define CAN_RI0R_RTR_Pos       (1U)
3224 #define CAN_RI0R_RTR_Msk       (0x1U << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
3225 #define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
3226 #define CAN_RI0R_IDE_Pos       (2U)
3227 #define CAN_RI0R_IDE_Msk       (0x1U << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
3228 #define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
3229 #define CAN_RI0R_EXID_Pos      (3U)
3230 #define CAN_RI0R_EXID_Msk      (0x3FFFFU << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
3231 #define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
3232 #define CAN_RI0R_STID_Pos      (21U)
3233 #define CAN_RI0R_STID_Msk      (0x7FFU << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
3234 #define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3235 
3236 /*******************  Bit definition for CAN_RDT0R register  ******************/
3237 #define CAN_RDT0R_DLC_Pos      (0U)
3238 #define CAN_RDT0R_DLC_Msk      (0xFU << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
3239 #define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
3240 #define CAN_RDT0R_FMI_Pos      (8U)
3241 #define CAN_RDT0R_FMI_Msk      (0xFFU << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
3242 #define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
3243 #define CAN_RDT0R_TIME_Pos     (16U)
3244 #define CAN_RDT0R_TIME_Msk     (0xFFFFU << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
3245 #define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
3246 
3247 /*******************  Bit definition for CAN_RDL0R register  ******************/
3248 #define CAN_RDL0R_DATA0_Pos    (0U)
3249 #define CAN_RDL0R_DATA0_Msk    (0xFFU << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
3250 #define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
3251 #define CAN_RDL0R_DATA1_Pos    (8U)
3252 #define CAN_RDL0R_DATA1_Msk    (0xFFU << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
3253 #define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
3254 #define CAN_RDL0R_DATA2_Pos    (16U)
3255 #define CAN_RDL0R_DATA2_Msk    (0xFFU << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
3256 #define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
3257 #define CAN_RDL0R_DATA3_Pos    (24U)
3258 #define CAN_RDL0R_DATA3_Msk    (0xFFU << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
3259 #define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
3260 
3261 /*******************  Bit definition for CAN_RDH0R register  ******************/
3262 #define CAN_RDH0R_DATA4_Pos    (0U)
3263 #define CAN_RDH0R_DATA4_Msk    (0xFFU << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
3264 #define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
3265 #define CAN_RDH0R_DATA5_Pos    (8U)
3266 #define CAN_RDH0R_DATA5_Msk    (0xFFU << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
3267 #define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
3268 #define CAN_RDH0R_DATA6_Pos    (16U)
3269 #define CAN_RDH0R_DATA6_Msk    (0xFFU << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
3270 #define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
3271 #define CAN_RDH0R_DATA7_Pos    (24U)
3272 #define CAN_RDH0R_DATA7_Msk    (0xFFU << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
3273 #define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
3274 
3275 /*******************  Bit definition for CAN_RI1R register  *******************/
3276 #define CAN_RI1R_RTR_Pos       (1U)
3277 #define CAN_RI1R_RTR_Msk       (0x1U << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
3278 #define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
3279 #define CAN_RI1R_IDE_Pos       (2U)
3280 #define CAN_RI1R_IDE_Msk       (0x1U << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
3281 #define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
3282 #define CAN_RI1R_EXID_Pos      (3U)
3283 #define CAN_RI1R_EXID_Msk      (0x3FFFFU << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
3284 #define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
3285 #define CAN_RI1R_STID_Pos      (21U)
3286 #define CAN_RI1R_STID_Msk      (0x7FFU << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
3287 #define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
3288 
3289 /*******************  Bit definition for CAN_RDT1R register  ******************/
3290 #define CAN_RDT1R_DLC_Pos      (0U)
3291 #define CAN_RDT1R_DLC_Msk      (0xFU << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
3292 #define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
3293 #define CAN_RDT1R_FMI_Pos      (8U)
3294 #define CAN_RDT1R_FMI_Msk      (0xFFU << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
3295 #define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
3296 #define CAN_RDT1R_TIME_Pos     (16U)
3297 #define CAN_RDT1R_TIME_Msk     (0xFFFFU << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
3298 #define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
3299 
3300 /*******************  Bit definition for CAN_RDL1R register  ******************/
3301 #define CAN_RDL1R_DATA0_Pos    (0U)
3302 #define CAN_RDL1R_DATA0_Msk    (0xFFU << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
3303 #define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
3304 #define CAN_RDL1R_DATA1_Pos    (8U)
3305 #define CAN_RDL1R_DATA1_Msk    (0xFFU << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
3306 #define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
3307 #define CAN_RDL1R_DATA2_Pos    (16U)
3308 #define CAN_RDL1R_DATA2_Msk    (0xFFU << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
3309 #define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
3310 #define CAN_RDL1R_DATA3_Pos    (24U)
3311 #define CAN_RDL1R_DATA3_Msk    (0xFFU << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
3312 #define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
3313 
3314 /*******************  Bit definition for CAN_RDH1R register  ******************/
3315 #define CAN_RDH1R_DATA4_Pos    (0U)
3316 #define CAN_RDH1R_DATA4_Msk    (0xFFU << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
3317 #define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
3318 #define CAN_RDH1R_DATA5_Pos    (8U)
3319 #define CAN_RDH1R_DATA5_Msk    (0xFFU << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
3320 #define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
3321 #define CAN_RDH1R_DATA6_Pos    (16U)
3322 #define CAN_RDH1R_DATA6_Msk    (0xFFU << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
3323 #define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
3324 #define CAN_RDH1R_DATA7_Pos    (24U)
3325 #define CAN_RDH1R_DATA7_Msk    (0xFFU << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
3326 #define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
3327 
3328 /*!<CAN filter registers */
3329 /*******************  Bit definition for CAN_FMR register  ********************/
3330 #define CAN_FMR_FINIT_Pos      (0U)
3331 #define CAN_FMR_FINIT_Msk      (0x1U << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
3332 #define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
3333 #define CAN_FMR_CAN2SB_Pos     (8U)
3334 #define CAN_FMR_CAN2SB_Msk     (0x3FU << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
3335 #define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank  */
3336 
3337 /*******************  Bit definition for CAN_FM1R register  *******************/
3338 #define CAN_FM1R_FBM_Pos       (0U)
3339 #define CAN_FM1R_FBM_Msk       (0x3FFFU << CAN_FM1R_FBM_Pos)                   /*!< 0x00003FFF */
3340 #define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
3341 #define CAN_FM1R_FBM0_Pos      (0U)
3342 #define CAN_FM1R_FBM0_Msk      (0x1U << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
3343 #define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
3344 #define CAN_FM1R_FBM1_Pos      (1U)
3345 #define CAN_FM1R_FBM1_Msk      (0x1U << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
3346 #define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
3347 #define CAN_FM1R_FBM2_Pos      (2U)
3348 #define CAN_FM1R_FBM2_Msk      (0x1U << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
3349 #define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
3350 #define CAN_FM1R_FBM3_Pos      (3U)
3351 #define CAN_FM1R_FBM3_Msk      (0x1U << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
3352 #define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
3353 #define CAN_FM1R_FBM4_Pos      (4U)
3354 #define CAN_FM1R_FBM4_Msk      (0x1U << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
3355 #define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
3356 #define CAN_FM1R_FBM5_Pos      (5U)
3357 #define CAN_FM1R_FBM5_Msk      (0x1U << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
3358 #define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
3359 #define CAN_FM1R_FBM6_Pos      (6U)
3360 #define CAN_FM1R_FBM6_Msk      (0x1U << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
3361 #define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
3362 #define CAN_FM1R_FBM7_Pos      (7U)
3363 #define CAN_FM1R_FBM7_Msk      (0x1U << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
3364 #define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
3365 #define CAN_FM1R_FBM8_Pos      (8U)
3366 #define CAN_FM1R_FBM8_Msk      (0x1U << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
3367 #define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
3368 #define CAN_FM1R_FBM9_Pos      (9U)
3369 #define CAN_FM1R_FBM9_Msk      (0x1U << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
3370 #define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
3371 #define CAN_FM1R_FBM10_Pos     (10U)
3372 #define CAN_FM1R_FBM10_Msk     (0x1U << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
3373 #define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
3374 #define CAN_FM1R_FBM11_Pos     (11U)
3375 #define CAN_FM1R_FBM11_Msk     (0x1U << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
3376 #define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
3377 #define CAN_FM1R_FBM12_Pos     (12U)
3378 #define CAN_FM1R_FBM12_Msk     (0x1U << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
3379 #define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
3380 #define CAN_FM1R_FBM13_Pos     (13U)
3381 #define CAN_FM1R_FBM13_Msk     (0x1U << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
3382 #define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
3383 
3384 /*******************  Bit definition for CAN_FS1R register  *******************/
3385 #define CAN_FS1R_FSC_Pos       (0U)
3386 #define CAN_FS1R_FSC_Msk       (0x3FFFU << CAN_FS1R_FSC_Pos)                   /*!< 0x00003FFF */
3387 #define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
3388 #define CAN_FS1R_FSC0_Pos      (0U)
3389 #define CAN_FS1R_FSC0_Msk      (0x1U << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
3390 #define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
3391 #define CAN_FS1R_FSC1_Pos      (1U)
3392 #define CAN_FS1R_FSC1_Msk      (0x1U << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
3393 #define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
3394 #define CAN_FS1R_FSC2_Pos      (2U)
3395 #define CAN_FS1R_FSC2_Msk      (0x1U << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
3396 #define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
3397 #define CAN_FS1R_FSC3_Pos      (3U)
3398 #define CAN_FS1R_FSC3_Msk      (0x1U << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
3399 #define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
3400 #define CAN_FS1R_FSC4_Pos      (4U)
3401 #define CAN_FS1R_FSC4_Msk      (0x1U << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
3402 #define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
3403 #define CAN_FS1R_FSC5_Pos      (5U)
3404 #define CAN_FS1R_FSC5_Msk      (0x1U << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
3405 #define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
3406 #define CAN_FS1R_FSC6_Pos      (6U)
3407 #define CAN_FS1R_FSC6_Msk      (0x1U << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
3408 #define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
3409 #define CAN_FS1R_FSC7_Pos      (7U)
3410 #define CAN_FS1R_FSC7_Msk      (0x1U << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
3411 #define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
3412 #define CAN_FS1R_FSC8_Pos      (8U)
3413 #define CAN_FS1R_FSC8_Msk      (0x1U << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
3414 #define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
3415 #define CAN_FS1R_FSC9_Pos      (9U)
3416 #define CAN_FS1R_FSC9_Msk      (0x1U << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
3417 #define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
3418 #define CAN_FS1R_FSC10_Pos     (10U)
3419 #define CAN_FS1R_FSC10_Msk     (0x1U << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
3420 #define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
3421 #define CAN_FS1R_FSC11_Pos     (11U)
3422 #define CAN_FS1R_FSC11_Msk     (0x1U << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
3423 #define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
3424 #define CAN_FS1R_FSC12_Pos     (12U)
3425 #define CAN_FS1R_FSC12_Msk     (0x1U << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
3426 #define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
3427 #define CAN_FS1R_FSC13_Pos     (13U)
3428 #define CAN_FS1R_FSC13_Msk     (0x1U << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
3429 #define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
3430 
3431 /******************  Bit definition for CAN_FFA1R register  *******************/
3432 #define CAN_FFA1R_FFA_Pos      (0U)
3433 #define CAN_FFA1R_FFA_Msk      (0x3FFFU << CAN_FFA1R_FFA_Pos)                  /*!< 0x00003FFF */
3434 #define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
3435 #define CAN_FFA1R_FFA0_Pos     (0U)
3436 #define CAN_FFA1R_FFA0_Msk     (0x1U << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
3437 #define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment for Filter 0 */
3438 #define CAN_FFA1R_FFA1_Pos     (1U)
3439 #define CAN_FFA1R_FFA1_Msk     (0x1U << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
3440 #define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment for Filter 1 */
3441 #define CAN_FFA1R_FFA2_Pos     (2U)
3442 #define CAN_FFA1R_FFA2_Msk     (0x1U << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
3443 #define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment for Filter 2 */
3444 #define CAN_FFA1R_FFA3_Pos     (3U)
3445 #define CAN_FFA1R_FFA3_Msk     (0x1U << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
3446 #define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment for Filter 3 */
3447 #define CAN_FFA1R_FFA4_Pos     (4U)
3448 #define CAN_FFA1R_FFA4_Msk     (0x1U << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
3449 #define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment for Filter 4 */
3450 #define CAN_FFA1R_FFA5_Pos     (5U)
3451 #define CAN_FFA1R_FFA5_Msk     (0x1U << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
3452 #define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment for Filter 5 */
3453 #define CAN_FFA1R_FFA6_Pos     (6U)
3454 #define CAN_FFA1R_FFA6_Msk     (0x1U << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
3455 #define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment for Filter 6 */
3456 #define CAN_FFA1R_FFA7_Pos     (7U)
3457 #define CAN_FFA1R_FFA7_Msk     (0x1U << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
3458 #define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment for Filter 7 */
3459 #define CAN_FFA1R_FFA8_Pos     (8U)
3460 #define CAN_FFA1R_FFA8_Msk     (0x1U << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
3461 #define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment for Filter 8 */
3462 #define CAN_FFA1R_FFA9_Pos     (9U)
3463 #define CAN_FFA1R_FFA9_Msk     (0x1U << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
3464 #define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment for Filter 9 */
3465 #define CAN_FFA1R_FFA10_Pos    (10U)
3466 #define CAN_FFA1R_FFA10_Msk    (0x1U << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
3467 #define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment for Filter 10 */
3468 #define CAN_FFA1R_FFA11_Pos    (11U)
3469 #define CAN_FFA1R_FFA11_Msk    (0x1U << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
3470 #define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment for Filter 11 */
3471 #define CAN_FFA1R_FFA12_Pos    (12U)
3472 #define CAN_FFA1R_FFA12_Msk    (0x1U << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
3473 #define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment for Filter 12 */
3474 #define CAN_FFA1R_FFA13_Pos    (13U)
3475 #define CAN_FFA1R_FFA13_Msk    (0x1U << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
3476 #define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment for Filter 13 */
3477 
3478 /*******************  Bit definition for CAN_FA1R register  *******************/
3479 #define CAN_FA1R_FACT_Pos      (0U)
3480 #define CAN_FA1R_FACT_Msk      (0x3FFFU << CAN_FA1R_FACT_Pos)                  /*!< 0x00003FFF */
3481 #define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
3482 #define CAN_FA1R_FACT0_Pos     (0U)
3483 #define CAN_FA1R_FACT0_Msk     (0x1U << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
3484 #define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter 0 Active */
3485 #define CAN_FA1R_FACT1_Pos     (1U)
3486 #define CAN_FA1R_FACT1_Msk     (0x1U << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
3487 #define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter 1 Active */
3488 #define CAN_FA1R_FACT2_Pos     (2U)
3489 #define CAN_FA1R_FACT2_Msk     (0x1U << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
3490 #define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter 2 Active */
3491 #define CAN_FA1R_FACT3_Pos     (3U)
3492 #define CAN_FA1R_FACT3_Msk     (0x1U << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
3493 #define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter 3 Active */
3494 #define CAN_FA1R_FACT4_Pos     (4U)
3495 #define CAN_FA1R_FACT4_Msk     (0x1U << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
3496 #define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter 4 Active */
3497 #define CAN_FA1R_FACT5_Pos     (5U)
3498 #define CAN_FA1R_FACT5_Msk     (0x1U << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
3499 #define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter 5 Active */
3500 #define CAN_FA1R_FACT6_Pos     (6U)
3501 #define CAN_FA1R_FACT6_Msk     (0x1U << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
3502 #define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter 6 Active */
3503 #define CAN_FA1R_FACT7_Pos     (7U)
3504 #define CAN_FA1R_FACT7_Msk     (0x1U << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
3505 #define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter 7 Active */
3506 #define CAN_FA1R_FACT8_Pos     (8U)
3507 #define CAN_FA1R_FACT8_Msk     (0x1U << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
3508 #define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter 8 Active */
3509 #define CAN_FA1R_FACT9_Pos     (9U)
3510 #define CAN_FA1R_FACT9_Msk     (0x1U << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
3511 #define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter 9 Active */
3512 #define CAN_FA1R_FACT10_Pos    (10U)
3513 #define CAN_FA1R_FACT10_Msk    (0x1U << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
3514 #define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter 10 Active */
3515 #define CAN_FA1R_FACT11_Pos    (11U)
3516 #define CAN_FA1R_FACT11_Msk    (0x1U << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
3517 #define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter 11 Active */
3518 #define CAN_FA1R_FACT12_Pos    (12U)
3519 #define CAN_FA1R_FACT12_Msk    (0x1U << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
3520 #define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter 12 Active */
3521 #define CAN_FA1R_FACT13_Pos    (13U)
3522 #define CAN_FA1R_FACT13_Msk    (0x1U << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
3523 #define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter 13 Active */
3524 
3525 /*******************  Bit definition for CAN_F0R1 register  *******************/
3526 #define CAN_F0R1_FB0_Pos       (0U)
3527 #define CAN_F0R1_FB0_Msk       (0x1U << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
3528 #define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
3529 #define CAN_F0R1_FB1_Pos       (1U)
3530 #define CAN_F0R1_FB1_Msk       (0x1U << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
3531 #define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
3532 #define CAN_F0R1_FB2_Pos       (2U)
3533 #define CAN_F0R1_FB2_Msk       (0x1U << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
3534 #define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
3535 #define CAN_F0R1_FB3_Pos       (3U)
3536 #define CAN_F0R1_FB3_Msk       (0x1U << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
3537 #define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
3538 #define CAN_F0R1_FB4_Pos       (4U)
3539 #define CAN_F0R1_FB4_Msk       (0x1U << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
3540 #define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
3541 #define CAN_F0R1_FB5_Pos       (5U)
3542 #define CAN_F0R1_FB5_Msk       (0x1U << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
3543 #define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
3544 #define CAN_F0R1_FB6_Pos       (6U)
3545 #define CAN_F0R1_FB6_Msk       (0x1U << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
3546 #define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
3547 #define CAN_F0R1_FB7_Pos       (7U)
3548 #define CAN_F0R1_FB7_Msk       (0x1U << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
3549 #define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
3550 #define CAN_F0R1_FB8_Pos       (8U)
3551 #define CAN_F0R1_FB8_Msk       (0x1U << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
3552 #define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
3553 #define CAN_F0R1_FB9_Pos       (9U)
3554 #define CAN_F0R1_FB9_Msk       (0x1U << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
3555 #define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
3556 #define CAN_F0R1_FB10_Pos      (10U)
3557 #define CAN_F0R1_FB10_Msk      (0x1U << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
3558 #define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
3559 #define CAN_F0R1_FB11_Pos      (11U)
3560 #define CAN_F0R1_FB11_Msk      (0x1U << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
3561 #define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
3562 #define CAN_F0R1_FB12_Pos      (12U)
3563 #define CAN_F0R1_FB12_Msk      (0x1U << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
3564 #define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
3565 #define CAN_F0R1_FB13_Pos      (13U)
3566 #define CAN_F0R1_FB13_Msk      (0x1U << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
3567 #define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
3568 #define CAN_F0R1_FB14_Pos      (14U)
3569 #define CAN_F0R1_FB14_Msk      (0x1U << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
3570 #define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
3571 #define CAN_F0R1_FB15_Pos      (15U)
3572 #define CAN_F0R1_FB15_Msk      (0x1U << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
3573 #define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
3574 #define CAN_F0R1_FB16_Pos      (16U)
3575 #define CAN_F0R1_FB16_Msk      (0x1U << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
3576 #define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
3577 #define CAN_F0R1_FB17_Pos      (17U)
3578 #define CAN_F0R1_FB17_Msk      (0x1U << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
3579 #define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
3580 #define CAN_F0R1_FB18_Pos      (18U)
3581 #define CAN_F0R1_FB18_Msk      (0x1U << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
3582 #define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
3583 #define CAN_F0R1_FB19_Pos      (19U)
3584 #define CAN_F0R1_FB19_Msk      (0x1U << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
3585 #define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
3586 #define CAN_F0R1_FB20_Pos      (20U)
3587 #define CAN_F0R1_FB20_Msk      (0x1U << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
3588 #define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
3589 #define CAN_F0R1_FB21_Pos      (21U)
3590 #define CAN_F0R1_FB21_Msk      (0x1U << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
3591 #define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
3592 #define CAN_F0R1_FB22_Pos      (22U)
3593 #define CAN_F0R1_FB22_Msk      (0x1U << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
3594 #define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
3595 #define CAN_F0R1_FB23_Pos      (23U)
3596 #define CAN_F0R1_FB23_Msk      (0x1U << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
3597 #define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
3598 #define CAN_F0R1_FB24_Pos      (24U)
3599 #define CAN_F0R1_FB24_Msk      (0x1U << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
3600 #define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
3601 #define CAN_F0R1_FB25_Pos      (25U)
3602 #define CAN_F0R1_FB25_Msk      (0x1U << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
3603 #define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
3604 #define CAN_F0R1_FB26_Pos      (26U)
3605 #define CAN_F0R1_FB26_Msk      (0x1U << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
3606 #define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
3607 #define CAN_F0R1_FB27_Pos      (27U)
3608 #define CAN_F0R1_FB27_Msk      (0x1U << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
3609 #define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
3610 #define CAN_F0R1_FB28_Pos      (28U)
3611 #define CAN_F0R1_FB28_Msk      (0x1U << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
3612 #define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
3613 #define CAN_F0R1_FB29_Pos      (29U)
3614 #define CAN_F0R1_FB29_Msk      (0x1U << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
3615 #define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
3616 #define CAN_F0R1_FB30_Pos      (30U)
3617 #define CAN_F0R1_FB30_Msk      (0x1U << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
3618 #define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
3619 #define CAN_F0R1_FB31_Pos      (31U)
3620 #define CAN_F0R1_FB31_Msk      (0x1U << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
3621 #define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
3622 
3623 /*******************  Bit definition for CAN_F1R1 register  *******************/
3624 #define CAN_F1R1_FB0_Pos       (0U)
3625 #define CAN_F1R1_FB0_Msk       (0x1U << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
3626 #define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
3627 #define CAN_F1R1_FB1_Pos       (1U)
3628 #define CAN_F1R1_FB1_Msk       (0x1U << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
3629 #define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
3630 #define CAN_F1R1_FB2_Pos       (2U)
3631 #define CAN_F1R1_FB2_Msk       (0x1U << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
3632 #define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
3633 #define CAN_F1R1_FB3_Pos       (3U)
3634 #define CAN_F1R1_FB3_Msk       (0x1U << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
3635 #define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
3636 #define CAN_F1R1_FB4_Pos       (4U)
3637 #define CAN_F1R1_FB4_Msk       (0x1U << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
3638 #define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
3639 #define CAN_F1R1_FB5_Pos       (5U)
3640 #define CAN_F1R1_FB5_Msk       (0x1U << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
3641 #define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
3642 #define CAN_F1R1_FB6_Pos       (6U)
3643 #define CAN_F1R1_FB6_Msk       (0x1U << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
3644 #define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
3645 #define CAN_F1R1_FB7_Pos       (7U)
3646 #define CAN_F1R1_FB7_Msk       (0x1U << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
3647 #define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
3648 #define CAN_F1R1_FB8_Pos       (8U)
3649 #define CAN_F1R1_FB8_Msk       (0x1U << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
3650 #define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
3651 #define CAN_F1R1_FB9_Pos       (9U)
3652 #define CAN_F1R1_FB9_Msk       (0x1U << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
3653 #define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
3654 #define CAN_F1R1_FB10_Pos      (10U)
3655 #define CAN_F1R1_FB10_Msk      (0x1U << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
3656 #define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
3657 #define CAN_F1R1_FB11_Pos      (11U)
3658 #define CAN_F1R1_FB11_Msk      (0x1U << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
3659 #define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
3660 #define CAN_F1R1_FB12_Pos      (12U)
3661 #define CAN_F1R1_FB12_Msk      (0x1U << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
3662 #define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
3663 #define CAN_F1R1_FB13_Pos      (13U)
3664 #define CAN_F1R1_FB13_Msk      (0x1U << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
3665 #define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
3666 #define CAN_F1R1_FB14_Pos      (14U)
3667 #define CAN_F1R1_FB14_Msk      (0x1U << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
3668 #define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
3669 #define CAN_F1R1_FB15_Pos      (15U)
3670 #define CAN_F1R1_FB15_Msk      (0x1U << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
3671 #define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
3672 #define CAN_F1R1_FB16_Pos      (16U)
3673 #define CAN_F1R1_FB16_Msk      (0x1U << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
3674 #define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
3675 #define CAN_F1R1_FB17_Pos      (17U)
3676 #define CAN_F1R1_FB17_Msk      (0x1U << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
3677 #define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
3678 #define CAN_F1R1_FB18_Pos      (18U)
3679 #define CAN_F1R1_FB18_Msk      (0x1U << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
3680 #define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
3681 #define CAN_F1R1_FB19_Pos      (19U)
3682 #define CAN_F1R1_FB19_Msk      (0x1U << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
3683 #define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
3684 #define CAN_F1R1_FB20_Pos      (20U)
3685 #define CAN_F1R1_FB20_Msk      (0x1U << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
3686 #define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
3687 #define CAN_F1R1_FB21_Pos      (21U)
3688 #define CAN_F1R1_FB21_Msk      (0x1U << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
3689 #define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
3690 #define CAN_F1R1_FB22_Pos      (22U)
3691 #define CAN_F1R1_FB22_Msk      (0x1U << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
3692 #define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
3693 #define CAN_F1R1_FB23_Pos      (23U)
3694 #define CAN_F1R1_FB23_Msk      (0x1U << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
3695 #define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
3696 #define CAN_F1R1_FB24_Pos      (24U)
3697 #define CAN_F1R1_FB24_Msk      (0x1U << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
3698 #define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
3699 #define CAN_F1R1_FB25_Pos      (25U)
3700 #define CAN_F1R1_FB25_Msk      (0x1U << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
3701 #define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
3702 #define CAN_F1R1_FB26_Pos      (26U)
3703 #define CAN_F1R1_FB26_Msk      (0x1U << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
3704 #define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
3705 #define CAN_F1R1_FB27_Pos      (27U)
3706 #define CAN_F1R1_FB27_Msk      (0x1U << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
3707 #define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
3708 #define CAN_F1R1_FB28_Pos      (28U)
3709 #define CAN_F1R1_FB28_Msk      (0x1U << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
3710 #define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
3711 #define CAN_F1R1_FB29_Pos      (29U)
3712 #define CAN_F1R1_FB29_Msk      (0x1U << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
3713 #define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
3714 #define CAN_F1R1_FB30_Pos      (30U)
3715 #define CAN_F1R1_FB30_Msk      (0x1U << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
3716 #define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
3717 #define CAN_F1R1_FB31_Pos      (31U)
3718 #define CAN_F1R1_FB31_Msk      (0x1U << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
3719 #define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
3720 
3721 /*******************  Bit definition for CAN_F2R1 register  *******************/
3722 #define CAN_F2R1_FB0_Pos       (0U)
3723 #define CAN_F2R1_FB0_Msk       (0x1U << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
3724 #define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
3725 #define CAN_F2R1_FB1_Pos       (1U)
3726 #define CAN_F2R1_FB1_Msk       (0x1U << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
3727 #define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
3728 #define CAN_F2R1_FB2_Pos       (2U)
3729 #define CAN_F2R1_FB2_Msk       (0x1U << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
3730 #define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
3731 #define CAN_F2R1_FB3_Pos       (3U)
3732 #define CAN_F2R1_FB3_Msk       (0x1U << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
3733 #define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
3734 #define CAN_F2R1_FB4_Pos       (4U)
3735 #define CAN_F2R1_FB4_Msk       (0x1U << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
3736 #define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
3737 #define CAN_F2R1_FB5_Pos       (5U)
3738 #define CAN_F2R1_FB5_Msk       (0x1U << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
3739 #define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
3740 #define CAN_F2R1_FB6_Pos       (6U)
3741 #define CAN_F2R1_FB6_Msk       (0x1U << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
3742 #define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
3743 #define CAN_F2R1_FB7_Pos       (7U)
3744 #define CAN_F2R1_FB7_Msk       (0x1U << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
3745 #define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
3746 #define CAN_F2R1_FB8_Pos       (8U)
3747 #define CAN_F2R1_FB8_Msk       (0x1U << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
3748 #define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
3749 #define CAN_F2R1_FB9_Pos       (9U)
3750 #define CAN_F2R1_FB9_Msk       (0x1U << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
3751 #define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
3752 #define CAN_F2R1_FB10_Pos      (10U)
3753 #define CAN_F2R1_FB10_Msk      (0x1U << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
3754 #define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
3755 #define CAN_F2R1_FB11_Pos      (11U)
3756 #define CAN_F2R1_FB11_Msk      (0x1U << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
3757 #define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
3758 #define CAN_F2R1_FB12_Pos      (12U)
3759 #define CAN_F2R1_FB12_Msk      (0x1U << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
3760 #define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
3761 #define CAN_F2R1_FB13_Pos      (13U)
3762 #define CAN_F2R1_FB13_Msk      (0x1U << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
3763 #define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
3764 #define CAN_F2R1_FB14_Pos      (14U)
3765 #define CAN_F2R1_FB14_Msk      (0x1U << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
3766 #define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
3767 #define CAN_F2R1_FB15_Pos      (15U)
3768 #define CAN_F2R1_FB15_Msk      (0x1U << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
3769 #define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
3770 #define CAN_F2R1_FB16_Pos      (16U)
3771 #define CAN_F2R1_FB16_Msk      (0x1U << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
3772 #define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
3773 #define CAN_F2R1_FB17_Pos      (17U)
3774 #define CAN_F2R1_FB17_Msk      (0x1U << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
3775 #define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
3776 #define CAN_F2R1_FB18_Pos      (18U)
3777 #define CAN_F2R1_FB18_Msk      (0x1U << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
3778 #define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
3779 #define CAN_F2R1_FB19_Pos      (19U)
3780 #define CAN_F2R1_FB19_Msk      (0x1U << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
3781 #define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
3782 #define CAN_F2R1_FB20_Pos      (20U)
3783 #define CAN_F2R1_FB20_Msk      (0x1U << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
3784 #define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
3785 #define CAN_F2R1_FB21_Pos      (21U)
3786 #define CAN_F2R1_FB21_Msk      (0x1U << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
3787 #define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
3788 #define CAN_F2R1_FB22_Pos      (22U)
3789 #define CAN_F2R1_FB22_Msk      (0x1U << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
3790 #define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
3791 #define CAN_F2R1_FB23_Pos      (23U)
3792 #define CAN_F2R1_FB23_Msk      (0x1U << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
3793 #define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
3794 #define CAN_F2R1_FB24_Pos      (24U)
3795 #define CAN_F2R1_FB24_Msk      (0x1U << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
3796 #define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
3797 #define CAN_F2R1_FB25_Pos      (25U)
3798 #define CAN_F2R1_FB25_Msk      (0x1U << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
3799 #define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
3800 #define CAN_F2R1_FB26_Pos      (26U)
3801 #define CAN_F2R1_FB26_Msk      (0x1U << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
3802 #define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
3803 #define CAN_F2R1_FB27_Pos      (27U)
3804 #define CAN_F2R1_FB27_Msk      (0x1U << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
3805 #define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
3806 #define CAN_F2R1_FB28_Pos      (28U)
3807 #define CAN_F2R1_FB28_Msk      (0x1U << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
3808 #define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
3809 #define CAN_F2R1_FB29_Pos      (29U)
3810 #define CAN_F2R1_FB29_Msk      (0x1U << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
3811 #define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
3812 #define CAN_F2R1_FB30_Pos      (30U)
3813 #define CAN_F2R1_FB30_Msk      (0x1U << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
3814 #define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
3815 #define CAN_F2R1_FB31_Pos      (31U)
3816 #define CAN_F2R1_FB31_Msk      (0x1U << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
3817 #define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
3818 
3819 /*******************  Bit definition for CAN_F3R1 register  *******************/
3820 #define CAN_F3R1_FB0_Pos       (0U)
3821 #define CAN_F3R1_FB0_Msk       (0x1U << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
3822 #define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
3823 #define CAN_F3R1_FB1_Pos       (1U)
3824 #define CAN_F3R1_FB1_Msk       (0x1U << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
3825 #define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
3826 #define CAN_F3R1_FB2_Pos       (2U)
3827 #define CAN_F3R1_FB2_Msk       (0x1U << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
3828 #define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
3829 #define CAN_F3R1_FB3_Pos       (3U)
3830 #define CAN_F3R1_FB3_Msk       (0x1U << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
3831 #define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
3832 #define CAN_F3R1_FB4_Pos       (4U)
3833 #define CAN_F3R1_FB4_Msk       (0x1U << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
3834 #define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
3835 #define CAN_F3R1_FB5_Pos       (5U)
3836 #define CAN_F3R1_FB5_Msk       (0x1U << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
3837 #define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
3838 #define CAN_F3R1_FB6_Pos       (6U)
3839 #define CAN_F3R1_FB6_Msk       (0x1U << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
3840 #define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
3841 #define CAN_F3R1_FB7_Pos       (7U)
3842 #define CAN_F3R1_FB7_Msk       (0x1U << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
3843 #define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
3844 #define CAN_F3R1_FB8_Pos       (8U)
3845 #define CAN_F3R1_FB8_Msk       (0x1U << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
3846 #define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
3847 #define CAN_F3R1_FB9_Pos       (9U)
3848 #define CAN_F3R1_FB9_Msk       (0x1U << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
3849 #define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
3850 #define CAN_F3R1_FB10_Pos      (10U)
3851 #define CAN_F3R1_FB10_Msk      (0x1U << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
3852 #define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
3853 #define CAN_F3R1_FB11_Pos      (11U)
3854 #define CAN_F3R1_FB11_Msk      (0x1U << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
3855 #define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
3856 #define CAN_F3R1_FB12_Pos      (12U)
3857 #define CAN_F3R1_FB12_Msk      (0x1U << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
3858 #define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
3859 #define CAN_F3R1_FB13_Pos      (13U)
3860 #define CAN_F3R1_FB13_Msk      (0x1U << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
3861 #define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
3862 #define CAN_F3R1_FB14_Pos      (14U)
3863 #define CAN_F3R1_FB14_Msk      (0x1U << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
3864 #define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
3865 #define CAN_F3R1_FB15_Pos      (15U)
3866 #define CAN_F3R1_FB15_Msk      (0x1U << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
3867 #define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
3868 #define CAN_F3R1_FB16_Pos      (16U)
3869 #define CAN_F3R1_FB16_Msk      (0x1U << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
3870 #define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
3871 #define CAN_F3R1_FB17_Pos      (17U)
3872 #define CAN_F3R1_FB17_Msk      (0x1U << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
3873 #define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
3874 #define CAN_F3R1_FB18_Pos      (18U)
3875 #define CAN_F3R1_FB18_Msk      (0x1U << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
3876 #define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
3877 #define CAN_F3R1_FB19_Pos      (19U)
3878 #define CAN_F3R1_FB19_Msk      (0x1U << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
3879 #define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
3880 #define CAN_F3R1_FB20_Pos      (20U)
3881 #define CAN_F3R1_FB20_Msk      (0x1U << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
3882 #define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
3883 #define CAN_F3R1_FB21_Pos      (21U)
3884 #define CAN_F3R1_FB21_Msk      (0x1U << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
3885 #define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
3886 #define CAN_F3R1_FB22_Pos      (22U)
3887 #define CAN_F3R1_FB22_Msk      (0x1U << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
3888 #define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
3889 #define CAN_F3R1_FB23_Pos      (23U)
3890 #define CAN_F3R1_FB23_Msk      (0x1U << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
3891 #define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
3892 #define CAN_F3R1_FB24_Pos      (24U)
3893 #define CAN_F3R1_FB24_Msk      (0x1U << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
3894 #define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
3895 #define CAN_F3R1_FB25_Pos      (25U)
3896 #define CAN_F3R1_FB25_Msk      (0x1U << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
3897 #define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
3898 #define CAN_F3R1_FB26_Pos      (26U)
3899 #define CAN_F3R1_FB26_Msk      (0x1U << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
3900 #define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
3901 #define CAN_F3R1_FB27_Pos      (27U)
3902 #define CAN_F3R1_FB27_Msk      (0x1U << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
3903 #define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
3904 #define CAN_F3R1_FB28_Pos      (28U)
3905 #define CAN_F3R1_FB28_Msk      (0x1U << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
3906 #define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
3907 #define CAN_F3R1_FB29_Pos      (29U)
3908 #define CAN_F3R1_FB29_Msk      (0x1U << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
3909 #define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
3910 #define CAN_F3R1_FB30_Pos      (30U)
3911 #define CAN_F3R1_FB30_Msk      (0x1U << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
3912 #define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
3913 #define CAN_F3R1_FB31_Pos      (31U)
3914 #define CAN_F3R1_FB31_Msk      (0x1U << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
3915 #define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
3916 
3917 /*******************  Bit definition for CAN_F4R1 register  *******************/
3918 #define CAN_F4R1_FB0_Pos       (0U)
3919 #define CAN_F4R1_FB0_Msk       (0x1U << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
3920 #define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
3921 #define CAN_F4R1_FB1_Pos       (1U)
3922 #define CAN_F4R1_FB1_Msk       (0x1U << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
3923 #define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
3924 #define CAN_F4R1_FB2_Pos       (2U)
3925 #define CAN_F4R1_FB2_Msk       (0x1U << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
3926 #define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
3927 #define CAN_F4R1_FB3_Pos       (3U)
3928 #define CAN_F4R1_FB3_Msk       (0x1U << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
3929 #define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
3930 #define CAN_F4R1_FB4_Pos       (4U)
3931 #define CAN_F4R1_FB4_Msk       (0x1U << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
3932 #define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
3933 #define CAN_F4R1_FB5_Pos       (5U)
3934 #define CAN_F4R1_FB5_Msk       (0x1U << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
3935 #define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
3936 #define CAN_F4R1_FB6_Pos       (6U)
3937 #define CAN_F4R1_FB6_Msk       (0x1U << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
3938 #define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
3939 #define CAN_F4R1_FB7_Pos       (7U)
3940 #define CAN_F4R1_FB7_Msk       (0x1U << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
3941 #define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
3942 #define CAN_F4R1_FB8_Pos       (8U)
3943 #define CAN_F4R1_FB8_Msk       (0x1U << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
3944 #define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
3945 #define CAN_F4R1_FB9_Pos       (9U)
3946 #define CAN_F4R1_FB9_Msk       (0x1U << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
3947 #define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
3948 #define CAN_F4R1_FB10_Pos      (10U)
3949 #define CAN_F4R1_FB10_Msk      (0x1U << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
3950 #define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
3951 #define CAN_F4R1_FB11_Pos      (11U)
3952 #define CAN_F4R1_FB11_Msk      (0x1U << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
3953 #define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
3954 #define CAN_F4R1_FB12_Pos      (12U)
3955 #define CAN_F4R1_FB12_Msk      (0x1U << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
3956 #define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
3957 #define CAN_F4R1_FB13_Pos      (13U)
3958 #define CAN_F4R1_FB13_Msk      (0x1U << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
3959 #define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
3960 #define CAN_F4R1_FB14_Pos      (14U)
3961 #define CAN_F4R1_FB14_Msk      (0x1U << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
3962 #define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
3963 #define CAN_F4R1_FB15_Pos      (15U)
3964 #define CAN_F4R1_FB15_Msk      (0x1U << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
3965 #define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
3966 #define CAN_F4R1_FB16_Pos      (16U)
3967 #define CAN_F4R1_FB16_Msk      (0x1U << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
3968 #define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
3969 #define CAN_F4R1_FB17_Pos      (17U)
3970 #define CAN_F4R1_FB17_Msk      (0x1U << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
3971 #define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
3972 #define CAN_F4R1_FB18_Pos      (18U)
3973 #define CAN_F4R1_FB18_Msk      (0x1U << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
3974 #define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
3975 #define CAN_F4R1_FB19_Pos      (19U)
3976 #define CAN_F4R1_FB19_Msk      (0x1U << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
3977 #define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
3978 #define CAN_F4R1_FB20_Pos      (20U)
3979 #define CAN_F4R1_FB20_Msk      (0x1U << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
3980 #define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
3981 #define CAN_F4R1_FB21_Pos      (21U)
3982 #define CAN_F4R1_FB21_Msk      (0x1U << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
3983 #define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
3984 #define CAN_F4R1_FB22_Pos      (22U)
3985 #define CAN_F4R1_FB22_Msk      (0x1U << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
3986 #define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
3987 #define CAN_F4R1_FB23_Pos      (23U)
3988 #define CAN_F4R1_FB23_Msk      (0x1U << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
3989 #define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
3990 #define CAN_F4R1_FB24_Pos      (24U)
3991 #define CAN_F4R1_FB24_Msk      (0x1U << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
3992 #define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
3993 #define CAN_F4R1_FB25_Pos      (25U)
3994 #define CAN_F4R1_FB25_Msk      (0x1U << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
3995 #define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
3996 #define CAN_F4R1_FB26_Pos      (26U)
3997 #define CAN_F4R1_FB26_Msk      (0x1U << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
3998 #define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
3999 #define CAN_F4R1_FB27_Pos      (27U)
4000 #define CAN_F4R1_FB27_Msk      (0x1U << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
4001 #define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
4002 #define CAN_F4R1_FB28_Pos      (28U)
4003 #define CAN_F4R1_FB28_Msk      (0x1U << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
4004 #define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
4005 #define CAN_F4R1_FB29_Pos      (29U)
4006 #define CAN_F4R1_FB29_Msk      (0x1U << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
4007 #define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
4008 #define CAN_F4R1_FB30_Pos      (30U)
4009 #define CAN_F4R1_FB30_Msk      (0x1U << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
4010 #define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
4011 #define CAN_F4R1_FB31_Pos      (31U)
4012 #define CAN_F4R1_FB31_Msk      (0x1U << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
4013 #define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
4014 
4015 /*******************  Bit definition for CAN_F5R1 register  *******************/
4016 #define CAN_F5R1_FB0_Pos       (0U)
4017 #define CAN_F5R1_FB0_Msk       (0x1U << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
4018 #define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
4019 #define CAN_F5R1_FB1_Pos       (1U)
4020 #define CAN_F5R1_FB1_Msk       (0x1U << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
4021 #define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
4022 #define CAN_F5R1_FB2_Pos       (2U)
4023 #define CAN_F5R1_FB2_Msk       (0x1U << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
4024 #define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
4025 #define CAN_F5R1_FB3_Pos       (3U)
4026 #define CAN_F5R1_FB3_Msk       (0x1U << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
4027 #define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
4028 #define CAN_F5R1_FB4_Pos       (4U)
4029 #define CAN_F5R1_FB4_Msk       (0x1U << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
4030 #define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
4031 #define CAN_F5R1_FB5_Pos       (5U)
4032 #define CAN_F5R1_FB5_Msk       (0x1U << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
4033 #define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
4034 #define CAN_F5R1_FB6_Pos       (6U)
4035 #define CAN_F5R1_FB6_Msk       (0x1U << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
4036 #define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
4037 #define CAN_F5R1_FB7_Pos       (7U)
4038 #define CAN_F5R1_FB7_Msk       (0x1U << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
4039 #define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
4040 #define CAN_F5R1_FB8_Pos       (8U)
4041 #define CAN_F5R1_FB8_Msk       (0x1U << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
4042 #define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
4043 #define CAN_F5R1_FB9_Pos       (9U)
4044 #define CAN_F5R1_FB9_Msk       (0x1U << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
4045 #define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
4046 #define CAN_F5R1_FB10_Pos      (10U)
4047 #define CAN_F5R1_FB10_Msk      (0x1U << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
4048 #define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
4049 #define CAN_F5R1_FB11_Pos      (11U)
4050 #define CAN_F5R1_FB11_Msk      (0x1U << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
4051 #define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
4052 #define CAN_F5R1_FB12_Pos      (12U)
4053 #define CAN_F5R1_FB12_Msk      (0x1U << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
4054 #define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
4055 #define CAN_F5R1_FB13_Pos      (13U)
4056 #define CAN_F5R1_FB13_Msk      (0x1U << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
4057 #define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
4058 #define CAN_F5R1_FB14_Pos      (14U)
4059 #define CAN_F5R1_FB14_Msk      (0x1U << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
4060 #define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
4061 #define CAN_F5R1_FB15_Pos      (15U)
4062 #define CAN_F5R1_FB15_Msk      (0x1U << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
4063 #define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
4064 #define CAN_F5R1_FB16_Pos      (16U)
4065 #define CAN_F5R1_FB16_Msk      (0x1U << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
4066 #define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
4067 #define CAN_F5R1_FB17_Pos      (17U)
4068 #define CAN_F5R1_FB17_Msk      (0x1U << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
4069 #define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
4070 #define CAN_F5R1_FB18_Pos      (18U)
4071 #define CAN_F5R1_FB18_Msk      (0x1U << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
4072 #define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
4073 #define CAN_F5R1_FB19_Pos      (19U)
4074 #define CAN_F5R1_FB19_Msk      (0x1U << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
4075 #define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
4076 #define CAN_F5R1_FB20_Pos      (20U)
4077 #define CAN_F5R1_FB20_Msk      (0x1U << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
4078 #define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
4079 #define CAN_F5R1_FB21_Pos      (21U)
4080 #define CAN_F5R1_FB21_Msk      (0x1U << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
4081 #define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
4082 #define CAN_F5R1_FB22_Pos      (22U)
4083 #define CAN_F5R1_FB22_Msk      (0x1U << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
4084 #define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
4085 #define CAN_F5R1_FB23_Pos      (23U)
4086 #define CAN_F5R1_FB23_Msk      (0x1U << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
4087 #define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
4088 #define CAN_F5R1_FB24_Pos      (24U)
4089 #define CAN_F5R1_FB24_Msk      (0x1U << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
4090 #define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
4091 #define CAN_F5R1_FB25_Pos      (25U)
4092 #define CAN_F5R1_FB25_Msk      (0x1U << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
4093 #define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
4094 #define CAN_F5R1_FB26_Pos      (26U)
4095 #define CAN_F5R1_FB26_Msk      (0x1U << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
4096 #define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
4097 #define CAN_F5R1_FB27_Pos      (27U)
4098 #define CAN_F5R1_FB27_Msk      (0x1U << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
4099 #define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
4100 #define CAN_F5R1_FB28_Pos      (28U)
4101 #define CAN_F5R1_FB28_Msk      (0x1U << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
4102 #define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
4103 #define CAN_F5R1_FB29_Pos      (29U)
4104 #define CAN_F5R1_FB29_Msk      (0x1U << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
4105 #define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
4106 #define CAN_F5R1_FB30_Pos      (30U)
4107 #define CAN_F5R1_FB30_Msk      (0x1U << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
4108 #define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
4109 #define CAN_F5R1_FB31_Pos      (31U)
4110 #define CAN_F5R1_FB31_Msk      (0x1U << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
4111 #define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
4112 
4113 /*******************  Bit definition for CAN_F6R1 register  *******************/
4114 #define CAN_F6R1_FB0_Pos       (0U)
4115 #define CAN_F6R1_FB0_Msk       (0x1U << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
4116 #define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
4117 #define CAN_F6R1_FB1_Pos       (1U)
4118 #define CAN_F6R1_FB1_Msk       (0x1U << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
4119 #define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
4120 #define CAN_F6R1_FB2_Pos       (2U)
4121 #define CAN_F6R1_FB2_Msk       (0x1U << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
4122 #define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
4123 #define CAN_F6R1_FB3_Pos       (3U)
4124 #define CAN_F6R1_FB3_Msk       (0x1U << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
4125 #define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
4126 #define CAN_F6R1_FB4_Pos       (4U)
4127 #define CAN_F6R1_FB4_Msk       (0x1U << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
4128 #define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
4129 #define CAN_F6R1_FB5_Pos       (5U)
4130 #define CAN_F6R1_FB5_Msk       (0x1U << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
4131 #define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
4132 #define CAN_F6R1_FB6_Pos       (6U)
4133 #define CAN_F6R1_FB6_Msk       (0x1U << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
4134 #define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
4135 #define CAN_F6R1_FB7_Pos       (7U)
4136 #define CAN_F6R1_FB7_Msk       (0x1U << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
4137 #define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
4138 #define CAN_F6R1_FB8_Pos       (8U)
4139 #define CAN_F6R1_FB8_Msk       (0x1U << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
4140 #define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
4141 #define CAN_F6R1_FB9_Pos       (9U)
4142 #define CAN_F6R1_FB9_Msk       (0x1U << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
4143 #define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
4144 #define CAN_F6R1_FB10_Pos      (10U)
4145 #define CAN_F6R1_FB10_Msk      (0x1U << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
4146 #define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
4147 #define CAN_F6R1_FB11_Pos      (11U)
4148 #define CAN_F6R1_FB11_Msk      (0x1U << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
4149 #define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
4150 #define CAN_F6R1_FB12_Pos      (12U)
4151 #define CAN_F6R1_FB12_Msk      (0x1U << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
4152 #define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
4153 #define CAN_F6R1_FB13_Pos      (13U)
4154 #define CAN_F6R1_FB13_Msk      (0x1U << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
4155 #define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
4156 #define CAN_F6R1_FB14_Pos      (14U)
4157 #define CAN_F6R1_FB14_Msk      (0x1U << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
4158 #define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
4159 #define CAN_F6R1_FB15_Pos      (15U)
4160 #define CAN_F6R1_FB15_Msk      (0x1U << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
4161 #define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
4162 #define CAN_F6R1_FB16_Pos      (16U)
4163 #define CAN_F6R1_FB16_Msk      (0x1U << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
4164 #define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
4165 #define CAN_F6R1_FB17_Pos      (17U)
4166 #define CAN_F6R1_FB17_Msk      (0x1U << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
4167 #define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
4168 #define CAN_F6R1_FB18_Pos      (18U)
4169 #define CAN_F6R1_FB18_Msk      (0x1U << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
4170 #define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
4171 #define CAN_F6R1_FB19_Pos      (19U)
4172 #define CAN_F6R1_FB19_Msk      (0x1U << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
4173 #define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
4174 #define CAN_F6R1_FB20_Pos      (20U)
4175 #define CAN_F6R1_FB20_Msk      (0x1U << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
4176 #define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
4177 #define CAN_F6R1_FB21_Pos      (21U)
4178 #define CAN_F6R1_FB21_Msk      (0x1U << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
4179 #define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
4180 #define CAN_F6R1_FB22_Pos      (22U)
4181 #define CAN_F6R1_FB22_Msk      (0x1U << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
4182 #define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
4183 #define CAN_F6R1_FB23_Pos      (23U)
4184 #define CAN_F6R1_FB23_Msk      (0x1U << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
4185 #define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
4186 #define CAN_F6R1_FB24_Pos      (24U)
4187 #define CAN_F6R1_FB24_Msk      (0x1U << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
4188 #define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
4189 #define CAN_F6R1_FB25_Pos      (25U)
4190 #define CAN_F6R1_FB25_Msk      (0x1U << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
4191 #define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
4192 #define CAN_F6R1_FB26_Pos      (26U)
4193 #define CAN_F6R1_FB26_Msk      (0x1U << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
4194 #define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
4195 #define CAN_F6R1_FB27_Pos      (27U)
4196 #define CAN_F6R1_FB27_Msk      (0x1U << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
4197 #define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
4198 #define CAN_F6R1_FB28_Pos      (28U)
4199 #define CAN_F6R1_FB28_Msk      (0x1U << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
4200 #define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
4201 #define CAN_F6R1_FB29_Pos      (29U)
4202 #define CAN_F6R1_FB29_Msk      (0x1U << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
4203 #define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
4204 #define CAN_F6R1_FB30_Pos      (30U)
4205 #define CAN_F6R1_FB30_Msk      (0x1U << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
4206 #define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
4207 #define CAN_F6R1_FB31_Pos      (31U)
4208 #define CAN_F6R1_FB31_Msk      (0x1U << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
4209 #define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
4210 
4211 /*******************  Bit definition for CAN_F7R1 register  *******************/
4212 #define CAN_F7R1_FB0_Pos       (0U)
4213 #define CAN_F7R1_FB0_Msk       (0x1U << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
4214 #define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
4215 #define CAN_F7R1_FB1_Pos       (1U)
4216 #define CAN_F7R1_FB1_Msk       (0x1U << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
4217 #define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
4218 #define CAN_F7R1_FB2_Pos       (2U)
4219 #define CAN_F7R1_FB2_Msk       (0x1U << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
4220 #define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
4221 #define CAN_F7R1_FB3_Pos       (3U)
4222 #define CAN_F7R1_FB3_Msk       (0x1U << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
4223 #define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
4224 #define CAN_F7R1_FB4_Pos       (4U)
4225 #define CAN_F7R1_FB4_Msk       (0x1U << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
4226 #define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
4227 #define CAN_F7R1_FB5_Pos       (5U)
4228 #define CAN_F7R1_FB5_Msk       (0x1U << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
4229 #define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
4230 #define CAN_F7R1_FB6_Pos       (6U)
4231 #define CAN_F7R1_FB6_Msk       (0x1U << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
4232 #define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
4233 #define CAN_F7R1_FB7_Pos       (7U)
4234 #define CAN_F7R1_FB7_Msk       (0x1U << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
4235 #define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
4236 #define CAN_F7R1_FB8_Pos       (8U)
4237 #define CAN_F7R1_FB8_Msk       (0x1U << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
4238 #define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
4239 #define CAN_F7R1_FB9_Pos       (9U)
4240 #define CAN_F7R1_FB9_Msk       (0x1U << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
4241 #define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
4242 #define CAN_F7R1_FB10_Pos      (10U)
4243 #define CAN_F7R1_FB10_Msk      (0x1U << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
4244 #define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
4245 #define CAN_F7R1_FB11_Pos      (11U)
4246 #define CAN_F7R1_FB11_Msk      (0x1U << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
4247 #define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
4248 #define CAN_F7R1_FB12_Pos      (12U)
4249 #define CAN_F7R1_FB12_Msk      (0x1U << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
4250 #define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
4251 #define CAN_F7R1_FB13_Pos      (13U)
4252 #define CAN_F7R1_FB13_Msk      (0x1U << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
4253 #define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
4254 #define CAN_F7R1_FB14_Pos      (14U)
4255 #define CAN_F7R1_FB14_Msk      (0x1U << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
4256 #define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
4257 #define CAN_F7R1_FB15_Pos      (15U)
4258 #define CAN_F7R1_FB15_Msk      (0x1U << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
4259 #define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
4260 #define CAN_F7R1_FB16_Pos      (16U)
4261 #define CAN_F7R1_FB16_Msk      (0x1U << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
4262 #define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
4263 #define CAN_F7R1_FB17_Pos      (17U)
4264 #define CAN_F7R1_FB17_Msk      (0x1U << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
4265 #define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
4266 #define CAN_F7R1_FB18_Pos      (18U)
4267 #define CAN_F7R1_FB18_Msk      (0x1U << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
4268 #define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
4269 #define CAN_F7R1_FB19_Pos      (19U)
4270 #define CAN_F7R1_FB19_Msk      (0x1U << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
4271 #define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
4272 #define CAN_F7R1_FB20_Pos      (20U)
4273 #define CAN_F7R1_FB20_Msk      (0x1U << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
4274 #define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
4275 #define CAN_F7R1_FB21_Pos      (21U)
4276 #define CAN_F7R1_FB21_Msk      (0x1U << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
4277 #define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
4278 #define CAN_F7R1_FB22_Pos      (22U)
4279 #define CAN_F7R1_FB22_Msk      (0x1U << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
4280 #define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
4281 #define CAN_F7R1_FB23_Pos      (23U)
4282 #define CAN_F7R1_FB23_Msk      (0x1U << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
4283 #define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
4284 #define CAN_F7R1_FB24_Pos      (24U)
4285 #define CAN_F7R1_FB24_Msk      (0x1U << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
4286 #define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
4287 #define CAN_F7R1_FB25_Pos      (25U)
4288 #define CAN_F7R1_FB25_Msk      (0x1U << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
4289 #define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
4290 #define CAN_F7R1_FB26_Pos      (26U)
4291 #define CAN_F7R1_FB26_Msk      (0x1U << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
4292 #define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
4293 #define CAN_F7R1_FB27_Pos      (27U)
4294 #define CAN_F7R1_FB27_Msk      (0x1U << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
4295 #define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
4296 #define CAN_F7R1_FB28_Pos      (28U)
4297 #define CAN_F7R1_FB28_Msk      (0x1U << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
4298 #define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
4299 #define CAN_F7R1_FB29_Pos      (29U)
4300 #define CAN_F7R1_FB29_Msk      (0x1U << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
4301 #define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
4302 #define CAN_F7R1_FB30_Pos      (30U)
4303 #define CAN_F7R1_FB30_Msk      (0x1U << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
4304 #define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
4305 #define CAN_F7R1_FB31_Pos      (31U)
4306 #define CAN_F7R1_FB31_Msk      (0x1U << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
4307 #define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
4308 
4309 /*******************  Bit definition for CAN_F8R1 register  *******************/
4310 #define CAN_F8R1_FB0_Pos       (0U)
4311 #define CAN_F8R1_FB0_Msk       (0x1U << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
4312 #define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
4313 #define CAN_F8R1_FB1_Pos       (1U)
4314 #define CAN_F8R1_FB1_Msk       (0x1U << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
4315 #define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
4316 #define CAN_F8R1_FB2_Pos       (2U)
4317 #define CAN_F8R1_FB2_Msk       (0x1U << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
4318 #define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
4319 #define CAN_F8R1_FB3_Pos       (3U)
4320 #define CAN_F8R1_FB3_Msk       (0x1U << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
4321 #define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
4322 #define CAN_F8R1_FB4_Pos       (4U)
4323 #define CAN_F8R1_FB4_Msk       (0x1U << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
4324 #define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
4325 #define CAN_F8R1_FB5_Pos       (5U)
4326 #define CAN_F8R1_FB5_Msk       (0x1U << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
4327 #define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
4328 #define CAN_F8R1_FB6_Pos       (6U)
4329 #define CAN_F8R1_FB6_Msk       (0x1U << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
4330 #define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
4331 #define CAN_F8R1_FB7_Pos       (7U)
4332 #define CAN_F8R1_FB7_Msk       (0x1U << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
4333 #define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
4334 #define CAN_F8R1_FB8_Pos       (8U)
4335 #define CAN_F8R1_FB8_Msk       (0x1U << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
4336 #define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
4337 #define CAN_F8R1_FB9_Pos       (9U)
4338 #define CAN_F8R1_FB9_Msk       (0x1U << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
4339 #define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
4340 #define CAN_F8R1_FB10_Pos      (10U)
4341 #define CAN_F8R1_FB10_Msk      (0x1U << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
4342 #define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
4343 #define CAN_F8R1_FB11_Pos      (11U)
4344 #define CAN_F8R1_FB11_Msk      (0x1U << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
4345 #define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
4346 #define CAN_F8R1_FB12_Pos      (12U)
4347 #define CAN_F8R1_FB12_Msk      (0x1U << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
4348 #define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
4349 #define CAN_F8R1_FB13_Pos      (13U)
4350 #define CAN_F8R1_FB13_Msk      (0x1U << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
4351 #define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
4352 #define CAN_F8R1_FB14_Pos      (14U)
4353 #define CAN_F8R1_FB14_Msk      (0x1U << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
4354 #define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
4355 #define CAN_F8R1_FB15_Pos      (15U)
4356 #define CAN_F8R1_FB15_Msk      (0x1U << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
4357 #define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
4358 #define CAN_F8R1_FB16_Pos      (16U)
4359 #define CAN_F8R1_FB16_Msk      (0x1U << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
4360 #define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
4361 #define CAN_F8R1_FB17_Pos      (17U)
4362 #define CAN_F8R1_FB17_Msk      (0x1U << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
4363 #define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
4364 #define CAN_F8R1_FB18_Pos      (18U)
4365 #define CAN_F8R1_FB18_Msk      (0x1U << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
4366 #define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
4367 #define CAN_F8R1_FB19_Pos      (19U)
4368 #define CAN_F8R1_FB19_Msk      (0x1U << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
4369 #define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
4370 #define CAN_F8R1_FB20_Pos      (20U)
4371 #define CAN_F8R1_FB20_Msk      (0x1U << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
4372 #define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
4373 #define CAN_F8R1_FB21_Pos      (21U)
4374 #define CAN_F8R1_FB21_Msk      (0x1U << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
4375 #define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
4376 #define CAN_F8R1_FB22_Pos      (22U)
4377 #define CAN_F8R1_FB22_Msk      (0x1U << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
4378 #define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
4379 #define CAN_F8R1_FB23_Pos      (23U)
4380 #define CAN_F8R1_FB23_Msk      (0x1U << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
4381 #define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
4382 #define CAN_F8R1_FB24_Pos      (24U)
4383 #define CAN_F8R1_FB24_Msk      (0x1U << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
4384 #define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
4385 #define CAN_F8R1_FB25_Pos      (25U)
4386 #define CAN_F8R1_FB25_Msk      (0x1U << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
4387 #define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
4388 #define CAN_F8R1_FB26_Pos      (26U)
4389 #define CAN_F8R1_FB26_Msk      (0x1U << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
4390 #define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
4391 #define CAN_F8R1_FB27_Pos      (27U)
4392 #define CAN_F8R1_FB27_Msk      (0x1U << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
4393 #define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
4394 #define CAN_F8R1_FB28_Pos      (28U)
4395 #define CAN_F8R1_FB28_Msk      (0x1U << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
4396 #define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
4397 #define CAN_F8R1_FB29_Pos      (29U)
4398 #define CAN_F8R1_FB29_Msk      (0x1U << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
4399 #define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
4400 #define CAN_F8R1_FB30_Pos      (30U)
4401 #define CAN_F8R1_FB30_Msk      (0x1U << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
4402 #define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
4403 #define CAN_F8R1_FB31_Pos      (31U)
4404 #define CAN_F8R1_FB31_Msk      (0x1U << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
4405 #define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
4406 
4407 /*******************  Bit definition for CAN_F9R1 register  *******************/
4408 #define CAN_F9R1_FB0_Pos       (0U)
4409 #define CAN_F9R1_FB0_Msk       (0x1U << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
4410 #define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
4411 #define CAN_F9R1_FB1_Pos       (1U)
4412 #define CAN_F9R1_FB1_Msk       (0x1U << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
4413 #define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
4414 #define CAN_F9R1_FB2_Pos       (2U)
4415 #define CAN_F9R1_FB2_Msk       (0x1U << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
4416 #define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
4417 #define CAN_F9R1_FB3_Pos       (3U)
4418 #define CAN_F9R1_FB3_Msk       (0x1U << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
4419 #define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
4420 #define CAN_F9R1_FB4_Pos       (4U)
4421 #define CAN_F9R1_FB4_Msk       (0x1U << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
4422 #define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
4423 #define CAN_F9R1_FB5_Pos       (5U)
4424 #define CAN_F9R1_FB5_Msk       (0x1U << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
4425 #define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
4426 #define CAN_F9R1_FB6_Pos       (6U)
4427 #define CAN_F9R1_FB6_Msk       (0x1U << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
4428 #define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
4429 #define CAN_F9R1_FB7_Pos       (7U)
4430 #define CAN_F9R1_FB7_Msk       (0x1U << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
4431 #define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
4432 #define CAN_F9R1_FB8_Pos       (8U)
4433 #define CAN_F9R1_FB8_Msk       (0x1U << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
4434 #define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
4435 #define CAN_F9R1_FB9_Pos       (9U)
4436 #define CAN_F9R1_FB9_Msk       (0x1U << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
4437 #define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
4438 #define CAN_F9R1_FB10_Pos      (10U)
4439 #define CAN_F9R1_FB10_Msk      (0x1U << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
4440 #define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
4441 #define CAN_F9R1_FB11_Pos      (11U)
4442 #define CAN_F9R1_FB11_Msk      (0x1U << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
4443 #define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
4444 #define CAN_F9R1_FB12_Pos      (12U)
4445 #define CAN_F9R1_FB12_Msk      (0x1U << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
4446 #define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
4447 #define CAN_F9R1_FB13_Pos      (13U)
4448 #define CAN_F9R1_FB13_Msk      (0x1U << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
4449 #define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
4450 #define CAN_F9R1_FB14_Pos      (14U)
4451 #define CAN_F9R1_FB14_Msk      (0x1U << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
4452 #define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
4453 #define CAN_F9R1_FB15_Pos      (15U)
4454 #define CAN_F9R1_FB15_Msk      (0x1U << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
4455 #define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
4456 #define CAN_F9R1_FB16_Pos      (16U)
4457 #define CAN_F9R1_FB16_Msk      (0x1U << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
4458 #define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
4459 #define CAN_F9R1_FB17_Pos      (17U)
4460 #define CAN_F9R1_FB17_Msk      (0x1U << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
4461 #define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
4462 #define CAN_F9R1_FB18_Pos      (18U)
4463 #define CAN_F9R1_FB18_Msk      (0x1U << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
4464 #define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
4465 #define CAN_F9R1_FB19_Pos      (19U)
4466 #define CAN_F9R1_FB19_Msk      (0x1U << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
4467 #define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
4468 #define CAN_F9R1_FB20_Pos      (20U)
4469 #define CAN_F9R1_FB20_Msk      (0x1U << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
4470 #define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
4471 #define CAN_F9R1_FB21_Pos      (21U)
4472 #define CAN_F9R1_FB21_Msk      (0x1U << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
4473 #define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
4474 #define CAN_F9R1_FB22_Pos      (22U)
4475 #define CAN_F9R1_FB22_Msk      (0x1U << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
4476 #define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
4477 #define CAN_F9R1_FB23_Pos      (23U)
4478 #define CAN_F9R1_FB23_Msk      (0x1U << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
4479 #define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
4480 #define CAN_F9R1_FB24_Pos      (24U)
4481 #define CAN_F9R1_FB24_Msk      (0x1U << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
4482 #define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
4483 #define CAN_F9R1_FB25_Pos      (25U)
4484 #define CAN_F9R1_FB25_Msk      (0x1U << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
4485 #define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
4486 #define CAN_F9R1_FB26_Pos      (26U)
4487 #define CAN_F9R1_FB26_Msk      (0x1U << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
4488 #define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
4489 #define CAN_F9R1_FB27_Pos      (27U)
4490 #define CAN_F9R1_FB27_Msk      (0x1U << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
4491 #define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
4492 #define CAN_F9R1_FB28_Pos      (28U)
4493 #define CAN_F9R1_FB28_Msk      (0x1U << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
4494 #define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
4495 #define CAN_F9R1_FB29_Pos      (29U)
4496 #define CAN_F9R1_FB29_Msk      (0x1U << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
4497 #define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
4498 #define CAN_F9R1_FB30_Pos      (30U)
4499 #define CAN_F9R1_FB30_Msk      (0x1U << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
4500 #define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
4501 #define CAN_F9R1_FB31_Pos      (31U)
4502 #define CAN_F9R1_FB31_Msk      (0x1U << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
4503 #define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
4504 
4505 /*******************  Bit definition for CAN_F10R1 register  ******************/
4506 #define CAN_F10R1_FB0_Pos      (0U)
4507 #define CAN_F10R1_FB0_Msk      (0x1U << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
4508 #define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
4509 #define CAN_F10R1_FB1_Pos      (1U)
4510 #define CAN_F10R1_FB1_Msk      (0x1U << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
4511 #define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
4512 #define CAN_F10R1_FB2_Pos      (2U)
4513 #define CAN_F10R1_FB2_Msk      (0x1U << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
4514 #define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
4515 #define CAN_F10R1_FB3_Pos      (3U)
4516 #define CAN_F10R1_FB3_Msk      (0x1U << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
4517 #define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
4518 #define CAN_F10R1_FB4_Pos      (4U)
4519 #define CAN_F10R1_FB4_Msk      (0x1U << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
4520 #define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
4521 #define CAN_F10R1_FB5_Pos      (5U)
4522 #define CAN_F10R1_FB5_Msk      (0x1U << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
4523 #define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
4524 #define CAN_F10R1_FB6_Pos      (6U)
4525 #define CAN_F10R1_FB6_Msk      (0x1U << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
4526 #define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
4527 #define CAN_F10R1_FB7_Pos      (7U)
4528 #define CAN_F10R1_FB7_Msk      (0x1U << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
4529 #define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
4530 #define CAN_F10R1_FB8_Pos      (8U)
4531 #define CAN_F10R1_FB8_Msk      (0x1U << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
4532 #define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
4533 #define CAN_F10R1_FB9_Pos      (9U)
4534 #define CAN_F10R1_FB9_Msk      (0x1U << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
4535 #define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
4536 #define CAN_F10R1_FB10_Pos     (10U)
4537 #define CAN_F10R1_FB10_Msk     (0x1U << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
4538 #define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
4539 #define CAN_F10R1_FB11_Pos     (11U)
4540 #define CAN_F10R1_FB11_Msk     (0x1U << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
4541 #define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
4542 #define CAN_F10R1_FB12_Pos     (12U)
4543 #define CAN_F10R1_FB12_Msk     (0x1U << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
4544 #define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
4545 #define CAN_F10R1_FB13_Pos     (13U)
4546 #define CAN_F10R1_FB13_Msk     (0x1U << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
4547 #define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
4548 #define CAN_F10R1_FB14_Pos     (14U)
4549 #define CAN_F10R1_FB14_Msk     (0x1U << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
4550 #define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
4551 #define CAN_F10R1_FB15_Pos     (15U)
4552 #define CAN_F10R1_FB15_Msk     (0x1U << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
4553 #define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
4554 #define CAN_F10R1_FB16_Pos     (16U)
4555 #define CAN_F10R1_FB16_Msk     (0x1U << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
4556 #define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
4557 #define CAN_F10R1_FB17_Pos     (17U)
4558 #define CAN_F10R1_FB17_Msk     (0x1U << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
4559 #define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
4560 #define CAN_F10R1_FB18_Pos     (18U)
4561 #define CAN_F10R1_FB18_Msk     (0x1U << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
4562 #define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
4563 #define CAN_F10R1_FB19_Pos     (19U)
4564 #define CAN_F10R1_FB19_Msk     (0x1U << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
4565 #define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
4566 #define CAN_F10R1_FB20_Pos     (20U)
4567 #define CAN_F10R1_FB20_Msk     (0x1U << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
4568 #define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
4569 #define CAN_F10R1_FB21_Pos     (21U)
4570 #define CAN_F10R1_FB21_Msk     (0x1U << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
4571 #define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
4572 #define CAN_F10R1_FB22_Pos     (22U)
4573 #define CAN_F10R1_FB22_Msk     (0x1U << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
4574 #define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
4575 #define CAN_F10R1_FB23_Pos     (23U)
4576 #define CAN_F10R1_FB23_Msk     (0x1U << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
4577 #define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
4578 #define CAN_F10R1_FB24_Pos     (24U)
4579 #define CAN_F10R1_FB24_Msk     (0x1U << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
4580 #define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
4581 #define CAN_F10R1_FB25_Pos     (25U)
4582 #define CAN_F10R1_FB25_Msk     (0x1U << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
4583 #define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
4584 #define CAN_F10R1_FB26_Pos     (26U)
4585 #define CAN_F10R1_FB26_Msk     (0x1U << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
4586 #define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
4587 #define CAN_F10R1_FB27_Pos     (27U)
4588 #define CAN_F10R1_FB27_Msk     (0x1U << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
4589 #define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
4590 #define CAN_F10R1_FB28_Pos     (28U)
4591 #define CAN_F10R1_FB28_Msk     (0x1U << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
4592 #define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
4593 #define CAN_F10R1_FB29_Pos     (29U)
4594 #define CAN_F10R1_FB29_Msk     (0x1U << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
4595 #define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
4596 #define CAN_F10R1_FB30_Pos     (30U)
4597 #define CAN_F10R1_FB30_Msk     (0x1U << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
4598 #define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
4599 #define CAN_F10R1_FB31_Pos     (31U)
4600 #define CAN_F10R1_FB31_Msk     (0x1U << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
4601 #define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
4602 
4603 /*******************  Bit definition for CAN_F11R1 register  ******************/
4604 #define CAN_F11R1_FB0_Pos      (0U)
4605 #define CAN_F11R1_FB0_Msk      (0x1U << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
4606 #define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
4607 #define CAN_F11R1_FB1_Pos      (1U)
4608 #define CAN_F11R1_FB1_Msk      (0x1U << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
4609 #define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
4610 #define CAN_F11R1_FB2_Pos      (2U)
4611 #define CAN_F11R1_FB2_Msk      (0x1U << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
4612 #define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
4613 #define CAN_F11R1_FB3_Pos      (3U)
4614 #define CAN_F11R1_FB3_Msk      (0x1U << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
4615 #define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
4616 #define CAN_F11R1_FB4_Pos      (4U)
4617 #define CAN_F11R1_FB4_Msk      (0x1U << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
4618 #define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
4619 #define CAN_F11R1_FB5_Pos      (5U)
4620 #define CAN_F11R1_FB5_Msk      (0x1U << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
4621 #define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
4622 #define CAN_F11R1_FB6_Pos      (6U)
4623 #define CAN_F11R1_FB6_Msk      (0x1U << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
4624 #define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
4625 #define CAN_F11R1_FB7_Pos      (7U)
4626 #define CAN_F11R1_FB7_Msk      (0x1U << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
4627 #define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
4628 #define CAN_F11R1_FB8_Pos      (8U)
4629 #define CAN_F11R1_FB8_Msk      (0x1U << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
4630 #define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
4631 #define CAN_F11R1_FB9_Pos      (9U)
4632 #define CAN_F11R1_FB9_Msk      (0x1U << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
4633 #define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
4634 #define CAN_F11R1_FB10_Pos     (10U)
4635 #define CAN_F11R1_FB10_Msk     (0x1U << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
4636 #define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
4637 #define CAN_F11R1_FB11_Pos     (11U)
4638 #define CAN_F11R1_FB11_Msk     (0x1U << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
4639 #define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
4640 #define CAN_F11R1_FB12_Pos     (12U)
4641 #define CAN_F11R1_FB12_Msk     (0x1U << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
4642 #define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
4643 #define CAN_F11R1_FB13_Pos     (13U)
4644 #define CAN_F11R1_FB13_Msk     (0x1U << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
4645 #define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
4646 #define CAN_F11R1_FB14_Pos     (14U)
4647 #define CAN_F11R1_FB14_Msk     (0x1U << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
4648 #define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
4649 #define CAN_F11R1_FB15_Pos     (15U)
4650 #define CAN_F11R1_FB15_Msk     (0x1U << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
4651 #define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
4652 #define CAN_F11R1_FB16_Pos     (16U)
4653 #define CAN_F11R1_FB16_Msk     (0x1U << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
4654 #define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
4655 #define CAN_F11R1_FB17_Pos     (17U)
4656 #define CAN_F11R1_FB17_Msk     (0x1U << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
4657 #define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
4658 #define CAN_F11R1_FB18_Pos     (18U)
4659 #define CAN_F11R1_FB18_Msk     (0x1U << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
4660 #define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
4661 #define CAN_F11R1_FB19_Pos     (19U)
4662 #define CAN_F11R1_FB19_Msk     (0x1U << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
4663 #define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
4664 #define CAN_F11R1_FB20_Pos     (20U)
4665 #define CAN_F11R1_FB20_Msk     (0x1U << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
4666 #define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
4667 #define CAN_F11R1_FB21_Pos     (21U)
4668 #define CAN_F11R1_FB21_Msk     (0x1U << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
4669 #define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
4670 #define CAN_F11R1_FB22_Pos     (22U)
4671 #define CAN_F11R1_FB22_Msk     (0x1U << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
4672 #define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
4673 #define CAN_F11R1_FB23_Pos     (23U)
4674 #define CAN_F11R1_FB23_Msk     (0x1U << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
4675 #define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
4676 #define CAN_F11R1_FB24_Pos     (24U)
4677 #define CAN_F11R1_FB24_Msk     (0x1U << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
4678 #define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
4679 #define CAN_F11R1_FB25_Pos     (25U)
4680 #define CAN_F11R1_FB25_Msk     (0x1U << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
4681 #define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
4682 #define CAN_F11R1_FB26_Pos     (26U)
4683 #define CAN_F11R1_FB26_Msk     (0x1U << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
4684 #define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
4685 #define CAN_F11R1_FB27_Pos     (27U)
4686 #define CAN_F11R1_FB27_Msk     (0x1U << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
4687 #define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
4688 #define CAN_F11R1_FB28_Pos     (28U)
4689 #define CAN_F11R1_FB28_Msk     (0x1U << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
4690 #define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
4691 #define CAN_F11R1_FB29_Pos     (29U)
4692 #define CAN_F11R1_FB29_Msk     (0x1U << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
4693 #define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
4694 #define CAN_F11R1_FB30_Pos     (30U)
4695 #define CAN_F11R1_FB30_Msk     (0x1U << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
4696 #define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
4697 #define CAN_F11R1_FB31_Pos     (31U)
4698 #define CAN_F11R1_FB31_Msk     (0x1U << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
4699 #define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
4700 
4701 /*******************  Bit definition for CAN_F12R1 register  ******************/
4702 #define CAN_F12R1_FB0_Pos      (0U)
4703 #define CAN_F12R1_FB0_Msk      (0x1U << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
4704 #define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
4705 #define CAN_F12R1_FB1_Pos      (1U)
4706 #define CAN_F12R1_FB1_Msk      (0x1U << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
4707 #define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
4708 #define CAN_F12R1_FB2_Pos      (2U)
4709 #define CAN_F12R1_FB2_Msk      (0x1U << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
4710 #define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
4711 #define CAN_F12R1_FB3_Pos      (3U)
4712 #define CAN_F12R1_FB3_Msk      (0x1U << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
4713 #define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
4714 #define CAN_F12R1_FB4_Pos      (4U)
4715 #define CAN_F12R1_FB4_Msk      (0x1U << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
4716 #define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
4717 #define CAN_F12R1_FB5_Pos      (5U)
4718 #define CAN_F12R1_FB5_Msk      (0x1U << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
4719 #define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
4720 #define CAN_F12R1_FB6_Pos      (6U)
4721 #define CAN_F12R1_FB6_Msk      (0x1U << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
4722 #define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
4723 #define CAN_F12R1_FB7_Pos      (7U)
4724 #define CAN_F12R1_FB7_Msk      (0x1U << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
4725 #define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
4726 #define CAN_F12R1_FB8_Pos      (8U)
4727 #define CAN_F12R1_FB8_Msk      (0x1U << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
4728 #define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
4729 #define CAN_F12R1_FB9_Pos      (9U)
4730 #define CAN_F12R1_FB9_Msk      (0x1U << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
4731 #define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
4732 #define CAN_F12R1_FB10_Pos     (10U)
4733 #define CAN_F12R1_FB10_Msk     (0x1U << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
4734 #define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
4735 #define CAN_F12R1_FB11_Pos     (11U)
4736 #define CAN_F12R1_FB11_Msk     (0x1U << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
4737 #define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
4738 #define CAN_F12R1_FB12_Pos     (12U)
4739 #define CAN_F12R1_FB12_Msk     (0x1U << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
4740 #define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
4741 #define CAN_F12R1_FB13_Pos     (13U)
4742 #define CAN_F12R1_FB13_Msk     (0x1U << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
4743 #define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
4744 #define CAN_F12R1_FB14_Pos     (14U)
4745 #define CAN_F12R1_FB14_Msk     (0x1U << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
4746 #define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
4747 #define CAN_F12R1_FB15_Pos     (15U)
4748 #define CAN_F12R1_FB15_Msk     (0x1U << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
4749 #define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
4750 #define CAN_F12R1_FB16_Pos     (16U)
4751 #define CAN_F12R1_FB16_Msk     (0x1U << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
4752 #define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
4753 #define CAN_F12R1_FB17_Pos     (17U)
4754 #define CAN_F12R1_FB17_Msk     (0x1U << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
4755 #define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
4756 #define CAN_F12R1_FB18_Pos     (18U)
4757 #define CAN_F12R1_FB18_Msk     (0x1U << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
4758 #define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
4759 #define CAN_F12R1_FB19_Pos     (19U)
4760 #define CAN_F12R1_FB19_Msk     (0x1U << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
4761 #define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
4762 #define CAN_F12R1_FB20_Pos     (20U)
4763 #define CAN_F12R1_FB20_Msk     (0x1U << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
4764 #define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
4765 #define CAN_F12R1_FB21_Pos     (21U)
4766 #define CAN_F12R1_FB21_Msk     (0x1U << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
4767 #define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
4768 #define CAN_F12R1_FB22_Pos     (22U)
4769 #define CAN_F12R1_FB22_Msk     (0x1U << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
4770 #define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
4771 #define CAN_F12R1_FB23_Pos     (23U)
4772 #define CAN_F12R1_FB23_Msk     (0x1U << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
4773 #define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
4774 #define CAN_F12R1_FB24_Pos     (24U)
4775 #define CAN_F12R1_FB24_Msk     (0x1U << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
4776 #define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
4777 #define CAN_F12R1_FB25_Pos     (25U)
4778 #define CAN_F12R1_FB25_Msk     (0x1U << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
4779 #define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
4780 #define CAN_F12R1_FB26_Pos     (26U)
4781 #define CAN_F12R1_FB26_Msk     (0x1U << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
4782 #define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
4783 #define CAN_F12R1_FB27_Pos     (27U)
4784 #define CAN_F12R1_FB27_Msk     (0x1U << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
4785 #define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
4786 #define CAN_F12R1_FB28_Pos     (28U)
4787 #define CAN_F12R1_FB28_Msk     (0x1U << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
4788 #define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
4789 #define CAN_F12R1_FB29_Pos     (29U)
4790 #define CAN_F12R1_FB29_Msk     (0x1U << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
4791 #define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
4792 #define CAN_F12R1_FB30_Pos     (30U)
4793 #define CAN_F12R1_FB30_Msk     (0x1U << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
4794 #define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
4795 #define CAN_F12R1_FB31_Pos     (31U)
4796 #define CAN_F12R1_FB31_Msk     (0x1U << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
4797 #define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
4798 
4799 /*******************  Bit definition for CAN_F13R1 register  ******************/
4800 #define CAN_F13R1_FB0_Pos      (0U)
4801 #define CAN_F13R1_FB0_Msk      (0x1U << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
4802 #define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
4803 #define CAN_F13R1_FB1_Pos      (1U)
4804 #define CAN_F13R1_FB1_Msk      (0x1U << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
4805 #define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
4806 #define CAN_F13R1_FB2_Pos      (2U)
4807 #define CAN_F13R1_FB2_Msk      (0x1U << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
4808 #define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
4809 #define CAN_F13R1_FB3_Pos      (3U)
4810 #define CAN_F13R1_FB3_Msk      (0x1U << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
4811 #define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
4812 #define CAN_F13R1_FB4_Pos      (4U)
4813 #define CAN_F13R1_FB4_Msk      (0x1U << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
4814 #define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
4815 #define CAN_F13R1_FB5_Pos      (5U)
4816 #define CAN_F13R1_FB5_Msk      (0x1U << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
4817 #define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
4818 #define CAN_F13R1_FB6_Pos      (6U)
4819 #define CAN_F13R1_FB6_Msk      (0x1U << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
4820 #define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
4821 #define CAN_F13R1_FB7_Pos      (7U)
4822 #define CAN_F13R1_FB7_Msk      (0x1U << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
4823 #define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
4824 #define CAN_F13R1_FB8_Pos      (8U)
4825 #define CAN_F13R1_FB8_Msk      (0x1U << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
4826 #define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
4827 #define CAN_F13R1_FB9_Pos      (9U)
4828 #define CAN_F13R1_FB9_Msk      (0x1U << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
4829 #define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
4830 #define CAN_F13R1_FB10_Pos     (10U)
4831 #define CAN_F13R1_FB10_Msk     (0x1U << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
4832 #define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
4833 #define CAN_F13R1_FB11_Pos     (11U)
4834 #define CAN_F13R1_FB11_Msk     (0x1U << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
4835 #define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
4836 #define CAN_F13R1_FB12_Pos     (12U)
4837 #define CAN_F13R1_FB12_Msk     (0x1U << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
4838 #define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
4839 #define CAN_F13R1_FB13_Pos     (13U)
4840 #define CAN_F13R1_FB13_Msk     (0x1U << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
4841 #define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
4842 #define CAN_F13R1_FB14_Pos     (14U)
4843 #define CAN_F13R1_FB14_Msk     (0x1U << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
4844 #define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
4845 #define CAN_F13R1_FB15_Pos     (15U)
4846 #define CAN_F13R1_FB15_Msk     (0x1U << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
4847 #define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
4848 #define CAN_F13R1_FB16_Pos     (16U)
4849 #define CAN_F13R1_FB16_Msk     (0x1U << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
4850 #define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
4851 #define CAN_F13R1_FB17_Pos     (17U)
4852 #define CAN_F13R1_FB17_Msk     (0x1U << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
4853 #define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
4854 #define CAN_F13R1_FB18_Pos     (18U)
4855 #define CAN_F13R1_FB18_Msk     (0x1U << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
4856 #define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
4857 #define CAN_F13R1_FB19_Pos     (19U)
4858 #define CAN_F13R1_FB19_Msk     (0x1U << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
4859 #define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
4860 #define CAN_F13R1_FB20_Pos     (20U)
4861 #define CAN_F13R1_FB20_Msk     (0x1U << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
4862 #define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
4863 #define CAN_F13R1_FB21_Pos     (21U)
4864 #define CAN_F13R1_FB21_Msk     (0x1U << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
4865 #define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
4866 #define CAN_F13R1_FB22_Pos     (22U)
4867 #define CAN_F13R1_FB22_Msk     (0x1U << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
4868 #define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
4869 #define CAN_F13R1_FB23_Pos     (23U)
4870 #define CAN_F13R1_FB23_Msk     (0x1U << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
4871 #define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
4872 #define CAN_F13R1_FB24_Pos     (24U)
4873 #define CAN_F13R1_FB24_Msk     (0x1U << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
4874 #define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
4875 #define CAN_F13R1_FB25_Pos     (25U)
4876 #define CAN_F13R1_FB25_Msk     (0x1U << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
4877 #define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
4878 #define CAN_F13R1_FB26_Pos     (26U)
4879 #define CAN_F13R1_FB26_Msk     (0x1U << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
4880 #define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
4881 #define CAN_F13R1_FB27_Pos     (27U)
4882 #define CAN_F13R1_FB27_Msk     (0x1U << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
4883 #define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
4884 #define CAN_F13R1_FB28_Pos     (28U)
4885 #define CAN_F13R1_FB28_Msk     (0x1U << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
4886 #define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
4887 #define CAN_F13R1_FB29_Pos     (29U)
4888 #define CAN_F13R1_FB29_Msk     (0x1U << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
4889 #define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
4890 #define CAN_F13R1_FB30_Pos     (30U)
4891 #define CAN_F13R1_FB30_Msk     (0x1U << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
4892 #define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
4893 #define CAN_F13R1_FB31_Pos     (31U)
4894 #define CAN_F13R1_FB31_Msk     (0x1U << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
4895 #define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
4896 
4897 /*******************  Bit definition for CAN_F0R2 register  *******************/
4898 #define CAN_F0R2_FB0_Pos       (0U)
4899 #define CAN_F0R2_FB0_Msk       (0x1U << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
4900 #define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
4901 #define CAN_F0R2_FB1_Pos       (1U)
4902 #define CAN_F0R2_FB1_Msk       (0x1U << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
4903 #define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
4904 #define CAN_F0R2_FB2_Pos       (2U)
4905 #define CAN_F0R2_FB2_Msk       (0x1U << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
4906 #define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
4907 #define CAN_F0R2_FB3_Pos       (3U)
4908 #define CAN_F0R2_FB3_Msk       (0x1U << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
4909 #define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
4910 #define CAN_F0R2_FB4_Pos       (4U)
4911 #define CAN_F0R2_FB4_Msk       (0x1U << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
4912 #define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
4913 #define CAN_F0R2_FB5_Pos       (5U)
4914 #define CAN_F0R2_FB5_Msk       (0x1U << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
4915 #define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
4916 #define CAN_F0R2_FB6_Pos       (6U)
4917 #define CAN_F0R2_FB6_Msk       (0x1U << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
4918 #define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
4919 #define CAN_F0R2_FB7_Pos       (7U)
4920 #define CAN_F0R2_FB7_Msk       (0x1U << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
4921 #define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
4922 #define CAN_F0R2_FB8_Pos       (8U)
4923 #define CAN_F0R2_FB8_Msk       (0x1U << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
4924 #define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
4925 #define CAN_F0R2_FB9_Pos       (9U)
4926 #define CAN_F0R2_FB9_Msk       (0x1U << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
4927 #define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
4928 #define CAN_F0R2_FB10_Pos      (10U)
4929 #define CAN_F0R2_FB10_Msk      (0x1U << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
4930 #define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
4931 #define CAN_F0R2_FB11_Pos      (11U)
4932 #define CAN_F0R2_FB11_Msk      (0x1U << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
4933 #define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
4934 #define CAN_F0R2_FB12_Pos      (12U)
4935 #define CAN_F0R2_FB12_Msk      (0x1U << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
4936 #define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
4937 #define CAN_F0R2_FB13_Pos      (13U)
4938 #define CAN_F0R2_FB13_Msk      (0x1U << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
4939 #define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
4940 #define CAN_F0R2_FB14_Pos      (14U)
4941 #define CAN_F0R2_FB14_Msk      (0x1U << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
4942 #define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
4943 #define CAN_F0R2_FB15_Pos      (15U)
4944 #define CAN_F0R2_FB15_Msk      (0x1U << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
4945 #define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
4946 #define CAN_F0R2_FB16_Pos      (16U)
4947 #define CAN_F0R2_FB16_Msk      (0x1U << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
4948 #define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
4949 #define CAN_F0R2_FB17_Pos      (17U)
4950 #define CAN_F0R2_FB17_Msk      (0x1U << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
4951 #define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
4952 #define CAN_F0R2_FB18_Pos      (18U)
4953 #define CAN_F0R2_FB18_Msk      (0x1U << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
4954 #define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
4955 #define CAN_F0R2_FB19_Pos      (19U)
4956 #define CAN_F0R2_FB19_Msk      (0x1U << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
4957 #define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
4958 #define CAN_F0R2_FB20_Pos      (20U)
4959 #define CAN_F0R2_FB20_Msk      (0x1U << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
4960 #define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
4961 #define CAN_F0R2_FB21_Pos      (21U)
4962 #define CAN_F0R2_FB21_Msk      (0x1U << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
4963 #define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
4964 #define CAN_F0R2_FB22_Pos      (22U)
4965 #define CAN_F0R2_FB22_Msk      (0x1U << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
4966 #define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
4967 #define CAN_F0R2_FB23_Pos      (23U)
4968 #define CAN_F0R2_FB23_Msk      (0x1U << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
4969 #define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
4970 #define CAN_F0R2_FB24_Pos      (24U)
4971 #define CAN_F0R2_FB24_Msk      (0x1U << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
4972 #define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
4973 #define CAN_F0R2_FB25_Pos      (25U)
4974 #define CAN_F0R2_FB25_Msk      (0x1U << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
4975 #define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
4976 #define CAN_F0R2_FB26_Pos      (26U)
4977 #define CAN_F0R2_FB26_Msk      (0x1U << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
4978 #define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
4979 #define CAN_F0R2_FB27_Pos      (27U)
4980 #define CAN_F0R2_FB27_Msk      (0x1U << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
4981 #define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
4982 #define CAN_F0R2_FB28_Pos      (28U)
4983 #define CAN_F0R2_FB28_Msk      (0x1U << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
4984 #define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
4985 #define CAN_F0R2_FB29_Pos      (29U)
4986 #define CAN_F0R2_FB29_Msk      (0x1U << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
4987 #define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
4988 #define CAN_F0R2_FB30_Pos      (30U)
4989 #define CAN_F0R2_FB30_Msk      (0x1U << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
4990 #define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
4991 #define CAN_F0R2_FB31_Pos      (31U)
4992 #define CAN_F0R2_FB31_Msk      (0x1U << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
4993 #define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
4994 
4995 /*******************  Bit definition for CAN_F1R2 register  *******************/
4996 #define CAN_F1R2_FB0_Pos       (0U)
4997 #define CAN_F1R2_FB0_Msk       (0x1U << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
4998 #define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
4999 #define CAN_F1R2_FB1_Pos       (1U)
5000 #define CAN_F1R2_FB1_Msk       (0x1U << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
5001 #define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
5002 #define CAN_F1R2_FB2_Pos       (2U)
5003 #define CAN_F1R2_FB2_Msk       (0x1U << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
5004 #define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
5005 #define CAN_F1R2_FB3_Pos       (3U)
5006 #define CAN_F1R2_FB3_Msk       (0x1U << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
5007 #define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
5008 #define CAN_F1R2_FB4_Pos       (4U)
5009 #define CAN_F1R2_FB4_Msk       (0x1U << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
5010 #define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
5011 #define CAN_F1R2_FB5_Pos       (5U)
5012 #define CAN_F1R2_FB5_Msk       (0x1U << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
5013 #define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
5014 #define CAN_F1R2_FB6_Pos       (6U)
5015 #define CAN_F1R2_FB6_Msk       (0x1U << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
5016 #define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
5017 #define CAN_F1R2_FB7_Pos       (7U)
5018 #define CAN_F1R2_FB7_Msk       (0x1U << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
5019 #define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
5020 #define CAN_F1R2_FB8_Pos       (8U)
5021 #define CAN_F1R2_FB8_Msk       (0x1U << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
5022 #define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
5023 #define CAN_F1R2_FB9_Pos       (9U)
5024 #define CAN_F1R2_FB9_Msk       (0x1U << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
5025 #define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
5026 #define CAN_F1R2_FB10_Pos      (10U)
5027 #define CAN_F1R2_FB10_Msk      (0x1U << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
5028 #define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
5029 #define CAN_F1R2_FB11_Pos      (11U)
5030 #define CAN_F1R2_FB11_Msk      (0x1U << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
5031 #define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
5032 #define CAN_F1R2_FB12_Pos      (12U)
5033 #define CAN_F1R2_FB12_Msk      (0x1U << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
5034 #define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
5035 #define CAN_F1R2_FB13_Pos      (13U)
5036 #define CAN_F1R2_FB13_Msk      (0x1U << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
5037 #define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
5038 #define CAN_F1R2_FB14_Pos      (14U)
5039 #define CAN_F1R2_FB14_Msk      (0x1U << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
5040 #define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
5041 #define CAN_F1R2_FB15_Pos      (15U)
5042 #define CAN_F1R2_FB15_Msk      (0x1U << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
5043 #define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
5044 #define CAN_F1R2_FB16_Pos      (16U)
5045 #define CAN_F1R2_FB16_Msk      (0x1U << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
5046 #define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
5047 #define CAN_F1R2_FB17_Pos      (17U)
5048 #define CAN_F1R2_FB17_Msk      (0x1U << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
5049 #define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
5050 #define CAN_F1R2_FB18_Pos      (18U)
5051 #define CAN_F1R2_FB18_Msk      (0x1U << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
5052 #define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
5053 #define CAN_F1R2_FB19_Pos      (19U)
5054 #define CAN_F1R2_FB19_Msk      (0x1U << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
5055 #define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
5056 #define CAN_F1R2_FB20_Pos      (20U)
5057 #define CAN_F1R2_FB20_Msk      (0x1U << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
5058 #define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
5059 #define CAN_F1R2_FB21_Pos      (21U)
5060 #define CAN_F1R2_FB21_Msk      (0x1U << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
5061 #define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
5062 #define CAN_F1R2_FB22_Pos      (22U)
5063 #define CAN_F1R2_FB22_Msk      (0x1U << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
5064 #define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
5065 #define CAN_F1R2_FB23_Pos      (23U)
5066 #define CAN_F1R2_FB23_Msk      (0x1U << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
5067 #define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
5068 #define CAN_F1R2_FB24_Pos      (24U)
5069 #define CAN_F1R2_FB24_Msk      (0x1U << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
5070 #define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
5071 #define CAN_F1R2_FB25_Pos      (25U)
5072 #define CAN_F1R2_FB25_Msk      (0x1U << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
5073 #define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
5074 #define CAN_F1R2_FB26_Pos      (26U)
5075 #define CAN_F1R2_FB26_Msk      (0x1U << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
5076 #define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
5077 #define CAN_F1R2_FB27_Pos      (27U)
5078 #define CAN_F1R2_FB27_Msk      (0x1U << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
5079 #define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
5080 #define CAN_F1R2_FB28_Pos      (28U)
5081 #define CAN_F1R2_FB28_Msk      (0x1U << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
5082 #define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
5083 #define CAN_F1R2_FB29_Pos      (29U)
5084 #define CAN_F1R2_FB29_Msk      (0x1U << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
5085 #define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
5086 #define CAN_F1R2_FB30_Pos      (30U)
5087 #define CAN_F1R2_FB30_Msk      (0x1U << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
5088 #define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
5089 #define CAN_F1R2_FB31_Pos      (31U)
5090 #define CAN_F1R2_FB31_Msk      (0x1U << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
5091 #define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
5092 
5093 /*******************  Bit definition for CAN_F2R2 register  *******************/
5094 #define CAN_F2R2_FB0_Pos       (0U)
5095 #define CAN_F2R2_FB0_Msk       (0x1U << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
5096 #define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
5097 #define CAN_F2R2_FB1_Pos       (1U)
5098 #define CAN_F2R2_FB1_Msk       (0x1U << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
5099 #define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
5100 #define CAN_F2R2_FB2_Pos       (2U)
5101 #define CAN_F2R2_FB2_Msk       (0x1U << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
5102 #define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
5103 #define CAN_F2R2_FB3_Pos       (3U)
5104 #define CAN_F2R2_FB3_Msk       (0x1U << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
5105 #define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
5106 #define CAN_F2R2_FB4_Pos       (4U)
5107 #define CAN_F2R2_FB4_Msk       (0x1U << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
5108 #define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
5109 #define CAN_F2R2_FB5_Pos       (5U)
5110 #define CAN_F2R2_FB5_Msk       (0x1U << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
5111 #define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
5112 #define CAN_F2R2_FB6_Pos       (6U)
5113 #define CAN_F2R2_FB6_Msk       (0x1U << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
5114 #define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
5115 #define CAN_F2R2_FB7_Pos       (7U)
5116 #define CAN_F2R2_FB7_Msk       (0x1U << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
5117 #define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
5118 #define CAN_F2R2_FB8_Pos       (8U)
5119 #define CAN_F2R2_FB8_Msk       (0x1U << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
5120 #define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
5121 #define CAN_F2R2_FB9_Pos       (9U)
5122 #define CAN_F2R2_FB9_Msk       (0x1U << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
5123 #define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
5124 #define CAN_F2R2_FB10_Pos      (10U)
5125 #define CAN_F2R2_FB10_Msk      (0x1U << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
5126 #define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
5127 #define CAN_F2R2_FB11_Pos      (11U)
5128 #define CAN_F2R2_FB11_Msk      (0x1U << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
5129 #define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
5130 #define CAN_F2R2_FB12_Pos      (12U)
5131 #define CAN_F2R2_FB12_Msk      (0x1U << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
5132 #define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
5133 #define CAN_F2R2_FB13_Pos      (13U)
5134 #define CAN_F2R2_FB13_Msk      (0x1U << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
5135 #define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
5136 #define CAN_F2R2_FB14_Pos      (14U)
5137 #define CAN_F2R2_FB14_Msk      (0x1U << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
5138 #define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
5139 #define CAN_F2R2_FB15_Pos      (15U)
5140 #define CAN_F2R2_FB15_Msk      (0x1U << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
5141 #define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
5142 #define CAN_F2R2_FB16_Pos      (16U)
5143 #define CAN_F2R2_FB16_Msk      (0x1U << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
5144 #define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
5145 #define CAN_F2R2_FB17_Pos      (17U)
5146 #define CAN_F2R2_FB17_Msk      (0x1U << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
5147 #define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
5148 #define CAN_F2R2_FB18_Pos      (18U)
5149 #define CAN_F2R2_FB18_Msk      (0x1U << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
5150 #define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
5151 #define CAN_F2R2_FB19_Pos      (19U)
5152 #define CAN_F2R2_FB19_Msk      (0x1U << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
5153 #define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
5154 #define CAN_F2R2_FB20_Pos      (20U)
5155 #define CAN_F2R2_FB20_Msk      (0x1U << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
5156 #define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
5157 #define CAN_F2R2_FB21_Pos      (21U)
5158 #define CAN_F2R2_FB21_Msk      (0x1U << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
5159 #define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
5160 #define CAN_F2R2_FB22_Pos      (22U)
5161 #define CAN_F2R2_FB22_Msk      (0x1U << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
5162 #define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
5163 #define CAN_F2R2_FB23_Pos      (23U)
5164 #define CAN_F2R2_FB23_Msk      (0x1U << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
5165 #define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
5166 #define CAN_F2R2_FB24_Pos      (24U)
5167 #define CAN_F2R2_FB24_Msk      (0x1U << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
5168 #define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
5169 #define CAN_F2R2_FB25_Pos      (25U)
5170 #define CAN_F2R2_FB25_Msk      (0x1U << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
5171 #define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
5172 #define CAN_F2R2_FB26_Pos      (26U)
5173 #define CAN_F2R2_FB26_Msk      (0x1U << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
5174 #define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
5175 #define CAN_F2R2_FB27_Pos      (27U)
5176 #define CAN_F2R2_FB27_Msk      (0x1U << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
5177 #define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
5178 #define CAN_F2R2_FB28_Pos      (28U)
5179 #define CAN_F2R2_FB28_Msk      (0x1U << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
5180 #define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
5181 #define CAN_F2R2_FB29_Pos      (29U)
5182 #define CAN_F2R2_FB29_Msk      (0x1U << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
5183 #define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
5184 #define CAN_F2R2_FB30_Pos      (30U)
5185 #define CAN_F2R2_FB30_Msk      (0x1U << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
5186 #define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
5187 #define CAN_F2R2_FB31_Pos      (31U)
5188 #define CAN_F2R2_FB31_Msk      (0x1U << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
5189 #define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
5190 
5191 /*******************  Bit definition for CAN_F3R2 register  *******************/
5192 #define CAN_F3R2_FB0_Pos       (0U)
5193 #define CAN_F3R2_FB0_Msk       (0x1U << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
5194 #define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
5195 #define CAN_F3R2_FB1_Pos       (1U)
5196 #define CAN_F3R2_FB1_Msk       (0x1U << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
5197 #define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
5198 #define CAN_F3R2_FB2_Pos       (2U)
5199 #define CAN_F3R2_FB2_Msk       (0x1U << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
5200 #define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
5201 #define CAN_F3R2_FB3_Pos       (3U)
5202 #define CAN_F3R2_FB3_Msk       (0x1U << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
5203 #define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
5204 #define CAN_F3R2_FB4_Pos       (4U)
5205 #define CAN_F3R2_FB4_Msk       (0x1U << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
5206 #define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
5207 #define CAN_F3R2_FB5_Pos       (5U)
5208 #define CAN_F3R2_FB5_Msk       (0x1U << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
5209 #define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
5210 #define CAN_F3R2_FB6_Pos       (6U)
5211 #define CAN_F3R2_FB6_Msk       (0x1U << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
5212 #define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
5213 #define CAN_F3R2_FB7_Pos       (7U)
5214 #define CAN_F3R2_FB7_Msk       (0x1U << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
5215 #define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
5216 #define CAN_F3R2_FB8_Pos       (8U)
5217 #define CAN_F3R2_FB8_Msk       (0x1U << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
5218 #define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
5219 #define CAN_F3R2_FB9_Pos       (9U)
5220 #define CAN_F3R2_FB9_Msk       (0x1U << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
5221 #define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
5222 #define CAN_F3R2_FB10_Pos      (10U)
5223 #define CAN_F3R2_FB10_Msk      (0x1U << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
5224 #define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
5225 #define CAN_F3R2_FB11_Pos      (11U)
5226 #define CAN_F3R2_FB11_Msk      (0x1U << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
5227 #define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
5228 #define CAN_F3R2_FB12_Pos      (12U)
5229 #define CAN_F3R2_FB12_Msk      (0x1U << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
5230 #define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
5231 #define CAN_F3R2_FB13_Pos      (13U)
5232 #define CAN_F3R2_FB13_Msk      (0x1U << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
5233 #define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
5234 #define CAN_F3R2_FB14_Pos      (14U)
5235 #define CAN_F3R2_FB14_Msk      (0x1U << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
5236 #define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
5237 #define CAN_F3R2_FB15_Pos      (15U)
5238 #define CAN_F3R2_FB15_Msk      (0x1U << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
5239 #define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
5240 #define CAN_F3R2_FB16_Pos      (16U)
5241 #define CAN_F3R2_FB16_Msk      (0x1U << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
5242 #define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
5243 #define CAN_F3R2_FB17_Pos      (17U)
5244 #define CAN_F3R2_FB17_Msk      (0x1U << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
5245 #define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
5246 #define CAN_F3R2_FB18_Pos      (18U)
5247 #define CAN_F3R2_FB18_Msk      (0x1U << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
5248 #define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
5249 #define CAN_F3R2_FB19_Pos      (19U)
5250 #define CAN_F3R2_FB19_Msk      (0x1U << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
5251 #define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
5252 #define CAN_F3R2_FB20_Pos      (20U)
5253 #define CAN_F3R2_FB20_Msk      (0x1U << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
5254 #define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
5255 #define CAN_F3R2_FB21_Pos      (21U)
5256 #define CAN_F3R2_FB21_Msk      (0x1U << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
5257 #define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
5258 #define CAN_F3R2_FB22_Pos      (22U)
5259 #define CAN_F3R2_FB22_Msk      (0x1U << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
5260 #define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
5261 #define CAN_F3R2_FB23_Pos      (23U)
5262 #define CAN_F3R2_FB23_Msk      (0x1U << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
5263 #define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
5264 #define CAN_F3R2_FB24_Pos      (24U)
5265 #define CAN_F3R2_FB24_Msk      (0x1U << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
5266 #define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
5267 #define CAN_F3R2_FB25_Pos      (25U)
5268 #define CAN_F3R2_FB25_Msk      (0x1U << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
5269 #define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
5270 #define CAN_F3R2_FB26_Pos      (26U)
5271 #define CAN_F3R2_FB26_Msk      (0x1U << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
5272 #define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
5273 #define CAN_F3R2_FB27_Pos      (27U)
5274 #define CAN_F3R2_FB27_Msk      (0x1U << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
5275 #define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
5276 #define CAN_F3R2_FB28_Pos      (28U)
5277 #define CAN_F3R2_FB28_Msk      (0x1U << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
5278 #define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
5279 #define CAN_F3R2_FB29_Pos      (29U)
5280 #define CAN_F3R2_FB29_Msk      (0x1U << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
5281 #define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
5282 #define CAN_F3R2_FB30_Pos      (30U)
5283 #define CAN_F3R2_FB30_Msk      (0x1U << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
5284 #define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
5285 #define CAN_F3R2_FB31_Pos      (31U)
5286 #define CAN_F3R2_FB31_Msk      (0x1U << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
5287 #define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
5288 
5289 /*******************  Bit definition for CAN_F4R2 register  *******************/
5290 #define CAN_F4R2_FB0_Pos       (0U)
5291 #define CAN_F4R2_FB0_Msk       (0x1U << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
5292 #define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
5293 #define CAN_F4R2_FB1_Pos       (1U)
5294 #define CAN_F4R2_FB1_Msk       (0x1U << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
5295 #define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
5296 #define CAN_F4R2_FB2_Pos       (2U)
5297 #define CAN_F4R2_FB2_Msk       (0x1U << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
5298 #define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
5299 #define CAN_F4R2_FB3_Pos       (3U)
5300 #define CAN_F4R2_FB3_Msk       (0x1U << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
5301 #define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
5302 #define CAN_F4R2_FB4_Pos       (4U)
5303 #define CAN_F4R2_FB4_Msk       (0x1U << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
5304 #define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
5305 #define CAN_F4R2_FB5_Pos       (5U)
5306 #define CAN_F4R2_FB5_Msk       (0x1U << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
5307 #define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
5308 #define CAN_F4R2_FB6_Pos       (6U)
5309 #define CAN_F4R2_FB6_Msk       (0x1U << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
5310 #define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
5311 #define CAN_F4R2_FB7_Pos       (7U)
5312 #define CAN_F4R2_FB7_Msk       (0x1U << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
5313 #define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
5314 #define CAN_F4R2_FB8_Pos       (8U)
5315 #define CAN_F4R2_FB8_Msk       (0x1U << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
5316 #define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
5317 #define CAN_F4R2_FB9_Pos       (9U)
5318 #define CAN_F4R2_FB9_Msk       (0x1U << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
5319 #define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
5320 #define CAN_F4R2_FB10_Pos      (10U)
5321 #define CAN_F4R2_FB10_Msk      (0x1U << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
5322 #define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
5323 #define CAN_F4R2_FB11_Pos      (11U)
5324 #define CAN_F4R2_FB11_Msk      (0x1U << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
5325 #define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
5326 #define CAN_F4R2_FB12_Pos      (12U)
5327 #define CAN_F4R2_FB12_Msk      (0x1U << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
5328 #define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
5329 #define CAN_F4R2_FB13_Pos      (13U)
5330 #define CAN_F4R2_FB13_Msk      (0x1U << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
5331 #define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
5332 #define CAN_F4R2_FB14_Pos      (14U)
5333 #define CAN_F4R2_FB14_Msk      (0x1U << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
5334 #define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
5335 #define CAN_F4R2_FB15_Pos      (15U)
5336 #define CAN_F4R2_FB15_Msk      (0x1U << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
5337 #define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
5338 #define CAN_F4R2_FB16_Pos      (16U)
5339 #define CAN_F4R2_FB16_Msk      (0x1U << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
5340 #define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
5341 #define CAN_F4R2_FB17_Pos      (17U)
5342 #define CAN_F4R2_FB17_Msk      (0x1U << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
5343 #define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
5344 #define CAN_F4R2_FB18_Pos      (18U)
5345 #define CAN_F4R2_FB18_Msk      (0x1U << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
5346 #define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
5347 #define CAN_F4R2_FB19_Pos      (19U)
5348 #define CAN_F4R2_FB19_Msk      (0x1U << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
5349 #define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
5350 #define CAN_F4R2_FB20_Pos      (20U)
5351 #define CAN_F4R2_FB20_Msk      (0x1U << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
5352 #define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
5353 #define CAN_F4R2_FB21_Pos      (21U)
5354 #define CAN_F4R2_FB21_Msk      (0x1U << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
5355 #define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
5356 #define CAN_F4R2_FB22_Pos      (22U)
5357 #define CAN_F4R2_FB22_Msk      (0x1U << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
5358 #define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
5359 #define CAN_F4R2_FB23_Pos      (23U)
5360 #define CAN_F4R2_FB23_Msk      (0x1U << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
5361 #define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
5362 #define CAN_F4R2_FB24_Pos      (24U)
5363 #define CAN_F4R2_FB24_Msk      (0x1U << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
5364 #define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
5365 #define CAN_F4R2_FB25_Pos      (25U)
5366 #define CAN_F4R2_FB25_Msk      (0x1U << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
5367 #define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
5368 #define CAN_F4R2_FB26_Pos      (26U)
5369 #define CAN_F4R2_FB26_Msk      (0x1U << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
5370 #define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
5371 #define CAN_F4R2_FB27_Pos      (27U)
5372 #define CAN_F4R2_FB27_Msk      (0x1U << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
5373 #define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
5374 #define CAN_F4R2_FB28_Pos      (28U)
5375 #define CAN_F4R2_FB28_Msk      (0x1U << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
5376 #define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
5377 #define CAN_F4R2_FB29_Pos      (29U)
5378 #define CAN_F4R2_FB29_Msk      (0x1U << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
5379 #define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
5380 #define CAN_F4R2_FB30_Pos      (30U)
5381 #define CAN_F4R2_FB30_Msk      (0x1U << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
5382 #define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
5383 #define CAN_F4R2_FB31_Pos      (31U)
5384 #define CAN_F4R2_FB31_Msk      (0x1U << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
5385 #define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
5386 
5387 /*******************  Bit definition for CAN_F5R2 register  *******************/
5388 #define CAN_F5R2_FB0_Pos       (0U)
5389 #define CAN_F5R2_FB0_Msk       (0x1U << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
5390 #define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
5391 #define CAN_F5R2_FB1_Pos       (1U)
5392 #define CAN_F5R2_FB1_Msk       (0x1U << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
5393 #define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
5394 #define CAN_F5R2_FB2_Pos       (2U)
5395 #define CAN_F5R2_FB2_Msk       (0x1U << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
5396 #define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
5397 #define CAN_F5R2_FB3_Pos       (3U)
5398 #define CAN_F5R2_FB3_Msk       (0x1U << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
5399 #define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
5400 #define CAN_F5R2_FB4_Pos       (4U)
5401 #define CAN_F5R2_FB4_Msk       (0x1U << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
5402 #define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
5403 #define CAN_F5R2_FB5_Pos       (5U)
5404 #define CAN_F5R2_FB5_Msk       (0x1U << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
5405 #define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
5406 #define CAN_F5R2_FB6_Pos       (6U)
5407 #define CAN_F5R2_FB6_Msk       (0x1U << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
5408 #define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
5409 #define CAN_F5R2_FB7_Pos       (7U)
5410 #define CAN_F5R2_FB7_Msk       (0x1U << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
5411 #define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
5412 #define CAN_F5R2_FB8_Pos       (8U)
5413 #define CAN_F5R2_FB8_Msk       (0x1U << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
5414 #define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
5415 #define CAN_F5R2_FB9_Pos       (9U)
5416 #define CAN_F5R2_FB9_Msk       (0x1U << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
5417 #define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
5418 #define CAN_F5R2_FB10_Pos      (10U)
5419 #define CAN_F5R2_FB10_Msk      (0x1U << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
5420 #define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
5421 #define CAN_F5R2_FB11_Pos      (11U)
5422 #define CAN_F5R2_FB11_Msk      (0x1U << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
5423 #define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
5424 #define CAN_F5R2_FB12_Pos      (12U)
5425 #define CAN_F5R2_FB12_Msk      (0x1U << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
5426 #define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
5427 #define CAN_F5R2_FB13_Pos      (13U)
5428 #define CAN_F5R2_FB13_Msk      (0x1U << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
5429 #define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
5430 #define CAN_F5R2_FB14_Pos      (14U)
5431 #define CAN_F5R2_FB14_Msk      (0x1U << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
5432 #define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
5433 #define CAN_F5R2_FB15_Pos      (15U)
5434 #define CAN_F5R2_FB15_Msk      (0x1U << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
5435 #define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
5436 #define CAN_F5R2_FB16_Pos      (16U)
5437 #define CAN_F5R2_FB16_Msk      (0x1U << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
5438 #define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
5439 #define CAN_F5R2_FB17_Pos      (17U)
5440 #define CAN_F5R2_FB17_Msk      (0x1U << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
5441 #define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
5442 #define CAN_F5R2_FB18_Pos      (18U)
5443 #define CAN_F5R2_FB18_Msk      (0x1U << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
5444 #define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
5445 #define CAN_F5R2_FB19_Pos      (19U)
5446 #define CAN_F5R2_FB19_Msk      (0x1U << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
5447 #define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
5448 #define CAN_F5R2_FB20_Pos      (20U)
5449 #define CAN_F5R2_FB20_Msk      (0x1U << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
5450 #define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
5451 #define CAN_F5R2_FB21_Pos      (21U)
5452 #define CAN_F5R2_FB21_Msk      (0x1U << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
5453 #define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
5454 #define CAN_F5R2_FB22_Pos      (22U)
5455 #define CAN_F5R2_FB22_Msk      (0x1U << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
5456 #define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
5457 #define CAN_F5R2_FB23_Pos      (23U)
5458 #define CAN_F5R2_FB23_Msk      (0x1U << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
5459 #define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
5460 #define CAN_F5R2_FB24_Pos      (24U)
5461 #define CAN_F5R2_FB24_Msk      (0x1U << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
5462 #define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
5463 #define CAN_F5R2_FB25_Pos      (25U)
5464 #define CAN_F5R2_FB25_Msk      (0x1U << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
5465 #define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
5466 #define CAN_F5R2_FB26_Pos      (26U)
5467 #define CAN_F5R2_FB26_Msk      (0x1U << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
5468 #define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
5469 #define CAN_F5R2_FB27_Pos      (27U)
5470 #define CAN_F5R2_FB27_Msk      (0x1U << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
5471 #define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
5472 #define CAN_F5R2_FB28_Pos      (28U)
5473 #define CAN_F5R2_FB28_Msk      (0x1U << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
5474 #define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
5475 #define CAN_F5R2_FB29_Pos      (29U)
5476 #define CAN_F5R2_FB29_Msk      (0x1U << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
5477 #define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
5478 #define CAN_F5R2_FB30_Pos      (30U)
5479 #define CAN_F5R2_FB30_Msk      (0x1U << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
5480 #define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
5481 #define CAN_F5R2_FB31_Pos      (31U)
5482 #define CAN_F5R2_FB31_Msk      (0x1U << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
5483 #define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
5484 
5485 /*******************  Bit definition for CAN_F6R2 register  *******************/
5486 #define CAN_F6R2_FB0_Pos       (0U)
5487 #define CAN_F6R2_FB0_Msk       (0x1U << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
5488 #define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
5489 #define CAN_F6R2_FB1_Pos       (1U)
5490 #define CAN_F6R2_FB1_Msk       (0x1U << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
5491 #define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
5492 #define CAN_F6R2_FB2_Pos       (2U)
5493 #define CAN_F6R2_FB2_Msk       (0x1U << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
5494 #define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
5495 #define CAN_F6R2_FB3_Pos       (3U)
5496 #define CAN_F6R2_FB3_Msk       (0x1U << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
5497 #define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
5498 #define CAN_F6R2_FB4_Pos       (4U)
5499 #define CAN_F6R2_FB4_Msk       (0x1U << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
5500 #define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
5501 #define CAN_F6R2_FB5_Pos       (5U)
5502 #define CAN_F6R2_FB5_Msk       (0x1U << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
5503 #define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
5504 #define CAN_F6R2_FB6_Pos       (6U)
5505 #define CAN_F6R2_FB6_Msk       (0x1U << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
5506 #define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
5507 #define CAN_F6R2_FB7_Pos       (7U)
5508 #define CAN_F6R2_FB7_Msk       (0x1U << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
5509 #define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
5510 #define CAN_F6R2_FB8_Pos       (8U)
5511 #define CAN_F6R2_FB8_Msk       (0x1U << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
5512 #define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
5513 #define CAN_F6R2_FB9_Pos       (9U)
5514 #define CAN_F6R2_FB9_Msk       (0x1U << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
5515 #define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
5516 #define CAN_F6R2_FB10_Pos      (10U)
5517 #define CAN_F6R2_FB10_Msk      (0x1U << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
5518 #define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
5519 #define CAN_F6R2_FB11_Pos      (11U)
5520 #define CAN_F6R2_FB11_Msk      (0x1U << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
5521 #define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
5522 #define CAN_F6R2_FB12_Pos      (12U)
5523 #define CAN_F6R2_FB12_Msk      (0x1U << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
5524 #define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
5525 #define CAN_F6R2_FB13_Pos      (13U)
5526 #define CAN_F6R2_FB13_Msk      (0x1U << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
5527 #define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
5528 #define CAN_F6R2_FB14_Pos      (14U)
5529 #define CAN_F6R2_FB14_Msk      (0x1U << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
5530 #define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
5531 #define CAN_F6R2_FB15_Pos      (15U)
5532 #define CAN_F6R2_FB15_Msk      (0x1U << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
5533 #define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
5534 #define CAN_F6R2_FB16_Pos      (16U)
5535 #define CAN_F6R2_FB16_Msk      (0x1U << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
5536 #define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
5537 #define CAN_F6R2_FB17_Pos      (17U)
5538 #define CAN_F6R2_FB17_Msk      (0x1U << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
5539 #define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
5540 #define CAN_F6R2_FB18_Pos      (18U)
5541 #define CAN_F6R2_FB18_Msk      (0x1U << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
5542 #define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
5543 #define CAN_F6R2_FB19_Pos      (19U)
5544 #define CAN_F6R2_FB19_Msk      (0x1U << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
5545 #define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
5546 #define CAN_F6R2_FB20_Pos      (20U)
5547 #define CAN_F6R2_FB20_Msk      (0x1U << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
5548 #define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
5549 #define CAN_F6R2_FB21_Pos      (21U)
5550 #define CAN_F6R2_FB21_Msk      (0x1U << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
5551 #define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
5552 #define CAN_F6R2_FB22_Pos      (22U)
5553 #define CAN_F6R2_FB22_Msk      (0x1U << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
5554 #define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
5555 #define CAN_F6R2_FB23_Pos      (23U)
5556 #define CAN_F6R2_FB23_Msk      (0x1U << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
5557 #define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
5558 #define CAN_F6R2_FB24_Pos      (24U)
5559 #define CAN_F6R2_FB24_Msk      (0x1U << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
5560 #define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
5561 #define CAN_F6R2_FB25_Pos      (25U)
5562 #define CAN_F6R2_FB25_Msk      (0x1U << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
5563 #define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
5564 #define CAN_F6R2_FB26_Pos      (26U)
5565 #define CAN_F6R2_FB26_Msk      (0x1U << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
5566 #define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
5567 #define CAN_F6R2_FB27_Pos      (27U)
5568 #define CAN_F6R2_FB27_Msk      (0x1U << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
5569 #define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
5570 #define CAN_F6R2_FB28_Pos      (28U)
5571 #define CAN_F6R2_FB28_Msk      (0x1U << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
5572 #define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
5573 #define CAN_F6R2_FB29_Pos      (29U)
5574 #define CAN_F6R2_FB29_Msk      (0x1U << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
5575 #define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
5576 #define CAN_F6R2_FB30_Pos      (30U)
5577 #define CAN_F6R2_FB30_Msk      (0x1U << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
5578 #define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
5579 #define CAN_F6R2_FB31_Pos      (31U)
5580 #define CAN_F6R2_FB31_Msk      (0x1U << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
5581 #define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
5582 
5583 /*******************  Bit definition for CAN_F7R2 register  *******************/
5584 #define CAN_F7R2_FB0_Pos       (0U)
5585 #define CAN_F7R2_FB0_Msk       (0x1U << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
5586 #define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
5587 #define CAN_F7R2_FB1_Pos       (1U)
5588 #define CAN_F7R2_FB1_Msk       (0x1U << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
5589 #define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
5590 #define CAN_F7R2_FB2_Pos       (2U)
5591 #define CAN_F7R2_FB2_Msk       (0x1U << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
5592 #define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
5593 #define CAN_F7R2_FB3_Pos       (3U)
5594 #define CAN_F7R2_FB3_Msk       (0x1U << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
5595 #define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
5596 #define CAN_F7R2_FB4_Pos       (4U)
5597 #define CAN_F7R2_FB4_Msk       (0x1U << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
5598 #define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
5599 #define CAN_F7R2_FB5_Pos       (5U)
5600 #define CAN_F7R2_FB5_Msk       (0x1U << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
5601 #define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
5602 #define CAN_F7R2_FB6_Pos       (6U)
5603 #define CAN_F7R2_FB6_Msk       (0x1U << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
5604 #define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
5605 #define CAN_F7R2_FB7_Pos       (7U)
5606 #define CAN_F7R2_FB7_Msk       (0x1U << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
5607 #define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
5608 #define CAN_F7R2_FB8_Pos       (8U)
5609 #define CAN_F7R2_FB8_Msk       (0x1U << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
5610 #define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
5611 #define CAN_F7R2_FB9_Pos       (9U)
5612 #define CAN_F7R2_FB9_Msk       (0x1U << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
5613 #define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
5614 #define CAN_F7R2_FB10_Pos      (10U)
5615 #define CAN_F7R2_FB10_Msk      (0x1U << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
5616 #define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
5617 #define CAN_F7R2_FB11_Pos      (11U)
5618 #define CAN_F7R2_FB11_Msk      (0x1U << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
5619 #define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
5620 #define CAN_F7R2_FB12_Pos      (12U)
5621 #define CAN_F7R2_FB12_Msk      (0x1U << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
5622 #define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
5623 #define CAN_F7R2_FB13_Pos      (13U)
5624 #define CAN_F7R2_FB13_Msk      (0x1U << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
5625 #define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
5626 #define CAN_F7R2_FB14_Pos      (14U)
5627 #define CAN_F7R2_FB14_Msk      (0x1U << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
5628 #define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
5629 #define CAN_F7R2_FB15_Pos      (15U)
5630 #define CAN_F7R2_FB15_Msk      (0x1U << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
5631 #define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
5632 #define CAN_F7R2_FB16_Pos      (16U)
5633 #define CAN_F7R2_FB16_Msk      (0x1U << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
5634 #define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
5635 #define CAN_F7R2_FB17_Pos      (17U)
5636 #define CAN_F7R2_FB17_Msk      (0x1U << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
5637 #define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
5638 #define CAN_F7R2_FB18_Pos      (18U)
5639 #define CAN_F7R2_FB18_Msk      (0x1U << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
5640 #define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
5641 #define CAN_F7R2_FB19_Pos      (19U)
5642 #define CAN_F7R2_FB19_Msk      (0x1U << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
5643 #define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
5644 #define CAN_F7R2_FB20_Pos      (20U)
5645 #define CAN_F7R2_FB20_Msk      (0x1U << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
5646 #define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
5647 #define CAN_F7R2_FB21_Pos      (21U)
5648 #define CAN_F7R2_FB21_Msk      (0x1U << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
5649 #define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
5650 #define CAN_F7R2_FB22_Pos      (22U)
5651 #define CAN_F7R2_FB22_Msk      (0x1U << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
5652 #define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
5653 #define CAN_F7R2_FB23_Pos      (23U)
5654 #define CAN_F7R2_FB23_Msk      (0x1U << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
5655 #define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
5656 #define CAN_F7R2_FB24_Pos      (24U)
5657 #define CAN_F7R2_FB24_Msk      (0x1U << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
5658 #define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
5659 #define CAN_F7R2_FB25_Pos      (25U)
5660 #define CAN_F7R2_FB25_Msk      (0x1U << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
5661 #define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
5662 #define CAN_F7R2_FB26_Pos      (26U)
5663 #define CAN_F7R2_FB26_Msk      (0x1U << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
5664 #define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
5665 #define CAN_F7R2_FB27_Pos      (27U)
5666 #define CAN_F7R2_FB27_Msk      (0x1U << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
5667 #define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
5668 #define CAN_F7R2_FB28_Pos      (28U)
5669 #define CAN_F7R2_FB28_Msk      (0x1U << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
5670 #define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
5671 #define CAN_F7R2_FB29_Pos      (29U)
5672 #define CAN_F7R2_FB29_Msk      (0x1U << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
5673 #define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
5674 #define CAN_F7R2_FB30_Pos      (30U)
5675 #define CAN_F7R2_FB30_Msk      (0x1U << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
5676 #define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
5677 #define CAN_F7R2_FB31_Pos      (31U)
5678 #define CAN_F7R2_FB31_Msk      (0x1U << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
5679 #define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
5680 
5681 /*******************  Bit definition for CAN_F8R2 register  *******************/
5682 #define CAN_F8R2_FB0_Pos       (0U)
5683 #define CAN_F8R2_FB0_Msk       (0x1U << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
5684 #define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
5685 #define CAN_F8R2_FB1_Pos       (1U)
5686 #define CAN_F8R2_FB1_Msk       (0x1U << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
5687 #define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
5688 #define CAN_F8R2_FB2_Pos       (2U)
5689 #define CAN_F8R2_FB2_Msk       (0x1U << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
5690 #define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
5691 #define CAN_F8R2_FB3_Pos       (3U)
5692 #define CAN_F8R2_FB3_Msk       (0x1U << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
5693 #define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
5694 #define CAN_F8R2_FB4_Pos       (4U)
5695 #define CAN_F8R2_FB4_Msk       (0x1U << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
5696 #define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
5697 #define CAN_F8R2_FB5_Pos       (5U)
5698 #define CAN_F8R2_FB5_Msk       (0x1U << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
5699 #define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
5700 #define CAN_F8R2_FB6_Pos       (6U)
5701 #define CAN_F8R2_FB6_Msk       (0x1U << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
5702 #define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
5703 #define CAN_F8R2_FB7_Pos       (7U)
5704 #define CAN_F8R2_FB7_Msk       (0x1U << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
5705 #define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
5706 #define CAN_F8R2_FB8_Pos       (8U)
5707 #define CAN_F8R2_FB8_Msk       (0x1U << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
5708 #define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
5709 #define CAN_F8R2_FB9_Pos       (9U)
5710 #define CAN_F8R2_FB9_Msk       (0x1U << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
5711 #define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
5712 #define CAN_F8R2_FB10_Pos      (10U)
5713 #define CAN_F8R2_FB10_Msk      (0x1U << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
5714 #define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
5715 #define CAN_F8R2_FB11_Pos      (11U)
5716 #define CAN_F8R2_FB11_Msk      (0x1U << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
5717 #define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
5718 #define CAN_F8R2_FB12_Pos      (12U)
5719 #define CAN_F8R2_FB12_Msk      (0x1U << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
5720 #define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
5721 #define CAN_F8R2_FB13_Pos      (13U)
5722 #define CAN_F8R2_FB13_Msk      (0x1U << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
5723 #define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
5724 #define CAN_F8R2_FB14_Pos      (14U)
5725 #define CAN_F8R2_FB14_Msk      (0x1U << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
5726 #define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
5727 #define CAN_F8R2_FB15_Pos      (15U)
5728 #define CAN_F8R2_FB15_Msk      (0x1U << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
5729 #define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
5730 #define CAN_F8R2_FB16_Pos      (16U)
5731 #define CAN_F8R2_FB16_Msk      (0x1U << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
5732 #define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
5733 #define CAN_F8R2_FB17_Pos      (17U)
5734 #define CAN_F8R2_FB17_Msk      (0x1U << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
5735 #define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
5736 #define CAN_F8R2_FB18_Pos      (18U)
5737 #define CAN_F8R2_FB18_Msk      (0x1U << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
5738 #define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
5739 #define CAN_F8R2_FB19_Pos      (19U)
5740 #define CAN_F8R2_FB19_Msk      (0x1U << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
5741 #define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
5742 #define CAN_F8R2_FB20_Pos      (20U)
5743 #define CAN_F8R2_FB20_Msk      (0x1U << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
5744 #define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
5745 #define CAN_F8R2_FB21_Pos      (21U)
5746 #define CAN_F8R2_FB21_Msk      (0x1U << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
5747 #define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
5748 #define CAN_F8R2_FB22_Pos      (22U)
5749 #define CAN_F8R2_FB22_Msk      (0x1U << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
5750 #define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
5751 #define CAN_F8R2_FB23_Pos      (23U)
5752 #define CAN_F8R2_FB23_Msk      (0x1U << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
5753 #define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
5754 #define CAN_F8R2_FB24_Pos      (24U)
5755 #define CAN_F8R2_FB24_Msk      (0x1U << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
5756 #define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
5757 #define CAN_F8R2_FB25_Pos      (25U)
5758 #define CAN_F8R2_FB25_Msk      (0x1U << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
5759 #define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
5760 #define CAN_F8R2_FB26_Pos      (26U)
5761 #define CAN_F8R2_FB26_Msk      (0x1U << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
5762 #define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
5763 #define CAN_F8R2_FB27_Pos      (27U)
5764 #define CAN_F8R2_FB27_Msk      (0x1U << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
5765 #define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
5766 #define CAN_F8R2_FB28_Pos      (28U)
5767 #define CAN_F8R2_FB28_Msk      (0x1U << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
5768 #define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
5769 #define CAN_F8R2_FB29_Pos      (29U)
5770 #define CAN_F8R2_FB29_Msk      (0x1U << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
5771 #define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
5772 #define CAN_F8R2_FB30_Pos      (30U)
5773 #define CAN_F8R2_FB30_Msk      (0x1U << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
5774 #define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
5775 #define CAN_F8R2_FB31_Pos      (31U)
5776 #define CAN_F8R2_FB31_Msk      (0x1U << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
5777 #define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
5778 
5779 /*******************  Bit definition for CAN_F9R2 register  *******************/
5780 #define CAN_F9R2_FB0_Pos       (0U)
5781 #define CAN_F9R2_FB0_Msk       (0x1U << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
5782 #define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
5783 #define CAN_F9R2_FB1_Pos       (1U)
5784 #define CAN_F9R2_FB1_Msk       (0x1U << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
5785 #define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
5786 #define CAN_F9R2_FB2_Pos       (2U)
5787 #define CAN_F9R2_FB2_Msk       (0x1U << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
5788 #define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
5789 #define CAN_F9R2_FB3_Pos       (3U)
5790 #define CAN_F9R2_FB3_Msk       (0x1U << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
5791 #define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
5792 #define CAN_F9R2_FB4_Pos       (4U)
5793 #define CAN_F9R2_FB4_Msk       (0x1U << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
5794 #define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
5795 #define CAN_F9R2_FB5_Pos       (5U)
5796 #define CAN_F9R2_FB5_Msk       (0x1U << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
5797 #define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
5798 #define CAN_F9R2_FB6_Pos       (6U)
5799 #define CAN_F9R2_FB6_Msk       (0x1U << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
5800 #define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
5801 #define CAN_F9R2_FB7_Pos       (7U)
5802 #define CAN_F9R2_FB7_Msk       (0x1U << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
5803 #define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
5804 #define CAN_F9R2_FB8_Pos       (8U)
5805 #define CAN_F9R2_FB8_Msk       (0x1U << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
5806 #define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
5807 #define CAN_F9R2_FB9_Pos       (9U)
5808 #define CAN_F9R2_FB9_Msk       (0x1U << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
5809 #define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
5810 #define CAN_F9R2_FB10_Pos      (10U)
5811 #define CAN_F9R2_FB10_Msk      (0x1U << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
5812 #define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
5813 #define CAN_F9R2_FB11_Pos      (11U)
5814 #define CAN_F9R2_FB11_Msk      (0x1U << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
5815 #define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
5816 #define CAN_F9R2_FB12_Pos      (12U)
5817 #define CAN_F9R2_FB12_Msk      (0x1U << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
5818 #define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
5819 #define CAN_F9R2_FB13_Pos      (13U)
5820 #define CAN_F9R2_FB13_Msk      (0x1U << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
5821 #define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
5822 #define CAN_F9R2_FB14_Pos      (14U)
5823 #define CAN_F9R2_FB14_Msk      (0x1U << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
5824 #define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
5825 #define CAN_F9R2_FB15_Pos      (15U)
5826 #define CAN_F9R2_FB15_Msk      (0x1U << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
5827 #define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
5828 #define CAN_F9R2_FB16_Pos      (16U)
5829 #define CAN_F9R2_FB16_Msk      (0x1U << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
5830 #define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
5831 #define CAN_F9R2_FB17_Pos      (17U)
5832 #define CAN_F9R2_FB17_Msk      (0x1U << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
5833 #define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
5834 #define CAN_F9R2_FB18_Pos      (18U)
5835 #define CAN_F9R2_FB18_Msk      (0x1U << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
5836 #define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
5837 #define CAN_F9R2_FB19_Pos      (19U)
5838 #define CAN_F9R2_FB19_Msk      (0x1U << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
5839 #define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
5840 #define CAN_F9R2_FB20_Pos      (20U)
5841 #define CAN_F9R2_FB20_Msk      (0x1U << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
5842 #define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
5843 #define CAN_F9R2_FB21_Pos      (21U)
5844 #define CAN_F9R2_FB21_Msk      (0x1U << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
5845 #define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
5846 #define CAN_F9R2_FB22_Pos      (22U)
5847 #define CAN_F9R2_FB22_Msk      (0x1U << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
5848 #define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
5849 #define CAN_F9R2_FB23_Pos      (23U)
5850 #define CAN_F9R2_FB23_Msk      (0x1U << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
5851 #define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
5852 #define CAN_F9R2_FB24_Pos      (24U)
5853 #define CAN_F9R2_FB24_Msk      (0x1U << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
5854 #define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
5855 #define CAN_F9R2_FB25_Pos      (25U)
5856 #define CAN_F9R2_FB25_Msk      (0x1U << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
5857 #define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
5858 #define CAN_F9R2_FB26_Pos      (26U)
5859 #define CAN_F9R2_FB26_Msk      (0x1U << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
5860 #define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
5861 #define CAN_F9R2_FB27_Pos      (27U)
5862 #define CAN_F9R2_FB27_Msk      (0x1U << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
5863 #define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
5864 #define CAN_F9R2_FB28_Pos      (28U)
5865 #define CAN_F9R2_FB28_Msk      (0x1U << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
5866 #define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
5867 #define CAN_F9R2_FB29_Pos      (29U)
5868 #define CAN_F9R2_FB29_Msk      (0x1U << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
5869 #define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
5870 #define CAN_F9R2_FB30_Pos      (30U)
5871 #define CAN_F9R2_FB30_Msk      (0x1U << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
5872 #define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
5873 #define CAN_F9R2_FB31_Pos      (31U)
5874 #define CAN_F9R2_FB31_Msk      (0x1U << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
5875 #define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
5876 
5877 /*******************  Bit definition for CAN_F10R2 register  ******************/
5878 #define CAN_F10R2_FB0_Pos      (0U)
5879 #define CAN_F10R2_FB0_Msk      (0x1U << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
5880 #define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
5881 #define CAN_F10R2_FB1_Pos      (1U)
5882 #define CAN_F10R2_FB1_Msk      (0x1U << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
5883 #define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
5884 #define CAN_F10R2_FB2_Pos      (2U)
5885 #define CAN_F10R2_FB2_Msk      (0x1U << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
5886 #define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
5887 #define CAN_F10R2_FB3_Pos      (3U)
5888 #define CAN_F10R2_FB3_Msk      (0x1U << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
5889 #define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
5890 #define CAN_F10R2_FB4_Pos      (4U)
5891 #define CAN_F10R2_FB4_Msk      (0x1U << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
5892 #define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
5893 #define CAN_F10R2_FB5_Pos      (5U)
5894 #define CAN_F10R2_FB5_Msk      (0x1U << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
5895 #define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
5896 #define CAN_F10R2_FB6_Pos      (6U)
5897 #define CAN_F10R2_FB6_Msk      (0x1U << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
5898 #define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
5899 #define CAN_F10R2_FB7_Pos      (7U)
5900 #define CAN_F10R2_FB7_Msk      (0x1U << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
5901 #define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
5902 #define CAN_F10R2_FB8_Pos      (8U)
5903 #define CAN_F10R2_FB8_Msk      (0x1U << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
5904 #define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
5905 #define CAN_F10R2_FB9_Pos      (9U)
5906 #define CAN_F10R2_FB9_Msk      (0x1U << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
5907 #define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
5908 #define CAN_F10R2_FB10_Pos     (10U)
5909 #define CAN_F10R2_FB10_Msk     (0x1U << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
5910 #define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
5911 #define CAN_F10R2_FB11_Pos     (11U)
5912 #define CAN_F10R2_FB11_Msk     (0x1U << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
5913 #define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
5914 #define CAN_F10R2_FB12_Pos     (12U)
5915 #define CAN_F10R2_FB12_Msk     (0x1U << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
5916 #define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
5917 #define CAN_F10R2_FB13_Pos     (13U)
5918 #define CAN_F10R2_FB13_Msk     (0x1U << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
5919 #define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
5920 #define CAN_F10R2_FB14_Pos     (14U)
5921 #define CAN_F10R2_FB14_Msk     (0x1U << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
5922 #define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
5923 #define CAN_F10R2_FB15_Pos     (15U)
5924 #define CAN_F10R2_FB15_Msk     (0x1U << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
5925 #define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
5926 #define CAN_F10R2_FB16_Pos     (16U)
5927 #define CAN_F10R2_FB16_Msk     (0x1U << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
5928 #define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
5929 #define CAN_F10R2_FB17_Pos     (17U)
5930 #define CAN_F10R2_FB17_Msk     (0x1U << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
5931 #define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
5932 #define CAN_F10R2_FB18_Pos     (18U)
5933 #define CAN_F10R2_FB18_Msk     (0x1U << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
5934 #define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
5935 #define CAN_F10R2_FB19_Pos     (19U)
5936 #define CAN_F10R2_FB19_Msk     (0x1U << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
5937 #define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
5938 #define CAN_F10R2_FB20_Pos     (20U)
5939 #define CAN_F10R2_FB20_Msk     (0x1U << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
5940 #define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
5941 #define CAN_F10R2_FB21_Pos     (21U)
5942 #define CAN_F10R2_FB21_Msk     (0x1U << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
5943 #define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
5944 #define CAN_F10R2_FB22_Pos     (22U)
5945 #define CAN_F10R2_FB22_Msk     (0x1U << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
5946 #define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
5947 #define CAN_F10R2_FB23_Pos     (23U)
5948 #define CAN_F10R2_FB23_Msk     (0x1U << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
5949 #define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
5950 #define CAN_F10R2_FB24_Pos     (24U)
5951 #define CAN_F10R2_FB24_Msk     (0x1U << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
5952 #define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
5953 #define CAN_F10R2_FB25_Pos     (25U)
5954 #define CAN_F10R2_FB25_Msk     (0x1U << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
5955 #define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
5956 #define CAN_F10R2_FB26_Pos     (26U)
5957 #define CAN_F10R2_FB26_Msk     (0x1U << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
5958 #define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
5959 #define CAN_F10R2_FB27_Pos     (27U)
5960 #define CAN_F10R2_FB27_Msk     (0x1U << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
5961 #define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
5962 #define CAN_F10R2_FB28_Pos     (28U)
5963 #define CAN_F10R2_FB28_Msk     (0x1U << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
5964 #define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
5965 #define CAN_F10R2_FB29_Pos     (29U)
5966 #define CAN_F10R2_FB29_Msk     (0x1U << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
5967 #define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
5968 #define CAN_F10R2_FB30_Pos     (30U)
5969 #define CAN_F10R2_FB30_Msk     (0x1U << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
5970 #define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
5971 #define CAN_F10R2_FB31_Pos     (31U)
5972 #define CAN_F10R2_FB31_Msk     (0x1U << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
5973 #define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
5974 
5975 /*******************  Bit definition for CAN_F11R2 register  ******************/
5976 #define CAN_F11R2_FB0_Pos      (0U)
5977 #define CAN_F11R2_FB0_Msk      (0x1U << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
5978 #define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
5979 #define CAN_F11R2_FB1_Pos      (1U)
5980 #define CAN_F11R2_FB1_Msk      (0x1U << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
5981 #define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
5982 #define CAN_F11R2_FB2_Pos      (2U)
5983 #define CAN_F11R2_FB2_Msk      (0x1U << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
5984 #define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
5985 #define CAN_F11R2_FB3_Pos      (3U)
5986 #define CAN_F11R2_FB3_Msk      (0x1U << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
5987 #define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
5988 #define CAN_F11R2_FB4_Pos      (4U)
5989 #define CAN_F11R2_FB4_Msk      (0x1U << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
5990 #define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
5991 #define CAN_F11R2_FB5_Pos      (5U)
5992 #define CAN_F11R2_FB5_Msk      (0x1U << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
5993 #define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
5994 #define CAN_F11R2_FB6_Pos      (6U)
5995 #define CAN_F11R2_FB6_Msk      (0x1U << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
5996 #define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
5997 #define CAN_F11R2_FB7_Pos      (7U)
5998 #define CAN_F11R2_FB7_Msk      (0x1U << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
5999 #define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
6000 #define CAN_F11R2_FB8_Pos      (8U)
6001 #define CAN_F11R2_FB8_Msk      (0x1U << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
6002 #define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
6003 #define CAN_F11R2_FB9_Pos      (9U)
6004 #define CAN_F11R2_FB9_Msk      (0x1U << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
6005 #define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
6006 #define CAN_F11R2_FB10_Pos     (10U)
6007 #define CAN_F11R2_FB10_Msk     (0x1U << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
6008 #define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
6009 #define CAN_F11R2_FB11_Pos     (11U)
6010 #define CAN_F11R2_FB11_Msk     (0x1U << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
6011 #define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
6012 #define CAN_F11R2_FB12_Pos     (12U)
6013 #define CAN_F11R2_FB12_Msk     (0x1U << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
6014 #define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
6015 #define CAN_F11R2_FB13_Pos     (13U)
6016 #define CAN_F11R2_FB13_Msk     (0x1U << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
6017 #define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
6018 #define CAN_F11R2_FB14_Pos     (14U)
6019 #define CAN_F11R2_FB14_Msk     (0x1U << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
6020 #define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
6021 #define CAN_F11R2_FB15_Pos     (15U)
6022 #define CAN_F11R2_FB15_Msk     (0x1U << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
6023 #define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
6024 #define CAN_F11R2_FB16_Pos     (16U)
6025 #define CAN_F11R2_FB16_Msk     (0x1U << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
6026 #define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
6027 #define CAN_F11R2_FB17_Pos     (17U)
6028 #define CAN_F11R2_FB17_Msk     (0x1U << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
6029 #define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
6030 #define CAN_F11R2_FB18_Pos     (18U)
6031 #define CAN_F11R2_FB18_Msk     (0x1U << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
6032 #define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
6033 #define CAN_F11R2_FB19_Pos     (19U)
6034 #define CAN_F11R2_FB19_Msk     (0x1U << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
6035 #define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
6036 #define CAN_F11R2_FB20_Pos     (20U)
6037 #define CAN_F11R2_FB20_Msk     (0x1U << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
6038 #define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
6039 #define CAN_F11R2_FB21_Pos     (21U)
6040 #define CAN_F11R2_FB21_Msk     (0x1U << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
6041 #define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
6042 #define CAN_F11R2_FB22_Pos     (22U)
6043 #define CAN_F11R2_FB22_Msk     (0x1U << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
6044 #define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
6045 #define CAN_F11R2_FB23_Pos     (23U)
6046 #define CAN_F11R2_FB23_Msk     (0x1U << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
6047 #define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
6048 #define CAN_F11R2_FB24_Pos     (24U)
6049 #define CAN_F11R2_FB24_Msk     (0x1U << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
6050 #define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
6051 #define CAN_F11R2_FB25_Pos     (25U)
6052 #define CAN_F11R2_FB25_Msk     (0x1U << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
6053 #define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
6054 #define CAN_F11R2_FB26_Pos     (26U)
6055 #define CAN_F11R2_FB26_Msk     (0x1U << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
6056 #define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
6057 #define CAN_F11R2_FB27_Pos     (27U)
6058 #define CAN_F11R2_FB27_Msk     (0x1U << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
6059 #define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
6060 #define CAN_F11R2_FB28_Pos     (28U)
6061 #define CAN_F11R2_FB28_Msk     (0x1U << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
6062 #define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
6063 #define CAN_F11R2_FB29_Pos     (29U)
6064 #define CAN_F11R2_FB29_Msk     (0x1U << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
6065 #define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
6066 #define CAN_F11R2_FB30_Pos     (30U)
6067 #define CAN_F11R2_FB30_Msk     (0x1U << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
6068 #define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
6069 #define CAN_F11R2_FB31_Pos     (31U)
6070 #define CAN_F11R2_FB31_Msk     (0x1U << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
6071 #define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
6072 
6073 /*******************  Bit definition for CAN_F12R2 register  ******************/
6074 #define CAN_F12R2_FB0_Pos      (0U)
6075 #define CAN_F12R2_FB0_Msk      (0x1U << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
6076 #define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
6077 #define CAN_F12R2_FB1_Pos      (1U)
6078 #define CAN_F12R2_FB1_Msk      (0x1U << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
6079 #define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
6080 #define CAN_F12R2_FB2_Pos      (2U)
6081 #define CAN_F12R2_FB2_Msk      (0x1U << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
6082 #define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
6083 #define CAN_F12R2_FB3_Pos      (3U)
6084 #define CAN_F12R2_FB3_Msk      (0x1U << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
6085 #define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
6086 #define CAN_F12R2_FB4_Pos      (4U)
6087 #define CAN_F12R2_FB4_Msk      (0x1U << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
6088 #define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
6089 #define CAN_F12R2_FB5_Pos      (5U)
6090 #define CAN_F12R2_FB5_Msk      (0x1U << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
6091 #define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
6092 #define CAN_F12R2_FB6_Pos      (6U)
6093 #define CAN_F12R2_FB6_Msk      (0x1U << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
6094 #define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
6095 #define CAN_F12R2_FB7_Pos      (7U)
6096 #define CAN_F12R2_FB7_Msk      (0x1U << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
6097 #define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
6098 #define CAN_F12R2_FB8_Pos      (8U)
6099 #define CAN_F12R2_FB8_Msk      (0x1U << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
6100 #define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
6101 #define CAN_F12R2_FB9_Pos      (9U)
6102 #define CAN_F12R2_FB9_Msk      (0x1U << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
6103 #define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
6104 #define CAN_F12R2_FB10_Pos     (10U)
6105 #define CAN_F12R2_FB10_Msk     (0x1U << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
6106 #define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
6107 #define CAN_F12R2_FB11_Pos     (11U)
6108 #define CAN_F12R2_FB11_Msk     (0x1U << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
6109 #define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
6110 #define CAN_F12R2_FB12_Pos     (12U)
6111 #define CAN_F12R2_FB12_Msk     (0x1U << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
6112 #define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
6113 #define CAN_F12R2_FB13_Pos     (13U)
6114 #define CAN_F12R2_FB13_Msk     (0x1U << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
6115 #define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
6116 #define CAN_F12R2_FB14_Pos     (14U)
6117 #define CAN_F12R2_FB14_Msk     (0x1U << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
6118 #define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
6119 #define CAN_F12R2_FB15_Pos     (15U)
6120 #define CAN_F12R2_FB15_Msk     (0x1U << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
6121 #define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
6122 #define CAN_F12R2_FB16_Pos     (16U)
6123 #define CAN_F12R2_FB16_Msk     (0x1U << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
6124 #define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
6125 #define CAN_F12R2_FB17_Pos     (17U)
6126 #define CAN_F12R2_FB17_Msk     (0x1U << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
6127 #define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
6128 #define CAN_F12R2_FB18_Pos     (18U)
6129 #define CAN_F12R2_FB18_Msk     (0x1U << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
6130 #define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
6131 #define CAN_F12R2_FB19_Pos     (19U)
6132 #define CAN_F12R2_FB19_Msk     (0x1U << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
6133 #define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
6134 #define CAN_F12R2_FB20_Pos     (20U)
6135 #define CAN_F12R2_FB20_Msk     (0x1U << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
6136 #define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
6137 #define CAN_F12R2_FB21_Pos     (21U)
6138 #define CAN_F12R2_FB21_Msk     (0x1U << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
6139 #define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
6140 #define CAN_F12R2_FB22_Pos     (22U)
6141 #define CAN_F12R2_FB22_Msk     (0x1U << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
6142 #define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
6143 #define CAN_F12R2_FB23_Pos     (23U)
6144 #define CAN_F12R2_FB23_Msk     (0x1U << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
6145 #define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
6146 #define CAN_F12R2_FB24_Pos     (24U)
6147 #define CAN_F12R2_FB24_Msk     (0x1U << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
6148 #define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
6149 #define CAN_F12R2_FB25_Pos     (25U)
6150 #define CAN_F12R2_FB25_Msk     (0x1U << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
6151 #define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
6152 #define CAN_F12R2_FB26_Pos     (26U)
6153 #define CAN_F12R2_FB26_Msk     (0x1U << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
6154 #define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
6155 #define CAN_F12R2_FB27_Pos     (27U)
6156 #define CAN_F12R2_FB27_Msk     (0x1U << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
6157 #define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
6158 #define CAN_F12R2_FB28_Pos     (28U)
6159 #define CAN_F12R2_FB28_Msk     (0x1U << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
6160 #define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
6161 #define CAN_F12R2_FB29_Pos     (29U)
6162 #define CAN_F12R2_FB29_Msk     (0x1U << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
6163 #define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
6164 #define CAN_F12R2_FB30_Pos     (30U)
6165 #define CAN_F12R2_FB30_Msk     (0x1U << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
6166 #define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
6167 #define CAN_F12R2_FB31_Pos     (31U)
6168 #define CAN_F12R2_FB31_Msk     (0x1U << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
6169 #define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
6170 
6171 /*******************  Bit definition for CAN_F13R2 register  ******************/
6172 #define CAN_F13R2_FB0_Pos      (0U)
6173 #define CAN_F13R2_FB0_Msk      (0x1U << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
6174 #define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
6175 #define CAN_F13R2_FB1_Pos      (1U)
6176 #define CAN_F13R2_FB1_Msk      (0x1U << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
6177 #define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
6178 #define CAN_F13R2_FB2_Pos      (2U)
6179 #define CAN_F13R2_FB2_Msk      (0x1U << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
6180 #define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
6181 #define CAN_F13R2_FB3_Pos      (3U)
6182 #define CAN_F13R2_FB3_Msk      (0x1U << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
6183 #define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
6184 #define CAN_F13R2_FB4_Pos      (4U)
6185 #define CAN_F13R2_FB4_Msk      (0x1U << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
6186 #define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
6187 #define CAN_F13R2_FB5_Pos      (5U)
6188 #define CAN_F13R2_FB5_Msk      (0x1U << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
6189 #define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
6190 #define CAN_F13R2_FB6_Pos      (6U)
6191 #define CAN_F13R2_FB6_Msk      (0x1U << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
6192 #define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
6193 #define CAN_F13R2_FB7_Pos      (7U)
6194 #define CAN_F13R2_FB7_Msk      (0x1U << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
6195 #define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
6196 #define CAN_F13R2_FB8_Pos      (8U)
6197 #define CAN_F13R2_FB8_Msk      (0x1U << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
6198 #define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
6199 #define CAN_F13R2_FB9_Pos      (9U)
6200 #define CAN_F13R2_FB9_Msk      (0x1U << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
6201 #define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
6202 #define CAN_F13R2_FB10_Pos     (10U)
6203 #define CAN_F13R2_FB10_Msk     (0x1U << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
6204 #define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
6205 #define CAN_F13R2_FB11_Pos     (11U)
6206 #define CAN_F13R2_FB11_Msk     (0x1U << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
6207 #define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
6208 #define CAN_F13R2_FB12_Pos     (12U)
6209 #define CAN_F13R2_FB12_Msk     (0x1U << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
6210 #define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
6211 #define CAN_F13R2_FB13_Pos     (13U)
6212 #define CAN_F13R2_FB13_Msk     (0x1U << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
6213 #define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
6214 #define CAN_F13R2_FB14_Pos     (14U)
6215 #define CAN_F13R2_FB14_Msk     (0x1U << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
6216 #define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
6217 #define CAN_F13R2_FB15_Pos     (15U)
6218 #define CAN_F13R2_FB15_Msk     (0x1U << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
6219 #define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
6220 #define CAN_F13R2_FB16_Pos     (16U)
6221 #define CAN_F13R2_FB16_Msk     (0x1U << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
6222 #define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
6223 #define CAN_F13R2_FB17_Pos     (17U)
6224 #define CAN_F13R2_FB17_Msk     (0x1U << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
6225 #define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
6226 #define CAN_F13R2_FB18_Pos     (18U)
6227 #define CAN_F13R2_FB18_Msk     (0x1U << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
6228 #define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
6229 #define CAN_F13R2_FB19_Pos     (19U)
6230 #define CAN_F13R2_FB19_Msk     (0x1U << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
6231 #define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
6232 #define CAN_F13R2_FB20_Pos     (20U)
6233 #define CAN_F13R2_FB20_Msk     (0x1U << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
6234 #define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
6235 #define CAN_F13R2_FB21_Pos     (21U)
6236 #define CAN_F13R2_FB21_Msk     (0x1U << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
6237 #define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
6238 #define CAN_F13R2_FB22_Pos     (22U)
6239 #define CAN_F13R2_FB22_Msk     (0x1U << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
6240 #define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
6241 #define CAN_F13R2_FB23_Pos     (23U)
6242 #define CAN_F13R2_FB23_Msk     (0x1U << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
6243 #define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
6244 #define CAN_F13R2_FB24_Pos     (24U)
6245 #define CAN_F13R2_FB24_Msk     (0x1U << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
6246 #define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
6247 #define CAN_F13R2_FB25_Pos     (25U)
6248 #define CAN_F13R2_FB25_Msk     (0x1U << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
6249 #define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
6250 #define CAN_F13R2_FB26_Pos     (26U)
6251 #define CAN_F13R2_FB26_Msk     (0x1U << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
6252 #define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
6253 #define CAN_F13R2_FB27_Pos     (27U)
6254 #define CAN_F13R2_FB27_Msk     (0x1U << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
6255 #define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
6256 #define CAN_F13R2_FB28_Pos     (28U)
6257 #define CAN_F13R2_FB28_Msk     (0x1U << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
6258 #define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
6259 #define CAN_F13R2_FB29_Pos     (29U)
6260 #define CAN_F13R2_FB29_Msk     (0x1U << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
6261 #define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
6262 #define CAN_F13R2_FB30_Pos     (30U)
6263 #define CAN_F13R2_FB30_Msk     (0x1U << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
6264 #define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
6265 #define CAN_F13R2_FB31_Pos     (31U)
6266 #define CAN_F13R2_FB31_Msk     (0x1U << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
6267 #define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
6268 
6269 /******************************************************************************/
6270 /*                                                                            */
6271 /*                          CRC calculation unit                              */
6272 /*                                                                            */
6273 /******************************************************************************/
6274 /*******************  Bit definition for CRC_DR register  *********************/
6275 #define CRC_DR_DR_Pos            (0U)
6276 #define CRC_DR_DR_Msk            (0xFFFFFFFFU << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
6277 #define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
6278 
6279 /*******************  Bit definition for CRC_IDR register  ********************/
6280 #define CRC_IDR_IDR_Pos          (0U)
6281 #define CRC_IDR_IDR_Msk          (0xFFU << CRC_IDR_IDR_Pos)                    /*!< 0x000000FF */
6282 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bit data register bits */
6283 
6284 /********************  Bit definition for CRC_CR register  ********************/
6285 #define CRC_CR_RESET_Pos         (0U)
6286 #define CRC_CR_RESET_Msk         (0x1U << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
6287 #define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
6288 #define CRC_CR_POLYSIZE_Pos      (3U)
6289 #define CRC_CR_POLYSIZE_Msk      (0x3U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
6290 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
6291 #define CRC_CR_POLYSIZE_0        (0x1U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
6292 #define CRC_CR_POLYSIZE_1        (0x2U << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
6293 #define CRC_CR_REV_IN_Pos        (5U)
6294 #define CRC_CR_REV_IN_Msk        (0x3U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
6295 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
6296 #define CRC_CR_REV_IN_0          (0x1U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
6297 #define CRC_CR_REV_IN_1          (0x2U << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
6298 #define CRC_CR_REV_OUT_Pos       (7U)
6299 #define CRC_CR_REV_OUT_Msk       (0x1U << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
6300 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
6301 
6302 /*******************  Bit definition for CRC_INIT register  *******************/
6303 #define CRC_INIT_INIT_Pos        (0U)
6304 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFU << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
6305 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
6306 
6307 /*******************  Bit definition for CRC_POL register  ********************/
6308 #define CRC_POL_POL_Pos          (0U)
6309 #define CRC_POL_POL_Msk          (0xFFFFFFFFU << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
6310 #define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
6311 
6312 /******************************************************************************/
6313 /*                                                                            */
6314 /*                          CRS Clock Recovery System                         */
6315 /******************************************************************************/
6316 
6317 /*******************  Bit definition for CRS_CR register  *********************/
6318 #define CRS_CR_SYNCOKIE_Pos       (0U)
6319 #define CRS_CR_SYNCOKIE_Msk       (0x1U << CRS_CR_SYNCOKIE_Pos)                /*!< 0x00000001 */
6320 #define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
6321 #define CRS_CR_SYNCWARNIE_Pos     (1U)
6322 #define CRS_CR_SYNCWARNIE_Msk     (0x1U << CRS_CR_SYNCWARNIE_Pos)              /*!< 0x00000002 */
6323 #define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
6324 #define CRS_CR_ERRIE_Pos          (2U)
6325 #define CRS_CR_ERRIE_Msk          (0x1U << CRS_CR_ERRIE_Pos)                   /*!< 0x00000004 */
6326 #define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
6327 #define CRS_CR_ESYNCIE_Pos        (3U)
6328 #define CRS_CR_ESYNCIE_Msk        (0x1U << CRS_CR_ESYNCIE_Pos)                 /*!< 0x00000008 */
6329 #define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
6330 #define CRS_CR_CEN_Pos            (5U)
6331 #define CRS_CR_CEN_Msk            (0x1U << CRS_CR_CEN_Pos)                     /*!< 0x00000020 */
6332 #define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
6333 #define CRS_CR_AUTOTRIMEN_Pos     (6U)
6334 #define CRS_CR_AUTOTRIMEN_Msk     (0x1U << CRS_CR_AUTOTRIMEN_Pos)              /*!< 0x00000040 */
6335 #define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
6336 #define CRS_CR_SWSYNC_Pos         (7U)
6337 #define CRS_CR_SWSYNC_Msk         (0x1U << CRS_CR_SWSYNC_Pos)                  /*!< 0x00000080 */
6338 #define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
6339 #define CRS_CR_TRIM_Pos           (8U)
6340 #define CRS_CR_TRIM_Msk           (0x3FU << CRS_CR_TRIM_Pos)                   /*!< 0x00003F00 */
6341 #define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
6342 
6343 /*******************  Bit definition for CRS_CFGR register  *********************/
6344 #define CRS_CFGR_RELOAD_Pos       (0U)
6345 #define CRS_CFGR_RELOAD_Msk       (0xFFFFU << CRS_CFGR_RELOAD_Pos)             /*!< 0x0000FFFF */
6346 #define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
6347 #define CRS_CFGR_FELIM_Pos        (16U)
6348 #define CRS_CFGR_FELIM_Msk        (0xFFU << CRS_CFGR_FELIM_Pos)                /*!< 0x00FF0000 */
6349 #define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
6350 
6351 #define CRS_CFGR_SYNCDIV_Pos      (24U)
6352 #define CRS_CFGR_SYNCDIV_Msk      (0x7U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x07000000 */
6353 #define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
6354 #define CRS_CFGR_SYNCDIV_0        (0x1U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
6355 #define CRS_CFGR_SYNCDIV_1        (0x2U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
6356 #define CRS_CFGR_SYNCDIV_2        (0x4U << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
6357 
6358 #define CRS_CFGR_SYNCSRC_Pos      (28U)
6359 #define CRS_CFGR_SYNCSRC_Msk      (0x3U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x30000000 */
6360 #define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
6361 #define CRS_CFGR_SYNCSRC_0        (0x1U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
6362 #define CRS_CFGR_SYNCSRC_1        (0x2U << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
6363 
6364 #define CRS_CFGR_SYNCPOL_Pos      (31U)
6365 #define CRS_CFGR_SYNCPOL_Msk      (0x1U << CRS_CFGR_SYNCPOL_Pos)               /*!< 0x80000000 */
6366 #define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
6367 
6368 /*******************  Bit definition for CRS_ISR register  *********************/
6369 #define CRS_ISR_SYNCOKF_Pos       (0U)
6370 #define CRS_ISR_SYNCOKF_Msk       (0x1U << CRS_ISR_SYNCOKF_Pos)                /*!< 0x00000001 */
6371 #define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
6372 #define CRS_ISR_SYNCWARNF_Pos     (1U)
6373 #define CRS_ISR_SYNCWARNF_Msk     (0x1U << CRS_ISR_SYNCWARNF_Pos)              /*!< 0x00000002 */
6374 #define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
6375 #define CRS_ISR_ERRF_Pos          (2U)
6376 #define CRS_ISR_ERRF_Msk          (0x1U << CRS_ISR_ERRF_Pos)                   /*!< 0x00000004 */
6377 #define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
6378 #define CRS_ISR_ESYNCF_Pos        (3U)
6379 #define CRS_ISR_ESYNCF_Msk        (0x1U << CRS_ISR_ESYNCF_Pos)                 /*!< 0x00000008 */
6380 #define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
6381 #define CRS_ISR_SYNCERR_Pos       (8U)
6382 #define CRS_ISR_SYNCERR_Msk       (0x1U << CRS_ISR_SYNCERR_Pos)                /*!< 0x00000100 */
6383 #define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
6384 #define CRS_ISR_SYNCMISS_Pos      (9U)
6385 #define CRS_ISR_SYNCMISS_Msk      (0x1U << CRS_ISR_SYNCMISS_Pos)               /*!< 0x00000200 */
6386 #define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
6387 #define CRS_ISR_TRIMOVF_Pos       (10U)
6388 #define CRS_ISR_TRIMOVF_Msk       (0x1U << CRS_ISR_TRIMOVF_Pos)                /*!< 0x00000400 */
6389 #define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
6390 #define CRS_ISR_FEDIR_Pos         (15U)
6391 #define CRS_ISR_FEDIR_Msk         (0x1U << CRS_ISR_FEDIR_Pos)                  /*!< 0x00008000 */
6392 #define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
6393 #define CRS_ISR_FECAP_Pos         (16U)
6394 #define CRS_ISR_FECAP_Msk         (0xFFFFU << CRS_ISR_FECAP_Pos)               /*!< 0xFFFF0000 */
6395 #define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
6396 
6397 /*******************  Bit definition for CRS_ICR register  *********************/
6398 #define CRS_ICR_SYNCOKC_Pos       (0U)
6399 #define CRS_ICR_SYNCOKC_Msk       (0x1U << CRS_ICR_SYNCOKC_Pos)                /*!< 0x00000001 */
6400 #define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
6401 #define CRS_ICR_SYNCWARNC_Pos     (1U)
6402 #define CRS_ICR_SYNCWARNC_Msk     (0x1U << CRS_ICR_SYNCWARNC_Pos)              /*!< 0x00000002 */
6403 #define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
6404 #define CRS_ICR_ERRC_Pos          (2U)
6405 #define CRS_ICR_ERRC_Msk          (0x1U << CRS_ICR_ERRC_Pos)                   /*!< 0x00000004 */
6406 #define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
6407 #define CRS_ICR_ESYNCC_Pos        (3U)
6408 #define CRS_ICR_ESYNCC_Msk        (0x1U << CRS_ICR_ESYNCC_Pos)                 /*!< 0x00000008 */
6409 #define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
6410 
6411 /******************************************************************************/
6412 /*                                                                            */
6413 /*                       Advanced Encryption Standard (AES)                   */
6414 /*                                                                            */
6415 /******************************************************************************/
6416 /*******************  Bit definition for AES_CR register  *********************/
6417 #define AES_CR_EN_Pos            (0U)
6418 #define AES_CR_EN_Msk            (0x1U << AES_CR_EN_Pos)                       /*!< 0x00000001 */
6419 #define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
6420 #define AES_CR_DATATYPE_Pos      (1U)
6421 #define AES_CR_DATATYPE_Msk      (0x3U << AES_CR_DATATYPE_Pos)                 /*!< 0x00000006 */
6422 #define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
6423 #define AES_CR_DATATYPE_0        (0x1U << AES_CR_DATATYPE_Pos)                 /*!< 0x00000002 */
6424 #define AES_CR_DATATYPE_1        (0x2U << AES_CR_DATATYPE_Pos)                 /*!< 0x00000004 */
6425 
6426 #define AES_CR_MODE_Pos          (3U)
6427 #define AES_CR_MODE_Msk          (0x3U << AES_CR_MODE_Pos)                     /*!< 0x00000018 */
6428 #define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
6429 #define AES_CR_MODE_0            (0x1U << AES_CR_MODE_Pos)                     /*!< 0x00000008 */
6430 #define AES_CR_MODE_1            (0x2U << AES_CR_MODE_Pos)                     /*!< 0x00000010 */
6431 
6432 #define AES_CR_CHMOD_Pos         (5U)
6433 #define AES_CR_CHMOD_Msk         (0x803U << AES_CR_CHMOD_Pos)                  /*!< 0x00010060 */
6434 #define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
6435 #define AES_CR_CHMOD_0           (0x001U << AES_CR_CHMOD_Pos)                  /*!< 0x00000020 */
6436 #define AES_CR_CHMOD_1           (0x002U << AES_CR_CHMOD_Pos)                  /*!< 0x00000040 */
6437 #define AES_CR_CHMOD_2           (0x800U << AES_CR_CHMOD_Pos)                  /*!< 0x00010000 */
6438 
6439 #define AES_CR_CCFC_Pos          (7U)
6440 #define AES_CR_CCFC_Msk          (0x1U << AES_CR_CCFC_Pos)                     /*!< 0x00000080 */
6441 #define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
6442 #define AES_CR_ERRC_Pos          (8U)
6443 #define AES_CR_ERRC_Msk          (0x1U << AES_CR_ERRC_Pos)                     /*!< 0x00000100 */
6444 #define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
6445 #define AES_CR_CCFIE_Pos         (9U)
6446 #define AES_CR_CCFIE_Msk         (0x1U << AES_CR_CCFIE_Pos)                    /*!< 0x00000200 */
6447 #define AES_CR_CCFIE             AES_CR_CCFIE_Msk                              /*!< Computation Complete Flag Interrupt Enable */
6448 #define AES_CR_ERRIE_Pos         (10U)
6449 #define AES_CR_ERRIE_Msk         (0x1U << AES_CR_ERRIE_Pos)                    /*!< 0x00000400 */
6450 #define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
6451 #define AES_CR_DMAINEN_Pos       (11U)
6452 #define AES_CR_DMAINEN_Msk       (0x1U << AES_CR_DMAINEN_Pos)                  /*!< 0x00000800 */
6453 #define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< Enable data input phase DMA management  */
6454 #define AES_CR_DMAOUTEN_Pos      (12U)
6455 #define AES_CR_DMAOUTEN_Msk      (0x1U << AES_CR_DMAOUTEN_Pos)                 /*!< 0x00001000 */
6456 #define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< Enable data output phase DMA management */
6457 
6458 #define AES_CR_GCMPH_Pos         (13U)
6459 #define AES_CR_GCMPH_Msk         (0x3U << AES_CR_GCMPH_Pos)                    /*!< 0x00006000 */
6460 #define AES_CR_GCMPH             AES_CR_GCMPH_Msk                              /*!< GCM Phase */
6461 #define AES_CR_GCMPH_0           (0x1U << AES_CR_GCMPH_Pos)                    /*!< 0x00002000 */
6462 #define AES_CR_GCMPH_1           (0x2U << AES_CR_GCMPH_Pos)                    /*!< 0x00004000 */
6463 
6464 #define AES_CR_KEYSIZE_Pos       (18U)
6465 #define AES_CR_KEYSIZE_Msk       (0x1U << AES_CR_KEYSIZE_Pos)                  /*!< 0x00040000 */
6466 #define AES_CR_KEYSIZE           AES_CR_KEYSIZE_Msk                            /*!< Key size selection */
6467 
6468 /*******************  Bit definition for AES_SR register  *********************/
6469 #define AES_SR_CCF_Pos           (0U)
6470 #define AES_SR_CCF_Msk           (0x1U << AES_SR_CCF_Pos)                      /*!< 0x00000001 */
6471 #define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
6472 #define AES_SR_RDERR_Pos         (1U)
6473 #define AES_SR_RDERR_Msk         (0x1U << AES_SR_RDERR_Pos)                    /*!< 0x00000002 */
6474 #define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
6475 #define AES_SR_WRERR_Pos         (2U)
6476 #define AES_SR_WRERR_Msk         (0x1U << AES_SR_WRERR_Pos)                    /*!< 0x00000004 */
6477 #define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
6478 #define AES_SR_BUSY_Pos          (3U)
6479 #define AES_SR_BUSY_Msk          (0x1U << AES_SR_BUSY_Pos)                     /*!< 0x00000008 */
6480 #define AES_SR_BUSY              AES_SR_BUSY_Msk                               /*!< Busy Flag */
6481 
6482 /*******************  Bit definition for AES_DINR register  *******************/
6483 #define AES_DINR_Pos             (0U)
6484 #define AES_DINR_Msk             (0xFFFFFFFFU << AES_DINR_Pos)                 /*!< 0xFFFFFFFF */
6485 #define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
6486 
6487 /*******************  Bit definition for AES_DOUTR register  ******************/
6488 #define AES_DOUTR_Pos            (0U)
6489 #define AES_DOUTR_Msk            (0xFFFFFFFFU << AES_DOUTR_Pos)                /*!< 0xFFFFFFFF */
6490 #define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
6491 
6492 /*******************  Bit definition for AES_KEYR0 register  ******************/
6493 #define AES_KEYR0_Pos            (0U)
6494 #define AES_KEYR0_Msk            (0xFFFFFFFFU << AES_KEYR0_Pos)                /*!< 0xFFFFFFFF */
6495 #define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
6496 
6497 /*******************  Bit definition for AES_KEYR1 register  ******************/
6498 #define AES_KEYR1_Pos            (0U)
6499 #define AES_KEYR1_Msk            (0xFFFFFFFFU << AES_KEYR1_Pos)                /*!< 0xFFFFFFFF */
6500 #define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
6501 
6502 /*******************  Bit definition for AES_KEYR2 register  ******************/
6503 #define AES_KEYR2_Pos            (0U)
6504 #define AES_KEYR2_Msk            (0xFFFFFFFFU << AES_KEYR2_Pos)                /*!< 0xFFFFFFFF */
6505 #define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
6506 
6507 /*******************  Bit definition for AES_KEYR3 register  ******************/
6508 #define AES_KEYR3_Pos            (0U)
6509 #define AES_KEYR3_Msk            (0xFFFFFFFFU << AES_KEYR3_Pos)                /*!< 0xFFFFFFFF */
6510 #define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
6511 
6512 /*******************  Bit definition for AES_KEYR4 register  ******************/
6513 #define AES_KEYR4_Pos            (0U)
6514 #define AES_KEYR4_Msk            (0xFFFFFFFFU << AES_KEYR4_Pos)                /*!< 0xFFFFFFFF */
6515 #define AES_KEYR4                AES_KEYR4_Msk                                 /*!< AES Key Register 4 */
6516 
6517 /*******************  Bit definition for AES_KEYR5 register  ******************/
6518 #define AES_KEYR5_Pos            (0U)
6519 #define AES_KEYR5_Msk            (0xFFFFFFFFU << AES_KEYR5_Pos)                /*!< 0xFFFFFFFF */
6520 #define AES_KEYR5                AES_KEYR5_Msk                                 /*!< AES Key Register 5 */
6521 
6522 /*******************  Bit definition for AES_KEYR6 register  ******************/
6523 #define AES_KEYR6_Pos            (0U)
6524 #define AES_KEYR6_Msk            (0xFFFFFFFFU << AES_KEYR6_Pos)                /*!< 0xFFFFFFFF */
6525 #define AES_KEYR6                AES_KEYR6_Msk                                 /*!< AES Key Register 6 */
6526 
6527 /*******************  Bit definition for AES_KEYR7 register  ******************/
6528 #define AES_KEYR7_Pos            (0U)
6529 #define AES_KEYR7_Msk            (0xFFFFFFFFU << AES_KEYR7_Pos)                /*!< 0xFFFFFFFF */
6530 #define AES_KEYR7                AES_KEYR7_Msk                                 /*!< AES Key Register 7 */
6531 
6532 /*******************  Bit definition for AES_IVR0 register   ******************/
6533 #define AES_IVR0_Pos             (0U)
6534 #define AES_IVR0_Msk             (0xFFFFFFFFU << AES_IVR0_Pos)                 /*!< 0xFFFFFFFF */
6535 #define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
6536 
6537 /*******************  Bit definition for AES_IVR1 register   ******************/
6538 #define AES_IVR1_Pos             (0U)
6539 #define AES_IVR1_Msk             (0xFFFFFFFFU << AES_IVR1_Pos)                 /*!< 0xFFFFFFFF */
6540 #define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
6541 
6542 /*******************  Bit definition for AES_IVR2 register   ******************/
6543 #define AES_IVR2_Pos             (0U)
6544 #define AES_IVR2_Msk             (0xFFFFFFFFU << AES_IVR2_Pos)                 /*!< 0xFFFFFFFF */
6545 #define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
6546 
6547 /*******************  Bit definition for AES_IVR3 register   ******************/
6548 #define AES_IVR3_Pos             (0U)
6549 #define AES_IVR3_Msk             (0xFFFFFFFFU << AES_IVR3_Pos)                 /*!< 0xFFFFFFFF */
6550 #define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
6551 
6552 /*******************  Bit definition for AES_SUSP0R register  ******************/
6553 #define AES_SUSP0R_Pos           (0U)
6554 #define AES_SUSP0R_Msk           (0xFFFFFFFFU << AES_SUSP0R_Pos)               /*!< 0xFFFFFFFF */
6555 #define AES_SUSP0R               AES_SUSP0R_Msk                                /*!< AES Suspend registers 0 */
6556 
6557 /*******************  Bit definition for AES_SUSP1R register  ******************/
6558 #define AES_SUSP1R_Pos           (0U)
6559 #define AES_SUSP1R_Msk           (0xFFFFFFFFU << AES_SUSP1R_Pos)               /*!< 0xFFFFFFFF */
6560 #define AES_SUSP1R               AES_SUSP1R_Msk                                /*!< AES Suspend registers 1 */
6561 
6562 /*******************  Bit definition for AES_SUSP2R register  ******************/
6563 #define AES_SUSP2R_Pos           (0U)
6564 #define AES_SUSP2R_Msk           (0xFFFFFFFFU << AES_SUSP2R_Pos)               /*!< 0xFFFFFFFF */
6565 #define AES_SUSP2R               AES_SUSP2R_Msk                                /*!< AES Suspend registers 2 */
6566 
6567 /*******************  Bit definition for AES_SUSP3R register  ******************/
6568 #define AES_SUSP3R_Pos           (0U)
6569 #define AES_SUSP3R_Msk           (0xFFFFFFFFU << AES_SUSP3R_Pos)               /*!< 0xFFFFFFFF */
6570 #define AES_SUSP3R               AES_SUSP3R_Msk                                /*!< AES Suspend registers 3 */
6571 
6572 /*******************  Bit definition for AES_SUSP4R register  ******************/
6573 #define AES_SUSP4R_Pos           (0U)
6574 #define AES_SUSP4R_Msk           (0xFFFFFFFFU << AES_SUSP4R_Pos)               /*!< 0xFFFFFFFF */
6575 #define AES_SUSP4R               AES_SUSP4R_Msk                                /*!< AES Suspend registers 4 */
6576 
6577 /*******************  Bit definition for AES_SUSP5R register  ******************/
6578 #define AES_SUSP5R_Pos           (0U)
6579 #define AES_SUSP5R_Msk           (0xFFFFFFFFU << AES_SUSP5R_Pos)               /*!< 0xFFFFFFFF */
6580 #define AES_SUSP5R               AES_SUSP5R_Msk                                /*!< AES Suspend registers 5 */
6581 
6582 /*******************  Bit definition for AES_SUSP6R register  ******************/
6583 #define AES_SUSP6R_Pos           (0U)
6584 #define AES_SUSP6R_Msk           (0xFFFFFFFFU << AES_SUSP6R_Pos)               /*!< 0xFFFFFFFF */
6585 #define AES_SUSP6R               AES_SUSP6R_Msk                                /*!< AES Suspend registers 6 */
6586 
6587 /*******************  Bit definition for AES_SUSP7R register  ******************/
6588 #define AES_SUSP7R_Pos           (0U)
6589 #define AES_SUSP7R_Msk           (0xFFFFFFFFU << AES_SUSP7R_Pos)               /*!< 0xFFFFFFFF */
6590 #define AES_SUSP7R               AES_SUSP7R_Msk                                /*!< AES Suspend registers 7 */
6591 
6592 /******************************************************************************/
6593 /*                                                                            */
6594 /*                      Digital to Analog Converter                           */
6595 /*                                                                            */
6596 /******************************************************************************/
6597 /*
6598  * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
6599  */
6600 #define DAC_CHANNEL2_SUPPORT                           /*!< DAC feature available only on specific devices: DAC channel 2 available */
6601 
6602 /********************  Bit definition for DAC_CR register  ********************/
6603 #define DAC_CR_EN1_Pos              (0U)
6604 #define DAC_CR_EN1_Msk              (0x1U << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
6605 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
6606 #define DAC_CR_TEN1_Pos             (2U)
6607 #define DAC_CR_TEN1_Msk             (0x1U << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
6608 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
6609 
6610 #define DAC_CR_TSEL1_Pos            (3U)
6611 #define DAC_CR_TSEL1_Msk            (0x7U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
6612 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
6613 #define DAC_CR_TSEL1_0              (0x1U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
6614 #define DAC_CR_TSEL1_1              (0x2U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
6615 #define DAC_CR_TSEL1_2              (0x4U << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
6616 
6617 #define DAC_CR_WAVE1_Pos            (6U)
6618 #define DAC_CR_WAVE1_Msk            (0x3U << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
6619 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
6620 #define DAC_CR_WAVE1_0              (0x1U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
6621 #define DAC_CR_WAVE1_1              (0x2U << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
6622 
6623 #define DAC_CR_MAMP1_Pos            (8U)
6624 #define DAC_CR_MAMP1_Msk            (0xFU << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
6625 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
6626 #define DAC_CR_MAMP1_0              (0x1U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
6627 #define DAC_CR_MAMP1_1              (0x2U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
6628 #define DAC_CR_MAMP1_2              (0x4U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
6629 #define DAC_CR_MAMP1_3              (0x8U << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
6630 
6631 #define DAC_CR_DMAEN1_Pos           (12U)
6632 #define DAC_CR_DMAEN1_Msk           (0x1U << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
6633 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
6634 #define DAC_CR_DMAUDRIE1_Pos        (13U)
6635 #define DAC_CR_DMAUDRIE1_Msk        (0x1U << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
6636 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
6637 #define DAC_CR_CEN1_Pos             (14U)
6638 #define DAC_CR_CEN1_Msk             (0x1U << DAC_CR_CEN1_Pos)                  /*!< 0x00004000 */
6639 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
6640 
6641 #define DAC_CR_EN2_Pos              (16U)
6642 #define DAC_CR_EN2_Msk              (0x1U << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
6643 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
6644 #define DAC_CR_TEN2_Pos             (18U)
6645 #define DAC_CR_TEN2_Msk             (0x1U << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
6646 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
6647 
6648 #define DAC_CR_TSEL2_Pos            (19U)
6649 #define DAC_CR_TSEL2_Msk            (0x7U << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
6650 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
6651 #define DAC_CR_TSEL2_0              (0x1U << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
6652 #define DAC_CR_TSEL2_1              (0x2U << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
6653 #define DAC_CR_TSEL2_2              (0x4U << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
6654 
6655 #define DAC_CR_WAVE2_Pos            (22U)
6656 #define DAC_CR_WAVE2_Msk            (0x3U << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
6657 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
6658 #define DAC_CR_WAVE2_0              (0x1U << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
6659 #define DAC_CR_WAVE2_1              (0x2U << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
6660 
6661 #define DAC_CR_MAMP2_Pos            (24U)
6662 #define DAC_CR_MAMP2_Msk            (0xFU << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
6663 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
6664 #define DAC_CR_MAMP2_0              (0x1U << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
6665 #define DAC_CR_MAMP2_1              (0x2U << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
6666 #define DAC_CR_MAMP2_2              (0x4U << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
6667 #define DAC_CR_MAMP2_3              (0x8U << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
6668 
6669 #define DAC_CR_DMAEN2_Pos           (28U)
6670 #define DAC_CR_DMAEN2_Msk           (0x1U << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
6671 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
6672 #define DAC_CR_DMAUDRIE2_Pos        (29U)
6673 #define DAC_CR_DMAUDRIE2_Msk        (0x1U << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
6674 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
6675 #define DAC_CR_CEN2_Pos             (30U)
6676 #define DAC_CR_CEN2_Msk             (0x1U << DAC_CR_CEN2_Pos)                  /*!< 0x40000000 */
6677 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
6678 
6679 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
6680 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
6681 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
6682 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
6683 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
6684 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
6685 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
6686 
6687 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
6688 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
6689 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
6690 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
6691 
6692 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
6693 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
6694 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
6695 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
6696 
6697 /******************  Bit definition for DAC_DHR8R1 register  ******************/
6698 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
6699 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
6700 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
6701 
6702 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
6703 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
6704 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
6705 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
6706 
6707 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
6708 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
6709 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
6710 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
6711 
6712 /******************  Bit definition for DAC_DHR8R2 register  ******************/
6713 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
6714 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
6715 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
6716 
6717 /*****************  Bit definition for DAC_DHR12RD register  ******************/
6718 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
6719 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
6720 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
6721 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
6722 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
6723 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
6724 
6725 /*****************  Bit definition for DAC_DHR12LD register  ******************/
6726 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
6727 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
6728 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
6729 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
6730 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
6731 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
6732 
6733 /******************  Bit definition for DAC_DHR8RD register  ******************/
6734 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
6735 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
6736 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
6737 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
6738 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
6739 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
6740 
6741 /*******************  Bit definition for DAC_DOR1 register  *******************/
6742 #define DAC_DOR1_DACC1DOR_Pos       (0U)
6743 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFU << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
6744 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
6745 
6746 /*******************  Bit definition for DAC_DOR2 register  *******************/
6747 #define DAC_DOR2_DACC2DOR_Pos       (0U)
6748 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFU << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
6749 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
6750 
6751 /********************  Bit definition for DAC_SR register  ********************/
6752 #define DAC_SR_DMAUDR1_Pos          (13U)
6753 #define DAC_SR_DMAUDR1_Msk          (0x1U << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
6754 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
6755 #define DAC_SR_CAL_FLAG1_Pos        (14U)
6756 #define DAC_SR_CAL_FLAG1_Msk        (0x1U << DAC_SR_CAL_FLAG1_Pos)             /*!< 0x00004000 */
6757 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
6758 #define DAC_SR_BWST1_Pos            (15U)
6759 #define DAC_SR_BWST1_Msk            (0x1U << DAC_SR_BWST1_Pos)                 /*!< 0x00008000 */
6760 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
6761 
6762 #define DAC_SR_DMAUDR2_Pos          (29U)
6763 #define DAC_SR_DMAUDR2_Msk          (0x1U << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
6764 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
6765 #define DAC_SR_CAL_FLAG2_Pos        (30U)
6766 #define DAC_SR_CAL_FLAG2_Msk        (0x1U << DAC_SR_CAL_FLAG2_Pos)             /*!< 0x40000000 */
6767 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
6768 #define DAC_SR_BWST2_Pos            (31U)
6769 #define DAC_SR_BWST2_Msk            (0x1U << DAC_SR_BWST2_Pos)                 /*!< 0x80000000 */
6770 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
6771 
6772 /*******************  Bit definition for DAC_CCR register  ********************/
6773 #define DAC_CCR_OTRIM1_Pos          (0U)
6774 #define DAC_CCR_OTRIM1_Msk          (0x1FU << DAC_CCR_OTRIM1_Pos)              /*!< 0x0000001F */
6775 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
6776 #define DAC_CCR_OTRIM2_Pos          (16U)
6777 #define DAC_CCR_OTRIM2_Msk          (0x1FU << DAC_CCR_OTRIM2_Pos)              /*!< 0x001F0000 */
6778 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
6779 
6780 /*******************  Bit definition for DAC_MCR register  *******************/
6781 #define DAC_MCR_MODE1_Pos           (0U)
6782 #define DAC_MCR_MODE1_Msk           (0x7U << DAC_MCR_MODE1_Pos)                /*!< 0x00000007 */
6783 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
6784 #define DAC_MCR_MODE1_0             (0x1U << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
6785 #define DAC_MCR_MODE1_1             (0x2U << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
6786 #define DAC_MCR_MODE1_2             (0x4U << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
6787 
6788 #define DAC_MCR_MODE2_Pos           (16U)
6789 #define DAC_MCR_MODE2_Msk           (0x7U << DAC_MCR_MODE2_Pos)                /*!< 0x00070000 */
6790 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
6791 #define DAC_MCR_MODE2_0             (0x1U << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
6792 #define DAC_MCR_MODE2_1             (0x2U << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
6793 #define DAC_MCR_MODE2_2             (0x4U << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
6794 
6795 /******************  Bit definition for DAC_SHSR1 register  ******************/
6796 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
6797 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFU << DAC_SHSR1_TSAMPLE1_Pos)         /*!< 0x000003FF */
6798 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
6799 
6800 /******************  Bit definition for DAC_SHSR2 register  ******************/
6801 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
6802 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFU << DAC_SHSR2_TSAMPLE2_Pos)         /*!< 0x000003FF */
6803 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
6804 
6805 /******************  Bit definition for DAC_SHHR register  ******************/
6806 #define DAC_SHHR_THOLD1_Pos         (0U)
6807 #define DAC_SHHR_THOLD1_Msk         (0x3FFU << DAC_SHHR_THOLD1_Pos)            /*!< 0x000003FF */
6808 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
6809 #define DAC_SHHR_THOLD2_Pos         (16U)
6810 #define DAC_SHHR_THOLD2_Msk         (0x3FFU << DAC_SHHR_THOLD2_Pos)            /*!< 0x03FF0000 */
6811 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
6812 
6813 /******************  Bit definition for DAC_SHRR register  ******************/
6814 #define DAC_SHRR_TREFRESH1_Pos      (0U)
6815 #define DAC_SHRR_TREFRESH1_Msk      (0xFFU << DAC_SHRR_TREFRESH1_Pos)          /*!< 0x000000FF */
6816 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
6817 #define DAC_SHRR_TREFRESH2_Pos      (16U)
6818 #define DAC_SHRR_TREFRESH2_Msk      (0xFFU << DAC_SHRR_TREFRESH2_Pos)          /*!< 0x00FF0000 */
6819 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
6820 
6821 /******************************************************************************/
6822 /*                                                                            */
6823 /*                                    DCMI                                    */
6824 /*                                                                            */
6825 /******************************************************************************/
6826 /********************  Bits definition for DCMI_CR register  ******************/
6827 #define DCMI_CR_CAPTURE_Pos           (0U)
6828 #define DCMI_CR_CAPTURE_Msk           (0x1U << DCMI_CR_CAPTURE_Pos)            /*!< 0x00000001 */
6829 #define DCMI_CR_CAPTURE               DCMI_CR_CAPTURE_Msk                      /*!< DCMI Capture enable */
6830 #define DCMI_CR_CM_Pos                (1U)
6831 #define DCMI_CR_CM_Msk                (0x1U << DCMI_CR_CM_Pos)                 /*!< 0x00000002 */
6832 #define DCMI_CR_CM                    DCMI_CR_CM_Msk                           /*!< DCMI Capture mode */
6833 #define DCMI_CR_CROP_Pos              (2U)
6834 #define DCMI_CR_CROP_Msk              (0x1U << DCMI_CR_CROP_Pos)               /*!< 0x00000004 */
6835 #define DCMI_CR_CROP                  DCMI_CR_CROP_Msk                         /*!< DCMI Crop feature */
6836 #define DCMI_CR_JPEG_Pos              (3U)
6837 #define DCMI_CR_JPEG_Msk              (0x1U << DCMI_CR_JPEG_Pos)               /*!< 0x00000008 */
6838 #define DCMI_CR_JPEG                  DCMI_CR_JPEG_Msk                         /*!< DCMI JPEG format */
6839 #define DCMI_CR_ESS_Pos               (4U)
6840 #define DCMI_CR_ESS_Msk               (0x1U << DCMI_CR_ESS_Pos)                /*!< 0x00000010 */
6841 #define DCMI_CR_ESS                   DCMI_CR_ESS_Msk                          /*!< DCMI Embedded synchronization select */
6842 #define DCMI_CR_PCKPOL_Pos            (5U)
6843 #define DCMI_CR_PCKPOL_Msk            (0x1U << DCMI_CR_PCKPOL_Pos)             /*!< 0x00000020 */
6844 #define DCMI_CR_PCKPOL                DCMI_CR_PCKPOL_Msk                       /*!< DCMI Pixel clock polarity */
6845 #define DCMI_CR_HSPOL_Pos             (6U)
6846 #define DCMI_CR_HSPOL_Msk             (0x1U << DCMI_CR_HSPOL_Pos)              /*!< 0x00000040 */
6847 #define DCMI_CR_HSPOL                 DCMI_CR_HSPOL_Msk                        /*!< DCMI Horizontal synchronization polarity */
6848 #define DCMI_CR_VSPOL_Pos             (7U)
6849 #define DCMI_CR_VSPOL_Msk             (0x1U << DCMI_CR_VSPOL_Pos)              /*!< 0x00000080 */
6850 #define DCMI_CR_VSPOL                 DCMI_CR_VSPOL_Msk                        /*!< DCMI Vertical synchronization polarity */
6851 #define DCMI_CR_FCRC_Pos              (8U)
6852 #define DCMI_CR_FCRC_Msk              (0x3U << DCMI_CR_FCRC_Pos)               /*!< 0x00000300 */
6853 #define DCMI_CR_FCRC                  DCMI_CR_FCRC_Msk                         /*!< DCMI Frame capture rate control FCRC[1:0] */
6854 #define DCMI_CR_FCRC_0                (0x1U << DCMI_CR_FCRC_Pos)               /*!< 0x00000100 */
6855 #define DCMI_CR_FCRC_1                (0x2U << DCMI_CR_FCRC_Pos)               /*!< 0x00000200 */
6856 #define DCMI_CR_EDM_Pos               (10U)
6857 #define DCMI_CR_EDM_Msk               (0x3U << DCMI_CR_EDM_Pos)                /*!< 0x00000C00 */
6858 #define DCMI_CR_EDM                   DCMI_CR_EDM_Msk                          /*!< DCMI Extended data mode EDM[1:0] */
6859 #define DCMI_CR_EDM_0                 (0x1U << DCMI_CR_EDM_Pos)                /*!< 0x00000400 */
6860 #define DCMI_CR_EDM_1                 (0x2U << DCMI_CR_EDM_Pos)                /*!< 0x00000800 */
6861 #define DCMI_CR_ENABLE_Pos            (14U)
6862 #define DCMI_CR_ENABLE_Msk            (0x1U << DCMI_CR_ENABLE_Pos)             /*!< 0x00004000 */
6863 #define DCMI_CR_ENABLE                DCMI_CR_ENABLE_Msk                       /*!< DCMI DCMI enable */
6864 #define DCMI_CR_BSM_Pos               (16U)
6865 #define DCMI_CR_BSM_Msk               (0x3U << DCMI_CR_BSM_Pos)                /*!< 0x00030000 */
6866 #define DCMI_CR_BSM                   DCMI_CR_BSM_Msk                          /*!< DCMI Byte Select mode BSM[1:0] */
6867 #define DCMI_CR_BSM_0                 (0x1U << DCMI_CR_BSM_Pos)                /*!< 0x00010000 */
6868 #define DCMI_CR_BSM_1                 (0x2U << DCMI_CR_BSM_Pos)                /*!< 0x00020000 */
6869 #define DCMI_CR_OEBS_Pos              (18U)
6870 #define DCMI_CR_OEBS_Msk              (0x1U << DCMI_CR_OEBS_Pos)               /*!< 0x00040000 */
6871 #define DCMI_CR_OEBS                  DCMI_CR_OEBS_Msk                         /*!< DCMI Odd/Even Byte Select (Byte Select Start) */
6872 #define DCMI_CR_LSM_Pos               (19U)
6873 #define DCMI_CR_LSM_Msk               (0x1U << DCMI_CR_LSM_Pos)                /*!< 0x00080000 */
6874 #define DCMI_CR_LSM                   DCMI_CR_LSM_Msk                          /*!< DCMI Line Select mode */
6875 #define DCMI_CR_OELS_Pos              (20U)
6876 #define DCMI_CR_OELS_Msk              (0x1U << DCMI_CR_OELS_Pos)               /*!< 0x00100000 */
6877 #define DCMI_CR_OELS                  DCMI_CR_OELS_Msk                         /*!< DCMI Odd/Even Line Select (Line Select Start) */
6878 
6879 /********************  Bits definition for DCMI_SR register  ******************/
6880 #define DCMI_SR_HSYNC_Pos             (0U)
6881 #define DCMI_SR_HSYNC_Msk             (0x1U << DCMI_SR_HSYNC_Pos)              /*!< 0x00000001 */
6882 #define DCMI_SR_HSYNC                 DCMI_SR_HSYNC_Msk
6883 #define DCMI_SR_VSYNC_Pos             (1U)
6884 #define DCMI_SR_VSYNC_Msk             (0x1U << DCMI_SR_VSYNC_Pos)              /*!< 0x00000002 */
6885 #define DCMI_SR_VSYNC                 DCMI_SR_VSYNC_Msk
6886 #define DCMI_SR_FNE_Pos               (2U)
6887 #define DCMI_SR_FNE_Msk               (0x1U << DCMI_SR_FNE_Pos)                /*!< 0x00000004 */
6888 #define DCMI_SR_FNE                   DCMI_SR_FNE_Msk                          /*!< DCMI FIFO not empty */
6889 
6890 /********************  Bits definition for DCMI_RISR register  ****************/
6891 #define DCMI_RIS_FRAME_RIS_Pos        (0U)
6892 #define DCMI_RIS_FRAME_RIS_Msk        (0x1U << DCMI_RIS_FRAME_RIS_Pos)         /*!< 0x00000001 */
6893 #define DCMI_RIS_FRAME_RIS            DCMI_RIS_FRAME_RIS_Msk                   /*!< DCMI Capture complete raw interrupt status */
6894 #define DCMI_RIS_OVR_RIS_Pos          (1U)
6895 #define DCMI_RIS_OVR_RIS_Msk          (0x1U << DCMI_RIS_OVR_RIS_Pos)           /*!< 0x00000002 */
6896 #define DCMI_RIS_OVR_RIS              DCMI_RIS_OVR_RIS_Msk                     /*!< DCMI Overrun raw interrupt status */
6897 #define DCMI_RIS_ERR_RIS_Pos          (2U)
6898 #define DCMI_RIS_ERR_RIS_Msk          (0x1U << DCMI_RIS_ERR_RIS_Pos)           /*!< 0x00000004 */
6899 #define DCMI_RIS_ERR_RIS              DCMI_RIS_ERR_RIS_Msk                     /*!< DCMI Synchronization error raw interrupt status */
6900 #define DCMI_RIS_VSYNC_RIS_Pos        (3U)
6901 #define DCMI_RIS_VSYNC_RIS_Msk        (0x1U << DCMI_RIS_VSYNC_RIS_Pos)         /*!< 0x00000008 */
6902 #define DCMI_RIS_VSYNC_RIS            DCMI_RIS_VSYNC_RIS_Msk                   /*!< DCMI VSYNC raw interrupt status */
6903 #define DCMI_RIS_LINE_RIS_Pos         (4U)
6904 #define DCMI_RIS_LINE_RIS_Msk         (0x1U << DCMI_RIS_LINE_RIS_Pos)          /*!< 0x00000010 */
6905 #define DCMI_RIS_LINE_RIS             DCMI_RIS_LINE_RIS_Msk                    /*!< DCMI Line raw interrupt status */
6906 
6907 /********************  Bits definition for DCMI_IER register  *****************/
6908 #define DCMI_IER_FRAME_IE_Pos         (0U)
6909 #define DCMI_IER_FRAME_IE_Msk         (0x1U << DCMI_IER_FRAME_IE_Pos)          /*!< 0x00000001 */
6910 #define DCMI_IER_FRAME_IE             DCMI_IER_FRAME_IE_Msk                    /*!< DCMI Capture complete interrupt enable */
6911 #define DCMI_IER_OVR_IE_Pos           (1U)
6912 #define DCMI_IER_OVR_IE_Msk           (0x1U << DCMI_IER_OVR_IE_Pos)            /*!< 0x00000002 */
6913 #define DCMI_IER_OVR_IE               DCMI_IER_OVR_IE_Msk                      /*!< DCMI Overrun interrupt enable */
6914 #define DCMI_IER_ERR_IE_Pos           (2U)
6915 #define DCMI_IER_ERR_IE_Msk           (0x1U << DCMI_IER_ERR_IE_Pos)            /*!< 0x00000004 */
6916 #define DCMI_IER_ERR_IE               DCMI_IER_ERR_IE_Msk                      /*!< DCMI Synchronization error interrupt enable */
6917 #define DCMI_IER_VSYNC_IE_Pos         (3U)
6918 #define DCMI_IER_VSYNC_IE_Msk         (0x1U << DCMI_IER_VSYNC_IE_Pos)          /*!< 0x00000008 */
6919 #define DCMI_IER_VSYNC_IE             DCMI_IER_VSYNC_IE_Msk                    /*!< DCMI VSYNC interrupt enable */
6920 #define DCMI_IER_LINE_IE_Pos          (4U)
6921 #define DCMI_IER_LINE_IE_Msk          (0x1U << DCMI_IER_LINE_IE_Pos)           /*!< 0x00000010 */
6922 #define DCMI_IER_LINE_IE              DCMI_IER_LINE_IE_Msk                     /*!< DCMI Line interrupt enable */
6923 #define DCMI_IER_INT_IE_Pos           (0U)
6924 #define DCMI_IER_INT_IE_Msk           (0x1FU << DCMI_IER_INT_IE_Pos)           /*!< 0x0000001F */
6925 #define DCMI_IER_INT_IE               DCMI_IER_INT_IE_Msk
6926 
6927 /********************  Bits definition for DCMI_MIS register  *****************/
6928 #define DCMI_MIS_FRAME_MIS_Pos        (0U)
6929 #define DCMI_MIS_FRAME_MIS_Msk        (0x1U << DCMI_MIS_FRAME_MIS_Pos)         /*!< 0x00000001 */
6930 #define DCMI_MIS_FRAME_MIS            DCMI_MIS_FRAME_MIS_Msk                   /*!< DCMI Capture complete masked interrupt status */
6931 #define DCMI_MIS_OVR_MIS_Pos          (1U)
6932 #define DCMI_MIS_OVR_MIS_Msk          (0x1U << DCMI_MIS_OVR_MIS_Pos)           /*!< 0x00000002 */
6933 #define DCMI_MIS_OVR_MIS              DCMI_MIS_OVR_MIS_Msk                     /*!< DCMI Overrun masked interrupt status */
6934 #define DCMI_MIS_ERR_MIS_Pos          (2U)
6935 #define DCMI_MIS_ERR_MIS_Msk          (0x1U << DCMI_MIS_ERR_MIS_Pos)           /*!< 0x00000004 */
6936 #define DCMI_MIS_ERR_MIS              DCMI_MIS_ERR_MIS_Msk                     /*!< DCMI Synchronization error masked interrupt status */
6937 #define DCMI_MIS_VSYNC_MIS_Pos        (3U)
6938 #define DCMI_MIS_VSYNC_MIS_Msk        (0x1U << DCMI_MIS_VSYNC_MIS_Pos)         /*!< 0x00000008 */
6939 #define DCMI_MIS_VSYNC_MIS            DCMI_MIS_VSYNC_MIS_Msk                   /*!< DCMI VSYNC masked interrupt status */
6940 #define DCMI_MIS_LINE_MIS_Pos         (4U)
6941 #define DCMI_MIS_LINE_MIS_Msk         (0x1U << DCMI_MIS_LINE_MIS_Pos)          /*!< 0x00000010 */
6942 #define DCMI_MIS_LINE_MIS             DCMI_MIS_LINE_MIS_Msk                    /*!< DCMI Line masked interrupt status */
6943 
6944 /********************  Bits definition for DCMI_ICR register  *****************/
6945 #define DCMI_ICR_FRAME_ISC_Pos        (0U)
6946 #define DCMI_ICR_FRAME_ISC_Msk        (0x1U << DCMI_ICR_FRAME_ISC_Pos)         /*!< 0x00000001 */
6947 #define DCMI_ICR_FRAME_ISC            DCMI_ICR_FRAME_ISC_Msk                   /*!< DCMI Capture complete interrupt status clear */
6948 #define DCMI_ICR_OVR_ISC_Pos          (1U)
6949 #define DCMI_ICR_OVR_ISC_Msk          (0x1U << DCMI_ICR_OVR_ISC_Pos)           /*!< 0x00000002 */
6950 #define DCMI_ICR_OVR_ISC              DCMI_ICR_OVR_ISC_Msk                     /*!< DCMI Overrun interrupt status clear */
6951 #define DCMI_ICR_ERR_ISC_Pos          (2U)
6952 #define DCMI_ICR_ERR_ISC_Msk          (0x1U << DCMI_ICR_ERR_ISC_Pos)           /*!< 0x00000004 */
6953 #define DCMI_ICR_ERR_ISC              DCMI_ICR_ERR_ISC_Msk                     /*!< DCMI Synchronization error interrupt status clear */
6954 #define DCMI_ICR_VSYNC_ISC_Pos        (3U)
6955 #define DCMI_ICR_VSYNC_ISC_Msk        (0x1U << DCMI_ICR_VSYNC_ISC_Pos)         /*!< 0x00000008 */
6956 #define DCMI_ICR_VSYNC_ISC            DCMI_ICR_VSYNC_ISC_Msk                   /*!< DCMI Vertical synch interrupt status clear */
6957 #define DCMI_ICR_LINE_ISC_Pos         (4U)
6958 #define DCMI_ICR_LINE_ISC_Msk         (0x1U << DCMI_ICR_LINE_ISC_Pos)          /*!< 0x00000010 */
6959 #define DCMI_ICR_LINE_ISC             DCMI_ICR_LINE_ISC_Msk                    /*!< DCMI line interrupt status clear */
6960 
6961 /********************  Bits definition for DCMI_ESCR register  ****************/
6962 #define DCMI_ESCR_FSC_Pos             (0U)
6963 #define DCMI_ESCR_FSC_Msk             (0xFFU << DCMI_ESCR_FSC_Pos)             /*!< 0x000000FF */
6964 #define DCMI_ESCR_FSC                 DCMI_ESCR_FSC_Msk                        /*!< DCMI Frame start delimiter code FSC[7:0] */
6965 #define DCMI_ESCR_FSC_0               (0x01U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000001 */
6966 #define DCMI_ESCR_FSC_1               (0x02U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000002 */
6967 #define DCMI_ESCR_FSC_2               (0x04U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000004 */
6968 #define DCMI_ESCR_FSC_3               (0x08U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000008 */
6969 #define DCMI_ESCR_FSC_4               (0x10U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000010 */
6970 #define DCMI_ESCR_FSC_5               (0x20U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000020 */
6971 #define DCMI_ESCR_FSC_6               (0x40U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000040 */
6972 #define DCMI_ESCR_FSC_7               (0x80U << DCMI_ESCR_FSC_Pos)             /*!< 0x00000080 */
6973 #define DCMI_ESCR_LSC_Pos             (8U)
6974 #define DCMI_ESCR_LSC_Msk             (0xFFU << DCMI_ESCR_LSC_Pos)             /*!< 0x0000FF00 */
6975 #define DCMI_ESCR_LSC                 DCMI_ESCR_LSC_Msk                        /*!< DCMI Line start delimiter code LSC[7:0] */
6976 #define DCMI_ESCR_LSC_0               (0x01U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000100 */
6977 #define DCMI_ESCR_LSC_1               (0x02U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000200 */
6978 #define DCMI_ESCR_LSC_2               (0x04U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000400 */
6979 #define DCMI_ESCR_LSC_3               (0x08U << DCMI_ESCR_LSC_Pos)             /*!< 0x00000800 */
6980 #define DCMI_ESCR_LSC_4               (0x10U << DCMI_ESCR_LSC_Pos)             /*!< 0x00001000 */
6981 #define DCMI_ESCR_LSC_5               (0x20U << DCMI_ESCR_LSC_Pos)             /*!< 0x00002000 */
6982 #define DCMI_ESCR_LSC_6               (0x40U << DCMI_ESCR_LSC_Pos)             /*!< 0x00004000 */
6983 #define DCMI_ESCR_LSC_7               (0x80U << DCMI_ESCR_LSC_Pos)             /*!< 0x00008000 */
6984 #define DCMI_ESCR_LEC_Pos             (16U)
6985 #define DCMI_ESCR_LEC_Msk             (0xFFU << DCMI_ESCR_LEC_Pos)             /*!< 0x00FF0000 */
6986 #define DCMI_ESCR_LEC                 DCMI_ESCR_LEC_Msk                        /*!< DCMI Line end delimiter code LEC[7:0] */
6987 #define DCMI_ESCR_LEC_0               (0x01U << DCMI_ESCR_LEC_Pos)             /*!< 0x00010000 */
6988 #define DCMI_ESCR_LEC_1               (0x02U << DCMI_ESCR_LEC_Pos)             /*!< 0x00020000 */
6989 #define DCMI_ESCR_LEC_2               (0x04U << DCMI_ESCR_LEC_Pos)             /*!< 0x00040000 */
6990 #define DCMI_ESCR_LEC_3               (0x08U << DCMI_ESCR_LEC_Pos)             /*!< 0x00080000 */
6991 #define DCMI_ESCR_LEC_4               (0x10U << DCMI_ESCR_LEC_Pos)             /*!< 0x00100000 */
6992 #define DCMI_ESCR_LEC_5               (0x20U << DCMI_ESCR_LEC_Pos)             /*!< 0x00200000 */
6993 #define DCMI_ESCR_LEC_6               (0x40U << DCMI_ESCR_LEC_Pos)             /*!< 0x00400000 */
6994 #define DCMI_ESCR_LEC_7               (0x80U << DCMI_ESCR_LEC_Pos)             /*!< 0x00800000 */
6995 #define DCMI_ESCR_FEC_Pos             (24U)
6996 #define DCMI_ESCR_FEC_Msk             (0xFFU << DCMI_ESCR_FEC_Pos)             /*!< 0xFF000000 */
6997 #define DCMI_ESCR_FEC                 DCMI_ESCR_FEC_Msk                        /*!< DCMI Frame end delimiter code FEC[7:0] */
6998 #define DCMI_ESCR_FEC_0               (0x01U << DCMI_ESCR_FEC_Pos)             /*!< 0x01000000 */
6999 #define DCMI_ESCR_FEC_1               (0x02U << DCMI_ESCR_FEC_Pos)             /*!< 0x02000000 */
7000 #define DCMI_ESCR_FEC_2               (0x04U << DCMI_ESCR_FEC_Pos)             /*!< 0x04000000 */
7001 #define DCMI_ESCR_FEC_3               (0x08U << DCMI_ESCR_FEC_Pos)             /*!< 0x08000000 */
7002 #define DCMI_ESCR_FEC_4               (0x10U << DCMI_ESCR_FEC_Pos)             /*!< 0x10000000 */
7003 #define DCMI_ESCR_FEC_5               (0x20U << DCMI_ESCR_FEC_Pos)             /*!< 0x20000000 */
7004 #define DCMI_ESCR_FEC_6               (0x40U << DCMI_ESCR_FEC_Pos)             /*!< 0x40000000 */
7005 #define DCMI_ESCR_FEC_7               (0x80U << DCMI_ESCR_FEC_Pos)             /*!< 0x80000000 */
7006 
7007 /********************  Bits definition for DCMI_ESUR register  ****************/
7008 #define DCMI_ESUR_FSU_Pos             (0U)
7009 #define DCMI_ESUR_FSU_Msk             (0xFFU << DCMI_ESUR_FSU_Pos)             /*!< 0x000000FF */
7010 #define DCMI_ESUR_FSU                 DCMI_ESUR_FSU_Msk                        /*!< DCMI Frame start delimiter unmask FSU[7:0] */
7011 #define DCMI_ESUR_FSU_0               (0x01U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000001 */
7012 #define DCMI_ESUR_FSU_1               (0x02U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000002 */
7013 #define DCMI_ESUR_FSU_2               (0x04U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000004 */
7014 #define DCMI_ESUR_FSU_3               (0x08U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000008 */
7015 #define DCMI_ESUR_FSU_4               (0x10U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000010 */
7016 #define DCMI_ESUR_FSU_5               (0x20U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000020 */
7017 #define DCMI_ESUR_FSU_6               (0x40U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000040 */
7018 #define DCMI_ESUR_FSU_7               (0x80U << DCMI_ESUR_FSU_Pos)             /*!< 0x00000080 */
7019 #define DCMI_ESUR_LSU_Pos             (8U)
7020 #define DCMI_ESUR_LSU_Msk             (0xFFU << DCMI_ESUR_LSU_Pos)             /*!< 0x0000FF00 */
7021 #define DCMI_ESUR_LSU                 DCMI_ESUR_LSU_Msk                        /*!< DCMI Line start delimiter unmask LSU[7:0] */
7022 #define DCMI_ESUR_LSU_0               (0x01U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000100 */
7023 #define DCMI_ESUR_LSU_1               (0x02U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000200 */
7024 #define DCMI_ESUR_LSU_2               (0x04U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000400 */
7025 #define DCMI_ESUR_LSU_3               (0x08U << DCMI_ESUR_LSU_Pos)             /*!< 0x00000800 */
7026 #define DCMI_ESUR_LSU_4               (0x10U << DCMI_ESUR_LSU_Pos)             /*!< 0x00001000 */
7027 #define DCMI_ESUR_LSU_5               (0x20U << DCMI_ESUR_LSU_Pos)             /*!< 0x00002000 */
7028 #define DCMI_ESUR_LSU_6               (0x40U << DCMI_ESUR_LSU_Pos)             /*!< 0x00004000 */
7029 #define DCMI_ESUR_LSU_7               (0x80U << DCMI_ESUR_LSU_Pos)             /*!< 0x00008000 */
7030 #define DCMI_ESUR_LEU_Pos             (16U)
7031 #define DCMI_ESUR_LEU_Msk             (0xFFU << DCMI_ESUR_LEU_Pos)             /*!< 0x00FF0000 */
7032 #define DCMI_ESUR_LEU                 DCMI_ESUR_LEU_Msk                        /*!< DCMI Line end delimiter unmask LEU[7:0] */
7033 #define DCMI_ESUR_LEU_0               (0x01U << DCMI_ESUR_LEU_Pos)             /*!< 0x00010000 */
7034 #define DCMI_ESUR_LEU_1               (0x02U << DCMI_ESUR_LEU_Pos)             /*!< 0x00020000 */
7035 #define DCMI_ESUR_LEU_2               (0x04U << DCMI_ESUR_LEU_Pos)             /*!< 0x00040000 */
7036 #define DCMI_ESUR_LEU_3               (0x08U << DCMI_ESUR_LEU_Pos)             /*!< 0x00080000 */
7037 #define DCMI_ESUR_LEU_4               (0x10U << DCMI_ESUR_LEU_Pos)             /*!< 0x00100000 */
7038 #define DCMI_ESUR_LEU_5               (0x20U << DCMI_ESUR_LEU_Pos)             /*!< 0x00200000 */
7039 #define DCMI_ESUR_LEU_6               (0x40U << DCMI_ESUR_LEU_Pos)             /*!< 0x00400000 */
7040 #define DCMI_ESUR_LEU_7               (0x80U << DCMI_ESUR_LEU_Pos)             /*!< 0x00800000 */
7041 #define DCMI_ESUR_FEU_Pos             (24U)
7042 #define DCMI_ESUR_FEU_Msk             (0xFFU << DCMI_ESUR_FEU_Pos)             /*!< 0xFF000000 */
7043 #define DCMI_ESUR_FEU                 DCMI_ESUR_FEU_Msk                        /*!< DCMI Frame end delimiter unmask FEU[7:0] */
7044 #define DCMI_ESUR_FEU_0               (0x01U << DCMI_ESUR_FEU_Pos)             /*!< 0x01000000 */
7045 #define DCMI_ESUR_FEU_1               (0x02U << DCMI_ESUR_FEU_Pos)             /*!< 0x02000000 */
7046 #define DCMI_ESUR_FEU_2               (0x04U << DCMI_ESUR_FEU_Pos)             /*!< 0x04000000 */
7047 #define DCMI_ESUR_FEU_3               (0x08U << DCMI_ESUR_FEU_Pos)             /*!< 0x08000000 */
7048 #define DCMI_ESUR_FEU_4               (0x10U << DCMI_ESUR_FEU_Pos)             /*!< 0x10000000 */
7049 #define DCMI_ESUR_FEU_5               (0x20U << DCMI_ESUR_FEU_Pos)             /*!< 0x20000000 */
7050 #define DCMI_ESUR_FEU_6               (0x40U << DCMI_ESUR_FEU_Pos)             /*!< 0x40000000 */
7051 #define DCMI_ESUR_FEU_7               (0x80U << DCMI_ESUR_FEU_Pos)             /*!< 0x80000000 */
7052 
7053 /********************  Bits definition for DCMI_CWSTRT register  **************/
7054 #define DCMI_CWSTRT_HOFFCNT_Pos       (0U)
7055 #define DCMI_CWSTRT_HOFFCNT_Msk       (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00003FFF */
7056 #define DCMI_CWSTRT_HOFFCNT           DCMI_CWSTRT_HOFFCNT_Msk                  /*!< DCMI Horizontal offset count HOFFCNT[13:0] */
7057 #define DCMI_CWSTRT_HOFFCNT_0         (0x0001U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000001 */
7058 #define DCMI_CWSTRT_HOFFCNT_1         (0x0002U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000002 */
7059 #define DCMI_CWSTRT_HOFFCNT_2         (0x0004U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000004 */
7060 #define DCMI_CWSTRT_HOFFCNT_3         (0x0008U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000008 */
7061 #define DCMI_CWSTRT_HOFFCNT_4         (0x0010U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000010 */
7062 #define DCMI_CWSTRT_HOFFCNT_5         (0x0020U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000020 */
7063 #define DCMI_CWSTRT_HOFFCNT_6         (0x0040U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000040 */
7064 #define DCMI_CWSTRT_HOFFCNT_7         (0x0080U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000080 */
7065 #define DCMI_CWSTRT_HOFFCNT_8         (0x0100U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000100 */
7066 #define DCMI_CWSTRT_HOFFCNT_9         (0x0200U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000200 */
7067 #define DCMI_CWSTRT_HOFFCNT_10        (0x0400U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000400 */
7068 #define DCMI_CWSTRT_HOFFCNT_11        (0x0800U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00000800 */
7069 #define DCMI_CWSTRT_HOFFCNT_12        (0x1000U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00001000 */
7070 #define DCMI_CWSTRT_HOFFCNT_13        (0x2000U << DCMI_CWSTRT_HOFFCNT_Pos)     /*!< 0x00002000 */
7071 #define DCMI_CWSTRT_VST_Pos           (16U)
7072 #define DCMI_CWSTRT_VST_Msk           (0x1FFFU << DCMI_CWSTRT_VST_Pos)         /*!< 0x1FFF0000 */
7073 #define DCMI_CWSTRT_VST               DCMI_CWSTRT_VST_Msk                      /*!< DCMI Vertical start line count VST[12:0] */
7074 #define DCMI_CWSTRT_VST_0             (0x0001U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00010000 */
7075 #define DCMI_CWSTRT_VST_1             (0x0002U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00020000 */
7076 #define DCMI_CWSTRT_VST_2             (0x0004U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00040000 */
7077 #define DCMI_CWSTRT_VST_3             (0x0008U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00080000 */
7078 #define DCMI_CWSTRT_VST_4             (0x0010U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00100000 */
7079 #define DCMI_CWSTRT_VST_5             (0x0020U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00200000 */
7080 #define DCMI_CWSTRT_VST_6             (0x0040U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00400000 */
7081 #define DCMI_CWSTRT_VST_7             (0x0080U << DCMI_CWSTRT_VST_Pos)         /*!< 0x00800000 */
7082 #define DCMI_CWSTRT_VST_8             (0x0100U << DCMI_CWSTRT_VST_Pos)         /*!< 0x01000000 */
7083 #define DCMI_CWSTRT_VST_9             (0x0200U << DCMI_CWSTRT_VST_Pos)         /*!< 0x02000000 */
7084 #define DCMI_CWSTRT_VST_10            (0x0400U << DCMI_CWSTRT_VST_Pos)         /*!< 0x04000000 */
7085 #define DCMI_CWSTRT_VST_11            (0x0800U << DCMI_CWSTRT_VST_Pos)         /*!< 0x08000000 */
7086 #define DCMI_CWSTRT_VST_12            (0x1000U << DCMI_CWSTRT_VST_Pos)         /*!< 0x10000000 */
7087 
7088 /********************  Bits definition for DCMI_CWSIZE register  **************/
7089 #define DCMI_CWSIZE_CAPCNT_Pos        (0U)
7090 #define DCMI_CWSIZE_CAPCNT_Msk        (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00003FFF */
7091 #define DCMI_CWSIZE_CAPCNT            DCMI_CWSIZE_CAPCNT_Msk                   /*!< DCMI Capture count CAPCNT[13:0] */
7092 #define DCMI_CWSIZE_CAPCNT_0          (0x0001U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000001 */
7093 #define DCMI_CWSIZE_CAPCNT_1          (0x0002U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000002 */
7094 #define DCMI_CWSIZE_CAPCNT_2          (0x0004U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000004 */
7095 #define DCMI_CWSIZE_CAPCNT_3          (0x0008U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000008 */
7096 #define DCMI_CWSIZE_CAPCNT_4          (0x0010U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000010 */
7097 #define DCMI_CWSIZE_CAPCNT_5          (0x0020U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000020 */
7098 #define DCMI_CWSIZE_CAPCNT_6          (0x0040U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000040 */
7099 #define DCMI_CWSIZE_CAPCNT_7          (0x0080U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000080 */
7100 #define DCMI_CWSIZE_CAPCNT_8          (0x0100U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000100 */
7101 #define DCMI_CWSIZE_CAPCNT_9          (0x0200U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000200 */
7102 #define DCMI_CWSIZE_CAPCNT_10         (0x0400U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000400 */
7103 #define DCMI_CWSIZE_CAPCNT_11         (0x0800U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00000800 */
7104 #define DCMI_CWSIZE_CAPCNT_12         (0x1000U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00001000 */
7105 #define DCMI_CWSIZE_CAPCNT_13         (0x2000U << DCMI_CWSIZE_CAPCNT_Pos)      /*!< 0x00002000 */
7106 #define DCMI_CWSIZE_VLINE_Pos         (16U)
7107 #define DCMI_CWSIZE_VLINE_Msk         (0x3FFFU << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x3FFF0000 */
7108 #define DCMI_CWSIZE_VLINE             DCMI_CWSIZE_VLINE_Msk                    /*!< DCMI Vertical line count VLINE[13:0] */
7109 #define DCMI_CWSIZE_VLINE_0           (0x0001U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00010000 */
7110 #define DCMI_CWSIZE_VLINE_1           (0x0002U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00020000 */
7111 #define DCMI_CWSIZE_VLINE_2           (0x0004U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00040000 */
7112 #define DCMI_CWSIZE_VLINE_3           (0x0008U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00080000 */
7113 #define DCMI_CWSIZE_VLINE_4           (0x0010U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00100000 */
7114 #define DCMI_CWSIZE_VLINE_5           (0x0020U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00200000 */
7115 #define DCMI_CWSIZE_VLINE_6           (0x0040U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00400000 */
7116 #define DCMI_CWSIZE_VLINE_7           (0x0080U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x00800000 */
7117 #define DCMI_CWSIZE_VLINE_8           (0x0100U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x01000000 */
7118 #define DCMI_CWSIZE_VLINE_9           (0x0200U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x02000000 */
7119 #define DCMI_CWSIZE_VLINE_10          (0x0400U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x04000000 */
7120 #define DCMI_CWSIZE_VLINE_11          (0x0800U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x08000000 */
7121 #define DCMI_CWSIZE_VLINE_12          (0x1000U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x10000000 */
7122 #define DCMI_CWSIZE_VLINE_13          (0x2000U << DCMI_CWSIZE_VLINE_Pos)       /*!< 0x20000000 */
7123 
7124 /********************  Bits definition for DCMI_DR register  **************/
7125 #define DCMI_DR_BYTE0_Pos             (0U)
7126 #define DCMI_DR_BYTE0_Msk             (0xFFU << DCMI_DR_BYTE0_Pos)             /*!< 0x000000FF */
7127 #define DCMI_DR_BYTE0                 DCMI_DR_BYTE0_Msk                        /*!< DCMI Data byte 0 Byte0[7:0] */
7128 #define DCMI_DR_BYTE0_0               (0x01U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000001 */
7129 #define DCMI_DR_BYTE0_1               (0x02U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000002 */
7130 #define DCMI_DR_BYTE0_2               (0x04U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000004 */
7131 #define DCMI_DR_BYTE0_3               (0x08U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000008 */
7132 #define DCMI_DR_BYTE0_4               (0x10U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000010 */
7133 #define DCMI_DR_BYTE0_5               (0x20U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000020 */
7134 #define DCMI_DR_BYTE0_6               (0x40U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000040 */
7135 #define DCMI_DR_BYTE0_7               (0x80U << DCMI_DR_BYTE0_Pos)             /*!< 0x00000080 */
7136 #define DCMI_DR_BYTE1_Pos             (8U)
7137 #define DCMI_DR_BYTE1_Msk             (0xFFU << DCMI_DR_BYTE1_Pos)             /*!< 0x0000FF00 */
7138 #define DCMI_DR_BYTE1                 DCMI_DR_BYTE1_Msk                        /*!< DCMI Data byte 1 Byte1[7:0] */
7139 #define DCMI_DR_BYTE1_0               (0x01U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000100 */
7140 #define DCMI_DR_BYTE1_1               (0x02U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000200 */
7141 #define DCMI_DR_BYTE1_2               (0x04U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000400 */
7142 #define DCMI_DR_BYTE1_3               (0x08U << DCMI_DR_BYTE1_Pos)             /*!< 0x00000800 */
7143 #define DCMI_DR_BYTE1_4               (0x10U << DCMI_DR_BYTE1_Pos)             /*!< 0x00001000 */
7144 #define DCMI_DR_BYTE1_5               (0x20U << DCMI_DR_BYTE1_Pos)             /*!< 0x00002000 */
7145 #define DCMI_DR_BYTE1_6               (0x40U << DCMI_DR_BYTE1_Pos)             /*!< 0x00004000 */
7146 #define DCMI_DR_BYTE1_7               (0x80U << DCMI_DR_BYTE1_Pos)             /*!< 0x00008000 */
7147 #define DCMI_DR_BYTE2_Pos             (16U)
7148 #define DCMI_DR_BYTE2_Msk             (0xFFU << DCMI_DR_BYTE2_Pos)             /*!< 0x00FF0000 */
7149 #define DCMI_DR_BYTE2                 DCMI_DR_BYTE2_Msk                        /*!< DCMI Data byte 2 Byte2[7:0] */
7150 #define DCMI_DR_BYTE2_0               (0x01U << DCMI_DR_BYTE2_Pos)             /*!< 0x00010000 */
7151 #define DCMI_DR_BYTE2_1               (0x02U << DCMI_DR_BYTE2_Pos)             /*!< 0x00020000 */
7152 #define DCMI_DR_BYTE2_2               (0x04U << DCMI_DR_BYTE2_Pos)             /*!< 0x00040000 */
7153 #define DCMI_DR_BYTE2_3               (0x08U << DCMI_DR_BYTE2_Pos)             /*!< 0x00080000 */
7154 #define DCMI_DR_BYTE2_4               (0x10U << DCMI_DR_BYTE2_Pos)             /*!< 0x00100000 */
7155 #define DCMI_DR_BYTE2_5               (0x20U << DCMI_DR_BYTE2_Pos)             /*!< 0x00200000 */
7156 #define DCMI_DR_BYTE2_6               (0x40U << DCMI_DR_BYTE2_Pos)             /*!< 0x00400000 */
7157 #define DCMI_DR_BYTE2_7               (0x80U << DCMI_DR_BYTE2_Pos)             /*!< 0x00800000 */
7158 #define DCMI_DR_BYTE3_Pos             (24U)
7159 #define DCMI_DR_BYTE3_Msk             (0xFFU << DCMI_DR_BYTE3_Pos)             /*!< 0xFF000000 */
7160 #define DCMI_DR_BYTE3                 DCMI_DR_BYTE3_Msk                        /*!< DCMI Data byte 3 Byte3[7:0] */
7161 #define DCMI_DR_BYTE3_0               (0x01U << DCMI_DR_BYTE3_Pos)             /*!< 0x01000000 */
7162 #define DCMI_DR_BYTE3_1               (0x02U << DCMI_DR_BYTE3_Pos)             /*!< 0x02000000 */
7163 #define DCMI_DR_BYTE3_2               (0x04U << DCMI_DR_BYTE3_Pos)             /*!< 0x04000000 */
7164 #define DCMI_DR_BYTE3_3               (0x08U << DCMI_DR_BYTE3_Pos)             /*!< 0x08000000 */
7165 #define DCMI_DR_BYTE3_4               (0x10U << DCMI_DR_BYTE3_Pos)             /*!< 0x10000000 */
7166 #define DCMI_DR_BYTE3_5               (0x20U << DCMI_DR_BYTE3_Pos)             /*!< 0x20000000 */
7167 #define DCMI_DR_BYTE3_6               (0x40U << DCMI_DR_BYTE3_Pos)             /*!< 0x40000000 */
7168 #define DCMI_DR_BYTE3_7               (0x80U << DCMI_DR_BYTE3_Pos)             /*!< 0x80000000 */
7169 
7170 /******************************************************************************/
7171 /*                                                                            */
7172 /*                 Digital Filter for Sigma Delta Modulators                  */
7173 /*                                                                            */
7174 /******************************************************************************/
7175 
7176 /****************   DFSDM channel configuration registers  ********************/
7177 
7178 /***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
7179 #define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)
7180 #define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1U << DFSDM_CHCFGR1_DFSDMEN_Pos)    /*!< 0x80000000 */
7181 #define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
7182 #define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)
7183 #define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1U << DFSDM_CHCFGR1_CKOUTSRC_Pos)   /*!< 0x40000000 */
7184 #define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
7185 #define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)
7186 #define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFU << DFSDM_CHCFGR1_CKOUTDIV_Pos)  /*!< 0x00FF0000 */
7187 #define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
7188 #define DFSDM_CHCFGR1_DATPACK_Pos       (14U)
7189 #define DFSDM_CHCFGR1_DATPACK_Msk       (0x3U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x0000C000 */
7190 #define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
7191 #define DFSDM_CHCFGR1_DATPACK_1         (0x2U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
7192 #define DFSDM_CHCFGR1_DATPACK_0         (0x1U << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
7193 #define DFSDM_CHCFGR1_DATMPX_Pos        (12U)
7194 #define DFSDM_CHCFGR1_DATMPX_Msk        (0x3U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00003000 */
7195 #define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
7196 #define DFSDM_CHCFGR1_DATMPX_1          (0x2U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
7197 #define DFSDM_CHCFGR1_DATMPX_0          (0x1U << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
7198 #define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)
7199 #define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1U << DFSDM_CHCFGR1_CHINSEL_Pos)    /*!< 0x00000100 */
7200 #define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
7201 #define DFSDM_CHCFGR1_CHEN_Pos          (7U)
7202 #define DFSDM_CHCFGR1_CHEN_Msk          (0x1U << DFSDM_CHCFGR1_CHEN_Pos)       /*!< 0x00000080 */
7203 #define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
7204 #define DFSDM_CHCFGR1_CKABEN_Pos        (6U)
7205 #define DFSDM_CHCFGR1_CKABEN_Msk        (0x1U << DFSDM_CHCFGR1_CKABEN_Pos)     /*!< 0x00000040 */
7206 #define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
7207 #define DFSDM_CHCFGR1_SCDEN_Pos         (5U)
7208 #define DFSDM_CHCFGR1_SCDEN_Msk         (0x1U << DFSDM_CHCFGR1_SCDEN_Pos)      /*!< 0x00000020 */
7209 #define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
7210 #define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)
7211 #define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x0000000C */
7212 #define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
7213 #define DFSDM_CHCFGR1_SPICKSEL_1        (0x2U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
7214 #define DFSDM_CHCFGR1_SPICKSEL_0        (0x1U << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
7215 #define DFSDM_CHCFGR1_SITP_Pos          (0U)
7216 #define DFSDM_CHCFGR1_SITP_Msk          (0x3U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000003 */
7217 #define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
7218 #define DFSDM_CHCFGR1_SITP_1            (0x2U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
7219 #define DFSDM_CHCFGR1_SITP_0            (0x1U << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
7220 
7221 /***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
7222 #define DFSDM_CHCFGR2_OFFSET_Pos        (8U)
7223 #define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFU << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
7224 #define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
7225 #define DFSDM_CHCFGR2_DTRBS_Pos         (3U)
7226 #define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FU << DFSDM_CHCFGR2_DTRBS_Pos)     /*!< 0x000000F8 */
7227 #define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
7228 
7229 /****************  Bit definition for DFSDM_CHAWSCDR register *****************/
7230 #define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)
7231 #define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00C00000 */
7232 #define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
7233 #define DFSDM_CHAWSCDR_AWFORD_1         (0x2U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
7234 #define DFSDM_CHAWSCDR_AWFORD_0         (0x1U << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
7235 #define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)
7236 #define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FU << DFSDM_CHAWSCDR_AWFOSR_Pos)   /*!< 0x001F0000 */
7237 #define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
7238 #define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)
7239 #define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFU << DFSDM_CHAWSCDR_BKSCD_Pos)     /*!< 0x0000F000 */
7240 #define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
7241 #define DFSDM_CHAWSCDR_SCDT_Pos         (0U)
7242 #define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFU << DFSDM_CHAWSCDR_SCDT_Pos)     /*!< 0x000000FF */
7243 #define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
7244 
7245 /****************  Bit definition for DFSDM_CHWDATR register *******************/
7246 #define DFSDM_CHWDATR_WDATA_Pos         (0U)
7247 #define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFU << DFSDM_CHWDATR_WDATA_Pos)   /*!< 0x0000FFFF */
7248 #define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
7249 
7250 /****************  Bit definition for DFSDM_CHDATINR register *****************/
7251 #define DFSDM_CHDATINR_INDAT0_Pos       (0U)
7252 #define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
7253 #define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
7254 #define DFSDM_CHDATINR_INDAT1_Pos       (16U)
7255 #define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFU << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
7256 #define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
7257 
7258 /************************   DFSDM module registers  ****************************/
7259 
7260 /*****************  Bit definition for DFSDM_FLTCR1 register *******************/
7261 #define DFSDM_FLTCR1_AWFSEL_Pos         (30U)
7262 #define DFSDM_FLTCR1_AWFSEL_Msk         (0x1U << DFSDM_FLTCR1_AWFSEL_Pos)      /*!< 0x40000000 */
7263 #define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
7264 #define DFSDM_FLTCR1_FAST_Pos           (29U)
7265 #define DFSDM_FLTCR1_FAST_Msk           (0x1U << DFSDM_FLTCR1_FAST_Pos)        /*!< 0x20000000 */
7266 #define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
7267 #define DFSDM_FLTCR1_RCH_Pos            (24U)
7268 #define DFSDM_FLTCR1_RCH_Msk            (0x7U << DFSDM_FLTCR1_RCH_Pos)         /*!< 0x07000000 */
7269 #define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
7270 #define DFSDM_FLTCR1_RDMAEN_Pos         (21U)
7271 #define DFSDM_FLTCR1_RDMAEN_Msk         (0x1U << DFSDM_FLTCR1_RDMAEN_Pos)      /*!< 0x00200000 */
7272 #define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
7273 #define DFSDM_FLTCR1_RSYNC_Pos          (19U)
7274 #define DFSDM_FLTCR1_RSYNC_Msk          (0x1U << DFSDM_FLTCR1_RSYNC_Pos)       /*!< 0x00080000 */
7275 #define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
7276 #define DFSDM_FLTCR1_RCONT_Pos          (18U)
7277 #define DFSDM_FLTCR1_RCONT_Msk          (0x1U << DFSDM_FLTCR1_RCONT_Pos)       /*!< 0x00040000 */
7278 #define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
7279 #define DFSDM_FLTCR1_RSWSTART_Pos       (17U)
7280 #define DFSDM_FLTCR1_RSWSTART_Msk       (0x1U << DFSDM_FLTCR1_RSWSTART_Pos)    /*!< 0x00020000 */
7281 #define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
7282 #define DFSDM_FLTCR1_JEXTEN_Pos         (13U)
7283 #define DFSDM_FLTCR1_JEXTEN_Msk         (0x3U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00006000 */
7284 #define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
7285 #define DFSDM_FLTCR1_JEXTEN_1           (0x2U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
7286 #define DFSDM_FLTCR1_JEXTEN_0           (0x1U << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
7287 #define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)
7288 #define DFSDM_FLTCR1_JEXTSEL_Msk        (0x7U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000700 */
7289 #define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */
7290 #define DFSDM_FLTCR1_JEXTSEL_2          (0x4U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000400 */
7291 #define DFSDM_FLTCR1_JEXTSEL_1          (0x2U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000200 */
7292 #define DFSDM_FLTCR1_JEXTSEL_0          (0x1U << DFSDM_FLTCR1_JEXTSEL_Pos)     /*!< 0x00000100 */
7293 #define DFSDM_FLTCR1_JDMAEN_Pos         (5U)
7294 #define DFSDM_FLTCR1_JDMAEN_Msk         (0x1U << DFSDM_FLTCR1_JDMAEN_Pos)      /*!< 0x00000020 */
7295 #define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
7296 #define DFSDM_FLTCR1_JSCAN_Pos          (4U)
7297 #define DFSDM_FLTCR1_JSCAN_Msk          (0x1U << DFSDM_FLTCR1_JSCAN_Pos)       /*!< 0x00000010 */
7298 #define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
7299 #define DFSDM_FLTCR1_JSYNC_Pos          (3U)
7300 #define DFSDM_FLTCR1_JSYNC_Msk          (0x1U << DFSDM_FLTCR1_JSYNC_Pos)       /*!< 0x00000008 */
7301 #define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
7302 #define DFSDM_FLTCR1_JSWSTART_Pos       (1U)
7303 #define DFSDM_FLTCR1_JSWSTART_Msk       (0x1U << DFSDM_FLTCR1_JSWSTART_Pos)    /*!< 0x00000002 */
7304 #define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
7305 #define DFSDM_FLTCR1_DFEN_Pos           (0U)
7306 #define DFSDM_FLTCR1_DFEN_Msk           (0x1U << DFSDM_FLTCR1_DFEN_Pos)        /*!< 0x00000001 */
7307 #define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
7308 
7309 /*****************  Bit definition for DFSDM_FLTCR2 register *******************/
7310 #define DFSDM_FLTCR2_AWDCH_Pos          (16U)
7311 #define DFSDM_FLTCR2_AWDCH_Msk          (0xFFU << DFSDM_FLTCR2_AWDCH_Pos)      /*!< 0x00FF0000 */
7312 #define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
7313 #define DFSDM_FLTCR2_EXCH_Pos           (8U)
7314 #define DFSDM_FLTCR2_EXCH_Msk           (0xFFU << DFSDM_FLTCR2_EXCH_Pos)       /*!< 0x0000FF00 */
7315 #define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
7316 #define DFSDM_FLTCR2_CKABIE_Pos         (6U)
7317 #define DFSDM_FLTCR2_CKABIE_Msk         (0x1U << DFSDM_FLTCR2_CKABIE_Pos)      /*!< 0x00000040 */
7318 #define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
7319 #define DFSDM_FLTCR2_SCDIE_Pos          (5U)
7320 #define DFSDM_FLTCR2_SCDIE_Msk          (0x1U << DFSDM_FLTCR2_SCDIE_Pos)       /*!< 0x00000020 */
7321 #define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
7322 #define DFSDM_FLTCR2_AWDIE_Pos          (4U)
7323 #define DFSDM_FLTCR2_AWDIE_Msk          (0x1U << DFSDM_FLTCR2_AWDIE_Pos)       /*!< 0x00000010 */
7324 #define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
7325 #define DFSDM_FLTCR2_ROVRIE_Pos         (3U)
7326 #define DFSDM_FLTCR2_ROVRIE_Msk         (0x1U << DFSDM_FLTCR2_ROVRIE_Pos)      /*!< 0x00000008 */
7327 #define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
7328 #define DFSDM_FLTCR2_JOVRIE_Pos         (2U)
7329 #define DFSDM_FLTCR2_JOVRIE_Msk         (0x1U << DFSDM_FLTCR2_JOVRIE_Pos)      /*!< 0x00000004 */
7330 #define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
7331 #define DFSDM_FLTCR2_REOCIE_Pos         (1U)
7332 #define DFSDM_FLTCR2_REOCIE_Msk         (0x1U << DFSDM_FLTCR2_REOCIE_Pos)      /*!< 0x00000002 */
7333 #define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
7334 #define DFSDM_FLTCR2_JEOCIE_Pos         (0U)
7335 #define DFSDM_FLTCR2_JEOCIE_Msk         (0x1U << DFSDM_FLTCR2_JEOCIE_Pos)      /*!< 0x00000001 */
7336 #define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
7337 
7338 /*****************  Bit definition for DFSDM_FLTISR register *******************/
7339 #define DFSDM_FLTISR_SCDF_Pos           (24U)
7340 #define DFSDM_FLTISR_SCDF_Msk           (0xFFU << DFSDM_FLTISR_SCDF_Pos)       /*!< 0xFF000000 */
7341 #define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
7342 #define DFSDM_FLTISR_CKABF_Pos          (16U)
7343 #define DFSDM_FLTISR_CKABF_Msk          (0xFFU << DFSDM_FLTISR_CKABF_Pos)      /*!< 0x00FF0000 */
7344 #define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
7345 #define DFSDM_FLTISR_RCIP_Pos           (14U)
7346 #define DFSDM_FLTISR_RCIP_Msk           (0x1U << DFSDM_FLTISR_RCIP_Pos)        /*!< 0x00004000 */
7347 #define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
7348 #define DFSDM_FLTISR_JCIP_Pos           (13U)
7349 #define DFSDM_FLTISR_JCIP_Msk           (0x1U << DFSDM_FLTISR_JCIP_Pos)        /*!< 0x00002000 */
7350 #define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
7351 #define DFSDM_FLTISR_AWDF_Pos           (4U)
7352 #define DFSDM_FLTISR_AWDF_Msk           (0x1U << DFSDM_FLTISR_AWDF_Pos)        /*!< 0x00000010 */
7353 #define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
7354 #define DFSDM_FLTISR_ROVRF_Pos          (3U)
7355 #define DFSDM_FLTISR_ROVRF_Msk          (0x1U << DFSDM_FLTISR_ROVRF_Pos)       /*!< 0x00000008 */
7356 #define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
7357 #define DFSDM_FLTISR_JOVRF_Pos          (2U)
7358 #define DFSDM_FLTISR_JOVRF_Msk          (0x1U << DFSDM_FLTISR_JOVRF_Pos)       /*!< 0x00000004 */
7359 #define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
7360 #define DFSDM_FLTISR_REOCF_Pos          (1U)
7361 #define DFSDM_FLTISR_REOCF_Msk          (0x1U << DFSDM_FLTISR_REOCF_Pos)       /*!< 0x00000002 */
7362 #define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
7363 #define DFSDM_FLTISR_JEOCF_Pos          (0U)
7364 #define DFSDM_FLTISR_JEOCF_Msk          (0x1U << DFSDM_FLTISR_JEOCF_Pos)       /*!< 0x00000001 */
7365 #define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
7366 
7367 /*****************  Bit definition for DFSDM_FLTICR register *******************/
7368 #define DFSDM_FLTICR_CLRSCSDF_Pos       (24U)
7369 #define DFSDM_FLTICR_CLRSCSDF_Msk       (0xFFU << DFSDM_FLTICR_CLRSCSDF_Pos)   /*!< 0xFF000000 */
7370 #define DFSDM_FLTICR_CLRSCSDF           DFSDM_FLTICR_CLRSCSDF_Msk              /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
7371 #define DFSDM_FLTICR_CLRCKABF_Pos       (16U)
7372 #define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFU << DFSDM_FLTICR_CLRCKABF_Pos)   /*!< 0x00FF0000 */
7373 #define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
7374 #define DFSDM_FLTICR_CLRROVRF_Pos       (3U)
7375 #define DFSDM_FLTICR_CLRROVRF_Msk       (0x1U << DFSDM_FLTICR_CLRROVRF_Pos)    /*!< 0x00000008 */
7376 #define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
7377 #define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)
7378 #define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1U << DFSDM_FLTICR_CLRJOVRF_Pos)    /*!< 0x00000004 */
7379 #define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
7380 
7381 /****************  Bit definition for DFSDM_FLTJCHGR register ******************/
7382 #define DFSDM_FLTJCHGR_JCHG_Pos         (0U)
7383 #define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFU << DFSDM_FLTJCHGR_JCHG_Pos)     /*!< 0x000000FF */
7384 #define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
7385 
7386 /*****************  Bit definition for DFSDM_FLTFCR register *******************/
7387 #define DFSDM_FLTFCR_FORD_Pos           (29U)
7388 #define DFSDM_FLTFCR_FORD_Msk           (0x7U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0xE0000000 */
7389 #define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
7390 #define DFSDM_FLTFCR_FORD_2             (0x4U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
7391 #define DFSDM_FLTFCR_FORD_1             (0x2U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
7392 #define DFSDM_FLTFCR_FORD_0             (0x1U << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
7393 #define DFSDM_FLTFCR_FOSR_Pos           (16U)
7394 #define DFSDM_FLTFCR_FOSR_Msk           (0x3FFU << DFSDM_FLTFCR_FOSR_Pos)      /*!< 0x03FF0000 */
7395 #define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
7396 #define DFSDM_FLTFCR_IOSR_Pos           (0U)
7397 #define DFSDM_FLTFCR_IOSR_Msk           (0xFFU << DFSDM_FLTFCR_IOSR_Pos)       /*!< 0x000000FF */
7398 #define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
7399 
7400 /***************  Bit definition for DFSDM_FLTJDATAR register *****************/
7401 #define DFSDM_FLTJDATAR_JDATA_Pos       (8U)
7402 #define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFU << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
7403 #define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
7404 #define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)
7405 #define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7U << DFSDM_FLTJDATAR_JDATACH_Pos)  /*!< 0x00000007 */
7406 #define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
7407 
7408 /***************  Bit definition for DFSDM_FLTRDATAR register *****************/
7409 #define DFSDM_FLTRDATAR_RDATA_Pos       (8U)
7410 #define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFU << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
7411 #define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
7412 #define DFSDM_FLTRDATAR_RPEND_Pos       (4U)
7413 #define DFSDM_FLTRDATAR_RPEND_Msk       (0x1U << DFSDM_FLTRDATAR_RPEND_Pos)    /*!< 0x00000010 */
7414 #define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
7415 #define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)
7416 #define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7U << DFSDM_FLTRDATAR_RDATACH_Pos)  /*!< 0x00000007 */
7417 #define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
7418 
7419 /***************  Bit definition for DFSDM_FLTAWHTR register ******************/
7420 #define DFSDM_FLTAWHTR_AWHT_Pos         (8U)
7421 #define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFU << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
7422 #define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
7423 #define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)
7424 #define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFU << DFSDM_FLTAWHTR_BKAWH_Pos)     /*!< 0x0000000F */
7425 #define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
7426 
7427 /***************  Bit definition for DFSDM_FLTAWLTR register ******************/
7428 #define DFSDM_FLTAWLTR_AWLT_Pos         (8U)
7429 #define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFU << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
7430 #define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWLT[23:0] Analog watchdog low threshold */
7431 #define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)
7432 #define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFU << DFSDM_FLTAWLTR_BKAWL_Pos)     /*!< 0x0000000F */
7433 #define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
7434 
7435 /***************  Bit definition for DFSDM_FLTAWSR register *******************/
7436 #define DFSDM_FLTAWSR_AWHTF_Pos         (8U)
7437 #define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWHTF_Pos)     /*!< 0x0000FF00 */
7438 #define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
7439 #define DFSDM_FLTAWSR_AWLTF_Pos         (0U)
7440 #define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFU << DFSDM_FLTAWSR_AWLTF_Pos)     /*!< 0x000000FF */
7441 #define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
7442 
7443 /***************  Bit definition for DFSDM_FLTAWCFR register ******************/
7444 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)
7445 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
7446 #define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
7447 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)
7448 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFU << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
7449 #define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
7450 
7451 /***************  Bit definition for DFSDM_FLTEXMAX register ******************/
7452 #define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)
7453 #define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFU << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
7454 #define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
7455 #define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)
7456 #define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7U << DFSDM_FLTEXMAX_EXMAXCH_Pos)   /*!< 0x00000007 */
7457 #define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
7458 
7459 /***************  Bit definition for DFSDM_FLTEXMIN register ******************/
7460 #define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)
7461 #define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFU << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
7462 #define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
7463 #define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)
7464 #define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7U << DFSDM_FLTEXMIN_EXMINCH_Pos)   /*!< 0x00000007 */
7465 #define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
7466 
7467 /***************  Bit definition for DFSDM_FLTCNVTIMR register ****************/
7468 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)
7469 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFU << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
7470 #define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
7471 
7472 /******************************************************************************/
7473 /*                                                                            */
7474 /*                           DMA Controller (DMA)                             */
7475 /*                                                                            */
7476 /******************************************************************************/
7477 
7478 /*******************  Bit definition for DMA_ISR register  ********************/
7479 #define DMA_ISR_GIF1_Pos       (0U)
7480 #define DMA_ISR_GIF1_Msk       (0x1U << DMA_ISR_GIF1_Pos)                      /*!< 0x00000001 */
7481 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
7482 #define DMA_ISR_TCIF1_Pos      (1U)
7483 #define DMA_ISR_TCIF1_Msk      (0x1U << DMA_ISR_TCIF1_Pos)                     /*!< 0x00000002 */
7484 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
7485 #define DMA_ISR_HTIF1_Pos      (2U)
7486 #define DMA_ISR_HTIF1_Msk      (0x1U << DMA_ISR_HTIF1_Pos)                     /*!< 0x00000004 */
7487 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
7488 #define DMA_ISR_TEIF1_Pos      (3U)
7489 #define DMA_ISR_TEIF1_Msk      (0x1U << DMA_ISR_TEIF1_Pos)                     /*!< 0x00000008 */
7490 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
7491 #define DMA_ISR_GIF2_Pos       (4U)
7492 #define DMA_ISR_GIF2_Msk       (0x1U << DMA_ISR_GIF2_Pos)                      /*!< 0x00000010 */
7493 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
7494 #define DMA_ISR_TCIF2_Pos      (5U)
7495 #define DMA_ISR_TCIF2_Msk      (0x1U << DMA_ISR_TCIF2_Pos)                     /*!< 0x00000020 */
7496 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
7497 #define DMA_ISR_HTIF2_Pos      (6U)
7498 #define DMA_ISR_HTIF2_Msk      (0x1U << DMA_ISR_HTIF2_Pos)                     /*!< 0x00000040 */
7499 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
7500 #define DMA_ISR_TEIF2_Pos      (7U)
7501 #define DMA_ISR_TEIF2_Msk      (0x1U << DMA_ISR_TEIF2_Pos)                     /*!< 0x00000080 */
7502 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
7503 #define DMA_ISR_GIF3_Pos       (8U)
7504 #define DMA_ISR_GIF3_Msk       (0x1U << DMA_ISR_GIF3_Pos)                      /*!< 0x00000100 */
7505 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
7506 #define DMA_ISR_TCIF3_Pos      (9U)
7507 #define DMA_ISR_TCIF3_Msk      (0x1U << DMA_ISR_TCIF3_Pos)                     /*!< 0x00000200 */
7508 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
7509 #define DMA_ISR_HTIF3_Pos      (10U)
7510 #define DMA_ISR_HTIF3_Msk      (0x1U << DMA_ISR_HTIF3_Pos)                     /*!< 0x00000400 */
7511 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
7512 #define DMA_ISR_TEIF3_Pos      (11U)
7513 #define DMA_ISR_TEIF3_Msk      (0x1U << DMA_ISR_TEIF3_Pos)                     /*!< 0x00000800 */
7514 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
7515 #define DMA_ISR_GIF4_Pos       (12U)
7516 #define DMA_ISR_GIF4_Msk       (0x1U << DMA_ISR_GIF4_Pos)                      /*!< 0x00001000 */
7517 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
7518 #define DMA_ISR_TCIF4_Pos      (13U)
7519 #define DMA_ISR_TCIF4_Msk      (0x1U << DMA_ISR_TCIF4_Pos)                     /*!< 0x00002000 */
7520 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
7521 #define DMA_ISR_HTIF4_Pos      (14U)
7522 #define DMA_ISR_HTIF4_Msk      (0x1U << DMA_ISR_HTIF4_Pos)                     /*!< 0x00004000 */
7523 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
7524 #define DMA_ISR_TEIF4_Pos      (15U)
7525 #define DMA_ISR_TEIF4_Msk      (0x1U << DMA_ISR_TEIF4_Pos)                     /*!< 0x00008000 */
7526 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
7527 #define DMA_ISR_GIF5_Pos       (16U)
7528 #define DMA_ISR_GIF5_Msk       (0x1U << DMA_ISR_GIF5_Pos)                      /*!< 0x00010000 */
7529 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
7530 #define DMA_ISR_TCIF5_Pos      (17U)
7531 #define DMA_ISR_TCIF5_Msk      (0x1U << DMA_ISR_TCIF5_Pos)                     /*!< 0x00020000 */
7532 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
7533 #define DMA_ISR_HTIF5_Pos      (18U)
7534 #define DMA_ISR_HTIF5_Msk      (0x1U << DMA_ISR_HTIF5_Pos)                     /*!< 0x00040000 */
7535 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
7536 #define DMA_ISR_TEIF5_Pos      (19U)
7537 #define DMA_ISR_TEIF5_Msk      (0x1U << DMA_ISR_TEIF5_Pos)                     /*!< 0x00080000 */
7538 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
7539 #define DMA_ISR_GIF6_Pos       (20U)
7540 #define DMA_ISR_GIF6_Msk       (0x1U << DMA_ISR_GIF6_Pos)                      /*!< 0x00100000 */
7541 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
7542 #define DMA_ISR_TCIF6_Pos      (21U)
7543 #define DMA_ISR_TCIF6_Msk      (0x1U << DMA_ISR_TCIF6_Pos)                     /*!< 0x00200000 */
7544 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
7545 #define DMA_ISR_HTIF6_Pos      (22U)
7546 #define DMA_ISR_HTIF6_Msk      (0x1U << DMA_ISR_HTIF6_Pos)                     /*!< 0x00400000 */
7547 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
7548 #define DMA_ISR_TEIF6_Pos      (23U)
7549 #define DMA_ISR_TEIF6_Msk      (0x1U << DMA_ISR_TEIF6_Pos)                     /*!< 0x00800000 */
7550 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
7551 #define DMA_ISR_GIF7_Pos       (24U)
7552 #define DMA_ISR_GIF7_Msk       (0x1U << DMA_ISR_GIF7_Pos)                      /*!< 0x01000000 */
7553 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
7554 #define DMA_ISR_TCIF7_Pos      (25U)
7555 #define DMA_ISR_TCIF7_Msk      (0x1U << DMA_ISR_TCIF7_Pos)                     /*!< 0x02000000 */
7556 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
7557 #define DMA_ISR_HTIF7_Pos      (26U)
7558 #define DMA_ISR_HTIF7_Msk      (0x1U << DMA_ISR_HTIF7_Pos)                     /*!< 0x04000000 */
7559 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
7560 #define DMA_ISR_TEIF7_Pos      (27U)
7561 #define DMA_ISR_TEIF7_Msk      (0x1U << DMA_ISR_TEIF7_Pos)                     /*!< 0x08000000 */
7562 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
7563 
7564 /*******************  Bit definition for DMA_IFCR register  *******************/
7565 #define DMA_IFCR_CGIF1_Pos     (0U)
7566 #define DMA_IFCR_CGIF1_Msk     (0x1U << DMA_IFCR_CGIF1_Pos)                    /*!< 0x00000001 */
7567 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
7568 #define DMA_IFCR_CTCIF1_Pos    (1U)
7569 #define DMA_IFCR_CTCIF1_Msk    (0x1U << DMA_IFCR_CTCIF1_Pos)                   /*!< 0x00000002 */
7570 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
7571 #define DMA_IFCR_CHTIF1_Pos    (2U)
7572 #define DMA_IFCR_CHTIF1_Msk    (0x1U << DMA_IFCR_CHTIF1_Pos)                   /*!< 0x00000004 */
7573 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
7574 #define DMA_IFCR_CTEIF1_Pos    (3U)
7575 #define DMA_IFCR_CTEIF1_Msk    (0x1U << DMA_IFCR_CTEIF1_Pos)                   /*!< 0x00000008 */
7576 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
7577 #define DMA_IFCR_CGIF2_Pos     (4U)
7578 #define DMA_IFCR_CGIF2_Msk     (0x1U << DMA_IFCR_CGIF2_Pos)                    /*!< 0x00000010 */
7579 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
7580 #define DMA_IFCR_CTCIF2_Pos    (5U)
7581 #define DMA_IFCR_CTCIF2_Msk    (0x1U << DMA_IFCR_CTCIF2_Pos)                   /*!< 0x00000020 */
7582 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
7583 #define DMA_IFCR_CHTIF2_Pos    (6U)
7584 #define DMA_IFCR_CHTIF2_Msk    (0x1U << DMA_IFCR_CHTIF2_Pos)                   /*!< 0x00000040 */
7585 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
7586 #define DMA_IFCR_CTEIF2_Pos    (7U)
7587 #define DMA_IFCR_CTEIF2_Msk    (0x1U << DMA_IFCR_CTEIF2_Pos)                   /*!< 0x00000080 */
7588 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
7589 #define DMA_IFCR_CGIF3_Pos     (8U)
7590 #define DMA_IFCR_CGIF3_Msk     (0x1U << DMA_IFCR_CGIF3_Pos)                    /*!< 0x00000100 */
7591 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
7592 #define DMA_IFCR_CTCIF3_Pos    (9U)
7593 #define DMA_IFCR_CTCIF3_Msk    (0x1U << DMA_IFCR_CTCIF3_Pos)                   /*!< 0x00000200 */
7594 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
7595 #define DMA_IFCR_CHTIF3_Pos    (10U)
7596 #define DMA_IFCR_CHTIF3_Msk    (0x1U << DMA_IFCR_CHTIF3_Pos)                   /*!< 0x00000400 */
7597 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
7598 #define DMA_IFCR_CTEIF3_Pos    (11U)
7599 #define DMA_IFCR_CTEIF3_Msk    (0x1U << DMA_IFCR_CTEIF3_Pos)                   /*!< 0x00000800 */
7600 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
7601 #define DMA_IFCR_CGIF4_Pos     (12U)
7602 #define DMA_IFCR_CGIF4_Msk     (0x1U << DMA_IFCR_CGIF4_Pos)                    /*!< 0x00001000 */
7603 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
7604 #define DMA_IFCR_CTCIF4_Pos    (13U)
7605 #define DMA_IFCR_CTCIF4_Msk    (0x1U << DMA_IFCR_CTCIF4_Pos)                   /*!< 0x00002000 */
7606 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
7607 #define DMA_IFCR_CHTIF4_Pos    (14U)
7608 #define DMA_IFCR_CHTIF4_Msk    (0x1U << DMA_IFCR_CHTIF4_Pos)                   /*!< 0x00004000 */
7609 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
7610 #define DMA_IFCR_CTEIF4_Pos    (15U)
7611 #define DMA_IFCR_CTEIF4_Msk    (0x1U << DMA_IFCR_CTEIF4_Pos)                   /*!< 0x00008000 */
7612 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
7613 #define DMA_IFCR_CGIF5_Pos     (16U)
7614 #define DMA_IFCR_CGIF5_Msk     (0x1U << DMA_IFCR_CGIF5_Pos)                    /*!< 0x00010000 */
7615 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
7616 #define DMA_IFCR_CTCIF5_Pos    (17U)
7617 #define DMA_IFCR_CTCIF5_Msk    (0x1U << DMA_IFCR_CTCIF5_Pos)                   /*!< 0x00020000 */
7618 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
7619 #define DMA_IFCR_CHTIF5_Pos    (18U)
7620 #define DMA_IFCR_CHTIF5_Msk    (0x1U << DMA_IFCR_CHTIF5_Pos)                   /*!< 0x00040000 */
7621 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
7622 #define DMA_IFCR_CTEIF5_Pos    (19U)
7623 #define DMA_IFCR_CTEIF5_Msk    (0x1U << DMA_IFCR_CTEIF5_Pos)                   /*!< 0x00080000 */
7624 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
7625 #define DMA_IFCR_CGIF6_Pos     (20U)
7626 #define DMA_IFCR_CGIF6_Msk     (0x1U << DMA_IFCR_CGIF6_Pos)                    /*!< 0x00100000 */
7627 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
7628 #define DMA_IFCR_CTCIF6_Pos    (21U)
7629 #define DMA_IFCR_CTCIF6_Msk    (0x1U << DMA_IFCR_CTCIF6_Pos)                   /*!< 0x00200000 */
7630 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
7631 #define DMA_IFCR_CHTIF6_Pos    (22U)
7632 #define DMA_IFCR_CHTIF6_Msk    (0x1U << DMA_IFCR_CHTIF6_Pos)                   /*!< 0x00400000 */
7633 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
7634 #define DMA_IFCR_CTEIF6_Pos    (23U)
7635 #define DMA_IFCR_CTEIF6_Msk    (0x1U << DMA_IFCR_CTEIF6_Pos)                   /*!< 0x00800000 */
7636 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
7637 #define DMA_IFCR_CGIF7_Pos     (24U)
7638 #define DMA_IFCR_CGIF7_Msk     (0x1U << DMA_IFCR_CGIF7_Pos)                    /*!< 0x01000000 */
7639 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
7640 #define DMA_IFCR_CTCIF7_Pos    (25U)
7641 #define DMA_IFCR_CTCIF7_Msk    (0x1U << DMA_IFCR_CTCIF7_Pos)                   /*!< 0x02000000 */
7642 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
7643 #define DMA_IFCR_CHTIF7_Pos    (26U)
7644 #define DMA_IFCR_CHTIF7_Msk    (0x1U << DMA_IFCR_CHTIF7_Pos)                   /*!< 0x04000000 */
7645 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
7646 #define DMA_IFCR_CTEIF7_Pos    (27U)
7647 #define DMA_IFCR_CTEIF7_Msk    (0x1U << DMA_IFCR_CTEIF7_Pos)                   /*!< 0x08000000 */
7648 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
7649 
7650 /*******************  Bit definition for DMA_CCR register  ********************/
7651 #define DMA_CCR_EN_Pos         (0U)
7652 #define DMA_CCR_EN_Msk         (0x1U << DMA_CCR_EN_Pos)                        /*!< 0x00000001 */
7653 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
7654 #define DMA_CCR_TCIE_Pos       (1U)
7655 #define DMA_CCR_TCIE_Msk       (0x1U << DMA_CCR_TCIE_Pos)                      /*!< 0x00000002 */
7656 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
7657 #define DMA_CCR_HTIE_Pos       (2U)
7658 #define DMA_CCR_HTIE_Msk       (0x1U << DMA_CCR_HTIE_Pos)                      /*!< 0x00000004 */
7659 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
7660 #define DMA_CCR_TEIE_Pos       (3U)
7661 #define DMA_CCR_TEIE_Msk       (0x1U << DMA_CCR_TEIE_Pos)                      /*!< 0x00000008 */
7662 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
7663 #define DMA_CCR_DIR_Pos        (4U)
7664 #define DMA_CCR_DIR_Msk        (0x1U << DMA_CCR_DIR_Pos)                       /*!< 0x00000010 */
7665 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
7666 #define DMA_CCR_CIRC_Pos       (5U)
7667 #define DMA_CCR_CIRC_Msk       (0x1U << DMA_CCR_CIRC_Pos)                      /*!< 0x00000020 */
7668 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
7669 #define DMA_CCR_PINC_Pos       (6U)
7670 #define DMA_CCR_PINC_Msk       (0x1U << DMA_CCR_PINC_Pos)                      /*!< 0x00000040 */
7671 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
7672 #define DMA_CCR_MINC_Pos       (7U)
7673 #define DMA_CCR_MINC_Msk       (0x1U << DMA_CCR_MINC_Pos)                      /*!< 0x00000080 */
7674 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
7675 
7676 #define DMA_CCR_PSIZE_Pos      (8U)
7677 #define DMA_CCR_PSIZE_Msk      (0x3U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000300 */
7678 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
7679 #define DMA_CCR_PSIZE_0        (0x1U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000100 */
7680 #define DMA_CCR_PSIZE_1        (0x2U << DMA_CCR_PSIZE_Pos)                     /*!< 0x00000200 */
7681 
7682 #define DMA_CCR_MSIZE_Pos      (10U)
7683 #define DMA_CCR_MSIZE_Msk      (0x3U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000C00 */
7684 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
7685 #define DMA_CCR_MSIZE_0        (0x1U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000400 */
7686 #define DMA_CCR_MSIZE_1        (0x2U << DMA_CCR_MSIZE_Pos)                     /*!< 0x00000800 */
7687 
7688 #define DMA_CCR_PL_Pos         (12U)
7689 #define DMA_CCR_PL_Msk         (0x3U << DMA_CCR_PL_Pos)                        /*!< 0x00003000 */
7690 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
7691 #define DMA_CCR_PL_0           (0x1U << DMA_CCR_PL_Pos)                        /*!< 0x00001000 */
7692 #define DMA_CCR_PL_1           (0x2U << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
7693 
7694 #define DMA_CCR_MEM2MEM_Pos    (14U)
7695 #define DMA_CCR_MEM2MEM_Msk    (0x1U << DMA_CCR_MEM2MEM_Pos)                   /*!< 0x00004000 */
7696 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
7697 
7698 /******************  Bit definition for DMA_CNDTR register  *******************/
7699 #define DMA_CNDTR_NDT_Pos      (0U)
7700 #define DMA_CNDTR_NDT_Msk      (0xFFFFU << DMA_CNDTR_NDT_Pos)                  /*!< 0x0000FFFF */
7701 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
7702 
7703 /******************  Bit definition for DMA_CPAR register  ********************/
7704 #define DMA_CPAR_PA_Pos        (0U)
7705 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFU << DMA_CPAR_PA_Pos)                /*!< 0xFFFFFFFF */
7706 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
7707 
7708 /******************  Bit definition for DMA_CMAR register  ********************/
7709 #define DMA_CMAR_MA_Pos        (0U)
7710 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFU << DMA_CMAR_MA_Pos)                /*!< 0xFFFFFFFF */
7711 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
7712 
7713 
7714 /*******************  Bit definition for DMA_CSELR register  *******************/
7715 #define DMA_CSELR_C1S_Pos      (0U)
7716 #define DMA_CSELR_C1S_Msk      (0xFU << DMA_CSELR_C1S_Pos)                     /*!< 0x0000000F */
7717 #define DMA_CSELR_C1S          DMA_CSELR_C1S_Msk                               /*!< Channel 1 Selection */
7718 #define DMA_CSELR_C2S_Pos      (4U)
7719 #define DMA_CSELR_C2S_Msk      (0xFU << DMA_CSELR_C2S_Pos)                     /*!< 0x000000F0 */
7720 #define DMA_CSELR_C2S          DMA_CSELR_C2S_Msk                               /*!< Channel 2 Selection */
7721 #define DMA_CSELR_C3S_Pos      (8U)
7722 #define DMA_CSELR_C3S_Msk      (0xFU << DMA_CSELR_C3S_Pos)                     /*!< 0x00000F00 */
7723 #define DMA_CSELR_C3S          DMA_CSELR_C3S_Msk                               /*!< Channel 3 Selection */
7724 #define DMA_CSELR_C4S_Pos      (12U)
7725 #define DMA_CSELR_C4S_Msk      (0xFU << DMA_CSELR_C4S_Pos)                     /*!< 0x0000F000 */
7726 #define DMA_CSELR_C4S          DMA_CSELR_C4S_Msk                               /*!< Channel 4 Selection */
7727 #define DMA_CSELR_C5S_Pos      (16U)
7728 #define DMA_CSELR_C5S_Msk      (0xFU << DMA_CSELR_C5S_Pos)                     /*!< 0x000F0000 */
7729 #define DMA_CSELR_C5S          DMA_CSELR_C5S_Msk                               /*!< Channel 5 Selection */
7730 #define DMA_CSELR_C6S_Pos      (20U)
7731 #define DMA_CSELR_C6S_Msk      (0xFU << DMA_CSELR_C6S_Pos)                     /*!< 0x00F00000 */
7732 #define DMA_CSELR_C6S          DMA_CSELR_C6S_Msk                               /*!< Channel 6 Selection */
7733 #define DMA_CSELR_C7S_Pos      (24U)
7734 #define DMA_CSELR_C7S_Msk      (0xFU << DMA_CSELR_C7S_Pos)                     /*!< 0x0F000000 */
7735 #define DMA_CSELR_C7S          DMA_CSELR_C7S_Msk                               /*!< Channel 7 Selection */
7736 
7737 /******************************************************************************/
7738 /*                                                                            */
7739 /*                         AHB Master DMA2D Controller (DMA2D)                */
7740 /*                                                                            */
7741 /******************************************************************************/
7742 
7743 /********************  Bit definition for DMA2D_CR register  ******************/
7744 
7745 #define DMA2D_CR_START_Pos         (0U)
7746 #define DMA2D_CR_START_Msk         (0x1U << DMA2D_CR_START_Pos)                /*!< 0x00000001 */
7747 #define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer */
7748 #define DMA2D_CR_SUSP_Pos          (1U)
7749 #define DMA2D_CR_SUSP_Msk          (0x1U << DMA2D_CR_SUSP_Pos)                 /*!< 0x00000002 */
7750 #define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer */
7751 #define DMA2D_CR_ABORT_Pos         (2U)
7752 #define DMA2D_CR_ABORT_Msk         (0x1U << DMA2D_CR_ABORT_Pos)                /*!< 0x00000004 */
7753 #define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer */
7754 #define DMA2D_CR_TEIE_Pos          (8U)
7755 #define DMA2D_CR_TEIE_Msk          (0x1U << DMA2D_CR_TEIE_Pos)                 /*!< 0x00000100 */
7756 #define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable */
7757 #define DMA2D_CR_TCIE_Pos          (9U)
7758 #define DMA2D_CR_TCIE_Msk          (0x1U << DMA2D_CR_TCIE_Pos)                 /*!< 0x00000200 */
7759 #define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable */
7760 #define DMA2D_CR_TWIE_Pos          (10U)
7761 #define DMA2D_CR_TWIE_Msk          (0x1U << DMA2D_CR_TWIE_Pos)                 /*!< 0x00000400 */
7762 #define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable */
7763 #define DMA2D_CR_CAEIE_Pos         (11U)
7764 #define DMA2D_CR_CAEIE_Msk         (0x1U << DMA2D_CR_CAEIE_Pos)                /*!< 0x00000800 */
7765 #define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable */
7766 #define DMA2D_CR_CTCIE_Pos         (12U)
7767 #define DMA2D_CR_CTCIE_Msk         (0x1U << DMA2D_CR_CTCIE_Pos)                /*!< 0x00001000 */
7768 #define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
7769 #define DMA2D_CR_CEIE_Pos          (13U)
7770 #define DMA2D_CR_CEIE_Msk          (0x1U << DMA2D_CR_CEIE_Pos)                 /*!< 0x00002000 */
7771 #define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable */
7772 #define DMA2D_CR_MODE_Pos          (16U)
7773 #define DMA2D_CR_MODE_Msk          (0x3U << DMA2D_CR_MODE_Pos)                 /*!< 0x00030000 */
7774 #define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[1:0] */
7775 #define DMA2D_CR_MODE_0            (0x1U << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
7776 #define DMA2D_CR_MODE_1            (0x2U << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
7777 
7778 /********************  Bit definition for DMA2D_ISR register  *****************/
7779 
7780 #define DMA2D_ISR_TEIF_Pos         (0U)
7781 #define DMA2D_ISR_TEIF_Msk         (0x1U << DMA2D_ISR_TEIF_Pos)                /*!< 0x00000001 */
7782 #define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag */
7783 #define DMA2D_ISR_TCIF_Pos         (1U)
7784 #define DMA2D_ISR_TCIF_Msk         (0x1U << DMA2D_ISR_TCIF_Pos)                /*!< 0x00000002 */
7785 #define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag */
7786 #define DMA2D_ISR_TWIF_Pos         (2U)
7787 #define DMA2D_ISR_TWIF_Msk         (0x1U << DMA2D_ISR_TWIF_Pos)                /*!< 0x00000004 */
7788 #define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag */
7789 #define DMA2D_ISR_CAEIF_Pos        (3U)
7790 #define DMA2D_ISR_CAEIF_Msk        (0x1U << DMA2D_ISR_CAEIF_Pos)               /*!< 0x00000008 */
7791 #define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag */
7792 #define DMA2D_ISR_CTCIF_Pos        (4U)
7793 #define DMA2D_ISR_CTCIF_Msk        (0x1U << DMA2D_ISR_CTCIF_Pos)               /*!< 0x00000010 */
7794 #define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
7795 #define DMA2D_ISR_CEIF_Pos         (5U)
7796 #define DMA2D_ISR_CEIF_Msk         (0x1U << DMA2D_ISR_CEIF_Pos)                /*!< 0x00000020 */
7797 #define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag */
7798 
7799 /********************  Bit definition for DMA2D_IFCR register  ****************/
7800 
7801 #define DMA2D_IFCR_CTEIF_Pos       (0U)
7802 #define DMA2D_IFCR_CTEIF_Msk       (0x1U << DMA2D_IFCR_CTEIF_Pos)              /*!< 0x00000001 */
7803 #define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag */
7804 #define DMA2D_IFCR_CTCIF_Pos       (1U)
7805 #define DMA2D_IFCR_CTCIF_Msk       (0x1U << DMA2D_IFCR_CTCIF_Pos)              /*!< 0x00000002 */
7806 #define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag */
7807 #define DMA2D_IFCR_CTWIF_Pos       (2U)
7808 #define DMA2D_IFCR_CTWIF_Msk       (0x1U << DMA2D_IFCR_CTWIF_Pos)              /*!< 0x00000004 */
7809 #define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag */
7810 #define DMA2D_IFCR_CAECIF_Pos      (3U)
7811 #define DMA2D_IFCR_CAECIF_Msk      (0x1U << DMA2D_IFCR_CAECIF_Pos)             /*!< 0x00000008 */
7812 #define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag */
7813 #define DMA2D_IFCR_CCTCIF_Pos      (4U)
7814 #define DMA2D_IFCR_CCTCIF_Msk      (0x1U << DMA2D_IFCR_CCTCIF_Pos)             /*!< 0x00000010 */
7815 #define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
7816 #define DMA2D_IFCR_CCEIF_Pos       (5U)
7817 #define DMA2D_IFCR_CCEIF_Msk       (0x1U << DMA2D_IFCR_CCEIF_Pos)              /*!< 0x00000020 */
7818 #define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag */
7819 
7820 /********************  Bit definition for DMA2D_FGMAR register  ***************/
7821 
7822 #define DMA2D_FGMAR_MA_Pos         (0U)
7823 #define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
7824 #define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Memory Address */
7825 
7826 /********************  Bit definition for DMA2D_FGOR register  ****************/
7827 
7828 #define DMA2D_FGOR_LO_Pos          (0U)
7829 #define DMA2D_FGOR_LO_Msk          (0x3FFFU << DMA2D_FGOR_LO_Pos)              /*!< 0x00003FFF */
7830 #define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
7831 
7832 /********************  Bit definition for DMA2D_BGMAR register  ***************/
7833 
7834 #define DMA2D_BGMAR_MA_Pos         (0U)
7835 #define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos)         /*!< 0xFFFFFFFF */
7836 #define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Memory Address */
7837 
7838 /********************  Bit definition for DMA2D_BGOR register  ****************/
7839 
7840 #define DMA2D_BGOR_LO_Pos          (0U)
7841 #define DMA2D_BGOR_LO_Msk          (0x3FFFU << DMA2D_BGOR_LO_Pos)              /*!< 0x00003FFF */
7842 #define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
7843 
7844 /********************  Bit definition for DMA2D_FGPFCCR register  *************/
7845 
7846 #define DMA2D_FGPFCCR_CM_Pos       (0U)
7847 #define DMA2D_FGPFCCR_CM_Msk       (0xFU << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x0000000F */
7848 #define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
7849 #define DMA2D_FGPFCCR_CM_0         (0x1U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
7850 #define DMA2D_FGPFCCR_CM_1         (0x2U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
7851 #define DMA2D_FGPFCCR_CM_2         (0x4U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
7852 #define DMA2D_FGPFCCR_CM_3         (0x8U << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
7853 #define DMA2D_FGPFCCR_CCM_Pos      (4U)
7854 #define DMA2D_FGPFCCR_CCM_Msk      (0x1U << DMA2D_FGPFCCR_CCM_Pos)             /*!< 0x00000010 */
7855 #define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
7856 #define DMA2D_FGPFCCR_START_Pos    (5U)
7857 #define DMA2D_FGPFCCR_START_Msk    (0x1U << DMA2D_FGPFCCR_START_Pos)           /*!< 0x00000020 */
7858 #define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
7859 #define DMA2D_FGPFCCR_CS_Pos       (8U)
7860 #define DMA2D_FGPFCCR_CS_Msk       (0xFFU << DMA2D_FGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
7861 #define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
7862 #define DMA2D_FGPFCCR_AM_Pos       (16U)
7863 #define DMA2D_FGPFCCR_AM_Msk       (0x3U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00030000 */
7864 #define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
7865 #define DMA2D_FGPFCCR_AM_0         (0x1U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
7866 #define DMA2D_FGPFCCR_AM_1         (0x2U << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
7867 #define DMA2D_FGPFCCR_AI_Pos       (20U)
7868 #define DMA2D_FGPFCCR_AI_Msk       (0x1U << DMA2D_FGPFCCR_AI_Pos)              /*!< 0x00100000 */
7869 #define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Alpha Inverted */
7870 #define DMA2D_FGPFCCR_RBS_Pos      (21U)
7871 #define DMA2D_FGPFCCR_RBS_Msk      (0x1U << DMA2D_FGPFCCR_RBS_Pos)             /*!< 0x00200000 */
7872 #define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
7873 #define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
7874 #define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
7875 #define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
7876 
7877 /********************  Bit definition for DMA2D_FGCOLR register  **************/
7878 
7879 #define DMA2D_FGCOLR_BLUE_Pos      (0U)
7880 #define DMA2D_FGCOLR_BLUE_Msk      (0xFFU << DMA2D_FGCOLR_BLUE_Pos)            /*!< 0x000000FF */
7881 #define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Blue Value */
7882 #define DMA2D_FGCOLR_GREEN_Pos     (8U)
7883 #define DMA2D_FGCOLR_GREEN_Msk     (0xFFU << DMA2D_FGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
7884 #define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Green Value */
7885 #define DMA2D_FGCOLR_RED_Pos       (16U)
7886 #define DMA2D_FGCOLR_RED_Msk       (0xFFU << DMA2D_FGCOLR_RED_Pos)             /*!< 0x00FF0000 */
7887 #define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Red Value */
7888 
7889 /********************  Bit definition for DMA2D_BGPFCCR register  *************/
7890 
7891 #define DMA2D_BGPFCCR_CM_Pos       (0U)
7892 #define DMA2D_BGPFCCR_CM_Msk       (0xFU << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x0000000F */
7893 #define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
7894 #define DMA2D_BGPFCCR_CM_0         (0x1U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
7895 #define DMA2D_BGPFCCR_CM_1         (0x2U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
7896 #define DMA2D_BGPFCCR_CM_2         (0x4U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
7897 #define DMA2D_BGPFCCR_CM_3         (0x8U << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */
7898 #define DMA2D_BGPFCCR_CCM_Pos      (4U)
7899 #define DMA2D_BGPFCCR_CCM_Msk      (0x1U << DMA2D_BGPFCCR_CCM_Pos)             /*!< 0x00000010 */
7900 #define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
7901 #define DMA2D_BGPFCCR_START_Pos    (5U)
7902 #define DMA2D_BGPFCCR_START_Msk    (0x1U << DMA2D_BGPFCCR_START_Pos)           /*!< 0x00000020 */
7903 #define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
7904 #define DMA2D_BGPFCCR_CS_Pos       (8U)
7905 #define DMA2D_BGPFCCR_CS_Msk       (0xFFU << DMA2D_BGPFCCR_CS_Pos)             /*!< 0x0000FF00 */
7906 #define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
7907 #define DMA2D_BGPFCCR_AM_Pos       (16U)
7908 #define DMA2D_BGPFCCR_AM_Msk       (0x3U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00030000 */
7909 #define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
7910 #define DMA2D_BGPFCCR_AM_0         (0x1U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
7911 #define DMA2D_BGPFCCR_AM_1         (0x2U << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
7912 #define DMA2D_BGPFCCR_AI_Pos       (20U)
7913 #define DMA2D_BGPFCCR_AI_Msk       (0x1U << DMA2D_BGPFCCR_AI_Pos)              /*!< 0x00100000 */
7914 #define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< Alpha Inverted */
7915 #define DMA2D_BGPFCCR_RBS_Pos      (21U)
7916 #define DMA2D_BGPFCCR_RBS_Msk      (0x1U << DMA2D_BGPFCCR_RBS_Pos)             /*!< 0x00200000 */
7917 #define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Red Blue Swap */
7918 #define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
7919 #define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos)          /*!< 0xFF000000 */
7920 #define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< Alpha value */
7921 
7922 /********************  Bit definition for DMA2D_BGCOLR register  **************/
7923 
7924 #define DMA2D_BGCOLR_BLUE_Pos      (0U)
7925 #define DMA2D_BGCOLR_BLUE_Msk      (0xFFU << DMA2D_BGCOLR_BLUE_Pos)            /*!< 0x000000FF */
7926 #define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Blue Value */
7927 #define DMA2D_BGCOLR_GREEN_Pos     (8U)
7928 #define DMA2D_BGCOLR_GREEN_Msk     (0xFFU << DMA2D_BGCOLR_GREEN_Pos)           /*!< 0x0000FF00 */
7929 #define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Green Value */
7930 #define DMA2D_BGCOLR_RED_Pos       (16U)
7931 #define DMA2D_BGCOLR_RED_Msk       (0xFFU << DMA2D_BGCOLR_RED_Pos)             /*!< 0x00FF0000 */
7932 #define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Red Value */
7933 
7934 /********************  Bit definition for DMA2D_FGCMAR register  **************/
7935 
7936 #define DMA2D_FGCMAR_MA_Pos        (0U)
7937 #define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
7938 #define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Memory Address */
7939 
7940 /********************  Bit definition for DMA2D_BGCMAR register  **************/
7941 
7942 #define DMA2D_BGCMAR_MA_Pos        (0U)
7943 #define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos)        /*!< 0xFFFFFFFF */
7944 #define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Memory Address */
7945 
7946 /********************  Bit definition for DMA2D_OPFCCR register  **************/
7947 
7948 #define DMA2D_OPFCCR_CM_Pos        (0U)
7949 #define DMA2D_OPFCCR_CM_Msk        (0x7U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000007 */
7950 #define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Color mode CM[2:0] */
7951 #define DMA2D_OPFCCR_CM_0          (0x1U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000001 */
7952 #define DMA2D_OPFCCR_CM_1          (0x2U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000002 */
7953 #define DMA2D_OPFCCR_CM_2          (0x4U << DMA2D_OPFCCR_CM_Pos)               /*!< 0x00000004 */
7954 #define DMA2D_OPFCCR_AI_Pos        (20U)
7955 #define DMA2D_OPFCCR_AI_Msk        (0x1U << DMA2D_OPFCCR_AI_Pos)               /*!< 0x00100000 */
7956 #define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Alpha Inverted */
7957 #define DMA2D_OPFCCR_RBS_Pos       (21U)
7958 #define DMA2D_OPFCCR_RBS_Msk       (0x1U << DMA2D_OPFCCR_RBS_Pos)              /*!< 0x00200000 */
7959 #define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Red Blue Swap */
7960 
7961 /********************  Bit definition for DMA2D_OCOLR register  ***************/
7962 
7963 /*!<Mode_ARGB8888/RGB888 */
7964 
7965 #define DMA2D_OCOLR_BLUE_1         (0x000000FFU)                               /*!< Blue Value */
7966 #define DMA2D_OCOLR_GREEN_1        (0x0000FF00U)                               /*!< Green Value  */
7967 #define DMA2D_OCOLR_RED_1          (0x00FF0000U)                               /*!< Red Value */
7968 #define DMA2D_OCOLR_ALPHA_1        (0xFF000000U)                               /*!< Alpha Channel Value */
7969 
7970 /*!<Mode_RGB565 */
7971 #define DMA2D_OCOLR_BLUE_2         (0x0000001FU)                               /*!< Blue Value */
7972 #define DMA2D_OCOLR_GREEN_2        (0x000007E0U)                               /*!< Green Value  */
7973 #define DMA2D_OCOLR_RED_2          (0x0000F800U)                               /*!< Red Value */
7974 
7975 /*!<Mode_ARGB1555 */
7976 #define DMA2D_OCOLR_BLUE_3         (0x0000001FU)                               /*!< Blue Value */
7977 #define DMA2D_OCOLR_GREEN_3        (0x000003E0U)                               /*!< Green Value  */
7978 #define DMA2D_OCOLR_RED_3          (0x00007C00U)                               /*!< Red Value */
7979 #define DMA2D_OCOLR_ALPHA_3        (0x00008000U)                               /*!< Alpha Channel Value */
7980 
7981 /*!<Mode_ARGB4444 */
7982 #define DMA2D_OCOLR_BLUE_4         (0x0000000FU)                               /*!< Blue Value */
7983 #define DMA2D_OCOLR_GREEN_4        (0x000000F0U)                               /*!< Green Value  */
7984 #define DMA2D_OCOLR_RED_4          (0x00000F00U)                               /*!< Red Value */
7985 #define DMA2D_OCOLR_ALPHA_4        (0x0000F000U)                               /*!< Alpha Channel Value */
7986 
7987 /********************  Bit definition for DMA2D_OMAR register  ****************/
7988 
7989 #define DMA2D_OMAR_MA_Pos          (0U)
7990 #define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos)          /*!< 0xFFFFFFFF */
7991 #define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Memory Address */
7992 
7993 /********************  Bit definition for DMA2D_OOR register  *****************/
7994 
7995 #define DMA2D_OOR_LO_Pos           (0U)
7996 #define DMA2D_OOR_LO_Msk           (0x3FFFU << DMA2D_OOR_LO_Pos)               /*!< 0x00003FFF */
7997 #define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Line Offset */
7998 
7999 /********************  Bit definition for DMA2D_NLR register  *****************/
8000 
8001 #define DMA2D_NLR_NL_Pos           (0U)
8002 #define DMA2D_NLR_NL_Msk           (0xFFFFU << DMA2D_NLR_NL_Pos)               /*!< 0x0000FFFF */
8003 #define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
8004 #define DMA2D_NLR_PL_Pos           (16U)
8005 #define DMA2D_NLR_PL_Msk           (0x3FFFU << DMA2D_NLR_PL_Pos)               /*!< 0x3FFF0000 */
8006 #define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
8007 
8008 /********************  Bit definition for DMA2D_LWR register  *****************/
8009 
8010 #define DMA2D_LWR_LW_Pos           (0U)
8011 #define DMA2D_LWR_LW_Msk           (0xFFFFU << DMA2D_LWR_LW_Pos)               /*!< 0x0000FFFF */
8012 #define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
8013 
8014 /********************  Bit definition for DMA2D_AMTCR register  ***************/
8015 
8016 #define DMA2D_AMTCR_EN_Pos         (0U)
8017 #define DMA2D_AMTCR_EN_Msk         (0x1U << DMA2D_AMTCR_EN_Pos)                /*!< 0x00000001 */
8018 #define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
8019 #define DMA2D_AMTCR_DT_Pos         (8U)
8020 #define DMA2D_AMTCR_DT_Msk         (0xFFU << DMA2D_AMTCR_DT_Pos)               /*!< 0x0000FF00 */
8021 #define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
8022 
8023 /********************  Bit definition for DMA2D_FGCLUT register  **************/
8024 
8025 /********************  Bit definition for DMA2D_BGCLUT register  **************/
8026 
8027 /******************************************************************************/
8028 /*                                                                            */
8029 /*                    External Interrupt/Event Controller                     */
8030 /*                                                                            */
8031 /******************************************************************************/
8032 /*******************  Bit definition for EXTI_IMR1 register  ******************/
8033 #define EXTI_IMR1_IM0_Pos        (0U)
8034 #define EXTI_IMR1_IM0_Msk        (0x1U << EXTI_IMR1_IM0_Pos)                   /*!< 0x00000001 */
8035 #define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< Interrupt Mask on line 0 */
8036 #define EXTI_IMR1_IM1_Pos        (1U)
8037 #define EXTI_IMR1_IM1_Msk        (0x1U << EXTI_IMR1_IM1_Pos)                   /*!< 0x00000002 */
8038 #define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< Interrupt Mask on line 1 */
8039 #define EXTI_IMR1_IM2_Pos        (2U)
8040 #define EXTI_IMR1_IM2_Msk        (0x1U << EXTI_IMR1_IM2_Pos)                   /*!< 0x00000004 */
8041 #define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< Interrupt Mask on line 2 */
8042 #define EXTI_IMR1_IM3_Pos        (3U)
8043 #define EXTI_IMR1_IM3_Msk        (0x1U << EXTI_IMR1_IM3_Pos)                   /*!< 0x00000008 */
8044 #define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< Interrupt Mask on line 3 */
8045 #define EXTI_IMR1_IM4_Pos        (4U)
8046 #define EXTI_IMR1_IM4_Msk        (0x1U << EXTI_IMR1_IM4_Pos)                   /*!< 0x00000010 */
8047 #define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< Interrupt Mask on line 4 */
8048 #define EXTI_IMR1_IM5_Pos        (5U)
8049 #define EXTI_IMR1_IM5_Msk        (0x1U << EXTI_IMR1_IM5_Pos)                   /*!< 0x00000020 */
8050 #define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< Interrupt Mask on line 5 */
8051 #define EXTI_IMR1_IM6_Pos        (6U)
8052 #define EXTI_IMR1_IM6_Msk        (0x1U << EXTI_IMR1_IM6_Pos)                   /*!< 0x00000040 */
8053 #define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< Interrupt Mask on line 6 */
8054 #define EXTI_IMR1_IM7_Pos        (7U)
8055 #define EXTI_IMR1_IM7_Msk        (0x1U << EXTI_IMR1_IM7_Pos)                   /*!< 0x00000080 */
8056 #define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< Interrupt Mask on line 7 */
8057 #define EXTI_IMR1_IM8_Pos        (8U)
8058 #define EXTI_IMR1_IM8_Msk        (0x1U << EXTI_IMR1_IM8_Pos)                   /*!< 0x00000100 */
8059 #define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< Interrupt Mask on line 8 */
8060 #define EXTI_IMR1_IM9_Pos        (9U)
8061 #define EXTI_IMR1_IM9_Msk        (0x1U << EXTI_IMR1_IM9_Pos)                   /*!< 0x00000200 */
8062 #define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< Interrupt Mask on line 9 */
8063 #define EXTI_IMR1_IM10_Pos       (10U)
8064 #define EXTI_IMR1_IM10_Msk       (0x1U << EXTI_IMR1_IM10_Pos)                  /*!< 0x00000400 */
8065 #define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< Interrupt Mask on line 10 */
8066 #define EXTI_IMR1_IM11_Pos       (11U)
8067 #define EXTI_IMR1_IM11_Msk       (0x1U << EXTI_IMR1_IM11_Pos)                  /*!< 0x00000800 */
8068 #define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< Interrupt Mask on line 11 */
8069 #define EXTI_IMR1_IM12_Pos       (12U)
8070 #define EXTI_IMR1_IM12_Msk       (0x1U << EXTI_IMR1_IM12_Pos)                  /*!< 0x00001000 */
8071 #define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< Interrupt Mask on line 12 */
8072 #define EXTI_IMR1_IM13_Pos       (13U)
8073 #define EXTI_IMR1_IM13_Msk       (0x1U << EXTI_IMR1_IM13_Pos)                  /*!< 0x00002000 */
8074 #define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< Interrupt Mask on line 13 */
8075 #define EXTI_IMR1_IM14_Pos       (14U)
8076 #define EXTI_IMR1_IM14_Msk       (0x1U << EXTI_IMR1_IM14_Pos)                  /*!< 0x00004000 */
8077 #define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< Interrupt Mask on line 14 */
8078 #define EXTI_IMR1_IM15_Pos       (15U)
8079 #define EXTI_IMR1_IM15_Msk       (0x1U << EXTI_IMR1_IM15_Pos)                  /*!< 0x00008000 */
8080 #define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< Interrupt Mask on line 15 */
8081 #define EXTI_IMR1_IM16_Pos       (16U)
8082 #define EXTI_IMR1_IM16_Msk       (0x1U << EXTI_IMR1_IM16_Pos)                  /*!< 0x00010000 */
8083 #define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< Interrupt Mask on line 16 */
8084 #define EXTI_IMR1_IM17_Pos       (17U)
8085 #define EXTI_IMR1_IM17_Msk       (0x1U << EXTI_IMR1_IM17_Pos)                  /*!< 0x00020000 */
8086 #define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< Interrupt Mask on line 17 */
8087 #define EXTI_IMR1_IM18_Pos       (18U)
8088 #define EXTI_IMR1_IM18_Msk       (0x1U << EXTI_IMR1_IM18_Pos)                  /*!< 0x00040000 */
8089 #define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< Interrupt Mask on line 18 */
8090 #define EXTI_IMR1_IM19_Pos       (19U)
8091 #define EXTI_IMR1_IM19_Msk       (0x1U << EXTI_IMR1_IM19_Pos)                  /*!< 0x00080000 */
8092 #define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< Interrupt Mask on line 19 */
8093 #define EXTI_IMR1_IM20_Pos       (20U)
8094 #define EXTI_IMR1_IM20_Msk       (0x1U << EXTI_IMR1_IM20_Pos)                  /*!< 0x00100000 */
8095 #define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< Interrupt Mask on line 20 */
8096 #define EXTI_IMR1_IM21_Pos       (21U)
8097 #define EXTI_IMR1_IM21_Msk       (0x1U << EXTI_IMR1_IM21_Pos)                  /*!< 0x00200000 */
8098 #define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< Interrupt Mask on line 21 */
8099 #define EXTI_IMR1_IM22_Pos       (22U)
8100 #define EXTI_IMR1_IM22_Msk       (0x1U << EXTI_IMR1_IM22_Pos)                  /*!< 0x00400000 */
8101 #define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< Interrupt Mask on line 22 */
8102 #define EXTI_IMR1_IM23_Pos       (23U)
8103 #define EXTI_IMR1_IM23_Msk       (0x1U << EXTI_IMR1_IM23_Pos)                  /*!< 0x00800000 */
8104 #define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< Interrupt Mask on line 23 */
8105 #define EXTI_IMR1_IM24_Pos       (24U)
8106 #define EXTI_IMR1_IM24_Msk       (0x1U << EXTI_IMR1_IM24_Pos)                  /*!< 0x01000000 */
8107 #define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< Interrupt Mask on line 24 */
8108 #define EXTI_IMR1_IM25_Pos       (25U)
8109 #define EXTI_IMR1_IM25_Msk       (0x1U << EXTI_IMR1_IM25_Pos)                  /*!< 0x02000000 */
8110 #define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< Interrupt Mask on line 25 */
8111 #define EXTI_IMR1_IM26_Pos       (26U)
8112 #define EXTI_IMR1_IM26_Msk       (0x1U << EXTI_IMR1_IM26_Pos)                  /*!< 0x04000000 */
8113 #define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< Interrupt Mask on line 26 */
8114 #define EXTI_IMR1_IM27_Pos       (27U)
8115 #define EXTI_IMR1_IM27_Msk       (0x1U << EXTI_IMR1_IM27_Pos)                  /*!< 0x08000000 */
8116 #define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< Interrupt Mask on line 27 */
8117 #define EXTI_IMR1_IM28_Pos       (28U)
8118 #define EXTI_IMR1_IM28_Msk       (0x1U << EXTI_IMR1_IM28_Pos)                  /*!< 0x10000000 */
8119 #define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< Interrupt Mask on line 28 */
8120 #define EXTI_IMR1_IM29_Pos       (29U)
8121 #define EXTI_IMR1_IM29_Msk       (0x1U << EXTI_IMR1_IM29_Pos)                  /*!< 0x20000000 */
8122 #define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< Interrupt Mask on line 29 */
8123 #define EXTI_IMR1_IM30_Pos       (30U)
8124 #define EXTI_IMR1_IM30_Msk       (0x1U << EXTI_IMR1_IM30_Pos)                  /*!< 0x40000000 */
8125 #define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< Interrupt Mask on line 30 */
8126 #define EXTI_IMR1_IM31_Pos       (31U)
8127 #define EXTI_IMR1_IM31_Msk       (0x1U << EXTI_IMR1_IM31_Pos)                  /*!< 0x80000000 */
8128 #define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< Interrupt Mask on line 31 */
8129 #define EXTI_IMR1_IM_Pos         (0U)
8130 #define EXTI_IMR1_IM_Msk         (0xFFFFFFFFU << EXTI_IMR1_IM_Pos)             /*!< 0xFFFFFFFF */
8131 #define EXTI_IMR1_IM             EXTI_IMR1_IM_Msk                              /*!< Interrupt Mask All */
8132 
8133 /*******************  Bit definition for EXTI_EMR1 register  ******************/
8134 #define EXTI_EMR1_EM0_Pos        (0U)
8135 #define EXTI_EMR1_EM0_Msk        (0x1U << EXTI_EMR1_EM0_Pos)                   /*!< 0x00000001 */
8136 #define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< Event Mask on line 0 */
8137 #define EXTI_EMR1_EM1_Pos        (1U)
8138 #define EXTI_EMR1_EM1_Msk        (0x1U << EXTI_EMR1_EM1_Pos)                   /*!< 0x00000002 */
8139 #define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< Event Mask on line 1 */
8140 #define EXTI_EMR1_EM2_Pos        (2U)
8141 #define EXTI_EMR1_EM2_Msk        (0x1U << EXTI_EMR1_EM2_Pos)                   /*!< 0x00000004 */
8142 #define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< Event Mask on line 2 */
8143 #define EXTI_EMR1_EM3_Pos        (3U)
8144 #define EXTI_EMR1_EM3_Msk        (0x1U << EXTI_EMR1_EM3_Pos)                   /*!< 0x00000008 */
8145 #define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< Event Mask on line 3 */
8146 #define EXTI_EMR1_EM4_Pos        (4U)
8147 #define EXTI_EMR1_EM4_Msk        (0x1U << EXTI_EMR1_EM4_Pos)                   /*!< 0x00000010 */
8148 #define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< Event Mask on line 4 */
8149 #define EXTI_EMR1_EM5_Pos        (5U)
8150 #define EXTI_EMR1_EM5_Msk        (0x1U << EXTI_EMR1_EM5_Pos)                   /*!< 0x00000020 */
8151 #define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< Event Mask on line 5 */
8152 #define EXTI_EMR1_EM6_Pos        (6U)
8153 #define EXTI_EMR1_EM6_Msk        (0x1U << EXTI_EMR1_EM6_Pos)                   /*!< 0x00000040 */
8154 #define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< Event Mask on line 6 */
8155 #define EXTI_EMR1_EM7_Pos        (7U)
8156 #define EXTI_EMR1_EM7_Msk        (0x1U << EXTI_EMR1_EM7_Pos)                   /*!< 0x00000080 */
8157 #define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< Event Mask on line 7 */
8158 #define EXTI_EMR1_EM8_Pos        (8U)
8159 #define EXTI_EMR1_EM8_Msk        (0x1U << EXTI_EMR1_EM8_Pos)                   /*!< 0x00000100 */
8160 #define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< Event Mask on line 8 */
8161 #define EXTI_EMR1_EM9_Pos        (9U)
8162 #define EXTI_EMR1_EM9_Msk        (0x1U << EXTI_EMR1_EM9_Pos)                   /*!< 0x00000200 */
8163 #define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< Event Mask on line 9 */
8164 #define EXTI_EMR1_EM10_Pos       (10U)
8165 #define EXTI_EMR1_EM10_Msk       (0x1U << EXTI_EMR1_EM10_Pos)                  /*!< 0x00000400 */
8166 #define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< Event Mask on line 10 */
8167 #define EXTI_EMR1_EM11_Pos       (11U)
8168 #define EXTI_EMR1_EM11_Msk       (0x1U << EXTI_EMR1_EM11_Pos)                  /*!< 0x00000800 */
8169 #define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< Event Mask on line 11 */
8170 #define EXTI_EMR1_EM12_Pos       (12U)
8171 #define EXTI_EMR1_EM12_Msk       (0x1U << EXTI_EMR1_EM12_Pos)                  /*!< 0x00001000 */
8172 #define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< Event Mask on line 12 */
8173 #define EXTI_EMR1_EM13_Pos       (13U)
8174 #define EXTI_EMR1_EM13_Msk       (0x1U << EXTI_EMR1_EM13_Pos)                  /*!< 0x00002000 */
8175 #define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< Event Mask on line 13 */
8176 #define EXTI_EMR1_EM14_Pos       (14U)
8177 #define EXTI_EMR1_EM14_Msk       (0x1U << EXTI_EMR1_EM14_Pos)                  /*!< 0x00004000 */
8178 #define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< Event Mask on line 14 */
8179 #define EXTI_EMR1_EM15_Pos       (15U)
8180 #define EXTI_EMR1_EM15_Msk       (0x1U << EXTI_EMR1_EM15_Pos)                  /*!< 0x00008000 */
8181 #define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< Event Mask on line 15 */
8182 #define EXTI_EMR1_EM16_Pos       (16U)
8183 #define EXTI_EMR1_EM16_Msk       (0x1U << EXTI_EMR1_EM16_Pos)                  /*!< 0x00010000 */
8184 #define EXTI_EMR1_EM16           EXTI_EMR1_EM16_Msk                            /*!< Event Mask on line 16 */
8185 #define EXTI_EMR1_EM17_Pos       (17U)
8186 #define EXTI_EMR1_EM17_Msk       (0x1U << EXTI_EMR1_EM17_Pos)                  /*!< 0x00020000 */
8187 #define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< Event Mask on line 17 */
8188 #define EXTI_EMR1_EM18_Pos       (18U)
8189 #define EXTI_EMR1_EM18_Msk       (0x1U << EXTI_EMR1_EM18_Pos)                  /*!< 0x00040000 */
8190 #define EXTI_EMR1_EM18           EXTI_EMR1_EM18_Msk                            /*!< Event Mask on line 18 */
8191 #define EXTI_EMR1_EM19_Pos       (19U)
8192 #define EXTI_EMR1_EM19_Msk       (0x1U << EXTI_EMR1_EM19_Pos)                  /*!< 0x00080000 */
8193 #define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< Event Mask on line 19 */
8194 #define EXTI_EMR1_EM20_Pos       (20U)
8195 #define EXTI_EMR1_EM20_Msk       (0x1U << EXTI_EMR1_EM20_Pos)                  /*!< 0x00100000 */
8196 #define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< Event Mask on line 20 */
8197 #define EXTI_EMR1_EM21_Pos       (21U)
8198 #define EXTI_EMR1_EM21_Msk       (0x1U << EXTI_EMR1_EM21_Pos)                  /*!< 0x00200000 */
8199 #define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< Event Mask on line 21 */
8200 #define EXTI_EMR1_EM22_Pos       (22U)
8201 #define EXTI_EMR1_EM22_Msk       (0x1U << EXTI_EMR1_EM22_Pos)                  /*!< 0x00400000 */
8202 #define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< Event Mask on line 22 */
8203 #define EXTI_EMR1_EM23_Pos       (23U)
8204 #define EXTI_EMR1_EM23_Msk       (0x1U << EXTI_EMR1_EM23_Pos)                  /*!< 0x00800000 */
8205 #define EXTI_EMR1_EM23           EXTI_EMR1_EM23_Msk                            /*!< Event Mask on line 23 */
8206 #define EXTI_EMR1_EM24_Pos       (24U)
8207 #define EXTI_EMR1_EM24_Msk       (0x1U << EXTI_EMR1_EM24_Pos)                  /*!< 0x01000000 */
8208 #define EXTI_EMR1_EM24           EXTI_EMR1_EM24_Msk                            /*!< Event Mask on line 24 */
8209 #define EXTI_EMR1_EM25_Pos       (25U)
8210 #define EXTI_EMR1_EM25_Msk       (0x1U << EXTI_EMR1_EM25_Pos)                  /*!< 0x02000000 */
8211 #define EXTI_EMR1_EM25           EXTI_EMR1_EM25_Msk                            /*!< Event Mask on line 25 */
8212 #define EXTI_EMR1_EM26_Pos       (26U)
8213 #define EXTI_EMR1_EM26_Msk       (0x1U << EXTI_EMR1_EM26_Pos)                  /*!< 0x04000000 */
8214 #define EXTI_EMR1_EM26           EXTI_EMR1_EM26_Msk                            /*!< Event Mask on line 26 */
8215 #define EXTI_EMR1_EM27_Pos       (27U)
8216 #define EXTI_EMR1_EM27_Msk       (0x1U << EXTI_EMR1_EM27_Pos)                  /*!< 0x08000000 */
8217 #define EXTI_EMR1_EM27           EXTI_EMR1_EM27_Msk                            /*!< Event Mask on line 27 */
8218 #define EXTI_EMR1_EM28_Pos       (28U)
8219 #define EXTI_EMR1_EM28_Msk       (0x1U << EXTI_EMR1_EM28_Pos)                  /*!< 0x10000000 */
8220 #define EXTI_EMR1_EM28           EXTI_EMR1_EM28_Msk                            /*!< Event Mask on line 28 */
8221 #define EXTI_EMR1_EM29_Pos       (29U)
8222 #define EXTI_EMR1_EM29_Msk       (0x1U << EXTI_EMR1_EM29_Pos)                  /*!< 0x20000000 */
8223 #define EXTI_EMR1_EM29           EXTI_EMR1_EM29_Msk                            /*!< Event Mask on line 29 */
8224 #define EXTI_EMR1_EM30_Pos       (30U)
8225 #define EXTI_EMR1_EM30_Msk       (0x1U << EXTI_EMR1_EM30_Pos)                  /*!< 0x40000000 */
8226 #define EXTI_EMR1_EM30           EXTI_EMR1_EM30_Msk                            /*!< Event Mask on line 30 */
8227 #define EXTI_EMR1_EM31_Pos       (31U)
8228 #define EXTI_EMR1_EM31_Msk       (0x1U << EXTI_EMR1_EM31_Pos)                  /*!< 0x80000000 */
8229 #define EXTI_EMR1_EM31           EXTI_EMR1_EM31_Msk                            /*!< Event Mask on line 31 */
8230 
8231 /******************  Bit definition for EXTI_RTSR1 register  ******************/
8232 #define EXTI_RTSR1_RT0_Pos       (0U)
8233 #define EXTI_RTSR1_RT0_Msk       (0x1U << EXTI_RTSR1_RT0_Pos)                  /*!< 0x00000001 */
8234 #define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
8235 #define EXTI_RTSR1_RT1_Pos       (1U)
8236 #define EXTI_RTSR1_RT1_Msk       (0x1U << EXTI_RTSR1_RT1_Pos)                  /*!< 0x00000002 */
8237 #define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
8238 #define EXTI_RTSR1_RT2_Pos       (2U)
8239 #define EXTI_RTSR1_RT2_Msk       (0x1U << EXTI_RTSR1_RT2_Pos)                  /*!< 0x00000004 */
8240 #define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
8241 #define EXTI_RTSR1_RT3_Pos       (3U)
8242 #define EXTI_RTSR1_RT3_Msk       (0x1U << EXTI_RTSR1_RT3_Pos)                  /*!< 0x00000008 */
8243 #define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
8244 #define EXTI_RTSR1_RT4_Pos       (4U)
8245 #define EXTI_RTSR1_RT4_Msk       (0x1U << EXTI_RTSR1_RT4_Pos)                  /*!< 0x00000010 */
8246 #define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
8247 #define EXTI_RTSR1_RT5_Pos       (5U)
8248 #define EXTI_RTSR1_RT5_Msk       (0x1U << EXTI_RTSR1_RT5_Pos)                  /*!< 0x00000020 */
8249 #define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
8250 #define EXTI_RTSR1_RT6_Pos       (6U)
8251 #define EXTI_RTSR1_RT6_Msk       (0x1U << EXTI_RTSR1_RT6_Pos)                  /*!< 0x00000040 */
8252 #define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
8253 #define EXTI_RTSR1_RT7_Pos       (7U)
8254 #define EXTI_RTSR1_RT7_Msk       (0x1U << EXTI_RTSR1_RT7_Pos)                  /*!< 0x00000080 */
8255 #define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
8256 #define EXTI_RTSR1_RT8_Pos       (8U)
8257 #define EXTI_RTSR1_RT8_Msk       (0x1U << EXTI_RTSR1_RT8_Pos)                  /*!< 0x00000100 */
8258 #define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
8259 #define EXTI_RTSR1_RT9_Pos       (9U)
8260 #define EXTI_RTSR1_RT9_Msk       (0x1U << EXTI_RTSR1_RT9_Pos)                  /*!< 0x00000200 */
8261 #define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
8262 #define EXTI_RTSR1_RT10_Pos      (10U)
8263 #define EXTI_RTSR1_RT10_Msk      (0x1U << EXTI_RTSR1_RT10_Pos)                 /*!< 0x00000400 */
8264 #define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
8265 #define EXTI_RTSR1_RT11_Pos      (11U)
8266 #define EXTI_RTSR1_RT11_Msk      (0x1U << EXTI_RTSR1_RT11_Pos)                 /*!< 0x00000800 */
8267 #define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
8268 #define EXTI_RTSR1_RT12_Pos      (12U)
8269 #define EXTI_RTSR1_RT12_Msk      (0x1U << EXTI_RTSR1_RT12_Pos)                 /*!< 0x00001000 */
8270 #define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
8271 #define EXTI_RTSR1_RT13_Pos      (13U)
8272 #define EXTI_RTSR1_RT13_Msk      (0x1U << EXTI_RTSR1_RT13_Pos)                 /*!< 0x00002000 */
8273 #define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
8274 #define EXTI_RTSR1_RT14_Pos      (14U)
8275 #define EXTI_RTSR1_RT14_Msk      (0x1U << EXTI_RTSR1_RT14_Pos)                 /*!< 0x00004000 */
8276 #define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
8277 #define EXTI_RTSR1_RT15_Pos      (15U)
8278 #define EXTI_RTSR1_RT15_Msk      (0x1U << EXTI_RTSR1_RT15_Pos)                 /*!< 0x00008000 */
8279 #define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
8280 #define EXTI_RTSR1_RT16_Pos      (16U)
8281 #define EXTI_RTSR1_RT16_Msk      (0x1U << EXTI_RTSR1_RT16_Pos)                 /*!< 0x00010000 */
8282 #define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
8283 #define EXTI_RTSR1_RT18_Pos      (18U)
8284 #define EXTI_RTSR1_RT18_Msk      (0x1U << EXTI_RTSR1_RT18_Pos)                 /*!< 0x00040000 */
8285 #define EXTI_RTSR1_RT18          EXTI_RTSR1_RT18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
8286 #define EXTI_RTSR1_RT19_Pos      (19U)
8287 #define EXTI_RTSR1_RT19_Msk      (0x1U << EXTI_RTSR1_RT19_Pos)                 /*!< 0x00080000 */
8288 #define EXTI_RTSR1_RT19          EXTI_RTSR1_RT19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
8289 #define EXTI_RTSR1_RT20_Pos      (20U)
8290 #define EXTI_RTSR1_RT20_Msk      (0x1U << EXTI_RTSR1_RT20_Pos)                 /*!< 0x00100000 */
8291 #define EXTI_RTSR1_RT20          EXTI_RTSR1_RT20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
8292 #define EXTI_RTSR1_RT21_Pos      (21U)
8293 #define EXTI_RTSR1_RT21_Msk      (0x1U << EXTI_RTSR1_RT21_Pos)                 /*!< 0x00200000 */
8294 #define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
8295 #define EXTI_RTSR1_RT22_Pos      (22U)
8296 #define EXTI_RTSR1_RT22_Msk      (0x1U << EXTI_RTSR1_RT22_Pos)                 /*!< 0x00400000 */
8297 #define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
8298 
8299 /******************  Bit definition for EXTI_FTSR1 register  ******************/
8300 #define EXTI_FTSR1_FT0_Pos       (0U)
8301 #define EXTI_FTSR1_FT0_Msk       (0x1U << EXTI_FTSR1_FT0_Pos)                  /*!< 0x00000001 */
8302 #define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
8303 #define EXTI_FTSR1_FT1_Pos       (1U)
8304 #define EXTI_FTSR1_FT1_Msk       (0x1U << EXTI_FTSR1_FT1_Pos)                  /*!< 0x00000002 */
8305 #define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
8306 #define EXTI_FTSR1_FT2_Pos       (2U)
8307 #define EXTI_FTSR1_FT2_Msk       (0x1U << EXTI_FTSR1_FT2_Pos)                  /*!< 0x00000004 */
8308 #define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
8309 #define EXTI_FTSR1_FT3_Pos       (3U)
8310 #define EXTI_FTSR1_FT3_Msk       (0x1U << EXTI_FTSR1_FT3_Pos)                  /*!< 0x00000008 */
8311 #define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
8312 #define EXTI_FTSR1_FT4_Pos       (4U)
8313 #define EXTI_FTSR1_FT4_Msk       (0x1U << EXTI_FTSR1_FT4_Pos)                  /*!< 0x00000010 */
8314 #define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
8315 #define EXTI_FTSR1_FT5_Pos       (5U)
8316 #define EXTI_FTSR1_FT5_Msk       (0x1U << EXTI_FTSR1_FT5_Pos)                  /*!< 0x00000020 */
8317 #define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
8318 #define EXTI_FTSR1_FT6_Pos       (6U)
8319 #define EXTI_FTSR1_FT6_Msk       (0x1U << EXTI_FTSR1_FT6_Pos)                  /*!< 0x00000040 */
8320 #define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
8321 #define EXTI_FTSR1_FT7_Pos       (7U)
8322 #define EXTI_FTSR1_FT7_Msk       (0x1U << EXTI_FTSR1_FT7_Pos)                  /*!< 0x00000080 */
8323 #define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
8324 #define EXTI_FTSR1_FT8_Pos       (8U)
8325 #define EXTI_FTSR1_FT8_Msk       (0x1U << EXTI_FTSR1_FT8_Pos)                  /*!< 0x00000100 */
8326 #define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
8327 #define EXTI_FTSR1_FT9_Pos       (9U)
8328 #define EXTI_FTSR1_FT9_Msk       (0x1U << EXTI_FTSR1_FT9_Pos)                  /*!< 0x00000200 */
8329 #define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
8330 #define EXTI_FTSR1_FT10_Pos      (10U)
8331 #define EXTI_FTSR1_FT10_Msk      (0x1U << EXTI_FTSR1_FT10_Pos)                 /*!< 0x00000400 */
8332 #define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
8333 #define EXTI_FTSR1_FT11_Pos      (11U)
8334 #define EXTI_FTSR1_FT11_Msk      (0x1U << EXTI_FTSR1_FT11_Pos)                 /*!< 0x00000800 */
8335 #define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
8336 #define EXTI_FTSR1_FT12_Pos      (12U)
8337 #define EXTI_FTSR1_FT12_Msk      (0x1U << EXTI_FTSR1_FT12_Pos)                 /*!< 0x00001000 */
8338 #define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
8339 #define EXTI_FTSR1_FT13_Pos      (13U)
8340 #define EXTI_FTSR1_FT13_Msk      (0x1U << EXTI_FTSR1_FT13_Pos)                 /*!< 0x00002000 */
8341 #define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
8342 #define EXTI_FTSR1_FT14_Pos      (14U)
8343 #define EXTI_FTSR1_FT14_Msk      (0x1U << EXTI_FTSR1_FT14_Pos)                 /*!< 0x00004000 */
8344 #define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
8345 #define EXTI_FTSR1_FT15_Pos      (15U)
8346 #define EXTI_FTSR1_FT15_Msk      (0x1U << EXTI_FTSR1_FT15_Pos)                 /*!< 0x00008000 */
8347 #define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
8348 #define EXTI_FTSR1_FT16_Pos      (16U)
8349 #define EXTI_FTSR1_FT16_Msk      (0x1U << EXTI_FTSR1_FT16_Pos)                 /*!< 0x00010000 */
8350 #define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
8351 #define EXTI_FTSR1_FT18_Pos      (18U)
8352 #define EXTI_FTSR1_FT18_Msk      (0x1U << EXTI_FTSR1_FT18_Pos)                 /*!< 0x00040000 */
8353 #define EXTI_FTSR1_FT18          EXTI_FTSR1_FT18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
8354 #define EXTI_FTSR1_FT19_Pos      (19U)
8355 #define EXTI_FTSR1_FT19_Msk      (0x1U << EXTI_FTSR1_FT19_Pos)                 /*!< 0x00080000 */
8356 #define EXTI_FTSR1_FT19          EXTI_FTSR1_FT19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
8357 #define EXTI_FTSR1_FT20_Pos      (20U)
8358 #define EXTI_FTSR1_FT20_Msk      (0x1U << EXTI_FTSR1_FT20_Pos)                 /*!< 0x00100000 */
8359 #define EXTI_FTSR1_FT20          EXTI_FTSR1_FT20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
8360 #define EXTI_FTSR1_FT21_Pos      (21U)
8361 #define EXTI_FTSR1_FT21_Msk      (0x1U << EXTI_FTSR1_FT21_Pos)                 /*!< 0x00200000 */
8362 #define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
8363 #define EXTI_FTSR1_FT22_Pos      (22U)
8364 #define EXTI_FTSR1_FT22_Msk      (0x1U << EXTI_FTSR1_FT22_Pos)                 /*!< 0x00400000 */
8365 #define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
8366 
8367 /******************  Bit definition for EXTI_SWIER1 register  *****************/
8368 #define EXTI_SWIER1_SWI0_Pos     (0U)
8369 #define EXTI_SWIER1_SWI0_Msk     (0x1U << EXTI_SWIER1_SWI0_Pos)                /*!< 0x00000001 */
8370 #define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
8371 #define EXTI_SWIER1_SWI1_Pos     (1U)
8372 #define EXTI_SWIER1_SWI1_Msk     (0x1U << EXTI_SWIER1_SWI1_Pos)                /*!< 0x00000002 */
8373 #define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
8374 #define EXTI_SWIER1_SWI2_Pos     (2U)
8375 #define EXTI_SWIER1_SWI2_Msk     (0x1U << EXTI_SWIER1_SWI2_Pos)                /*!< 0x00000004 */
8376 #define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
8377 #define EXTI_SWIER1_SWI3_Pos     (3U)
8378 #define EXTI_SWIER1_SWI3_Msk     (0x1U << EXTI_SWIER1_SWI3_Pos)                /*!< 0x00000008 */
8379 #define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
8380 #define EXTI_SWIER1_SWI4_Pos     (4U)
8381 #define EXTI_SWIER1_SWI4_Msk     (0x1U << EXTI_SWIER1_SWI4_Pos)                /*!< 0x00000010 */
8382 #define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
8383 #define EXTI_SWIER1_SWI5_Pos     (5U)
8384 #define EXTI_SWIER1_SWI5_Msk     (0x1U << EXTI_SWIER1_SWI5_Pos)                /*!< 0x00000020 */
8385 #define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
8386 #define EXTI_SWIER1_SWI6_Pos     (6U)
8387 #define EXTI_SWIER1_SWI6_Msk     (0x1U << EXTI_SWIER1_SWI6_Pos)                /*!< 0x00000040 */
8388 #define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
8389 #define EXTI_SWIER1_SWI7_Pos     (7U)
8390 #define EXTI_SWIER1_SWI7_Msk     (0x1U << EXTI_SWIER1_SWI7_Pos)                /*!< 0x00000080 */
8391 #define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
8392 #define EXTI_SWIER1_SWI8_Pos     (8U)
8393 #define EXTI_SWIER1_SWI8_Msk     (0x1U << EXTI_SWIER1_SWI8_Pos)                /*!< 0x00000100 */
8394 #define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
8395 #define EXTI_SWIER1_SWI9_Pos     (9U)
8396 #define EXTI_SWIER1_SWI9_Msk     (0x1U << EXTI_SWIER1_SWI9_Pos)                /*!< 0x00000200 */
8397 #define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
8398 #define EXTI_SWIER1_SWI10_Pos    (10U)
8399 #define EXTI_SWIER1_SWI10_Msk    (0x1U << EXTI_SWIER1_SWI10_Pos)               /*!< 0x00000400 */
8400 #define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
8401 #define EXTI_SWIER1_SWI11_Pos    (11U)
8402 #define EXTI_SWIER1_SWI11_Msk    (0x1U << EXTI_SWIER1_SWI11_Pos)               /*!< 0x00000800 */
8403 #define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
8404 #define EXTI_SWIER1_SWI12_Pos    (12U)
8405 #define EXTI_SWIER1_SWI12_Msk    (0x1U << EXTI_SWIER1_SWI12_Pos)               /*!< 0x00001000 */
8406 #define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
8407 #define EXTI_SWIER1_SWI13_Pos    (13U)
8408 #define EXTI_SWIER1_SWI13_Msk    (0x1U << EXTI_SWIER1_SWI13_Pos)               /*!< 0x00002000 */
8409 #define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
8410 #define EXTI_SWIER1_SWI14_Pos    (14U)
8411 #define EXTI_SWIER1_SWI14_Msk    (0x1U << EXTI_SWIER1_SWI14_Pos)               /*!< 0x00004000 */
8412 #define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
8413 #define EXTI_SWIER1_SWI15_Pos    (15U)
8414 #define EXTI_SWIER1_SWI15_Msk    (0x1U << EXTI_SWIER1_SWI15_Pos)               /*!< 0x00008000 */
8415 #define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
8416 #define EXTI_SWIER1_SWI16_Pos    (16U)
8417 #define EXTI_SWIER1_SWI16_Msk    (0x1U << EXTI_SWIER1_SWI16_Pos)               /*!< 0x00010000 */
8418 #define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
8419 #define EXTI_SWIER1_SWI18_Pos    (18U)
8420 #define EXTI_SWIER1_SWI18_Msk    (0x1U << EXTI_SWIER1_SWI18_Pos)               /*!< 0x00040000 */
8421 #define EXTI_SWIER1_SWI18        EXTI_SWIER1_SWI18_Msk                         /*!< Software Interrupt on line 18 */
8422 #define EXTI_SWIER1_SWI19_Pos    (19U)
8423 #define EXTI_SWIER1_SWI19_Msk    (0x1U << EXTI_SWIER1_SWI19_Pos)               /*!< 0x00080000 */
8424 #define EXTI_SWIER1_SWI19        EXTI_SWIER1_SWI19_Msk                         /*!< Software Interrupt on line 19 */
8425 #define EXTI_SWIER1_SWI20_Pos    (20U)
8426 #define EXTI_SWIER1_SWI20_Msk    (0x1U << EXTI_SWIER1_SWI20_Pos)               /*!< 0x00100000 */
8427 #define EXTI_SWIER1_SWI20        EXTI_SWIER1_SWI20_Msk                         /*!< Software Interrupt on line 20 */
8428 #define EXTI_SWIER1_SWI21_Pos    (21U)
8429 #define EXTI_SWIER1_SWI21_Msk    (0x1U << EXTI_SWIER1_SWI21_Pos)               /*!< 0x00200000 */
8430 #define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
8431 #define EXTI_SWIER1_SWI22_Pos    (22U)
8432 #define EXTI_SWIER1_SWI22_Msk    (0x1U << EXTI_SWIER1_SWI22_Pos)               /*!< 0x00400000 */
8433 #define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
8434 
8435 /*******************  Bit definition for EXTI_PR1 register  *******************/
8436 #define EXTI_PR1_PIF0_Pos        (0U)
8437 #define EXTI_PR1_PIF0_Msk        (0x1U << EXTI_PR1_PIF0_Pos)                   /*!< 0x00000001 */
8438 #define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
8439 #define EXTI_PR1_PIF1_Pos        (1U)
8440 #define EXTI_PR1_PIF1_Msk        (0x1U << EXTI_PR1_PIF1_Pos)                   /*!< 0x00000002 */
8441 #define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
8442 #define EXTI_PR1_PIF2_Pos        (2U)
8443 #define EXTI_PR1_PIF2_Msk        (0x1U << EXTI_PR1_PIF2_Pos)                   /*!< 0x00000004 */
8444 #define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
8445 #define EXTI_PR1_PIF3_Pos        (3U)
8446 #define EXTI_PR1_PIF3_Msk        (0x1U << EXTI_PR1_PIF3_Pos)                   /*!< 0x00000008 */
8447 #define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
8448 #define EXTI_PR1_PIF4_Pos        (4U)
8449 #define EXTI_PR1_PIF4_Msk        (0x1U << EXTI_PR1_PIF4_Pos)                   /*!< 0x00000010 */
8450 #define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
8451 #define EXTI_PR1_PIF5_Pos        (5U)
8452 #define EXTI_PR1_PIF5_Msk        (0x1U << EXTI_PR1_PIF5_Pos)                   /*!< 0x00000020 */
8453 #define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
8454 #define EXTI_PR1_PIF6_Pos        (6U)
8455 #define EXTI_PR1_PIF6_Msk        (0x1U << EXTI_PR1_PIF6_Pos)                   /*!< 0x00000040 */
8456 #define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
8457 #define EXTI_PR1_PIF7_Pos        (7U)
8458 #define EXTI_PR1_PIF7_Msk        (0x1U << EXTI_PR1_PIF7_Pos)                   /*!< 0x00000080 */
8459 #define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
8460 #define EXTI_PR1_PIF8_Pos        (8U)
8461 #define EXTI_PR1_PIF8_Msk        (0x1U << EXTI_PR1_PIF8_Pos)                   /*!< 0x00000100 */
8462 #define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
8463 #define EXTI_PR1_PIF9_Pos        (9U)
8464 #define EXTI_PR1_PIF9_Msk        (0x1U << EXTI_PR1_PIF9_Pos)                   /*!< 0x00000200 */
8465 #define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
8466 #define EXTI_PR1_PIF10_Pos       (10U)
8467 #define EXTI_PR1_PIF10_Msk       (0x1U << EXTI_PR1_PIF10_Pos)                  /*!< 0x00000400 */
8468 #define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
8469 #define EXTI_PR1_PIF11_Pos       (11U)
8470 #define EXTI_PR1_PIF11_Msk       (0x1U << EXTI_PR1_PIF11_Pos)                  /*!< 0x00000800 */
8471 #define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
8472 #define EXTI_PR1_PIF12_Pos       (12U)
8473 #define EXTI_PR1_PIF12_Msk       (0x1U << EXTI_PR1_PIF12_Pos)                  /*!< 0x00001000 */
8474 #define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
8475 #define EXTI_PR1_PIF13_Pos       (13U)
8476 #define EXTI_PR1_PIF13_Msk       (0x1U << EXTI_PR1_PIF13_Pos)                  /*!< 0x00002000 */
8477 #define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
8478 #define EXTI_PR1_PIF14_Pos       (14U)
8479 #define EXTI_PR1_PIF14_Msk       (0x1U << EXTI_PR1_PIF14_Pos)                  /*!< 0x00004000 */
8480 #define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
8481 #define EXTI_PR1_PIF15_Pos       (15U)
8482 #define EXTI_PR1_PIF15_Msk       (0x1U << EXTI_PR1_PIF15_Pos)                  /*!< 0x00008000 */
8483 #define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
8484 #define EXTI_PR1_PIF16_Pos       (16U)
8485 #define EXTI_PR1_PIF16_Msk       (0x1U << EXTI_PR1_PIF16_Pos)                  /*!< 0x00010000 */
8486 #define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
8487 #define EXTI_PR1_PIF18_Pos       (18U)
8488 #define EXTI_PR1_PIF18_Msk       (0x1U << EXTI_PR1_PIF18_Pos)                  /*!< 0x00040000 */
8489 #define EXTI_PR1_PIF18           EXTI_PR1_PIF18_Msk                            /*!< Pending bit for line 18 */
8490 #define EXTI_PR1_PIF19_Pos       (19U)
8491 #define EXTI_PR1_PIF19_Msk       (0x1U << EXTI_PR1_PIF19_Pos)                  /*!< 0x00080000 */
8492 #define EXTI_PR1_PIF19           EXTI_PR1_PIF19_Msk                            /*!< Pending bit for line 19 */
8493 #define EXTI_PR1_PIF20_Pos       (20U)
8494 #define EXTI_PR1_PIF20_Msk       (0x1U << EXTI_PR1_PIF20_Pos)                  /*!< 0x00100000 */
8495 #define EXTI_PR1_PIF20           EXTI_PR1_PIF20_Msk                            /*!< Pending bit for line 20 */
8496 #define EXTI_PR1_PIF21_Pos       (21U)
8497 #define EXTI_PR1_PIF21_Msk       (0x1U << EXTI_PR1_PIF21_Pos)                  /*!< 0x00200000 */
8498 #define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
8499 #define EXTI_PR1_PIF22_Pos       (22U)
8500 #define EXTI_PR1_PIF22_Msk       (0x1U << EXTI_PR1_PIF22_Pos)                  /*!< 0x00400000 */
8501 #define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
8502 
8503 /*******************  Bit definition for EXTI_IMR2 register  ******************/
8504 #define EXTI_IMR2_IM32_Pos       (0U)
8505 #define EXTI_IMR2_IM32_Msk       (0x1U << EXTI_IMR2_IM32_Pos)                  /*!< 0x00000001 */
8506 #define EXTI_IMR2_IM32           EXTI_IMR2_IM32_Msk                            /*!< Interrupt Mask on line 32 */
8507 #define EXTI_IMR2_IM33_Pos       (1U)
8508 #define EXTI_IMR2_IM33_Msk       (0x1U << EXTI_IMR2_IM33_Pos)                  /*!< 0x00000002 */
8509 #define EXTI_IMR2_IM33           EXTI_IMR2_IM33_Msk                            /*!< Interrupt Mask on line 33 */
8510 #define EXTI_IMR2_IM34_Pos       (2U)
8511 #define EXTI_IMR2_IM34_Msk       (0x1U << EXTI_IMR2_IM34_Pos)                  /*!< 0x00000004 */
8512 #define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< Interrupt Mask on line 34 */
8513 #define EXTI_IMR2_IM35_Pos       (3U)
8514 #define EXTI_IMR2_IM35_Msk       (0x1U << EXTI_IMR2_IM35_Pos)                  /*!< 0x00000008 */
8515 #define EXTI_IMR2_IM35           EXTI_IMR2_IM35_Msk                            /*!< Interrupt Mask on line 35 */
8516 #define EXTI_IMR2_IM36_Pos       (4U)
8517 #define EXTI_IMR2_IM36_Msk       (0x1U << EXTI_IMR2_IM36_Pos)                  /*!< 0x00000010 */
8518 #define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< Interrupt Mask on line 36 */
8519 #define EXTI_IMR2_IM37_Pos       (5U)
8520 #define EXTI_IMR2_IM37_Msk       (0x1U << EXTI_IMR2_IM37_Pos)                  /*!< 0x00000020 */
8521 #define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< Interrupt Mask on line 37 */
8522 #define EXTI_IMR2_IM38_Pos       (6U)
8523 #define EXTI_IMR2_IM38_Msk       (0x1U << EXTI_IMR2_IM38_Pos)                  /*!< 0x00000040 */
8524 #define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< Interrupt Mask on line 38 */
8525 #define EXTI_IMR2_IM39_Pos       (7U)
8526 #define EXTI_IMR2_IM39_Msk       (0x1U << EXTI_IMR2_IM39_Pos)                  /*!< 0x00000080 */
8527 #define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< Interrupt Mask on line 39 */
8528 #define EXTI_IMR2_IM40_Pos       (8U)
8529 #define EXTI_IMR2_IM40_Msk       (0x1U << EXTI_IMR2_IM40_Pos)                  /*!< 0x00000100 */
8530 #define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< Interrupt Mask on line 40 */
8531 #define EXTI_IMR2_IM_Pos         (0U)
8532 #define EXTI_IMR2_IM_Msk         (0x1FFU << EXTI_IMR2_IM_Pos)                  /*!< 0x000001FF */
8533 #define EXTI_IMR2_IM             EXTI_IMR2_IM_Msk                              /*!< Interrupt Mask all        */
8534 
8535 /*******************  Bit definition for EXTI_EMR2 register  ******************/
8536 #define EXTI_EMR2_EM32_Pos       (0U)
8537 #define EXTI_EMR2_EM32_Msk       (0x1U << EXTI_EMR2_EM32_Pos)                  /*!< 0x00000001 */
8538 #define EXTI_EMR2_EM32           EXTI_EMR2_EM32_Msk                            /*!< Event Mask on line 32 */
8539 #define EXTI_EMR2_EM33_Pos       (1U)
8540 #define EXTI_EMR2_EM33_Msk       (0x1U << EXTI_EMR2_EM33_Pos)                  /*!< 0x00000002 */
8541 #define EXTI_EMR2_EM33           EXTI_EMR2_EM33_Msk                            /*!< Event Mask on line 33 */
8542 #define EXTI_EMR2_EM34_Pos       (2U)
8543 #define EXTI_EMR2_EM34_Msk       (0x1U << EXTI_EMR2_EM34_Pos)                  /*!< 0x00000004 */
8544 #define EXTI_EMR2_EM34           EXTI_EMR2_EM34_Msk                            /*!< Event Mask on line 34 */
8545 #define EXTI_EMR2_EM35_Pos       (3U)
8546 #define EXTI_EMR2_EM35_Msk       (0x1U << EXTI_EMR2_EM35_Pos)                  /*!< 0x00000008 */
8547 #define EXTI_EMR2_EM35           EXTI_EMR2_EM35_Msk                            /*!< Event Mask on line 35 */
8548 #define EXTI_EMR2_EM36_Pos       (4U)
8549 #define EXTI_EMR2_EM36_Msk       (0x1U << EXTI_EMR2_EM36_Pos)                  /*!< 0x00000010 */
8550 #define EXTI_EMR2_EM36           EXTI_EMR2_EM36_Msk                            /*!< Event Mask on line 36 */
8551 #define EXTI_EMR2_EM37_Pos       (5U)
8552 #define EXTI_EMR2_EM37_Msk       (0x1U << EXTI_EMR2_EM37_Pos)                  /*!< 0x00000020 */
8553 #define EXTI_EMR2_EM37           EXTI_EMR2_EM37_Msk                            /*!< Event Mask on line 37 */
8554 #define EXTI_EMR2_EM38_Pos       (6U)
8555 #define EXTI_EMR2_EM38_Msk       (0x1U << EXTI_EMR2_EM38_Pos)                  /*!< 0x00000040 */
8556 #define EXTI_EMR2_EM38           EXTI_EMR2_EM38_Msk                            /*!< Event Mask on line 38 */
8557 #define EXTI_EMR2_EM39_Pos       (7U)
8558 #define EXTI_EMR2_EM39_Msk       (0x1U << EXTI_EMR2_EM39_Pos)                  /*!< 0x00000080 */
8559 #define EXTI_EMR2_EM39           EXTI_EMR2_EM39_Msk                            /*!< Event Mask on line 39 */
8560 #define EXTI_EMR2_EM40_Pos       (8U)
8561 #define EXTI_EMR2_EM40_Msk       (0x1U << EXTI_EMR2_EM40_Pos)                  /*!< 0x00000100 */
8562 #define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< Event Mask on line 40 */
8563 #define EXTI_EMR2_EM_Pos         (0U)
8564 #define EXTI_EMR2_EM_Msk         (0x1FFU << EXTI_EMR2_EM_Pos)                  /*!< 0x000001FF */
8565 #define EXTI_EMR2_EM             EXTI_EMR2_EM_Msk                              /*!< Interrupt Mask all        */
8566 
8567 /******************  Bit definition for EXTI_RTSR2 register  ******************/
8568 #define EXTI_RTSR2_RT35_Pos      (3U)
8569 #define EXTI_RTSR2_RT35_Msk      (0x1U << EXTI_RTSR2_RT35_Pos)                 /*!< 0x00000008 */
8570 #define EXTI_RTSR2_RT35          EXTI_RTSR2_RT35_Msk                           /*!< Rising trigger event configuration bit of line 35 */
8571 #define EXTI_RTSR2_RT36_Pos      (4U)
8572 #define EXTI_RTSR2_RT36_Msk      (0x1U << EXTI_RTSR2_RT36_Pos)                 /*!< 0x00000010 */
8573 #define EXTI_RTSR2_RT36          EXTI_RTSR2_RT36_Msk                           /*!< Rising trigger event configuration bit of line 36 */
8574 #define EXTI_RTSR2_RT37_Pos      (5U)
8575 #define EXTI_RTSR2_RT37_Msk      (0x1U << EXTI_RTSR2_RT37_Pos)                 /*!< 0x00000020 */
8576 #define EXTI_RTSR2_RT37          EXTI_RTSR2_RT37_Msk                           /*!< Rising trigger event configuration bit of line 37 */
8577 #define EXTI_RTSR2_RT38_Pos      (6U)
8578 #define EXTI_RTSR2_RT38_Msk      (0x1U << EXTI_RTSR2_RT38_Pos)                 /*!< 0x00000040 */
8579 #define EXTI_RTSR2_RT38          EXTI_RTSR2_RT38_Msk                           /*!< Rising trigger event configuration bit of line 38 */
8580 
8581 /******************  Bit definition for EXTI_FTSR2 register  ******************/
8582 #define EXTI_FTSR2_FT35_Pos      (3U)
8583 #define EXTI_FTSR2_FT35_Msk      (0x1U << EXTI_FTSR2_FT35_Pos)                 /*!< 0x00000008 */
8584 #define EXTI_FTSR2_FT35          EXTI_FTSR2_FT35_Msk                           /*!< Falling trigger event configuration bit of line 35 */
8585 #define EXTI_FTSR2_FT36_Pos      (4U)
8586 #define EXTI_FTSR2_FT36_Msk      (0x1U << EXTI_FTSR2_FT36_Pos)                 /*!< 0x00000010 */
8587 #define EXTI_FTSR2_FT36          EXTI_FTSR2_FT36_Msk                           /*!< Falling trigger event configuration bit of line 36 */
8588 #define EXTI_FTSR2_FT37_Pos      (5U)
8589 #define EXTI_FTSR2_FT37_Msk      (0x1U << EXTI_FTSR2_FT37_Pos)                 /*!< 0x00000020 */
8590 #define EXTI_FTSR2_FT37          EXTI_FTSR2_FT37_Msk                           /*!< Falling trigger event configuration bit of line 37 */
8591 #define EXTI_FTSR2_FT38_Pos      (6U)
8592 #define EXTI_FTSR2_FT38_Msk      (0x1U << EXTI_FTSR2_FT38_Pos)                 /*!< 0x00000040 */
8593 #define EXTI_FTSR2_FT38          EXTI_FTSR2_FT38_Msk                           /*!< Falling trigger event configuration bit of line 38 */
8594 
8595 /******************  Bit definition for EXTI_SWIER2 register  *****************/
8596 #define EXTI_SWIER2_SWI35_Pos    (3U)
8597 #define EXTI_SWIER2_SWI35_Msk    (0x1U << EXTI_SWIER2_SWI35_Pos)               /*!< 0x00000008 */
8598 #define EXTI_SWIER2_SWI35        EXTI_SWIER2_SWI35_Msk                         /*!< Software Interrupt on line 35 */
8599 #define EXTI_SWIER2_SWI36_Pos    (4U)
8600 #define EXTI_SWIER2_SWI36_Msk    (0x1U << EXTI_SWIER2_SWI36_Pos)               /*!< 0x00000010 */
8601 #define EXTI_SWIER2_SWI36        EXTI_SWIER2_SWI36_Msk                         /*!< Software Interrupt on line 36 */
8602 #define EXTI_SWIER2_SWI37_Pos    (5U)
8603 #define EXTI_SWIER2_SWI37_Msk    (0x1U << EXTI_SWIER2_SWI37_Pos)               /*!< 0x00000020 */
8604 #define EXTI_SWIER2_SWI37        EXTI_SWIER2_SWI37_Msk                         /*!< Software Interrupt on line 37 */
8605 #define EXTI_SWIER2_SWI38_Pos    (6U)
8606 #define EXTI_SWIER2_SWI38_Msk    (0x1U << EXTI_SWIER2_SWI38_Pos)               /*!< 0x00000040 */
8607 #define EXTI_SWIER2_SWI38        EXTI_SWIER2_SWI38_Msk                         /*!< Software Interrupt on line 38 */
8608 
8609 /*******************  Bit definition for EXTI_PR2 register  *******************/
8610 #define EXTI_PR2_PIF35_Pos       (3U)
8611 #define EXTI_PR2_PIF35_Msk       (0x1U << EXTI_PR2_PIF35_Pos)                  /*!< 0x00000008 */
8612 #define EXTI_PR2_PIF35           EXTI_PR2_PIF35_Msk                            /*!< Pending bit for line 35 */
8613 #define EXTI_PR2_PIF36_Pos       (4U)
8614 #define EXTI_PR2_PIF36_Msk       (0x1U << EXTI_PR2_PIF36_Pos)                  /*!< 0x00000010 */
8615 #define EXTI_PR2_PIF36           EXTI_PR2_PIF36_Msk                            /*!< Pending bit for line 36 */
8616 #define EXTI_PR2_PIF37_Pos       (5U)
8617 #define EXTI_PR2_PIF37_Msk       (0x1U << EXTI_PR2_PIF37_Pos)                  /*!< 0x00000020 */
8618 #define EXTI_PR2_PIF37           EXTI_PR2_PIF37_Msk                            /*!< Pending bit for line 37 */
8619 #define EXTI_PR2_PIF38_Pos       (6U)
8620 #define EXTI_PR2_PIF38_Msk       (0x1U << EXTI_PR2_PIF38_Pos)                  /*!< 0x00000040 */
8621 #define EXTI_PR2_PIF38           EXTI_PR2_PIF38_Msk                            /*!< Pending bit for line 38 */
8622 
8623 
8624 /******************************************************************************/
8625 /*                                                                            */
8626 /*                                    FLASH                                   */
8627 /*                                                                            */
8628 /******************************************************************************/
8629 /*******************  Bits definition for FLASH_ACR register  *****************/
8630 #define FLASH_ACR_LATENCY_Pos             (0U)
8631 #define FLASH_ACR_LATENCY_Msk             (0x7U << FLASH_ACR_LATENCY_Pos)      /*!< 0x00000007 */
8632 #define FLASH_ACR_LATENCY                 FLASH_ACR_LATENCY_Msk
8633 #define FLASH_ACR_LATENCY_0WS             (0x00000000U)
8634 #define FLASH_ACR_LATENCY_1WS             (0x00000001U)
8635 #define FLASH_ACR_LATENCY_2WS             (0x00000002U)
8636 #define FLASH_ACR_LATENCY_3WS             (0x00000003U)
8637 #define FLASH_ACR_LATENCY_4WS             (0x00000004U)
8638 #define FLASH_ACR_PRFTEN_Pos              (8U)
8639 #define FLASH_ACR_PRFTEN_Msk              (0x1U << FLASH_ACR_PRFTEN_Pos)       /*!< 0x00000100 */
8640 #define FLASH_ACR_PRFTEN                  FLASH_ACR_PRFTEN_Msk
8641 #define FLASH_ACR_ICEN_Pos                (9U)
8642 #define FLASH_ACR_ICEN_Msk                (0x1U << FLASH_ACR_ICEN_Pos)         /*!< 0x00000200 */
8643 #define FLASH_ACR_ICEN                    FLASH_ACR_ICEN_Msk
8644 #define FLASH_ACR_DCEN_Pos                (10U)
8645 #define FLASH_ACR_DCEN_Msk                (0x1U << FLASH_ACR_DCEN_Pos)         /*!< 0x00000400 */
8646 #define FLASH_ACR_DCEN                    FLASH_ACR_DCEN_Msk
8647 #define FLASH_ACR_ICRST_Pos               (11U)
8648 #define FLASH_ACR_ICRST_Msk               (0x1U << FLASH_ACR_ICRST_Pos)        /*!< 0x00000800 */
8649 #define FLASH_ACR_ICRST                   FLASH_ACR_ICRST_Msk
8650 #define FLASH_ACR_DCRST_Pos               (12U)
8651 #define FLASH_ACR_DCRST_Msk               (0x1U << FLASH_ACR_DCRST_Pos)        /*!< 0x00001000 */
8652 #define FLASH_ACR_DCRST                   FLASH_ACR_DCRST_Msk
8653 #define FLASH_ACR_RUN_PD_Pos              (13U)
8654 #define FLASH_ACR_RUN_PD_Msk              (0x1U << FLASH_ACR_RUN_PD_Pos)       /*!< 0x00002000 */
8655 #define FLASH_ACR_RUN_PD                  FLASH_ACR_RUN_PD_Msk                 /*!< Flash power down mode during run */
8656 #define FLASH_ACR_SLEEP_PD_Pos            (14U)
8657 #define FLASH_ACR_SLEEP_PD_Msk            (0x1U << FLASH_ACR_SLEEP_PD_Pos)     /*!< 0x00004000 */
8658 #define FLASH_ACR_SLEEP_PD                FLASH_ACR_SLEEP_PD_Msk               /*!< Flash power down mode during sleep */
8659 
8660 /*******************  Bits definition for FLASH_SR register  ******************/
8661 #define FLASH_SR_EOP_Pos                  (0U)
8662 #define FLASH_SR_EOP_Msk                  (0x1U << FLASH_SR_EOP_Pos)           /*!< 0x00000001 */
8663 #define FLASH_SR_EOP                      FLASH_SR_EOP_Msk
8664 #define FLASH_SR_OPERR_Pos                (1U)
8665 #define FLASH_SR_OPERR_Msk                (0x1U << FLASH_SR_OPERR_Pos)         /*!< 0x00000002 */
8666 #define FLASH_SR_OPERR                    FLASH_SR_OPERR_Msk
8667 #define FLASH_SR_PROGERR_Pos              (3U)
8668 #define FLASH_SR_PROGERR_Msk              (0x1U << FLASH_SR_PROGERR_Pos)       /*!< 0x00000008 */
8669 #define FLASH_SR_PROGERR                  FLASH_SR_PROGERR_Msk
8670 #define FLASH_SR_WRPERR_Pos               (4U)
8671 #define FLASH_SR_WRPERR_Msk               (0x1U << FLASH_SR_WRPERR_Pos)        /*!< 0x00000010 */
8672 #define FLASH_SR_WRPERR                   FLASH_SR_WRPERR_Msk
8673 #define FLASH_SR_PGAERR_Pos               (5U)
8674 #define FLASH_SR_PGAERR_Msk               (0x1U << FLASH_SR_PGAERR_Pos)        /*!< 0x00000020 */
8675 #define FLASH_SR_PGAERR                   FLASH_SR_PGAERR_Msk
8676 #define FLASH_SR_SIZERR_Pos               (6U)
8677 #define FLASH_SR_SIZERR_Msk               (0x1U << FLASH_SR_SIZERR_Pos)        /*!< 0x00000040 */
8678 #define FLASH_SR_SIZERR                   FLASH_SR_SIZERR_Msk
8679 #define FLASH_SR_PGSERR_Pos               (7U)
8680 #define FLASH_SR_PGSERR_Msk               (0x1U << FLASH_SR_PGSERR_Pos)        /*!< 0x00000080 */
8681 #define FLASH_SR_PGSERR                   FLASH_SR_PGSERR_Msk
8682 #define FLASH_SR_MISERR_Pos               (8U)
8683 #define FLASH_SR_MISERR_Msk               (0x1U << FLASH_SR_MISERR_Pos)        /*!< 0x00000100 */
8684 #define FLASH_SR_MISERR                   FLASH_SR_MISERR_Msk
8685 #define FLASH_SR_FASTERR_Pos              (9U)
8686 #define FLASH_SR_FASTERR_Msk              (0x1U << FLASH_SR_FASTERR_Pos)       /*!< 0x00000200 */
8687 #define FLASH_SR_FASTERR                  FLASH_SR_FASTERR_Msk
8688 #define FLASH_SR_RDERR_Pos                (14U)
8689 #define FLASH_SR_RDERR_Msk                (0x1U << FLASH_SR_RDERR_Pos)         /*!< 0x00004000 */
8690 #define FLASH_SR_RDERR                    FLASH_SR_RDERR_Msk
8691 #define FLASH_SR_OPTVERR_Pos              (15U)
8692 #define FLASH_SR_OPTVERR_Msk              (0x1U << FLASH_SR_OPTVERR_Pos)       /*!< 0x00008000 */
8693 #define FLASH_SR_OPTVERR                  FLASH_SR_OPTVERR_Msk
8694 #define FLASH_SR_BSY_Pos                  (16U)
8695 #define FLASH_SR_BSY_Msk                  (0x1U << FLASH_SR_BSY_Pos)           /*!< 0x00010000 */
8696 #define FLASH_SR_BSY                      FLASH_SR_BSY_Msk
8697 #define FLASH_SR_PEMPTY_Pos               (17U)
8698 #define FLASH_SR_PEMPTY_Msk               (0x1U << FLASH_SR_PEMPTY_Pos)        /*!< 0x00020000 */
8699 #define FLASH_SR_PEMPTY                   FLASH_SR_PEMPTY_Msk
8700 
8701 /*******************  Bits definition for FLASH_CR register  ******************/
8702 #define FLASH_CR_PG_Pos                   (0U)
8703 #define FLASH_CR_PG_Msk                   (0x1U << FLASH_CR_PG_Pos)            /*!< 0x00000001 */
8704 #define FLASH_CR_PG                       FLASH_CR_PG_Msk
8705 #define FLASH_CR_PER_Pos                  (1U)
8706 #define FLASH_CR_PER_Msk                  (0x1U << FLASH_CR_PER_Pos)           /*!< 0x00000002 */
8707 #define FLASH_CR_PER                      FLASH_CR_PER_Msk
8708 #define FLASH_CR_MER1_Pos                 (2U)
8709 #define FLASH_CR_MER1_Msk                 (0x1U << FLASH_CR_MER1_Pos)          /*!< 0x00000004 */
8710 #define FLASH_CR_MER1                     FLASH_CR_MER1_Msk
8711 #define FLASH_CR_PNB_Pos                  (3U)
8712 #define FLASH_CR_PNB_Msk                  (0xFFU << FLASH_CR_PNB_Pos)          /*!< 0x000007F8 */
8713 #define FLASH_CR_PNB                      FLASH_CR_PNB_Msk
8714 #define FLASH_CR_BKER_Pos                 (11U)
8715 #define FLASH_CR_BKER_Msk                 (0x1U << FLASH_CR_BKER_Pos)          /*!< 0x00000800 */
8716 #define FLASH_CR_BKER                     FLASH_CR_BKER_Msk
8717 #define FLASH_CR_MER2_Pos                 (15U)
8718 #define FLASH_CR_MER2_Msk                 (0x1U << FLASH_CR_MER2_Pos)          /*!< 0x00008000 */
8719 #define FLASH_CR_MER2                     FLASH_CR_MER2_Msk
8720 #define FLASH_CR_STRT_Pos                 (16U)
8721 #define FLASH_CR_STRT_Msk                 (0x1U << FLASH_CR_STRT_Pos)          /*!< 0x00010000 */
8722 #define FLASH_CR_STRT                     FLASH_CR_STRT_Msk
8723 #define FLASH_CR_OPTSTRT_Pos              (17U)
8724 #define FLASH_CR_OPTSTRT_Msk              (0x1U << FLASH_CR_OPTSTRT_Pos)       /*!< 0x00020000 */
8725 #define FLASH_CR_OPTSTRT                  FLASH_CR_OPTSTRT_Msk
8726 #define FLASH_CR_FSTPG_Pos                (18U)
8727 #define FLASH_CR_FSTPG_Msk                (0x1U << FLASH_CR_FSTPG_Pos)         /*!< 0x00040000 */
8728 #define FLASH_CR_FSTPG                    FLASH_CR_FSTPG_Msk
8729 #define FLASH_CR_EOPIE_Pos                (24U)
8730 #define FLASH_CR_EOPIE_Msk                (0x1U << FLASH_CR_EOPIE_Pos)         /*!< 0x01000000 */
8731 #define FLASH_CR_EOPIE                    FLASH_CR_EOPIE_Msk
8732 #define FLASH_CR_ERRIE_Pos                (25U)
8733 #define FLASH_CR_ERRIE_Msk                (0x1U << FLASH_CR_ERRIE_Pos)         /*!< 0x02000000 */
8734 #define FLASH_CR_ERRIE                    FLASH_CR_ERRIE_Msk
8735 #define FLASH_CR_RDERRIE_Pos              (26U)
8736 #define FLASH_CR_RDERRIE_Msk              (0x1U << FLASH_CR_RDERRIE_Pos)       /*!< 0x04000000 */
8737 #define FLASH_CR_RDERRIE                  FLASH_CR_RDERRIE_Msk
8738 #define FLASH_CR_OBL_LAUNCH_Pos           (27U)
8739 #define FLASH_CR_OBL_LAUNCH_Msk           (0x1U << FLASH_CR_OBL_LAUNCH_Pos)    /*!< 0x08000000 */
8740 #define FLASH_CR_OBL_LAUNCH               FLASH_CR_OBL_LAUNCH_Msk
8741 #define FLASH_CR_OPTLOCK_Pos              (30U)
8742 #define FLASH_CR_OPTLOCK_Msk              (0x1U << FLASH_CR_OPTLOCK_Pos)       /*!< 0x40000000 */
8743 #define FLASH_CR_OPTLOCK                  FLASH_CR_OPTLOCK_Msk
8744 #define FLASH_CR_LOCK_Pos                 (31U)
8745 #define FLASH_CR_LOCK_Msk                 (0x1U << FLASH_CR_LOCK_Pos)          /*!< 0x80000000 */
8746 #define FLASH_CR_LOCK                     FLASH_CR_LOCK_Msk
8747 
8748 /*******************  Bits definition for FLASH_ECCR register  ***************/
8749 #define FLASH_ECCR_ADDR_ECC_Pos           (0U)
8750 #define FLASH_ECCR_ADDR_ECC_Msk           (0x7FFFFU << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */
8751 #define FLASH_ECCR_ADDR_ECC               FLASH_ECCR_ADDR_ECC_Msk
8752 #define FLASH_ECCR_BK_ECC_Pos             (19U)
8753 #define FLASH_ECCR_BK_ECC_Msk             (0x1U << FLASH_ECCR_BK_ECC_Pos)      /*!< 0x00080000 */
8754 #define FLASH_ECCR_BK_ECC                 FLASH_ECCR_BK_ECC_Msk
8755 #define FLASH_ECCR_SYSF_ECC_Pos           (20U)
8756 #define FLASH_ECCR_SYSF_ECC_Msk           (0x1U << FLASH_ECCR_SYSF_ECC_Pos)    /*!< 0x00100000 */
8757 #define FLASH_ECCR_SYSF_ECC               FLASH_ECCR_SYSF_ECC_Msk
8758 #define FLASH_ECCR_ECCIE_Pos              (24U)
8759 #define FLASH_ECCR_ECCIE_Msk              (0x1U << FLASH_ECCR_ECCIE_Pos)       /*!< 0x01000000 */
8760 #define FLASH_ECCR_ECCIE                  FLASH_ECCR_ECCIE_Msk
8761 #define FLASH_ECCR_ECCC_Pos               (30U)
8762 #define FLASH_ECCR_ECCC_Msk               (0x1U << FLASH_ECCR_ECCC_Pos)        /*!< 0x40000000 */
8763 #define FLASH_ECCR_ECCC                   FLASH_ECCR_ECCC_Msk
8764 #define FLASH_ECCR_ECCD_Pos               (31U)
8765 #define FLASH_ECCR_ECCD_Msk               (0x1U << FLASH_ECCR_ECCD_Pos)        /*!< 0x80000000 */
8766 #define FLASH_ECCR_ECCD                   FLASH_ECCR_ECCD_Msk
8767 
8768 /*******************  Bits definition for FLASH_OPTR register  ***************/
8769 #define FLASH_OPTR_RDP_Pos                (0U)
8770 #define FLASH_OPTR_RDP_Msk                (0xFFU << FLASH_OPTR_RDP_Pos)        /*!< 0x000000FF */
8771 #define FLASH_OPTR_RDP                    FLASH_OPTR_RDP_Msk
8772 #define FLASH_OPTR_BOR_LEV_Pos            (8U)
8773 #define FLASH_OPTR_BOR_LEV_Msk            (0x7U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000700 */
8774 #define FLASH_OPTR_BOR_LEV                FLASH_OPTR_BOR_LEV_Msk
8775 #define FLASH_OPTR_BOR_LEV_0              (0x0U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000000 */
8776 #define FLASH_OPTR_BOR_LEV_1              (0x1U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000100 */
8777 #define FLASH_OPTR_BOR_LEV_2              (0x2U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000200 */
8778 #define FLASH_OPTR_BOR_LEV_3              (0x3U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000300 */
8779 #define FLASH_OPTR_BOR_LEV_4              (0x4U << FLASH_OPTR_BOR_LEV_Pos)     /*!< 0x00000400 */
8780 #define FLASH_OPTR_nRST_STOP_Pos          (12U)
8781 #define FLASH_OPTR_nRST_STOP_Msk          (0x1U << FLASH_OPTR_nRST_STOP_Pos)   /*!< 0x00001000 */
8782 #define FLASH_OPTR_nRST_STOP              FLASH_OPTR_nRST_STOP_Msk
8783 #define FLASH_OPTR_nRST_STDBY_Pos         (13U)
8784 #define FLASH_OPTR_nRST_STDBY_Msk         (0x1U << FLASH_OPTR_nRST_STDBY_Pos)  /*!< 0x00002000 */
8785 #define FLASH_OPTR_nRST_STDBY             FLASH_OPTR_nRST_STDBY_Msk
8786 #define FLASH_OPTR_nRST_SHDW_Pos          (14U)
8787 #define FLASH_OPTR_nRST_SHDW_Msk          (0x1U << FLASH_OPTR_nRST_SHDW_Pos)   /*!< 0x00004000 */
8788 #define FLASH_OPTR_nRST_SHDW              FLASH_OPTR_nRST_SHDW_Msk
8789 #define FLASH_OPTR_IWDG_SW_Pos            (16U)
8790 #define FLASH_OPTR_IWDG_SW_Msk            (0x1U << FLASH_OPTR_IWDG_SW_Pos)     /*!< 0x00010000 */
8791 #define FLASH_OPTR_IWDG_SW                FLASH_OPTR_IWDG_SW_Msk
8792 #define FLASH_OPTR_IWDG_STOP_Pos          (17U)
8793 #define FLASH_OPTR_IWDG_STOP_Msk          (0x1U << FLASH_OPTR_IWDG_STOP_Pos)   /*!< 0x00020000 */
8794 #define FLASH_OPTR_IWDG_STOP              FLASH_OPTR_IWDG_STOP_Msk
8795 #define FLASH_OPTR_IWDG_STDBY_Pos         (18U)
8796 #define FLASH_OPTR_IWDG_STDBY_Msk         (0x1U << FLASH_OPTR_IWDG_STDBY_Pos)  /*!< 0x00040000 */
8797 #define FLASH_OPTR_IWDG_STDBY             FLASH_OPTR_IWDG_STDBY_Msk
8798 #define FLASH_OPTR_WWDG_SW_Pos            (19U)
8799 #define FLASH_OPTR_WWDG_SW_Msk            (0x1U << FLASH_OPTR_WWDG_SW_Pos)     /*!< 0x00080000 */
8800 #define FLASH_OPTR_WWDG_SW                FLASH_OPTR_WWDG_SW_Msk
8801 #define FLASH_OPTR_BFB2_Pos               (20U)
8802 #define FLASH_OPTR_BFB2_Msk               (0x1U << FLASH_OPTR_BFB2_Pos)        /*!< 0x00100000 */
8803 #define FLASH_OPTR_BFB2                   FLASH_OPTR_BFB2_Msk
8804 #define FLASH_OPTR_DUALBANK_Pos           (21U)
8805 #define FLASH_OPTR_DUALBANK_Msk           (0x1U << FLASH_OPTR_DUALBANK_Pos)    /*!< 0x00200000 */
8806 #define FLASH_OPTR_DUALBANK               FLASH_OPTR_DUALBANK_Msk
8807 #define FLASH_OPTR_nBOOT1_Pos             (23U)
8808 #define FLASH_OPTR_nBOOT1_Msk             (0x1U << FLASH_OPTR_nBOOT1_Pos)      /*!< 0x00800000 */
8809 #define FLASH_OPTR_nBOOT1                 FLASH_OPTR_nBOOT1_Msk
8810 #define FLASH_OPTR_SRAM2_PE_Pos           (24U)
8811 #define FLASH_OPTR_SRAM2_PE_Msk           (0x1U << FLASH_OPTR_SRAM2_PE_Pos)    /*!< 0x01000000 */
8812 #define FLASH_OPTR_SRAM2_PE               FLASH_OPTR_SRAM2_PE_Msk
8813 #define FLASH_OPTR_SRAM2_RST_Pos          (25U)
8814 #define FLASH_OPTR_SRAM2_RST_Msk          (0x1U << FLASH_OPTR_SRAM2_RST_Pos)   /*!< 0x02000000 */
8815 #define FLASH_OPTR_SRAM2_RST              FLASH_OPTR_SRAM2_RST_Msk
8816 #define FLASH_OPTR_nSWBOOT0_Pos           (26U)
8817 #define FLASH_OPTR_nSWBOOT0_Msk           (0x1U << FLASH_OPTR_nSWBOOT0_Pos)    /*!< 0x04000000 */
8818 #define FLASH_OPTR_nSWBOOT0               FLASH_OPTR_nSWBOOT0_Msk
8819 #define FLASH_OPTR_nBOOT0_Pos             (27U)
8820 #define FLASH_OPTR_nBOOT0_Msk             (0x1U << FLASH_OPTR_nBOOT0_Pos)      /*!< 0x08000000 */
8821 #define FLASH_OPTR_nBOOT0                 FLASH_OPTR_nBOOT0_Msk
8822 
8823 /******************  Bits definition for FLASH_PCROP1SR register  **********/
8824 #define FLASH_PCROP1SR_PCROP1_STRT_Pos    (0U)
8825 #define FLASH_PCROP1SR_PCROP1_STRT_Msk    (0xFFFFU << FLASH_PCROP1SR_PCROP1_STRT_Pos) /*!< 0x0000FFFF */
8826 #define FLASH_PCROP1SR_PCROP1_STRT        FLASH_PCROP1SR_PCROP1_STRT_Msk
8827 
8828 /******************  Bits definition for FLASH_PCROP1ER register  ***********/
8829 #define FLASH_PCROP1ER_PCROP1_END_Pos     (0U)
8830 #define FLASH_PCROP1ER_PCROP1_END_Msk     (0xFFFFU << FLASH_PCROP1ER_PCROP1_END_Pos) /*!< 0x0000FFFF */
8831 #define FLASH_PCROP1ER_PCROP1_END         FLASH_PCROP1ER_PCROP1_END_Msk
8832 #define FLASH_PCROP1ER_PCROP_RDP_Pos      (31U)
8833 #define FLASH_PCROP1ER_PCROP_RDP_Msk      (0x1U << FLASH_PCROP1ER_PCROP_RDP_Pos) /*!< 0x80000000 */
8834 #define FLASH_PCROP1ER_PCROP_RDP          FLASH_PCROP1ER_PCROP_RDP_Msk
8835 
8836 /******************  Bits definition for FLASH_WRP1AR register  ***************/
8837 #define FLASH_WRP1AR_WRP1A_STRT_Pos       (0U)
8838 #define FLASH_WRP1AR_WRP1A_STRT_Msk       (0xFFU << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x000000FF */
8839 #define FLASH_WRP1AR_WRP1A_STRT           FLASH_WRP1AR_WRP1A_STRT_Msk
8840 #define FLASH_WRP1AR_WRP1A_END_Pos        (16U)
8841 #define FLASH_WRP1AR_WRP1A_END_Msk        (0xFFU << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x00FF0000 */
8842 #define FLASH_WRP1AR_WRP1A_END            FLASH_WRP1AR_WRP1A_END_Msk
8843 
8844 /******************  Bits definition for FLASH_WRPB1R register  ***************/
8845 #define FLASH_WRP1BR_WRP1B_STRT_Pos       (0U)
8846 #define FLASH_WRP1BR_WRP1B_STRT_Msk       (0xFFU << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x000000FF */
8847 #define FLASH_WRP1BR_WRP1B_STRT           FLASH_WRP1BR_WRP1B_STRT_Msk
8848 #define FLASH_WRP1BR_WRP1B_END_Pos        (16U)
8849 #define FLASH_WRP1BR_WRP1B_END_Msk        (0xFFU << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x00FF0000 */
8850 #define FLASH_WRP1BR_WRP1B_END            FLASH_WRP1BR_WRP1B_END_Msk
8851 
8852 /******************  Bits definition for FLASH_PCROP2SR register  **********/
8853 #define FLASH_PCROP2SR_PCROP2_STRT_Pos    (0U)
8854 #define FLASH_PCROP2SR_PCROP2_STRT_Msk    (0xFFFFU << FLASH_PCROP2SR_PCROP2_STRT_Pos) /*!< 0x0000FFFF */
8855 #define FLASH_PCROP2SR_PCROP2_STRT        FLASH_PCROP2SR_PCROP2_STRT_Msk
8856 
8857 /******************  Bits definition for FLASH_PCROP2ER register  ***********/
8858 #define FLASH_PCROP2ER_PCROP2_END_Pos     (0U)
8859 #define FLASH_PCROP2ER_PCROP2_END_Msk     (0xFFFFU << FLASH_PCROP2ER_PCROP2_END_Pos) /*!< 0x0000FFFF */
8860 #define FLASH_PCROP2ER_PCROP2_END         FLASH_PCROP2ER_PCROP2_END_Msk
8861 
8862 /******************  Bits definition for FLASH_WRP2AR register  ***************/
8863 #define FLASH_WRP2AR_WRP2A_STRT_Pos       (0U)
8864 #define FLASH_WRP2AR_WRP2A_STRT_Msk       (0xFFU << FLASH_WRP2AR_WRP2A_STRT_Pos) /*!< 0x000000FF */
8865 #define FLASH_WRP2AR_WRP2A_STRT           FLASH_WRP2AR_WRP2A_STRT_Msk
8866 #define FLASH_WRP2AR_WRP2A_END_Pos        (16U)
8867 #define FLASH_WRP2AR_WRP2A_END_Msk        (0xFFU << FLASH_WRP2AR_WRP2A_END_Pos) /*!< 0x00FF0000 */
8868 #define FLASH_WRP2AR_WRP2A_END            FLASH_WRP2AR_WRP2A_END_Msk
8869 
8870 /******************  Bits definition for FLASH_WRP2BR register  ***************/
8871 #define FLASH_WRP2BR_WRP2B_STRT_Pos       (0U)
8872 #define FLASH_WRP2BR_WRP2B_STRT_Msk       (0xFFU << FLASH_WRP2BR_WRP2B_STRT_Pos) /*!< 0x000000FF */
8873 #define FLASH_WRP2BR_WRP2B_STRT           FLASH_WRP2BR_WRP2B_STRT_Msk
8874 #define FLASH_WRP2BR_WRP2B_END_Pos        (16U)
8875 #define FLASH_WRP2BR_WRP2B_END_Msk        (0xFFU << FLASH_WRP2BR_WRP2B_END_Pos) /*!< 0x00FF0000 */
8876 #define FLASH_WRP2BR_WRP2B_END            FLASH_WRP2BR_WRP2B_END_Msk
8877 
8878 
8879 /******************************************************************************/
8880 /*                                                                            */
8881 /*                          Flexible Memory Controller                        */
8882 /*                                                                            */
8883 /******************************************************************************/
8884 /******************  Bit definition for FMC_BCR1 register  *******************/
8885 #define FMC_BCR1_CCLKEN_Pos        (20U)
8886 #define FMC_BCR1_CCLKEN_Msk        (0x1U << FMC_BCR1_CCLKEN_Pos)               /*!< 0x00100000 */
8887 #define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */
8888 #define FMC_BCR1_WFDIS_Pos         (21U)
8889 #define FMC_BCR1_WFDIS_Msk         (0x1U << FMC_BCR1_WFDIS_Pos)                /*!< 0x00200000 */
8890 #define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
8891 
8892 /******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
8893 #define FMC_BCRx_MBKEN_Pos         (0U)
8894 #define FMC_BCRx_MBKEN_Msk         (0x1U << FMC_BCRx_MBKEN_Pos)                /*!< 0x00000001 */
8895 #define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
8896 #define FMC_BCRx_MUXEN_Pos         (1U)
8897 #define FMC_BCRx_MUXEN_Msk         (0x1U << FMC_BCRx_MUXEN_Pos)                /*!< 0x00000002 */
8898 #define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
8899 
8900 #define FMC_BCRx_MTYP_Pos          (2U)
8901 #define FMC_BCRx_MTYP_Msk          (0x3U << FMC_BCRx_MTYP_Pos)                 /*!< 0x0000000C */
8902 #define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
8903 #define FMC_BCRx_MTYP_0            (0x1U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
8904 #define FMC_BCRx_MTYP_1            (0x2U << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
8905 
8906 #define FMC_BCRx_MWID_Pos          (4U)
8907 #define FMC_BCRx_MWID_Msk          (0x3U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000030 */
8908 #define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
8909 #define FMC_BCRx_MWID_0            (0x1U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
8910 #define FMC_BCRx_MWID_1            (0x2U << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
8911 
8912 #define FMC_BCRx_FACCEN_Pos        (6U)
8913 #define FMC_BCRx_FACCEN_Msk        (0x1U << FMC_BCRx_FACCEN_Pos)               /*!< 0x00000040 */
8914 #define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
8915 #define FMC_BCRx_BURSTEN_Pos       (8U)
8916 #define FMC_BCRx_BURSTEN_Msk       (0x1U << FMC_BCRx_BURSTEN_Pos)              /*!< 0x00000100 */
8917 #define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
8918 #define FMC_BCRx_WAITPOL_Pos       (9U)
8919 #define FMC_BCRx_WAITPOL_Msk       (0x1U << FMC_BCRx_WAITPOL_Pos)              /*!< 0x00000200 */
8920 #define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
8921 #define FMC_BCRx_WAITCFG_Pos       (11U)
8922 #define FMC_BCRx_WAITCFG_Msk       (0x1U << FMC_BCRx_WAITCFG_Pos)              /*!< 0x00000800 */
8923 #define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
8924 #define FMC_BCRx_WREN_Pos          (12U)
8925 #define FMC_BCRx_WREN_Msk          (0x1U << FMC_BCRx_WREN_Pos)                 /*!< 0x00001000 */
8926 #define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
8927 #define FMC_BCRx_WAITEN_Pos        (13U)
8928 #define FMC_BCRx_WAITEN_Msk        (0x1U << FMC_BCRx_WAITEN_Pos)               /*!< 0x00002000 */
8929 #define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
8930 #define FMC_BCRx_EXTMOD_Pos        (14U)
8931 #define FMC_BCRx_EXTMOD_Msk        (0x1U << FMC_BCRx_EXTMOD_Pos)               /*!< 0x00004000 */
8932 #define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
8933 #define FMC_BCRx_ASYNCWAIT_Pos     (15U)
8934 #define FMC_BCRx_ASYNCWAIT_Msk     (0x1U << FMC_BCRx_ASYNCWAIT_Pos)            /*!< 0x00008000 */
8935 #define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
8936 
8937 #define FMC_BCRx_CPSIZE_Pos        (16U)
8938 #define FMC_BCRx_CPSIZE_Msk        (0x7U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00070000 */
8939 #define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<CRAM page size             */
8940 #define FMC_BCRx_CPSIZE_0          (0x1U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
8941 #define FMC_BCRx_CPSIZE_1          (0x2U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
8942 #define FMC_BCRx_CPSIZE_2          (0x4U << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
8943 
8944 #define FMC_BCRx_CBURSTRW_Pos      (19U)
8945 #define FMC_BCRx_CBURSTRW_Msk      (0x1U << FMC_BCRx_CBURSTRW_Pos)             /*!< 0x00080000 */
8946 #define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
8947 
8948 /******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
8949 #define FMC_BTRx_ADDSET_Pos        (0U)
8950 #define FMC_BTRx_ADDSET_Msk        (0xFU << FMC_BTRx_ADDSET_Pos)               /*!< 0x0000000F */
8951 #define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
8952 #define FMC_BTRx_ADDSET_0          (0x1U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
8953 #define FMC_BTRx_ADDSET_1          (0x2U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
8954 #define FMC_BTRx_ADDSET_2          (0x4U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
8955 #define FMC_BTRx_ADDSET_3          (0x8U << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
8956 
8957 #define FMC_BTRx_ADDHLD_Pos        (4U)
8958 #define FMC_BTRx_ADDHLD_Msk        (0xFU << FMC_BTRx_ADDHLD_Pos)               /*!< 0x000000F0 */
8959 #define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
8960 #define FMC_BTRx_ADDHLD_0          (0x1U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
8961 #define FMC_BTRx_ADDHLD_1          (0x2U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
8962 #define FMC_BTRx_ADDHLD_2          (0x4U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
8963 #define FMC_BTRx_ADDHLD_3          (0x8U << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
8964 
8965 #define FMC_BTRx_DATAST_Pos        (8U)
8966 #define FMC_BTRx_DATAST_Msk        (0xFFU << FMC_BTRx_DATAST_Pos)              /*!< 0x0000FF00 */
8967 #define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
8968 #define FMC_BTRx_DATAST_0          (0x01U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
8969 #define FMC_BTRx_DATAST_1          (0x02U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
8970 #define FMC_BTRx_DATAST_2          (0x04U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
8971 #define FMC_BTRx_DATAST_3          (0x08U << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
8972 #define FMC_BTRx_DATAST_4          (0x10U << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
8973 #define FMC_BTRx_DATAST_5          (0x20U << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
8974 #define FMC_BTRx_DATAST_6          (0x40U << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
8975 #define FMC_BTRx_DATAST_7          (0x80U << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
8976 
8977 #define FMC_BTRx_BUSTURN_Pos       (16U)
8978 #define FMC_BTRx_BUSTURN_Msk       (0xFU << FMC_BTRx_BUSTURN_Pos)              /*!< 0x000F0000 */
8979 #define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8980 #define FMC_BTRx_BUSTURN_0         (0x1U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
8981 #define FMC_BTRx_BUSTURN_1         (0x2U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
8982 #define FMC_BTRx_BUSTURN_2         (0x4U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
8983 #define FMC_BTRx_BUSTURN_3         (0x8U << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
8984 
8985 #define FMC_BTRx_CLKDIV_Pos        (20U)
8986 #define FMC_BTRx_CLKDIV_Msk        (0xFU << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00F00000 */
8987 #define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8988 #define FMC_BTRx_CLKDIV_0          (0x1U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
8989 #define FMC_BTRx_CLKDIV_1          (0x2U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
8990 #define FMC_BTRx_CLKDIV_2          (0x4U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
8991 #define FMC_BTRx_CLKDIV_3          (0x8U << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
8992 
8993 #define FMC_BTRx_DATLAT_Pos        (24U)
8994 #define FMC_BTRx_DATLAT_Msk        (0xFU << FMC_BTRx_DATLAT_Pos)               /*!< 0x0F000000 */
8995 #define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLAT[3:0] bits (Data latency) */
8996 #define FMC_BTRx_DATLAT_0          (0x1U << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
8997 #define FMC_BTRx_DATLAT_1          (0x2U << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
8998 #define FMC_BTRx_DATLAT_2          (0x4U << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
8999 #define FMC_BTRx_DATLAT_3          (0x8U << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
9000 
9001 #define FMC_BTRx_ACCMOD_Pos        (28U)
9002 #define FMC_BTRx_ACCMOD_Msk        (0x3U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x30000000 */
9003 #define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
9004 #define FMC_BTRx_ACCMOD_0          (0x1U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
9005 #define FMC_BTRx_ACCMOD_1          (0x2U << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
9006 
9007 /******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
9008 #define FMC_BWTRx_ADDSET_Pos       (0U)
9009 #define FMC_BWTRx_ADDSET_Msk       (0xFU << FMC_BWTRx_ADDSET_Pos)              /*!< 0x0000000F */
9010 #define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
9011 #define FMC_BWTRx_ADDSET_0         (0x1U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
9012 #define FMC_BWTRx_ADDSET_1         (0x2U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
9013 #define FMC_BWTRx_ADDSET_2         (0x4U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
9014 #define FMC_BWTRx_ADDSET_3         (0x8U << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
9015 
9016 #define FMC_BWTRx_ADDHLD_Pos       (4U)
9017 #define FMC_BWTRx_ADDHLD_Msk       (0xFU << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
9018 #define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
9019 #define FMC_BWTRx_ADDHLD_0         (0x1U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
9020 #define FMC_BWTRx_ADDHLD_1         (0x2U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
9021 #define FMC_BWTRx_ADDHLD_2         (0x4U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
9022 #define FMC_BWTRx_ADDHLD_3         (0x8U << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
9023 
9024 #define FMC_BWTRx_DATAST_Pos       (8U)
9025 #define FMC_BWTRx_DATAST_Msk       (0xFFU << FMC_BWTRx_DATAST_Pos)             /*!< 0x0000FF00 */
9026 #define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
9027 #define FMC_BWTRx_DATAST_0         (0x01U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
9028 #define FMC_BWTRx_DATAST_1         (0x02U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
9029 #define FMC_BWTRx_DATAST_2         (0x04U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
9030 #define FMC_BWTRx_DATAST_3         (0x08U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
9031 #define FMC_BWTRx_DATAST_4         (0x10U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
9032 #define FMC_BWTRx_DATAST_5         (0x20U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
9033 #define FMC_BWTRx_DATAST_6         (0x40U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
9034 #define FMC_BWTRx_DATAST_7         (0x80U << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
9035 
9036 #define FMC_BWTRx_BUSTURN_Pos      (16U)
9037 #define FMC_BWTRx_BUSTURN_Msk      (0xFU << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
9038 #define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
9039 #define FMC_BWTRx_BUSTURN_0        (0x1U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
9040 #define FMC_BWTRx_BUSTURN_1        (0x2U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
9041 #define FMC_BWTRx_BUSTURN_2        (0x4U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
9042 #define FMC_BWTRx_BUSTURN_3        (0x8U << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
9043 
9044 #define FMC_BWTRx_ACCMOD_Pos       (28U)
9045 #define FMC_BWTRx_ACCMOD_Msk       (0x3U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x30000000 */
9046 #define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
9047 #define FMC_BWTRx_ACCMOD_0         (0x1U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
9048 #define FMC_BWTRx_ACCMOD_1         (0x2U << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
9049 
9050 /******************  Bit definition for FMC_PCR register  ********************/
9051 #define FMC_PCR_PWAITEN_Pos        (1U)
9052 #define FMC_PCR_PWAITEN_Msk        (0x1U << FMC_PCR_PWAITEN_Pos)               /*!< 0x00000002 */
9053 #define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
9054 #define FMC_PCR_PBKEN_Pos          (2U)
9055 #define FMC_PCR_PBKEN_Msk          (0x1U << FMC_PCR_PBKEN_Pos)                 /*!< 0x00000004 */
9056 #define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
9057 #define FMC_PCR_PTYP_Pos           (3U)
9058 #define FMC_PCR_PTYP_Msk           (0x1U << FMC_PCR_PTYP_Pos)                  /*!< 0x00000008 */
9059 #define FMC_PCR_PTYP               FMC_PCR_PTYP_Msk                            /*!<Memory type                               */
9060 
9061 #define FMC_PCR_PWID_Pos           (4U)
9062 #define FMC_PCR_PWID_Msk           (0x3U << FMC_PCR_PWID_Pos)                  /*!< 0x00000030 */
9063 #define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
9064 #define FMC_PCR_PWID_0             (0x1U << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
9065 #define FMC_PCR_PWID_1             (0x2U << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
9066 
9067 #define FMC_PCR_ECCEN_Pos          (6U)
9068 #define FMC_PCR_ECCEN_Msk          (0x1U << FMC_PCR_ECCEN_Pos)                 /*!< 0x00000040 */
9069 #define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
9070 
9071 #define FMC_PCR_TCLR_Pos           (9U)
9072 #define FMC_PCR_TCLR_Msk           (0xFU << FMC_PCR_TCLR_Pos)                  /*!< 0x00001E00 */
9073 #define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
9074 #define FMC_PCR_TCLR_0             (0x1U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
9075 #define FMC_PCR_TCLR_1             (0x2U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
9076 #define FMC_PCR_TCLR_2             (0x4U << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
9077 #define FMC_PCR_TCLR_3             (0x8U << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
9078 
9079 #define FMC_PCR_TAR_Pos            (13U)
9080 #define FMC_PCR_TAR_Msk            (0xFU << FMC_PCR_TAR_Pos)                   /*!< 0x0001E000 */
9081 #define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
9082 #define FMC_PCR_TAR_0              (0x1U << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
9083 #define FMC_PCR_TAR_1              (0x2U << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
9084 #define FMC_PCR_TAR_2              (0x4U << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
9085 #define FMC_PCR_TAR_3              (0x8U << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
9086 
9087 #define FMC_PCR_ECCPS_Pos          (17U)
9088 #define FMC_PCR_ECCPS_Msk          (0x7U << FMC_PCR_ECCPS_Pos)                 /*!< 0x000E0000 */
9089 #define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
9090 #define FMC_PCR_ECCPS_0            (0x1U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
9091 #define FMC_PCR_ECCPS_1            (0x2U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
9092 #define FMC_PCR_ECCPS_2            (0x4U << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
9093 
9094 /*******************  Bit definition for FMC_SR register  ********************/
9095 #define FMC_SR_IRS_Pos             (0U)
9096 #define FMC_SR_IRS_Msk             (0x1U << FMC_SR_IRS_Pos)                    /*!< 0x00000001 */
9097 #define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
9098 #define FMC_SR_ILS_Pos             (1U)
9099 #define FMC_SR_ILS_Msk             (0x1U << FMC_SR_ILS_Pos)                    /*!< 0x00000002 */
9100 #define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
9101 #define FMC_SR_IFS_Pos             (2U)
9102 #define FMC_SR_IFS_Msk             (0x1U << FMC_SR_IFS_Pos)                    /*!< 0x00000004 */
9103 #define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
9104 #define FMC_SR_IREN_Pos            (3U)
9105 #define FMC_SR_IREN_Msk            (0x1U << FMC_SR_IREN_Pos)                   /*!< 0x00000008 */
9106 #define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
9107 #define FMC_SR_ILEN_Pos            (4U)
9108 #define FMC_SR_ILEN_Msk            (0x1U << FMC_SR_ILEN_Pos)                   /*!< 0x00000010 */
9109 #define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
9110 #define FMC_SR_IFEN_Pos            (5U)
9111 #define FMC_SR_IFEN_Msk            (0x1U << FMC_SR_IFEN_Pos)                   /*!< 0x00000020 */
9112 #define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
9113 #define FMC_SR_FEMPT_Pos           (6U)
9114 #define FMC_SR_FEMPT_Msk           (0x1U << FMC_SR_FEMPT_Pos)                  /*!< 0x00000040 */
9115 #define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
9116 
9117 /******************  Bit definition for FMC_PMEM register  ******************/
9118 #define FMC_PMEM_MEMSET_Pos        (0U)
9119 #define FMC_PMEM_MEMSET_Msk        (0xFFU << FMC_PMEM_MEMSET_Pos)              /*!< 0x000000FF */
9120 #define FMC_PMEM_MEMSET            FMC_PMEM_MEMSET_Msk                         /*!<MEMSET[7:0] bits (Common memory setup time) */
9121 #define FMC_PMEM_MEMSET_0          (0x01U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000001 */
9122 #define FMC_PMEM_MEMSET_1          (0x02U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000002 */
9123 #define FMC_PMEM_MEMSET_2          (0x04U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000004 */
9124 #define FMC_PMEM_MEMSET_3          (0x08U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000008 */
9125 #define FMC_PMEM_MEMSET_4          (0x10U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000010 */
9126 #define FMC_PMEM_MEMSET_5          (0x20U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000020 */
9127 #define FMC_PMEM_MEMSET_6          (0x40U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000040 */
9128 #define FMC_PMEM_MEMSET_7          (0x80U << FMC_PMEM_MEMSET_Pos)              /*!< 0x00000080 */
9129 
9130 #define FMC_PMEM_MEMWAIT_Pos       (8U)
9131 #define FMC_PMEM_MEMWAIT_Msk       (0xFFU << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x0000FF00 */
9132 #define FMC_PMEM_MEMWAIT           FMC_PMEM_MEMWAIT_Msk                        /*!<MEMWAIT[7:0] bits (Common memory wait time) */
9133 #define FMC_PMEM_MEMWAIT_0         (0x01U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000100 */
9134 #define FMC_PMEM_MEMWAIT_1         (0x02U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000200 */
9135 #define FMC_PMEM_MEMWAIT_2         (0x04U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000400 */
9136 #define FMC_PMEM_MEMWAIT_3         (0x08U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00000800 */
9137 #define FMC_PMEM_MEMWAIT_4         (0x10U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00001000 */
9138 #define FMC_PMEM_MEMWAIT_5         (0x20U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00002000 */
9139 #define FMC_PMEM_MEMWAIT_6         (0x40U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00004000 */
9140 #define FMC_PMEM_MEMWAIT_7         (0x80U << FMC_PMEM_MEMWAIT_Pos)             /*!< 0x00008000 */
9141 
9142 #define FMC_PMEM_MEMHOLD_Pos       (16U)
9143 #define FMC_PMEM_MEMHOLD_Msk       (0xFFU << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00FF0000 */
9144 #define FMC_PMEM_MEMHOLD           FMC_PMEM_MEMHOLD_Msk                        /*!<MEMHOLD[7:0] bits (Common memory hold time) */
9145 #define FMC_PMEM_MEMHOLD_0         (0x01U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00010000 */
9146 #define FMC_PMEM_MEMHOLD_1         (0x02U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00020000 */
9147 #define FMC_PMEM_MEMHOLD_2         (0x04U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00040000 */
9148 #define FMC_PMEM_MEMHOLD_3         (0x08U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00080000 */
9149 #define FMC_PMEM_MEMHOLD_4         (0x10U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00100000 */
9150 #define FMC_PMEM_MEMHOLD_5         (0x20U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00200000 */
9151 #define FMC_PMEM_MEMHOLD_6         (0x40U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00400000 */
9152 #define FMC_PMEM_MEMHOLD_7         (0x80U << FMC_PMEM_MEMHOLD_Pos)             /*!< 0x00800000 */
9153 
9154 #define FMC_PMEM_MEMHIZ_Pos        (24U)
9155 #define FMC_PMEM_MEMHIZ_Msk        (0xFFU << FMC_PMEM_MEMHIZ_Pos)              /*!< 0xFF000000 */
9156 #define FMC_PMEM_MEMHIZ            FMC_PMEM_MEMHIZ_Msk                         /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
9157 #define FMC_PMEM_MEMHIZ_0          (0x01U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x01000000 */
9158 #define FMC_PMEM_MEMHIZ_1          (0x02U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x02000000 */
9159 #define FMC_PMEM_MEMHIZ_2          (0x04U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x04000000 */
9160 #define FMC_PMEM_MEMHIZ_3          (0x08U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x08000000 */
9161 #define FMC_PMEM_MEMHIZ_4          (0x10U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x10000000 */
9162 #define FMC_PMEM_MEMHIZ_5          (0x20U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x20000000 */
9163 #define FMC_PMEM_MEMHIZ_6          (0x40U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x40000000 */
9164 #define FMC_PMEM_MEMHIZ_7          (0x80U << FMC_PMEM_MEMHIZ_Pos)              /*!< 0x80000000 */
9165 
9166 /******************  Bit definition for FMC_PATT register  *******************/
9167 #define FMC_PATT_ATTSET_Pos        (0U)
9168 #define FMC_PATT_ATTSET_Msk        (0xFFU << FMC_PATT_ATTSET_Pos)              /*!< 0x000000FF */
9169 #define FMC_PATT_ATTSET            FMC_PATT_ATTSET_Msk                         /*!<ATTSET[7:0] bits (Attribute memory setup time) */
9170 #define FMC_PATT_ATTSET_0          (0x01U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000001 */
9171 #define FMC_PATT_ATTSET_1          (0x02U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000002 */
9172 #define FMC_PATT_ATTSET_2          (0x04U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000004 */
9173 #define FMC_PATT_ATTSET_3          (0x08U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000008 */
9174 #define FMC_PATT_ATTSET_4          (0x10U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000010 */
9175 #define FMC_PATT_ATTSET_5          (0x20U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000020 */
9176 #define FMC_PATT_ATTSET_6          (0x40U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000040 */
9177 #define FMC_PATT_ATTSET_7          (0x80U << FMC_PATT_ATTSET_Pos)              /*!< 0x00000080 */
9178 
9179 #define FMC_PATT_ATTWAIT_Pos       (8U)
9180 #define FMC_PATT_ATTWAIT_Msk       (0xFFU << FMC_PATT_ATTWAIT_Pos)             /*!< 0x0000FF00 */
9181 #define FMC_PATT_ATTWAIT           FMC_PATT_ATTWAIT_Msk                        /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
9182 #define FMC_PATT_ATTWAIT_0         (0x01U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000100 */
9183 #define FMC_PATT_ATTWAIT_1         (0x02U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000200 */
9184 #define FMC_PATT_ATTWAIT_2         (0x04U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000400 */
9185 #define FMC_PATT_ATTWAIT_3         (0x08U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00000800 */
9186 #define FMC_PATT_ATTWAIT_4         (0x10U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00001000 */
9187 #define FMC_PATT_ATTWAIT_5         (0x20U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00002000 */
9188 #define FMC_PATT_ATTWAIT_6         (0x40U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00004000 */
9189 #define FMC_PATT_ATTWAIT_7         (0x80U << FMC_PATT_ATTWAIT_Pos)             /*!< 0x00008000 */
9190 
9191 #define FMC_PATT_ATTHOLD_Pos       (16U)
9192 #define FMC_PATT_ATTHOLD_Msk       (0xFFU << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00FF0000 */
9193 #define FMC_PATT_ATTHOLD           FMC_PATT_ATTHOLD_Msk                        /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
9194 #define FMC_PATT_ATTHOLD_0         (0x01U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00010000 */
9195 #define FMC_PATT_ATTHOLD_1         (0x02U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00020000 */
9196 #define FMC_PATT_ATTHOLD_2         (0x04U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00040000 */
9197 #define FMC_PATT_ATTHOLD_3         (0x08U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00080000 */
9198 #define FMC_PATT_ATTHOLD_4         (0x10U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00100000 */
9199 #define FMC_PATT_ATTHOLD_5         (0x20U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00200000 */
9200 #define FMC_PATT_ATTHOLD_6         (0x40U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00400000 */
9201 #define FMC_PATT_ATTHOLD_7         (0x80U << FMC_PATT_ATTHOLD_Pos)             /*!< 0x00800000 */
9202 
9203 #define FMC_PATT_ATTHIZ_Pos        (24U)
9204 #define FMC_PATT_ATTHIZ_Msk        (0xFFU << FMC_PATT_ATTHIZ_Pos)              /*!< 0xFF000000 */
9205 #define FMC_PATT_ATTHIZ            FMC_PATT_ATTHIZ_Msk                         /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
9206 #define FMC_PATT_ATTHIZ_0          (0x01U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x01000000 */
9207 #define FMC_PATT_ATTHIZ_1          (0x02U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x02000000 */
9208 #define FMC_PATT_ATTHIZ_2          (0x04U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x04000000 */
9209 #define FMC_PATT_ATTHIZ_3          (0x08U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x08000000 */
9210 #define FMC_PATT_ATTHIZ_4          (0x10U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x10000000 */
9211 #define FMC_PATT_ATTHIZ_5          (0x20U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x20000000 */
9212 #define FMC_PATT_ATTHIZ_6          (0x40U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x40000000 */
9213 #define FMC_PATT_ATTHIZ_7          (0x80U << FMC_PATT_ATTHIZ_Pos)              /*!< 0x80000000 */
9214 
9215 /******************  Bit definition for FMC_ECCR register  *******************/
9216 #define FMC_ECCR_ECC_Pos           (0U)
9217 #define FMC_ECCR_ECC_Msk           (0xFFFFFFFFU << FMC_ECCR_ECC_Pos)           /*!< 0xFFFFFFFF */
9218 #define FMC_ECCR_ECC               FMC_ECCR_ECC_Msk                            /*!<ECC result */
9219 
9220 /******************************************************************************/
9221 /*                                                                            */
9222 /*                       General Purpose IOs (GPIO)                           */
9223 /*                                                                            */
9224 /******************************************************************************/
9225 /******************  Bits definition for GPIO_MODER register  *****************/
9226 #define GPIO_MODER_MODE0_Pos           (0U)
9227 #define GPIO_MODER_MODE0_Msk           (0x3U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */
9228 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
9229 #define GPIO_MODER_MODE0_0             (0x1U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
9230 #define GPIO_MODER_MODE0_1             (0x2U << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
9231 #define GPIO_MODER_MODE1_Pos           (2U)
9232 #define GPIO_MODER_MODE1_Msk           (0x3U << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */
9233 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
9234 #define GPIO_MODER_MODE1_0             (0x1U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
9235 #define GPIO_MODER_MODE1_1             (0x2U << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
9236 #define GPIO_MODER_MODE2_Pos           (4U)
9237 #define GPIO_MODER_MODE2_Msk           (0x3U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */
9238 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
9239 #define GPIO_MODER_MODE2_0             (0x1U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
9240 #define GPIO_MODER_MODE2_1             (0x2U << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
9241 #define GPIO_MODER_MODE3_Pos           (6U)
9242 #define GPIO_MODER_MODE3_Msk           (0x3U << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */
9243 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
9244 #define GPIO_MODER_MODE3_0             (0x1U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
9245 #define GPIO_MODER_MODE3_1             (0x2U << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
9246 #define GPIO_MODER_MODE4_Pos           (8U)
9247 #define GPIO_MODER_MODE4_Msk           (0x3U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */
9248 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
9249 #define GPIO_MODER_MODE4_0             (0x1U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
9250 #define GPIO_MODER_MODE4_1             (0x2U << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
9251 #define GPIO_MODER_MODE5_Pos           (10U)
9252 #define GPIO_MODER_MODE5_Msk           (0x3U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */
9253 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
9254 #define GPIO_MODER_MODE5_0             (0x1U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
9255 #define GPIO_MODER_MODE5_1             (0x2U << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
9256 #define GPIO_MODER_MODE6_Pos           (12U)
9257 #define GPIO_MODER_MODE6_Msk           (0x3U << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */
9258 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
9259 #define GPIO_MODER_MODE6_0             (0x1U << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
9260 #define GPIO_MODER_MODE6_1             (0x2U << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
9261 #define GPIO_MODER_MODE7_Pos           (14U)
9262 #define GPIO_MODER_MODE7_Msk           (0x3U << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */
9263 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
9264 #define GPIO_MODER_MODE7_0             (0x1U << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
9265 #define GPIO_MODER_MODE7_1             (0x2U << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
9266 #define GPIO_MODER_MODE8_Pos           (16U)
9267 #define GPIO_MODER_MODE8_Msk           (0x3U << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */
9268 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
9269 #define GPIO_MODER_MODE8_0             (0x1U << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
9270 #define GPIO_MODER_MODE8_1             (0x2U << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
9271 #define GPIO_MODER_MODE9_Pos           (18U)
9272 #define GPIO_MODER_MODE9_Msk           (0x3U << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */
9273 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
9274 #define GPIO_MODER_MODE9_0             (0x1U << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
9275 #define GPIO_MODER_MODE9_1             (0x2U << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
9276 #define GPIO_MODER_MODE10_Pos          (20U)
9277 #define GPIO_MODER_MODE10_Msk          (0x3U << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */
9278 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
9279 #define GPIO_MODER_MODE10_0            (0x1U << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
9280 #define GPIO_MODER_MODE10_1            (0x2U << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
9281 #define GPIO_MODER_MODE11_Pos          (22U)
9282 #define GPIO_MODER_MODE11_Msk          (0x3U << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */
9283 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
9284 #define GPIO_MODER_MODE11_0            (0x1U << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
9285 #define GPIO_MODER_MODE11_1            (0x2U << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
9286 #define GPIO_MODER_MODE12_Pos          (24U)
9287 #define GPIO_MODER_MODE12_Msk          (0x3U << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */
9288 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
9289 #define GPIO_MODER_MODE12_0            (0x1U << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
9290 #define GPIO_MODER_MODE12_1            (0x2U << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
9291 #define GPIO_MODER_MODE13_Pos          (26U)
9292 #define GPIO_MODER_MODE13_Msk          (0x3U << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */
9293 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
9294 #define GPIO_MODER_MODE13_0            (0x1U << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
9295 #define GPIO_MODER_MODE13_1            (0x2U << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
9296 #define GPIO_MODER_MODE14_Pos          (28U)
9297 #define GPIO_MODER_MODE14_Msk          (0x3U << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */
9298 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
9299 #define GPIO_MODER_MODE14_0            (0x1U << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
9300 #define GPIO_MODER_MODE14_1            (0x2U << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
9301 #define GPIO_MODER_MODE15_Pos          (30U)
9302 #define GPIO_MODER_MODE15_Msk          (0x3U << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */
9303 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
9304 #define GPIO_MODER_MODE15_0            (0x1U << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
9305 #define GPIO_MODER_MODE15_1            (0x2U << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
9306 
9307 /* Legacy defines */
9308 #define GPIO_MODER_MODER0                   GPIO_MODER_MODE0
9309 #define GPIO_MODER_MODER0_0                 GPIO_MODER_MODE0_0
9310 #define GPIO_MODER_MODER0_1                 GPIO_MODER_MODE0_1
9311 #define GPIO_MODER_MODER1                   GPIO_MODER_MODE1
9312 #define GPIO_MODER_MODER1_0                 GPIO_MODER_MODE1_0
9313 #define GPIO_MODER_MODER1_1                 GPIO_MODER_MODE1_1
9314 #define GPIO_MODER_MODER2                   GPIO_MODER_MODE2
9315 #define GPIO_MODER_MODER2_0                 GPIO_MODER_MODE2_0
9316 #define GPIO_MODER_MODER2_1                 GPIO_MODER_MODE2_1
9317 #define GPIO_MODER_MODER3                   GPIO_MODER_MODE3
9318 #define GPIO_MODER_MODER3_0                 GPIO_MODER_MODE3_0
9319 #define GPIO_MODER_MODER3_1                 GPIO_MODER_MODE3_1
9320 #define GPIO_MODER_MODER4                   GPIO_MODER_MODE4
9321 #define GPIO_MODER_MODER4_0                 GPIO_MODER_MODE4_0
9322 #define GPIO_MODER_MODER4_1                 GPIO_MODER_MODE4_1
9323 #define GPIO_MODER_MODER5                   GPIO_MODER_MODE5
9324 #define GPIO_MODER_MODER5_0                 GPIO_MODER_MODE5_0
9325 #define GPIO_MODER_MODER5_1                 GPIO_MODER_MODE5_1
9326 #define GPIO_MODER_MODER6                   GPIO_MODER_MODE6
9327 #define GPIO_MODER_MODER6_0                 GPIO_MODER_MODE6_0
9328 #define GPIO_MODER_MODER6_1                 GPIO_MODER_MODE6_1
9329 #define GPIO_MODER_MODER7                   GPIO_MODER_MODE7
9330 #define GPIO_MODER_MODER7_0                 GPIO_MODER_MODE7_0
9331 #define GPIO_MODER_MODER7_1                 GPIO_MODER_MODE7_1
9332 #define GPIO_MODER_MODER8                   GPIO_MODER_MODE8
9333 #define GPIO_MODER_MODER8_0                 GPIO_MODER_MODE8_0
9334 #define GPIO_MODER_MODER8_1                 GPIO_MODER_MODE8_1
9335 #define GPIO_MODER_MODER9                   GPIO_MODER_MODE9
9336 #define GPIO_MODER_MODER9_0                 GPIO_MODER_MODE9_0
9337 #define GPIO_MODER_MODER9_1                 GPIO_MODER_MODE9_1
9338 #define GPIO_MODER_MODER10                  GPIO_MODER_MODE10
9339 #define GPIO_MODER_MODER10_0                GPIO_MODER_MODE10_0
9340 #define GPIO_MODER_MODER10_1                GPIO_MODER_MODE10_1
9341 #define GPIO_MODER_MODER11                  GPIO_MODER_MODE11
9342 #define GPIO_MODER_MODER11_0                GPIO_MODER_MODE11_0
9343 #define GPIO_MODER_MODER11_1                GPIO_MODER_MODE11_1
9344 #define GPIO_MODER_MODER12                  GPIO_MODER_MODE12
9345 #define GPIO_MODER_MODER12_0                GPIO_MODER_MODE12_0
9346 #define GPIO_MODER_MODER12_1                GPIO_MODER_MODE12_1
9347 #define GPIO_MODER_MODER13                  GPIO_MODER_MODE13
9348 #define GPIO_MODER_MODER13_0                GPIO_MODER_MODE13_0
9349 #define GPIO_MODER_MODER13_1                GPIO_MODER_MODE13_1
9350 #define GPIO_MODER_MODER14                  GPIO_MODER_MODE14
9351 #define GPIO_MODER_MODER14_0                GPIO_MODER_MODE14_0
9352 #define GPIO_MODER_MODER14_1                GPIO_MODER_MODE14_1
9353 #define GPIO_MODER_MODER15                  GPIO_MODER_MODE15
9354 #define GPIO_MODER_MODER15_0                GPIO_MODER_MODE15_0
9355 #define GPIO_MODER_MODER15_1                GPIO_MODER_MODE15_1
9356 
9357 /******************  Bits definition for GPIO_OTYPER register  ****************/
9358 #define GPIO_OTYPER_OT0_Pos            (0U)
9359 #define GPIO_OTYPER_OT0_Msk            (0x1U << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */
9360 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
9361 #define GPIO_OTYPER_OT1_Pos            (1U)
9362 #define GPIO_OTYPER_OT1_Msk            (0x1U << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */
9363 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
9364 #define GPIO_OTYPER_OT2_Pos            (2U)
9365 #define GPIO_OTYPER_OT2_Msk            (0x1U << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */
9366 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
9367 #define GPIO_OTYPER_OT3_Pos            (3U)
9368 #define GPIO_OTYPER_OT3_Msk            (0x1U << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */
9369 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
9370 #define GPIO_OTYPER_OT4_Pos            (4U)
9371 #define GPIO_OTYPER_OT4_Msk            (0x1U << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */
9372 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
9373 #define GPIO_OTYPER_OT5_Pos            (5U)
9374 #define GPIO_OTYPER_OT5_Msk            (0x1U << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */
9375 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
9376 #define GPIO_OTYPER_OT6_Pos            (6U)
9377 #define GPIO_OTYPER_OT6_Msk            (0x1U << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */
9378 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
9379 #define GPIO_OTYPER_OT7_Pos            (7U)
9380 #define GPIO_OTYPER_OT7_Msk            (0x1U << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */
9381 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
9382 #define GPIO_OTYPER_OT8_Pos            (8U)
9383 #define GPIO_OTYPER_OT8_Msk            (0x1U << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */
9384 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
9385 #define GPIO_OTYPER_OT9_Pos            (9U)
9386 #define GPIO_OTYPER_OT9_Msk            (0x1U << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */
9387 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
9388 #define GPIO_OTYPER_OT10_Pos           (10U)
9389 #define GPIO_OTYPER_OT10_Msk           (0x1U << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */
9390 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
9391 #define GPIO_OTYPER_OT11_Pos           (11U)
9392 #define GPIO_OTYPER_OT11_Msk           (0x1U << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */
9393 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
9394 #define GPIO_OTYPER_OT12_Pos           (12U)
9395 #define GPIO_OTYPER_OT12_Msk           (0x1U << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */
9396 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
9397 #define GPIO_OTYPER_OT13_Pos           (13U)
9398 #define GPIO_OTYPER_OT13_Msk           (0x1U << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */
9399 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
9400 #define GPIO_OTYPER_OT14_Pos           (14U)
9401 #define GPIO_OTYPER_OT14_Msk           (0x1U << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */
9402 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
9403 #define GPIO_OTYPER_OT15_Pos           (15U)
9404 #define GPIO_OTYPER_OT15_Msk           (0x1U << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */
9405 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
9406 
9407 /* Legacy defines */
9408 #define GPIO_OTYPER_OT_0                    GPIO_OTYPER_OT0
9409 #define GPIO_OTYPER_OT_1                    GPIO_OTYPER_OT1
9410 #define GPIO_OTYPER_OT_2                    GPIO_OTYPER_OT2
9411 #define GPIO_OTYPER_OT_3                    GPIO_OTYPER_OT3
9412 #define GPIO_OTYPER_OT_4                    GPIO_OTYPER_OT4
9413 #define GPIO_OTYPER_OT_5                    GPIO_OTYPER_OT5
9414 #define GPIO_OTYPER_OT_6                    GPIO_OTYPER_OT6
9415 #define GPIO_OTYPER_OT_7                    GPIO_OTYPER_OT7
9416 #define GPIO_OTYPER_OT_8                    GPIO_OTYPER_OT8
9417 #define GPIO_OTYPER_OT_9                    GPIO_OTYPER_OT9
9418 #define GPIO_OTYPER_OT_10                   GPIO_OTYPER_OT10
9419 #define GPIO_OTYPER_OT_11                   GPIO_OTYPER_OT11
9420 #define GPIO_OTYPER_OT_12                   GPIO_OTYPER_OT12
9421 #define GPIO_OTYPER_OT_13                   GPIO_OTYPER_OT13
9422 #define GPIO_OTYPER_OT_14                   GPIO_OTYPER_OT14
9423 #define GPIO_OTYPER_OT_15                   GPIO_OTYPER_OT15
9424 
9425 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
9426 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
9427 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */
9428 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
9429 #define GPIO_OSPEEDR_OSPEED0_0         (0x1U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
9430 #define GPIO_OSPEEDR_OSPEED0_1         (0x2U << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
9431 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
9432 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */
9433 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
9434 #define GPIO_OSPEEDR_OSPEED1_0         (0x1U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
9435 #define GPIO_OSPEEDR_OSPEED1_1         (0x2U << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
9436 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
9437 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */
9438 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
9439 #define GPIO_OSPEEDR_OSPEED2_0         (0x1U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
9440 #define GPIO_OSPEEDR_OSPEED2_1         (0x2U << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
9441 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
9442 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */
9443 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
9444 #define GPIO_OSPEEDR_OSPEED3_0         (0x1U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
9445 #define GPIO_OSPEEDR_OSPEED3_1         (0x2U << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
9446 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
9447 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */
9448 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
9449 #define GPIO_OSPEEDR_OSPEED4_0         (0x1U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
9450 #define GPIO_OSPEEDR_OSPEED4_1         (0x2U << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
9451 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
9452 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */
9453 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
9454 #define GPIO_OSPEEDR_OSPEED5_0         (0x1U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
9455 #define GPIO_OSPEEDR_OSPEED5_1         (0x2U << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
9456 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
9457 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */
9458 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
9459 #define GPIO_OSPEEDR_OSPEED6_0         (0x1U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
9460 #define GPIO_OSPEEDR_OSPEED6_1         (0x2U << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
9461 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
9462 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */
9463 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
9464 #define GPIO_OSPEEDR_OSPEED7_0         (0x1U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
9465 #define GPIO_OSPEEDR_OSPEED7_1         (0x2U << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
9466 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
9467 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */
9468 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
9469 #define GPIO_OSPEEDR_OSPEED8_0         (0x1U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
9470 #define GPIO_OSPEEDR_OSPEED8_1         (0x2U << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
9471 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
9472 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */
9473 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
9474 #define GPIO_OSPEEDR_OSPEED9_0         (0x1U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
9475 #define GPIO_OSPEEDR_OSPEED9_1         (0x2U << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
9476 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
9477 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */
9478 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
9479 #define GPIO_OSPEEDR_OSPEED10_0        (0x1U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
9480 #define GPIO_OSPEEDR_OSPEED10_1        (0x2U << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
9481 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
9482 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */
9483 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
9484 #define GPIO_OSPEEDR_OSPEED11_0        (0x1U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
9485 #define GPIO_OSPEEDR_OSPEED11_1        (0x2U << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
9486 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
9487 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */
9488 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
9489 #define GPIO_OSPEEDR_OSPEED12_0        (0x1U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
9490 #define GPIO_OSPEEDR_OSPEED12_1        (0x2U << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
9491 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
9492 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */
9493 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
9494 #define GPIO_OSPEEDR_OSPEED13_0        (0x1U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
9495 #define GPIO_OSPEEDR_OSPEED13_1        (0x2U << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
9496 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
9497 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */
9498 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
9499 #define GPIO_OSPEEDR_OSPEED14_0        (0x1U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
9500 #define GPIO_OSPEEDR_OSPEED14_1        (0x2U << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
9501 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
9502 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */
9503 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
9504 #define GPIO_OSPEEDR_OSPEED15_0        (0x1U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
9505 #define GPIO_OSPEEDR_OSPEED15_1        (0x2U << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
9506 
9507 /* Legacy defines */
9508 #define GPIO_OSPEEDER_OSPEEDR0              GPIO_OSPEEDR_OSPEED0
9509 #define GPIO_OSPEEDER_OSPEEDR0_0            GPIO_OSPEEDR_OSPEED0_0
9510 #define GPIO_OSPEEDER_OSPEEDR0_1            GPIO_OSPEEDR_OSPEED0_1
9511 #define GPIO_OSPEEDER_OSPEEDR1              GPIO_OSPEEDR_OSPEED1
9512 #define GPIO_OSPEEDER_OSPEEDR1_0            GPIO_OSPEEDR_OSPEED1_0
9513 #define GPIO_OSPEEDER_OSPEEDR1_1            GPIO_OSPEEDR_OSPEED1_1
9514 #define GPIO_OSPEEDER_OSPEEDR2              GPIO_OSPEEDR_OSPEED2
9515 #define GPIO_OSPEEDER_OSPEEDR2_0            GPIO_OSPEEDR_OSPEED2_0
9516 #define GPIO_OSPEEDER_OSPEEDR2_1            GPIO_OSPEEDR_OSPEED2_1
9517 #define GPIO_OSPEEDER_OSPEEDR3              GPIO_OSPEEDR_OSPEED3
9518 #define GPIO_OSPEEDER_OSPEEDR3_0            GPIO_OSPEEDR_OSPEED3_0
9519 #define GPIO_OSPEEDER_OSPEEDR3_1            GPIO_OSPEEDR_OSPEED3_1
9520 #define GPIO_OSPEEDER_OSPEEDR4              GPIO_OSPEEDR_OSPEED4
9521 #define GPIO_OSPEEDER_OSPEEDR4_0            GPIO_OSPEEDR_OSPEED4_0
9522 #define GPIO_OSPEEDER_OSPEEDR4_1            GPIO_OSPEEDR_OSPEED4_1
9523 #define GPIO_OSPEEDER_OSPEEDR5              GPIO_OSPEEDR_OSPEED5
9524 #define GPIO_OSPEEDER_OSPEEDR5_0            GPIO_OSPEEDR_OSPEED5_0
9525 #define GPIO_OSPEEDER_OSPEEDR5_1            GPIO_OSPEEDR_OSPEED5_1
9526 #define GPIO_OSPEEDER_OSPEEDR6              GPIO_OSPEEDR_OSPEED6
9527 #define GPIO_OSPEEDER_OSPEEDR6_0            GPIO_OSPEEDR_OSPEED6_0
9528 #define GPIO_OSPEEDER_OSPEEDR6_1            GPIO_OSPEEDR_OSPEED6_1
9529 #define GPIO_OSPEEDER_OSPEEDR7              GPIO_OSPEEDR_OSPEED7
9530 #define GPIO_OSPEEDER_OSPEEDR7_0            GPIO_OSPEEDR_OSPEED7_0
9531 #define GPIO_OSPEEDER_OSPEEDR7_1            GPIO_OSPEEDR_OSPEED7_1
9532 #define GPIO_OSPEEDER_OSPEEDR8              GPIO_OSPEEDR_OSPEED8
9533 #define GPIO_OSPEEDER_OSPEEDR8_0            GPIO_OSPEEDR_OSPEED8_0
9534 #define GPIO_OSPEEDER_OSPEEDR8_1            GPIO_OSPEEDR_OSPEED8_1
9535 #define GPIO_OSPEEDER_OSPEEDR9              GPIO_OSPEEDR_OSPEED9
9536 #define GPIO_OSPEEDER_OSPEEDR9_0            GPIO_OSPEEDR_OSPEED9_0
9537 #define GPIO_OSPEEDER_OSPEEDR9_1            GPIO_OSPEEDR_OSPEED9_1
9538 #define GPIO_OSPEEDER_OSPEEDR10             GPIO_OSPEEDR_OSPEED10
9539 #define GPIO_OSPEEDER_OSPEEDR10_0           GPIO_OSPEEDR_OSPEED10_0
9540 #define GPIO_OSPEEDER_OSPEEDR10_1           GPIO_OSPEEDR_OSPEED10_1
9541 #define GPIO_OSPEEDER_OSPEEDR11             GPIO_OSPEEDR_OSPEED11
9542 #define GPIO_OSPEEDER_OSPEEDR11_0           GPIO_OSPEEDR_OSPEED11_0
9543 #define GPIO_OSPEEDER_OSPEEDR11_1           GPIO_OSPEEDR_OSPEED11_1
9544 #define GPIO_OSPEEDER_OSPEEDR12             GPIO_OSPEEDR_OSPEED12
9545 #define GPIO_OSPEEDER_OSPEEDR12_0           GPIO_OSPEEDR_OSPEED12_0
9546 #define GPIO_OSPEEDER_OSPEEDR12_1           GPIO_OSPEEDR_OSPEED12_1
9547 #define GPIO_OSPEEDER_OSPEEDR13             GPIO_OSPEEDR_OSPEED13
9548 #define GPIO_OSPEEDER_OSPEEDR13_0           GPIO_OSPEEDR_OSPEED13_0
9549 #define GPIO_OSPEEDER_OSPEEDR13_1           GPIO_OSPEEDR_OSPEED13_1
9550 #define GPIO_OSPEEDER_OSPEEDR14             GPIO_OSPEEDR_OSPEED14
9551 #define GPIO_OSPEEDER_OSPEEDR14_0           GPIO_OSPEEDR_OSPEED14_0
9552 #define GPIO_OSPEEDER_OSPEEDR14_1           GPIO_OSPEEDR_OSPEED14_1
9553 #define GPIO_OSPEEDER_OSPEEDR15             GPIO_OSPEEDR_OSPEED15
9554 #define GPIO_OSPEEDER_OSPEEDR15_0           GPIO_OSPEEDR_OSPEED15_0
9555 #define GPIO_OSPEEDER_OSPEEDR15_1           GPIO_OSPEEDR_OSPEED15_1
9556 
9557 /******************  Bits definition for GPIO_PUPDR register  *****************/
9558 #define GPIO_PUPDR_PUPD0_Pos           (0U)
9559 #define GPIO_PUPDR_PUPD0_Msk           (0x3U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */
9560 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
9561 #define GPIO_PUPDR_PUPD0_0             (0x1U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
9562 #define GPIO_PUPDR_PUPD0_1             (0x2U << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
9563 #define GPIO_PUPDR_PUPD1_Pos           (2U)
9564 #define GPIO_PUPDR_PUPD1_Msk           (0x3U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */
9565 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
9566 #define GPIO_PUPDR_PUPD1_0             (0x1U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
9567 #define GPIO_PUPDR_PUPD1_1             (0x2U << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
9568 #define GPIO_PUPDR_PUPD2_Pos           (4U)
9569 #define GPIO_PUPDR_PUPD2_Msk           (0x3U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */
9570 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
9571 #define GPIO_PUPDR_PUPD2_0             (0x1U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
9572 #define GPIO_PUPDR_PUPD2_1             (0x2U << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
9573 #define GPIO_PUPDR_PUPD3_Pos           (6U)
9574 #define GPIO_PUPDR_PUPD3_Msk           (0x3U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */
9575 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
9576 #define GPIO_PUPDR_PUPD3_0             (0x1U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
9577 #define GPIO_PUPDR_PUPD3_1             (0x2U << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
9578 #define GPIO_PUPDR_PUPD4_Pos           (8U)
9579 #define GPIO_PUPDR_PUPD4_Msk           (0x3U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */
9580 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
9581 #define GPIO_PUPDR_PUPD4_0             (0x1U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
9582 #define GPIO_PUPDR_PUPD4_1             (0x2U << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
9583 #define GPIO_PUPDR_PUPD5_Pos           (10U)
9584 #define GPIO_PUPDR_PUPD5_Msk           (0x3U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */
9585 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
9586 #define GPIO_PUPDR_PUPD5_0             (0x1U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
9587 #define GPIO_PUPDR_PUPD5_1             (0x2U << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
9588 #define GPIO_PUPDR_PUPD6_Pos           (12U)
9589 #define GPIO_PUPDR_PUPD6_Msk           (0x3U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */
9590 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
9591 #define GPIO_PUPDR_PUPD6_0             (0x1U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
9592 #define GPIO_PUPDR_PUPD6_1             (0x2U << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
9593 #define GPIO_PUPDR_PUPD7_Pos           (14U)
9594 #define GPIO_PUPDR_PUPD7_Msk           (0x3U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */
9595 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
9596 #define GPIO_PUPDR_PUPD7_0             (0x1U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
9597 #define GPIO_PUPDR_PUPD7_1             (0x2U << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
9598 #define GPIO_PUPDR_PUPD8_Pos           (16U)
9599 #define GPIO_PUPDR_PUPD8_Msk           (0x3U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */
9600 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
9601 #define GPIO_PUPDR_PUPD8_0             (0x1U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
9602 #define GPIO_PUPDR_PUPD8_1             (0x2U << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
9603 #define GPIO_PUPDR_PUPD9_Pos           (18U)
9604 #define GPIO_PUPDR_PUPD9_Msk           (0x3U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */
9605 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
9606 #define GPIO_PUPDR_PUPD9_0             (0x1U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
9607 #define GPIO_PUPDR_PUPD9_1             (0x2U << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
9608 #define GPIO_PUPDR_PUPD10_Pos          (20U)
9609 #define GPIO_PUPDR_PUPD10_Msk          (0x3U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */
9610 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
9611 #define GPIO_PUPDR_PUPD10_0            (0x1U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
9612 #define GPIO_PUPDR_PUPD10_1            (0x2U << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
9613 #define GPIO_PUPDR_PUPD11_Pos          (22U)
9614 #define GPIO_PUPDR_PUPD11_Msk          (0x3U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */
9615 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
9616 #define GPIO_PUPDR_PUPD11_0            (0x1U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
9617 #define GPIO_PUPDR_PUPD11_1            (0x2U << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
9618 #define GPIO_PUPDR_PUPD12_Pos          (24U)
9619 #define GPIO_PUPDR_PUPD12_Msk          (0x3U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */
9620 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
9621 #define GPIO_PUPDR_PUPD12_0            (0x1U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
9622 #define GPIO_PUPDR_PUPD12_1            (0x2U << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
9623 #define GPIO_PUPDR_PUPD13_Pos          (26U)
9624 #define GPIO_PUPDR_PUPD13_Msk          (0x3U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */
9625 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
9626 #define GPIO_PUPDR_PUPD13_0            (0x1U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
9627 #define GPIO_PUPDR_PUPD13_1            (0x2U << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
9628 #define GPIO_PUPDR_PUPD14_Pos          (28U)
9629 #define GPIO_PUPDR_PUPD14_Msk          (0x3U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */
9630 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
9631 #define GPIO_PUPDR_PUPD14_0            (0x1U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
9632 #define GPIO_PUPDR_PUPD14_1            (0x2U << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
9633 #define GPIO_PUPDR_PUPD15_Pos          (30U)
9634 #define GPIO_PUPDR_PUPD15_Msk          (0x3U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */
9635 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
9636 #define GPIO_PUPDR_PUPD15_0            (0x1U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
9637 #define GPIO_PUPDR_PUPD15_1            (0x2U << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
9638 
9639 /* Legacy defines */
9640 #define GPIO_PUPDR_PUPDR0                   GPIO_PUPDR_PUPD0
9641 #define GPIO_PUPDR_PUPDR0_0                 GPIO_PUPDR_PUPD0_0
9642 #define GPIO_PUPDR_PUPDR0_1                 GPIO_PUPDR_PUPD0_1
9643 #define GPIO_PUPDR_PUPDR1                   GPIO_PUPDR_PUPD1
9644 #define GPIO_PUPDR_PUPDR1_0                 GPIO_PUPDR_PUPD1_0
9645 #define GPIO_PUPDR_PUPDR1_1                 GPIO_PUPDR_PUPD1_1
9646 #define GPIO_PUPDR_PUPDR2                   GPIO_PUPDR_PUPD2
9647 #define GPIO_PUPDR_PUPDR2_0                 GPIO_PUPDR_PUPD2_0
9648 #define GPIO_PUPDR_PUPDR2_1                 GPIO_PUPDR_PUPD2_1
9649 #define GPIO_PUPDR_PUPDR3                   GPIO_PUPDR_PUPD3
9650 #define GPIO_PUPDR_PUPDR3_0                 GPIO_PUPDR_PUPD3_0
9651 #define GPIO_PUPDR_PUPDR3_1                 GPIO_PUPDR_PUPD3_1
9652 #define GPIO_PUPDR_PUPDR4                   GPIO_PUPDR_PUPD4
9653 #define GPIO_PUPDR_PUPDR4_0                 GPIO_PUPDR_PUPD4_0
9654 #define GPIO_PUPDR_PUPDR4_1                 GPIO_PUPDR_PUPD4_1
9655 #define GPIO_PUPDR_PUPDR5                   GPIO_PUPDR_PUPD5
9656 #define GPIO_PUPDR_PUPDR5_0                 GPIO_PUPDR_PUPD5_0
9657 #define GPIO_PUPDR_PUPDR5_1                 GPIO_PUPDR_PUPD5_1
9658 #define GPIO_PUPDR_PUPDR6                   GPIO_PUPDR_PUPD6
9659 #define GPIO_PUPDR_PUPDR6_0                 GPIO_PUPDR_PUPD6_0
9660 #define GPIO_PUPDR_PUPDR6_1                 GPIO_PUPDR_PUPD6_1
9661 #define GPIO_PUPDR_PUPDR7                   GPIO_PUPDR_PUPD7
9662 #define GPIO_PUPDR_PUPDR7_0                 GPIO_PUPDR_PUPD7_0
9663 #define GPIO_PUPDR_PUPDR7_1                 GPIO_PUPDR_PUPD7_1
9664 #define GPIO_PUPDR_PUPDR8                   GPIO_PUPDR_PUPD8
9665 #define GPIO_PUPDR_PUPDR8_0                 GPIO_PUPDR_PUPD8_0
9666 #define GPIO_PUPDR_PUPDR8_1                 GPIO_PUPDR_PUPD8_1
9667 #define GPIO_PUPDR_PUPDR9                   GPIO_PUPDR_PUPD9
9668 #define GPIO_PUPDR_PUPDR9_0                 GPIO_PUPDR_PUPD9_0
9669 #define GPIO_PUPDR_PUPDR9_1                 GPIO_PUPDR_PUPD9_1
9670 #define GPIO_PUPDR_PUPDR10                  GPIO_PUPDR_PUPD10
9671 #define GPIO_PUPDR_PUPDR10_0                GPIO_PUPDR_PUPD10_0
9672 #define GPIO_PUPDR_PUPDR10_1                GPIO_PUPDR_PUPD10_1
9673 #define GPIO_PUPDR_PUPDR11                  GPIO_PUPDR_PUPD11
9674 #define GPIO_PUPDR_PUPDR11_0                GPIO_PUPDR_PUPD11_0
9675 #define GPIO_PUPDR_PUPDR11_1                GPIO_PUPDR_PUPD11_1
9676 #define GPIO_PUPDR_PUPDR12                  GPIO_PUPDR_PUPD12
9677 #define GPIO_PUPDR_PUPDR12_0                GPIO_PUPDR_PUPD12_0
9678 #define GPIO_PUPDR_PUPDR12_1                GPIO_PUPDR_PUPD12_1
9679 #define GPIO_PUPDR_PUPDR13                  GPIO_PUPDR_PUPD13
9680 #define GPIO_PUPDR_PUPDR13_0                GPIO_PUPDR_PUPD13_0
9681 #define GPIO_PUPDR_PUPDR13_1                GPIO_PUPDR_PUPD13_1
9682 #define GPIO_PUPDR_PUPDR14                  GPIO_PUPDR_PUPD14
9683 #define GPIO_PUPDR_PUPDR14_0                GPIO_PUPDR_PUPD14_0
9684 #define GPIO_PUPDR_PUPDR14_1                GPIO_PUPDR_PUPD14_1
9685 #define GPIO_PUPDR_PUPDR15                  GPIO_PUPDR_PUPD15
9686 #define GPIO_PUPDR_PUPDR15_0                GPIO_PUPDR_PUPD15_0
9687 #define GPIO_PUPDR_PUPDR15_1                GPIO_PUPDR_PUPD15_1
9688 
9689 /******************  Bits definition for GPIO_IDR register  *******************/
9690 #define GPIO_IDR_ID0_Pos               (0U)
9691 #define GPIO_IDR_ID0_Msk               (0x1U << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */
9692 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
9693 #define GPIO_IDR_ID1_Pos               (1U)
9694 #define GPIO_IDR_ID1_Msk               (0x1U << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */
9695 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
9696 #define GPIO_IDR_ID2_Pos               (2U)
9697 #define GPIO_IDR_ID2_Msk               (0x1U << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */
9698 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
9699 #define GPIO_IDR_ID3_Pos               (3U)
9700 #define GPIO_IDR_ID3_Msk               (0x1U << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */
9701 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
9702 #define GPIO_IDR_ID4_Pos               (4U)
9703 #define GPIO_IDR_ID4_Msk               (0x1U << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */
9704 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
9705 #define GPIO_IDR_ID5_Pos               (5U)
9706 #define GPIO_IDR_ID5_Msk               (0x1U << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */
9707 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
9708 #define GPIO_IDR_ID6_Pos               (6U)
9709 #define GPIO_IDR_ID6_Msk               (0x1U << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */
9710 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
9711 #define GPIO_IDR_ID7_Pos               (7U)
9712 #define GPIO_IDR_ID7_Msk               (0x1U << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */
9713 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
9714 #define GPIO_IDR_ID8_Pos               (8U)
9715 #define GPIO_IDR_ID8_Msk               (0x1U << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */
9716 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
9717 #define GPIO_IDR_ID9_Pos               (9U)
9718 #define GPIO_IDR_ID9_Msk               (0x1U << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */
9719 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
9720 #define GPIO_IDR_ID10_Pos              (10U)
9721 #define GPIO_IDR_ID10_Msk              (0x1U << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */
9722 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
9723 #define GPIO_IDR_ID11_Pos              (11U)
9724 #define GPIO_IDR_ID11_Msk              (0x1U << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */
9725 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
9726 #define GPIO_IDR_ID12_Pos              (12U)
9727 #define GPIO_IDR_ID12_Msk              (0x1U << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */
9728 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
9729 #define GPIO_IDR_ID13_Pos              (13U)
9730 #define GPIO_IDR_ID13_Msk              (0x1U << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */
9731 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
9732 #define GPIO_IDR_ID14_Pos              (14U)
9733 #define GPIO_IDR_ID14_Msk              (0x1U << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */
9734 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
9735 #define GPIO_IDR_ID15_Pos              (15U)
9736 #define GPIO_IDR_ID15_Msk              (0x1U << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */
9737 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
9738 
9739 /* Legacy defines */
9740 #define GPIO_IDR_IDR_0                      GPIO_IDR_ID0
9741 #define GPIO_IDR_IDR_1                      GPIO_IDR_ID1
9742 #define GPIO_IDR_IDR_2                      GPIO_IDR_ID2
9743 #define GPIO_IDR_IDR_3                      GPIO_IDR_ID3
9744 #define GPIO_IDR_IDR_4                      GPIO_IDR_ID4
9745 #define GPIO_IDR_IDR_5                      GPIO_IDR_ID5
9746 #define GPIO_IDR_IDR_6                      GPIO_IDR_ID6
9747 #define GPIO_IDR_IDR_7                      GPIO_IDR_ID7
9748 #define GPIO_IDR_IDR_8                      GPIO_IDR_ID8
9749 #define GPIO_IDR_IDR_9                      GPIO_IDR_ID9
9750 #define GPIO_IDR_IDR_10                     GPIO_IDR_ID10
9751 #define GPIO_IDR_IDR_11                     GPIO_IDR_ID11
9752 #define GPIO_IDR_IDR_12                     GPIO_IDR_ID12
9753 #define GPIO_IDR_IDR_13                     GPIO_IDR_ID13
9754 #define GPIO_IDR_IDR_14                     GPIO_IDR_ID14
9755 #define GPIO_IDR_IDR_15                     GPIO_IDR_ID15
9756 
9757 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
9758 #define GPIO_OTYPER_IDR_0                   GPIO_IDR_ID0
9759 #define GPIO_OTYPER_IDR_1                   GPIO_IDR_ID1
9760 #define GPIO_OTYPER_IDR_2                   GPIO_IDR_ID2
9761 #define GPIO_OTYPER_IDR_3                   GPIO_IDR_ID3
9762 #define GPIO_OTYPER_IDR_4                   GPIO_IDR_ID4
9763 #define GPIO_OTYPER_IDR_5                   GPIO_IDR_ID5
9764 #define GPIO_OTYPER_IDR_6                   GPIO_IDR_ID6
9765 #define GPIO_OTYPER_IDR_7                   GPIO_IDR_ID7
9766 #define GPIO_OTYPER_IDR_8                   GPIO_IDR_ID8
9767 #define GPIO_OTYPER_IDR_9                   GPIO_IDR_ID9
9768 #define GPIO_OTYPER_IDR_10                  GPIO_IDR_ID10
9769 #define GPIO_OTYPER_IDR_11                  GPIO_IDR_ID11
9770 #define GPIO_OTYPER_IDR_12                  GPIO_IDR_ID12
9771 #define GPIO_OTYPER_IDR_13                  GPIO_IDR_ID13
9772 #define GPIO_OTYPER_IDR_14                  GPIO_IDR_ID14
9773 #define GPIO_OTYPER_IDR_15                  GPIO_IDR_ID15
9774 
9775 /******************  Bits definition for GPIO_ODR register  *******************/
9776 #define GPIO_ODR_OD0_Pos               (0U)
9777 #define GPIO_ODR_OD0_Msk               (0x1U << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */
9778 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
9779 #define GPIO_ODR_OD1_Pos               (1U)
9780 #define GPIO_ODR_OD1_Msk               (0x1U << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */
9781 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
9782 #define GPIO_ODR_OD2_Pos               (2U)
9783 #define GPIO_ODR_OD2_Msk               (0x1U << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */
9784 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
9785 #define GPIO_ODR_OD3_Pos               (3U)
9786 #define GPIO_ODR_OD3_Msk               (0x1U << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */
9787 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
9788 #define GPIO_ODR_OD4_Pos               (4U)
9789 #define GPIO_ODR_OD4_Msk               (0x1U << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */
9790 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
9791 #define GPIO_ODR_OD5_Pos               (5U)
9792 #define GPIO_ODR_OD5_Msk               (0x1U << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */
9793 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
9794 #define GPIO_ODR_OD6_Pos               (6U)
9795 #define GPIO_ODR_OD6_Msk               (0x1U << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */
9796 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
9797 #define GPIO_ODR_OD7_Pos               (7U)
9798 #define GPIO_ODR_OD7_Msk               (0x1U << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */
9799 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
9800 #define GPIO_ODR_OD8_Pos               (8U)
9801 #define GPIO_ODR_OD8_Msk               (0x1U << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */
9802 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
9803 #define GPIO_ODR_OD9_Pos               (9U)
9804 #define GPIO_ODR_OD9_Msk               (0x1U << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */
9805 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
9806 #define GPIO_ODR_OD10_Pos              (10U)
9807 #define GPIO_ODR_OD10_Msk              (0x1U << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */
9808 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
9809 #define GPIO_ODR_OD11_Pos              (11U)
9810 #define GPIO_ODR_OD11_Msk              (0x1U << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */
9811 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
9812 #define GPIO_ODR_OD12_Pos              (12U)
9813 #define GPIO_ODR_OD12_Msk              (0x1U << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */
9814 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
9815 #define GPIO_ODR_OD13_Pos              (13U)
9816 #define GPIO_ODR_OD13_Msk              (0x1U << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */
9817 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
9818 #define GPIO_ODR_OD14_Pos              (14U)
9819 #define GPIO_ODR_OD14_Msk              (0x1U << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */
9820 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
9821 #define GPIO_ODR_OD15_Pos              (15U)
9822 #define GPIO_ODR_OD15_Msk              (0x1U << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */
9823 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
9824 
9825 /* Legacy defines */
9826 #define GPIO_ODR_ODR_0                      GPIO_ODR_OD0
9827 #define GPIO_ODR_ODR_1                      GPIO_ODR_OD1
9828 #define GPIO_ODR_ODR_2                      GPIO_ODR_OD2
9829 #define GPIO_ODR_ODR_3                      GPIO_ODR_OD3
9830 #define GPIO_ODR_ODR_4                      GPIO_ODR_OD4
9831 #define GPIO_ODR_ODR_5                      GPIO_ODR_OD5
9832 #define GPIO_ODR_ODR_6                      GPIO_ODR_OD6
9833 #define GPIO_ODR_ODR_7                      GPIO_ODR_OD7
9834 #define GPIO_ODR_ODR_8                      GPIO_ODR_OD8
9835 #define GPIO_ODR_ODR_9                      GPIO_ODR_OD9
9836 #define GPIO_ODR_ODR_10                     GPIO_ODR_OD10
9837 #define GPIO_ODR_ODR_11                     GPIO_ODR_OD11
9838 #define GPIO_ODR_ODR_12                     GPIO_ODR_OD12
9839 #define GPIO_ODR_ODR_13                     GPIO_ODR_OD13
9840 #define GPIO_ODR_ODR_14                     GPIO_ODR_OD14
9841 #define GPIO_ODR_ODR_15                     GPIO_ODR_OD15
9842 
9843 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
9844 #define GPIO_OTYPER_ODR_0                   GPIO_ODR_OD0
9845 #define GPIO_OTYPER_ODR_1                   GPIO_ODR_OD1
9846 #define GPIO_OTYPER_ODR_2                   GPIO_ODR_OD2
9847 #define GPIO_OTYPER_ODR_3                   GPIO_ODR_OD3
9848 #define GPIO_OTYPER_ODR_4                   GPIO_ODR_OD4
9849 #define GPIO_OTYPER_ODR_5                   GPIO_ODR_OD5
9850 #define GPIO_OTYPER_ODR_6                   GPIO_ODR_OD6
9851 #define GPIO_OTYPER_ODR_7                   GPIO_ODR_OD7
9852 #define GPIO_OTYPER_ODR_8                   GPIO_ODR_OD8
9853 #define GPIO_OTYPER_ODR_9                   GPIO_ODR_OD9
9854 #define GPIO_OTYPER_ODR_10                  GPIO_ODR_OD10
9855 #define GPIO_OTYPER_ODR_11                  GPIO_ODR_OD11
9856 #define GPIO_OTYPER_ODR_12                  GPIO_ODR_OD12
9857 #define GPIO_OTYPER_ODR_13                  GPIO_ODR_OD13
9858 #define GPIO_OTYPER_ODR_14                  GPIO_ODR_OD14
9859 #define GPIO_OTYPER_ODR_15                  GPIO_ODR_OD15
9860 
9861 /******************  Bits definition for GPIO_BSRR register  ******************/
9862 #define GPIO_BSRR_BS0_Pos              (0U)
9863 #define GPIO_BSRR_BS0_Msk              (0x1U << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */
9864 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
9865 #define GPIO_BSRR_BS1_Pos              (1U)
9866 #define GPIO_BSRR_BS1_Msk              (0x1U << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */
9867 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
9868 #define GPIO_BSRR_BS2_Pos              (2U)
9869 #define GPIO_BSRR_BS2_Msk              (0x1U << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */
9870 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
9871 #define GPIO_BSRR_BS3_Pos              (3U)
9872 #define GPIO_BSRR_BS3_Msk              (0x1U << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */
9873 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
9874 #define GPIO_BSRR_BS4_Pos              (4U)
9875 #define GPIO_BSRR_BS4_Msk              (0x1U << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */
9876 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
9877 #define GPIO_BSRR_BS5_Pos              (5U)
9878 #define GPIO_BSRR_BS5_Msk              (0x1U << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */
9879 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
9880 #define GPIO_BSRR_BS6_Pos              (6U)
9881 #define GPIO_BSRR_BS6_Msk              (0x1U << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */
9882 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
9883 #define GPIO_BSRR_BS7_Pos              (7U)
9884 #define GPIO_BSRR_BS7_Msk              (0x1U << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */
9885 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
9886 #define GPIO_BSRR_BS8_Pos              (8U)
9887 #define GPIO_BSRR_BS8_Msk              (0x1U << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */
9888 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
9889 #define GPIO_BSRR_BS9_Pos              (9U)
9890 #define GPIO_BSRR_BS9_Msk              (0x1U << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */
9891 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
9892 #define GPIO_BSRR_BS10_Pos             (10U)
9893 #define GPIO_BSRR_BS10_Msk             (0x1U << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */
9894 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
9895 #define GPIO_BSRR_BS11_Pos             (11U)
9896 #define GPIO_BSRR_BS11_Msk             (0x1U << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */
9897 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
9898 #define GPIO_BSRR_BS12_Pos             (12U)
9899 #define GPIO_BSRR_BS12_Msk             (0x1U << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */
9900 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
9901 #define GPIO_BSRR_BS13_Pos             (13U)
9902 #define GPIO_BSRR_BS13_Msk             (0x1U << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */
9903 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
9904 #define GPIO_BSRR_BS14_Pos             (14U)
9905 #define GPIO_BSRR_BS14_Msk             (0x1U << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */
9906 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
9907 #define GPIO_BSRR_BS15_Pos             (15U)
9908 #define GPIO_BSRR_BS15_Msk             (0x1U << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */
9909 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
9910 #define GPIO_BSRR_BR0_Pos              (16U)
9911 #define GPIO_BSRR_BR0_Msk              (0x1U << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */
9912 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
9913 #define GPIO_BSRR_BR1_Pos              (17U)
9914 #define GPIO_BSRR_BR1_Msk              (0x1U << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */
9915 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
9916 #define GPIO_BSRR_BR2_Pos              (18U)
9917 #define GPIO_BSRR_BR2_Msk              (0x1U << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */
9918 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
9919 #define GPIO_BSRR_BR3_Pos              (19U)
9920 #define GPIO_BSRR_BR3_Msk              (0x1U << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */
9921 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
9922 #define GPIO_BSRR_BR4_Pos              (20U)
9923 #define GPIO_BSRR_BR4_Msk              (0x1U << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */
9924 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
9925 #define GPIO_BSRR_BR5_Pos              (21U)
9926 #define GPIO_BSRR_BR5_Msk              (0x1U << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */
9927 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
9928 #define GPIO_BSRR_BR6_Pos              (22U)
9929 #define GPIO_BSRR_BR6_Msk              (0x1U << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */
9930 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
9931 #define GPIO_BSRR_BR7_Pos              (23U)
9932 #define GPIO_BSRR_BR7_Msk              (0x1U << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */
9933 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
9934 #define GPIO_BSRR_BR8_Pos              (24U)
9935 #define GPIO_BSRR_BR8_Msk              (0x1U << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */
9936 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
9937 #define GPIO_BSRR_BR9_Pos              (25U)
9938 #define GPIO_BSRR_BR9_Msk              (0x1U << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */
9939 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
9940 #define GPIO_BSRR_BR10_Pos             (26U)
9941 #define GPIO_BSRR_BR10_Msk             (0x1U << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */
9942 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
9943 #define GPIO_BSRR_BR11_Pos             (27U)
9944 #define GPIO_BSRR_BR11_Msk             (0x1U << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */
9945 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
9946 #define GPIO_BSRR_BR12_Pos             (28U)
9947 #define GPIO_BSRR_BR12_Msk             (0x1U << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */
9948 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
9949 #define GPIO_BSRR_BR13_Pos             (29U)
9950 #define GPIO_BSRR_BR13_Msk             (0x1U << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */
9951 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
9952 #define GPIO_BSRR_BR14_Pos             (30U)
9953 #define GPIO_BSRR_BR14_Msk             (0x1U << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */
9954 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
9955 #define GPIO_BSRR_BR15_Pos             (31U)
9956 #define GPIO_BSRR_BR15_Msk             (0x1U << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */
9957 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
9958 
9959 /* Legacy defines */
9960 #define GPIO_BSRR_BS_0                      GPIO_BSRR_BS0
9961 #define GPIO_BSRR_BS_1                      GPIO_BSRR_BS1
9962 #define GPIO_BSRR_BS_2                      GPIO_BSRR_BS2
9963 #define GPIO_BSRR_BS_3                      GPIO_BSRR_BS3
9964 #define GPIO_BSRR_BS_4                      GPIO_BSRR_BS4
9965 #define GPIO_BSRR_BS_5                      GPIO_BSRR_BS5
9966 #define GPIO_BSRR_BS_6                      GPIO_BSRR_BS6
9967 #define GPIO_BSRR_BS_7                      GPIO_BSRR_BS7
9968 #define GPIO_BSRR_BS_8                      GPIO_BSRR_BS8
9969 #define GPIO_BSRR_BS_9                      GPIO_BSRR_BS9
9970 #define GPIO_BSRR_BS_10                     GPIO_BSRR_BS10
9971 #define GPIO_BSRR_BS_11                     GPIO_BSRR_BS11
9972 #define GPIO_BSRR_BS_12                     GPIO_BSRR_BS12
9973 #define GPIO_BSRR_BS_13                     GPIO_BSRR_BS13
9974 #define GPIO_BSRR_BS_14                     GPIO_BSRR_BS14
9975 #define GPIO_BSRR_BS_15                     GPIO_BSRR_BS15
9976 #define GPIO_BSRR_BR_0                      GPIO_BSRR_BR0
9977 #define GPIO_BSRR_BR_1                      GPIO_BSRR_BR1
9978 #define GPIO_BSRR_BR_2                      GPIO_BSRR_BR2
9979 #define GPIO_BSRR_BR_3                      GPIO_BSRR_BR3
9980 #define GPIO_BSRR_BR_4                      GPIO_BSRR_BR4
9981 #define GPIO_BSRR_BR_5                      GPIO_BSRR_BR5
9982 #define GPIO_BSRR_BR_6                      GPIO_BSRR_BR6
9983 #define GPIO_BSRR_BR_7                      GPIO_BSRR_BR7
9984 #define GPIO_BSRR_BR_8                      GPIO_BSRR_BR8
9985 #define GPIO_BSRR_BR_9                      GPIO_BSRR_BR9
9986 #define GPIO_BSRR_BR_10                     GPIO_BSRR_BR10
9987 #define GPIO_BSRR_BR_11                     GPIO_BSRR_BR11
9988 #define GPIO_BSRR_BR_12                     GPIO_BSRR_BR12
9989 #define GPIO_BSRR_BR_13                     GPIO_BSRR_BR13
9990 #define GPIO_BSRR_BR_14                     GPIO_BSRR_BR14
9991 #define GPIO_BSRR_BR_15                     GPIO_BSRR_BR15
9992 
9993 /****************** Bit definition for GPIO_LCKR register *********************/
9994 #define GPIO_LCKR_LCK0_Pos             (0U)
9995 #define GPIO_LCKR_LCK0_Msk             (0x1U << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */
9996 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
9997 #define GPIO_LCKR_LCK1_Pos             (1U)
9998 #define GPIO_LCKR_LCK1_Msk             (0x1U << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */
9999 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
10000 #define GPIO_LCKR_LCK2_Pos             (2U)
10001 #define GPIO_LCKR_LCK2_Msk             (0x1U << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */
10002 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
10003 #define GPIO_LCKR_LCK3_Pos             (3U)
10004 #define GPIO_LCKR_LCK3_Msk             (0x1U << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */
10005 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
10006 #define GPIO_LCKR_LCK4_Pos             (4U)
10007 #define GPIO_LCKR_LCK4_Msk             (0x1U << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */
10008 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
10009 #define GPIO_LCKR_LCK5_Pos             (5U)
10010 #define GPIO_LCKR_LCK5_Msk             (0x1U << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */
10011 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
10012 #define GPIO_LCKR_LCK6_Pos             (6U)
10013 #define GPIO_LCKR_LCK6_Msk             (0x1U << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */
10014 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
10015 #define GPIO_LCKR_LCK7_Pos             (7U)
10016 #define GPIO_LCKR_LCK7_Msk             (0x1U << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */
10017 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
10018 #define GPIO_LCKR_LCK8_Pos             (8U)
10019 #define GPIO_LCKR_LCK8_Msk             (0x1U << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */
10020 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
10021 #define GPIO_LCKR_LCK9_Pos             (9U)
10022 #define GPIO_LCKR_LCK9_Msk             (0x1U << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */
10023 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
10024 #define GPIO_LCKR_LCK10_Pos            (10U)
10025 #define GPIO_LCKR_LCK10_Msk            (0x1U << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */
10026 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
10027 #define GPIO_LCKR_LCK11_Pos            (11U)
10028 #define GPIO_LCKR_LCK11_Msk            (0x1U << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */
10029 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
10030 #define GPIO_LCKR_LCK12_Pos            (12U)
10031 #define GPIO_LCKR_LCK12_Msk            (0x1U << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */
10032 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
10033 #define GPIO_LCKR_LCK13_Pos            (13U)
10034 #define GPIO_LCKR_LCK13_Msk            (0x1U << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */
10035 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
10036 #define GPIO_LCKR_LCK14_Pos            (14U)
10037 #define GPIO_LCKR_LCK14_Msk            (0x1U << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */
10038 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
10039 #define GPIO_LCKR_LCK15_Pos            (15U)
10040 #define GPIO_LCKR_LCK15_Msk            (0x1U << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */
10041 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
10042 #define GPIO_LCKR_LCKK_Pos             (16U)
10043 #define GPIO_LCKR_LCKK_Msk             (0x1U << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */
10044 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
10045 
10046 /****************** Bit definition for GPIO_AFRL register *********************/
10047 #define GPIO_AFRL_AFSEL0_Pos           (0U)
10048 #define GPIO_AFRL_AFSEL0_Msk           (0xFU << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
10049 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
10050 #define GPIO_AFRL_AFSEL0_0             (0x1U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
10051 #define GPIO_AFRL_AFSEL0_1             (0x2U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
10052 #define GPIO_AFRL_AFSEL0_2             (0x4U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
10053 #define GPIO_AFRL_AFSEL0_3             (0x8U << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
10054 #define GPIO_AFRL_AFSEL1_Pos           (4U)
10055 #define GPIO_AFRL_AFSEL1_Msk           (0xFU << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
10056 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
10057 #define GPIO_AFRL_AFSEL1_0             (0x1U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
10058 #define GPIO_AFRL_AFSEL1_1             (0x2U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
10059 #define GPIO_AFRL_AFSEL1_2             (0x4U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
10060 #define GPIO_AFRL_AFSEL1_3             (0x8U << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
10061 #define GPIO_AFRL_AFSEL2_Pos           (8U)
10062 #define GPIO_AFRL_AFSEL2_Msk           (0xFU << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
10063 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
10064 #define GPIO_AFRL_AFSEL2_0             (0x1U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
10065 #define GPIO_AFRL_AFSEL2_1             (0x2U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
10066 #define GPIO_AFRL_AFSEL2_2             (0x4U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
10067 #define GPIO_AFRL_AFSEL2_3             (0x8U << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
10068 #define GPIO_AFRL_AFSEL3_Pos           (12U)
10069 #define GPIO_AFRL_AFSEL3_Msk           (0xFU << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
10070 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
10071 #define GPIO_AFRL_AFSEL3_0             (0x1U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
10072 #define GPIO_AFRL_AFSEL3_1             (0x2U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
10073 #define GPIO_AFRL_AFSEL3_2             (0x4U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
10074 #define GPIO_AFRL_AFSEL3_3             (0x8U << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
10075 #define GPIO_AFRL_AFSEL4_Pos           (16U)
10076 #define GPIO_AFRL_AFSEL4_Msk           (0xFU << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
10077 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
10078 #define GPIO_AFRL_AFSEL4_0             (0x1U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
10079 #define GPIO_AFRL_AFSEL4_1             (0x2U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
10080 #define GPIO_AFRL_AFSEL4_2             (0x4U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
10081 #define GPIO_AFRL_AFSEL4_3             (0x8U << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
10082 #define GPIO_AFRL_AFSEL5_Pos           (20U)
10083 #define GPIO_AFRL_AFSEL5_Msk           (0xFU << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
10084 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
10085 #define GPIO_AFRL_AFSEL5_0             (0x1U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
10086 #define GPIO_AFRL_AFSEL5_1             (0x2U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
10087 #define GPIO_AFRL_AFSEL5_2             (0x4U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
10088 #define GPIO_AFRL_AFSEL5_3             (0x8U << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
10089 #define GPIO_AFRL_AFSEL6_Pos           (24U)
10090 #define GPIO_AFRL_AFSEL6_Msk           (0xFU << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
10091 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
10092 #define GPIO_AFRL_AFSEL6_0             (0x1U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
10093 #define GPIO_AFRL_AFSEL6_1             (0x2U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
10094 #define GPIO_AFRL_AFSEL6_2             (0x4U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
10095 #define GPIO_AFRL_AFSEL6_3             (0x8U << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
10096 #define GPIO_AFRL_AFSEL7_Pos           (28U)
10097 #define GPIO_AFRL_AFSEL7_Msk           (0xFU << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
10098 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
10099 #define GPIO_AFRL_AFSEL7_0             (0x1U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
10100 #define GPIO_AFRL_AFSEL7_1             (0x2U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
10101 #define GPIO_AFRL_AFSEL7_2             (0x4U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
10102 #define GPIO_AFRL_AFSEL7_3             (0x8U << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
10103 
10104 /* Legacy defines */
10105 #define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
10106 #define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
10107 #define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
10108 #define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
10109 #define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
10110 #define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
10111 #define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
10112 #define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
10113 
10114 /****************** Bit definition for GPIO_AFRH register *********************/
10115 #define GPIO_AFRH_AFSEL8_Pos           (0U)
10116 #define GPIO_AFRH_AFSEL8_Msk           (0xFU << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
10117 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
10118 #define GPIO_AFRH_AFSEL8_0             (0x1U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
10119 #define GPIO_AFRH_AFSEL8_1             (0x2U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
10120 #define GPIO_AFRH_AFSEL8_2             (0x4U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
10121 #define GPIO_AFRH_AFSEL8_3             (0x8U << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
10122 #define GPIO_AFRH_AFSEL9_Pos           (4U)
10123 #define GPIO_AFRH_AFSEL9_Msk           (0xFU << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
10124 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
10125 #define GPIO_AFRH_AFSEL9_0             (0x1U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
10126 #define GPIO_AFRH_AFSEL9_1             (0x2U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
10127 #define GPIO_AFRH_AFSEL9_2             (0x4U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
10128 #define GPIO_AFRH_AFSEL9_3             (0x8U << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
10129 #define GPIO_AFRH_AFSEL10_Pos          (8U)
10130 #define GPIO_AFRH_AFSEL10_Msk          (0xFU << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */
10131 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
10132 #define GPIO_AFRH_AFSEL10_0            (0x1U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
10133 #define GPIO_AFRH_AFSEL10_1            (0x2U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
10134 #define GPIO_AFRH_AFSEL10_2            (0x4U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
10135 #define GPIO_AFRH_AFSEL10_3            (0x8U << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
10136 #define GPIO_AFRH_AFSEL11_Pos          (12U)
10137 #define GPIO_AFRH_AFSEL11_Msk          (0xFU << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */
10138 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
10139 #define GPIO_AFRH_AFSEL11_0            (0x1U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
10140 #define GPIO_AFRH_AFSEL11_1            (0x2U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
10141 #define GPIO_AFRH_AFSEL11_2            (0x4U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
10142 #define GPIO_AFRH_AFSEL11_3            (0x8U << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
10143 #define GPIO_AFRH_AFSEL12_Pos          (16U)
10144 #define GPIO_AFRH_AFSEL12_Msk          (0xFU << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */
10145 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
10146 #define GPIO_AFRH_AFSEL12_0            (0x1U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
10147 #define GPIO_AFRH_AFSEL12_1            (0x2U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
10148 #define GPIO_AFRH_AFSEL12_2            (0x4U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
10149 #define GPIO_AFRH_AFSEL12_3            (0x8U << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
10150 #define GPIO_AFRH_AFSEL13_Pos          (20U)
10151 #define GPIO_AFRH_AFSEL13_Msk          (0xFU << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */
10152 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
10153 #define GPIO_AFRH_AFSEL13_0            (0x1U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
10154 #define GPIO_AFRH_AFSEL13_1            (0x2U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
10155 #define GPIO_AFRH_AFSEL13_2            (0x4U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
10156 #define GPIO_AFRH_AFSEL13_3            (0x8U << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
10157 #define GPIO_AFRH_AFSEL14_Pos          (24U)
10158 #define GPIO_AFRH_AFSEL14_Msk          (0xFU << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */
10159 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
10160 #define GPIO_AFRH_AFSEL14_0            (0x1U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
10161 #define GPIO_AFRH_AFSEL14_1            (0x2U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
10162 #define GPIO_AFRH_AFSEL14_2            (0x4U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
10163 #define GPIO_AFRH_AFSEL14_3            (0x8U << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
10164 #define GPIO_AFRH_AFSEL15_Pos          (28U)
10165 #define GPIO_AFRH_AFSEL15_Msk          (0xFU << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */
10166 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
10167 #define GPIO_AFRH_AFSEL15_0            (0x1U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
10168 #define GPIO_AFRH_AFSEL15_1            (0x2U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
10169 #define GPIO_AFRH_AFSEL15_2            (0x4U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
10170 #define GPIO_AFRH_AFSEL15_3            (0x8U << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
10171 
10172 /* Legacy defines */
10173 #define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
10174 #define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
10175 #define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
10176 #define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
10177 #define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
10178 #define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
10179 #define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
10180 #define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
10181 
10182 /******************  Bits definition for GPIO_BRR register  ******************/
10183 #define GPIO_BRR_BR0_Pos               (0U)
10184 #define GPIO_BRR_BR0_Msk               (0x1U << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */
10185 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
10186 #define GPIO_BRR_BR1_Pos               (1U)
10187 #define GPIO_BRR_BR1_Msk               (0x1U << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */
10188 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
10189 #define GPIO_BRR_BR2_Pos               (2U)
10190 #define GPIO_BRR_BR2_Msk               (0x1U << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */
10191 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
10192 #define GPIO_BRR_BR3_Pos               (3U)
10193 #define GPIO_BRR_BR3_Msk               (0x1U << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */
10194 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
10195 #define GPIO_BRR_BR4_Pos               (4U)
10196 #define GPIO_BRR_BR4_Msk               (0x1U << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */
10197 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
10198 #define GPIO_BRR_BR5_Pos               (5U)
10199 #define GPIO_BRR_BR5_Msk               (0x1U << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */
10200 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
10201 #define GPIO_BRR_BR6_Pos               (6U)
10202 #define GPIO_BRR_BR6_Msk               (0x1U << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */
10203 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
10204 #define GPIO_BRR_BR7_Pos               (7U)
10205 #define GPIO_BRR_BR7_Msk               (0x1U << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */
10206 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
10207 #define GPIO_BRR_BR8_Pos               (8U)
10208 #define GPIO_BRR_BR8_Msk               (0x1U << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */
10209 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
10210 #define GPIO_BRR_BR9_Pos               (9U)
10211 #define GPIO_BRR_BR9_Msk               (0x1U << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */
10212 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
10213 #define GPIO_BRR_BR10_Pos              (10U)
10214 #define GPIO_BRR_BR10_Msk              (0x1U << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */
10215 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
10216 #define GPIO_BRR_BR11_Pos              (11U)
10217 #define GPIO_BRR_BR11_Msk              (0x1U << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */
10218 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
10219 #define GPIO_BRR_BR12_Pos              (12U)
10220 #define GPIO_BRR_BR12_Msk              (0x1U << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */
10221 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
10222 #define GPIO_BRR_BR13_Pos              (13U)
10223 #define GPIO_BRR_BR13_Msk              (0x1U << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */
10224 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
10225 #define GPIO_BRR_BR14_Pos              (14U)
10226 #define GPIO_BRR_BR14_Msk              (0x1U << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */
10227 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
10228 #define GPIO_BRR_BR15_Pos              (15U)
10229 #define GPIO_BRR_BR15_Msk              (0x1U << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */
10230 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
10231 
10232 /* Legacy defines */
10233 #define GPIO_BRR_BR_0                       GPIO_BRR_BR0
10234 #define GPIO_BRR_BR_1                       GPIO_BRR_BR1
10235 #define GPIO_BRR_BR_2                       GPIO_BRR_BR2
10236 #define GPIO_BRR_BR_3                       GPIO_BRR_BR3
10237 #define GPIO_BRR_BR_4                       GPIO_BRR_BR4
10238 #define GPIO_BRR_BR_5                       GPIO_BRR_BR5
10239 #define GPIO_BRR_BR_6                       GPIO_BRR_BR6
10240 #define GPIO_BRR_BR_7                       GPIO_BRR_BR7
10241 #define GPIO_BRR_BR_8                       GPIO_BRR_BR8
10242 #define GPIO_BRR_BR_9                       GPIO_BRR_BR9
10243 #define GPIO_BRR_BR_10                      GPIO_BRR_BR10
10244 #define GPIO_BRR_BR_11                      GPIO_BRR_BR11
10245 #define GPIO_BRR_BR_12                      GPIO_BRR_BR12
10246 #define GPIO_BRR_BR_13                      GPIO_BRR_BR13
10247 #define GPIO_BRR_BR_14                      GPIO_BRR_BR14
10248 #define GPIO_BRR_BR_15                      GPIO_BRR_BR15
10249 
10250 
10251 
10252 /******************************************************************************/
10253 /*                                                                            */
10254 /*                                    HASH                                    */
10255 /*                                                                            */
10256 /******************************************************************************/
10257 /******************  Bits definition for HASH_CR register  ********************/
10258 #define HASH_CR_INIT_Pos          (2U)
10259 #define HASH_CR_INIT_Msk          (0x1U << HASH_CR_INIT_Pos)                   /*!< 0x00000004 */
10260 #define HASH_CR_INIT              HASH_CR_INIT_Msk
10261 #define HASH_CR_DMAE_Pos          (3U)
10262 #define HASH_CR_DMAE_Msk          (0x1U << HASH_CR_DMAE_Pos)                   /*!< 0x00000008 */
10263 #define HASH_CR_DMAE              HASH_CR_DMAE_Msk
10264 #define HASH_CR_DATATYPE_Pos      (4U)
10265 #define HASH_CR_DATATYPE_Msk      (0x3U << HASH_CR_DATATYPE_Pos)               /*!< 0x00000030 */
10266 #define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk
10267 #define HASH_CR_DATATYPE_0        (0x1U << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */
10268 #define HASH_CR_DATATYPE_1        (0x2U << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */
10269 #define HASH_CR_MODE_Pos          (6U)
10270 #define HASH_CR_MODE_Msk          (0x1U << HASH_CR_MODE_Pos)                   /*!< 0x00000040 */
10271 #define HASH_CR_MODE              HASH_CR_MODE_Msk
10272 #define HASH_CR_ALGO_Pos          (7U)
10273 #define HASH_CR_ALGO_Msk          (0x801U << HASH_CR_ALGO_Pos)                 /*!< 0x00040080 */
10274 #define HASH_CR_ALGO              HASH_CR_ALGO_Msk
10275 #define HASH_CR_ALGO_0            (0x001U << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */
10276 #define HASH_CR_ALGO_1            (0x800U << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */
10277 #define HASH_CR_NBW_Pos           (8U)
10278 #define HASH_CR_NBW_Msk           (0xFU << HASH_CR_NBW_Pos)                    /*!< 0x00000F00 */
10279 #define HASH_CR_NBW               HASH_CR_NBW_Msk
10280 #define HASH_CR_NBW_0             (0x1U << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */
10281 #define HASH_CR_NBW_1             (0x2U << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */
10282 #define HASH_CR_NBW_2             (0x4U << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */
10283 #define HASH_CR_NBW_3             (0x8U << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */
10284 #define HASH_CR_DINNE_Pos         (12U)
10285 #define HASH_CR_DINNE_Msk         (0x1U << HASH_CR_DINNE_Pos)                  /*!< 0x00001000 */
10286 #define HASH_CR_DINNE             HASH_CR_DINNE_Msk
10287 #define HASH_CR_MDMAT_Pos         (13U)
10288 #define HASH_CR_MDMAT_Msk         (0x1U << HASH_CR_MDMAT_Pos)                  /*!< 0x00002000 */
10289 #define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk
10290 #define HASH_CR_LKEY_Pos          (16U)
10291 #define HASH_CR_LKEY_Msk          (0x1U << HASH_CR_LKEY_Pos)                   /*!< 0x00010000 */
10292 #define HASH_CR_LKEY              HASH_CR_LKEY_Msk
10293 
10294 /******************  Bits definition for HASH_STR register  *******************/
10295 #define HASH_STR_NBLW_Pos         (0U)
10296 #define HASH_STR_NBLW_Msk         (0x1FU << HASH_STR_NBLW_Pos)                 /*!< 0x0000001F */
10297 #define HASH_STR_NBLW             HASH_STR_NBLW_Msk
10298 #define HASH_STR_NBLW_0           (0x01U << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */
10299 #define HASH_STR_NBLW_1           (0x02U << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */
10300 #define HASH_STR_NBLW_2           (0x04U << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */
10301 #define HASH_STR_NBLW_3           (0x08U << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */
10302 #define HASH_STR_NBLW_4           (0x10U << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */
10303 #define HASH_STR_DCAL_Pos         (8U)
10304 #define HASH_STR_DCAL_Msk         (0x1U << HASH_STR_DCAL_Pos)                  /*!< 0x00000100 */
10305 #define HASH_STR_DCAL             HASH_STR_DCAL_Msk
10306 
10307 /******************  Bits definition for HASH_IMR register  *******************/
10308 #define HASH_IMR_DINIE_Pos        (0U)
10309 #define HASH_IMR_DINIE_Msk        (0x1U << HASH_IMR_DINIE_Pos)                 /*!< 0x00000001 */
10310 #define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk
10311 #define HASH_IMR_DCIE_Pos         (1U)
10312 #define HASH_IMR_DCIE_Msk         (0x1U << HASH_IMR_DCIE_Pos)                  /*!< 0x00000002 */
10313 #define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk
10314 
10315 /******************  Bits definition for HASH_SR register  ********************/
10316 #define HASH_SR_DINIS_Pos         (0U)
10317 #define HASH_SR_DINIS_Msk         (0x1U << HASH_SR_DINIS_Pos)                  /*!< 0x00000001 */
10318 #define HASH_SR_DINIS             HASH_SR_DINIS_Msk
10319 #define HASH_SR_DCIS_Pos          (1U)
10320 #define HASH_SR_DCIS_Msk          (0x1U << HASH_SR_DCIS_Pos)                   /*!< 0x00000002 */
10321 #define HASH_SR_DCIS              HASH_SR_DCIS_Msk
10322 #define HASH_SR_DMAS_Pos          (2U)
10323 #define HASH_SR_DMAS_Msk          (0x1U << HASH_SR_DMAS_Pos)                   /*!< 0x00000004 */
10324 #define HASH_SR_DMAS              HASH_SR_DMAS_Msk
10325 #define HASH_SR_BUSY_Pos          (3U)
10326 #define HASH_SR_BUSY_Msk          (0x1U << HASH_SR_BUSY_Pos)                   /*!< 0x00000008 */
10327 #define HASH_SR_BUSY              HASH_SR_BUSY_Msk
10328 
10329 /******************************************************************************/
10330 /*                                                                            */
10331 /*                      Inter-integrated Circuit Interface (I2C)              */
10332 /*                                                                            */
10333 /******************************************************************************/
10334 /*******************  Bit definition for I2C_CR1 register  *******************/
10335 #define I2C_CR1_PE_Pos               (0U)
10336 #define I2C_CR1_PE_Msk               (0x1U << I2C_CR1_PE_Pos)                  /*!< 0x00000001 */
10337 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable                   */
10338 #define I2C_CR1_TXIE_Pos             (1U)
10339 #define I2C_CR1_TXIE_Msk             (0x1U << I2C_CR1_TXIE_Pos)                /*!< 0x00000002 */
10340 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable                 */
10341 #define I2C_CR1_RXIE_Pos             (2U)
10342 #define I2C_CR1_RXIE_Msk             (0x1U << I2C_CR1_RXIE_Pos)                /*!< 0x00000004 */
10343 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable                 */
10344 #define I2C_CR1_ADDRIE_Pos           (3U)
10345 #define I2C_CR1_ADDRIE_Msk           (0x1U << I2C_CR1_ADDRIE_Pos)              /*!< 0x00000008 */
10346 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable      */
10347 #define I2C_CR1_NACKIE_Pos           (4U)
10348 #define I2C_CR1_NACKIE_Msk           (0x1U << I2C_CR1_NACKIE_Pos)              /*!< 0x00000010 */
10349 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable      */
10350 #define I2C_CR1_STOPIE_Pos           (5U)
10351 #define I2C_CR1_STOPIE_Msk           (0x1U << I2C_CR1_STOPIE_Pos)              /*!< 0x00000020 */
10352 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable     */
10353 #define I2C_CR1_TCIE_Pos             (6U)
10354 #define I2C_CR1_TCIE_Msk             (0x1U << I2C_CR1_TCIE_Pos)                /*!< 0x00000040 */
10355 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable  */
10356 #define I2C_CR1_ERRIE_Pos            (7U)
10357 #define I2C_CR1_ERRIE_Msk            (0x1U << I2C_CR1_ERRIE_Pos)               /*!< 0x00000080 */
10358 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable             */
10359 #define I2C_CR1_DNF_Pos              (8U)
10360 #define I2C_CR1_DNF_Msk              (0xFU << I2C_CR1_DNF_Pos)                 /*!< 0x00000F00 */
10361 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter                */
10362 #define I2C_CR1_ANFOFF_Pos           (12U)
10363 #define I2C_CR1_ANFOFF_Msk           (0x1U << I2C_CR1_ANFOFF_Pos)              /*!< 0x00001000 */
10364 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF             */
10365 #define I2C_CR1_SWRST_Pos            (13U)
10366 #define I2C_CR1_SWRST_Msk            (0x1U << I2C_CR1_SWRST_Pos)               /*!< 0x00002000 */
10367 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset                      */
10368 #define I2C_CR1_TXDMAEN_Pos          (14U)
10369 #define I2C_CR1_TXDMAEN_Msk          (0x1U << I2C_CR1_TXDMAEN_Pos)             /*!< 0x00004000 */
10370 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable    */
10371 #define I2C_CR1_RXDMAEN_Pos          (15U)
10372 #define I2C_CR1_RXDMAEN_Msk          (0x1U << I2C_CR1_RXDMAEN_Pos)             /*!< 0x00008000 */
10373 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable       */
10374 #define I2C_CR1_SBC_Pos              (16U)
10375 #define I2C_CR1_SBC_Msk              (0x1U << I2C_CR1_SBC_Pos)                 /*!< 0x00010000 */
10376 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control                  */
10377 #define I2C_CR1_NOSTRETCH_Pos        (17U)
10378 #define I2C_CR1_NOSTRETCH_Msk        (0x1U << I2C_CR1_NOSTRETCH_Pos)           /*!< 0x00020000 */
10379 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable            */
10380 #define I2C_CR1_WUPEN_Pos            (18U)
10381 #define I2C_CR1_WUPEN_Msk            (0x1U << I2C_CR1_WUPEN_Pos)               /*!< 0x00040000 */
10382 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable             */
10383 #define I2C_CR1_GCEN_Pos             (19U)
10384 #define I2C_CR1_GCEN_Msk             (0x1U << I2C_CR1_GCEN_Pos)                /*!< 0x00080000 */
10385 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable                 */
10386 #define I2C_CR1_SMBHEN_Pos           (20U)
10387 #define I2C_CR1_SMBHEN_Msk           (0x1U << I2C_CR1_SMBHEN_Pos)              /*!< 0x00100000 */
10388 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable           */
10389 #define I2C_CR1_SMBDEN_Pos           (21U)
10390 #define I2C_CR1_SMBDEN_Msk           (0x1U << I2C_CR1_SMBDEN_Pos)              /*!< 0x00200000 */
10391 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
10392 #define I2C_CR1_ALERTEN_Pos          (22U)
10393 #define I2C_CR1_ALERTEN_Msk          (0x1U << I2C_CR1_ALERTEN_Pos)             /*!< 0x00400000 */
10394 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable                  */
10395 #define I2C_CR1_PECEN_Pos            (23U)
10396 #define I2C_CR1_PECEN_Msk            (0x1U << I2C_CR1_PECEN_Pos)               /*!< 0x00800000 */
10397 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable                          */
10398 
10399 /******************  Bit definition for I2C_CR2 register  ********************/
10400 #define I2C_CR2_SADD_Pos             (0U)
10401 #define I2C_CR2_SADD_Msk             (0x3FFU << I2C_CR2_SADD_Pos)              /*!< 0x000003FF */
10402 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode)                             */
10403 #define I2C_CR2_RD_WRN_Pos           (10U)
10404 #define I2C_CR2_RD_WRN_Msk           (0x1U << I2C_CR2_RD_WRN_Pos)              /*!< 0x00000400 */
10405 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode)                        */
10406 #define I2C_CR2_ADD10_Pos            (11U)
10407 #define I2C_CR2_ADD10_Msk            (0x1U << I2C_CR2_ADD10_Pos)               /*!< 0x00000800 */
10408 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode)                    */
10409 #define I2C_CR2_HEAD10R_Pos          (12U)
10410 #define I2C_CR2_HEAD10R_Msk          (0x1U << I2C_CR2_HEAD10R_Pos)             /*!< 0x00001000 */
10411 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
10412 #define I2C_CR2_START_Pos            (13U)
10413 #define I2C_CR2_START_Msk            (0x1U << I2C_CR2_START_Pos)               /*!< 0x00002000 */
10414 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation                                        */
10415 #define I2C_CR2_STOP_Pos             (14U)
10416 #define I2C_CR2_STOP_Msk             (0x1U << I2C_CR2_STOP_Pos)                /*!< 0x00004000 */
10417 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode)                           */
10418 #define I2C_CR2_NACK_Pos             (15U)
10419 #define I2C_CR2_NACK_Msk             (0x1U << I2C_CR2_NACK_Pos)                /*!< 0x00008000 */
10420 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode)                            */
10421 #define I2C_CR2_NBYTES_Pos           (16U)
10422 #define I2C_CR2_NBYTES_Msk           (0xFFU << I2C_CR2_NBYTES_Pos)             /*!< 0x00FF0000 */
10423 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes                                         */
10424 #define I2C_CR2_RELOAD_Pos           (24U)
10425 #define I2C_CR2_RELOAD_Msk           (0x1U << I2C_CR2_RELOAD_Pos)              /*!< 0x01000000 */
10426 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode                                      */
10427 #define I2C_CR2_AUTOEND_Pos          (25U)
10428 #define I2C_CR2_AUTOEND_Msk          (0x1U << I2C_CR2_AUTOEND_Pos)             /*!< 0x02000000 */
10429 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode)                        */
10430 #define I2C_CR2_PECBYTE_Pos          (26U)
10431 #define I2C_CR2_PECBYTE_Msk          (0x1U << I2C_CR2_PECBYTE_Pos)             /*!< 0x04000000 */
10432 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte                              */
10433 
10434 /*******************  Bit definition for I2C_OAR1 register  ******************/
10435 #define I2C_OAR1_OA1_Pos             (0U)
10436 #define I2C_OAR1_OA1_Msk             (0x3FFU << I2C_OAR1_OA1_Pos)              /*!< 0x000003FF */
10437 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1   */
10438 #define I2C_OAR1_OA1MODE_Pos         (10U)
10439 #define I2C_OAR1_OA1MODE_Msk         (0x1U << I2C_OAR1_OA1MODE_Pos)            /*!< 0x00000400 */
10440 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
10441 #define I2C_OAR1_OA1EN_Pos           (15U)
10442 #define I2C_OAR1_OA1EN_Msk           (0x1U << I2C_OAR1_OA1EN_Pos)              /*!< 0x00008000 */
10443 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable      */
10444 
10445 /*******************  Bit definition for I2C_OAR2 register  ******************/
10446 #define I2C_OAR2_OA2_Pos             (1U)
10447 #define I2C_OAR2_OA2_Msk             (0x7FU << I2C_OAR2_OA2_Pos)               /*!< 0x000000FE */
10448 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2                        */
10449 #define I2C_OAR2_OA2MSK_Pos          (8U)
10450 #define I2C_OAR2_OA2MSK_Msk          (0x7U << I2C_OAR2_OA2MSK_Pos)             /*!< 0x00000700 */
10451 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks                            */
10452 #define I2C_OAR2_OA2NOMASK           (0x00000000U)                             /*!< No mask                                        */
10453 #define I2C_OAR2_OA2MASK01_Pos       (8U)
10454 #define I2C_OAR2_OA2MASK01_Msk       (0x1U << I2C_OAR2_OA2MASK01_Pos)          /*!< 0x00000100 */
10455 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
10456 #define I2C_OAR2_OA2MASK02_Pos       (9U)
10457 #define I2C_OAR2_OA2MASK02_Msk       (0x1U << I2C_OAR2_OA2MASK02_Pos)          /*!< 0x00000200 */
10458 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
10459 #define I2C_OAR2_OA2MASK03_Pos       (8U)
10460 #define I2C_OAR2_OA2MASK03_Msk       (0x3U << I2C_OAR2_OA2MASK03_Pos)          /*!< 0x00000300 */
10461 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
10462 #define I2C_OAR2_OA2MASK04_Pos       (10U)
10463 #define I2C_OAR2_OA2MASK04_Msk       (0x1U << I2C_OAR2_OA2MASK04_Pos)          /*!< 0x00000400 */
10464 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
10465 #define I2C_OAR2_OA2MASK05_Pos       (8U)
10466 #define I2C_OAR2_OA2MASK05_Msk       (0x5U << I2C_OAR2_OA2MASK05_Pos)          /*!< 0x00000500 */
10467 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
10468 #define I2C_OAR2_OA2MASK06_Pos       (9U)
10469 #define I2C_OAR2_OA2MASK06_Msk       (0x3U << I2C_OAR2_OA2MASK06_Pos)          /*!< 0x00000600 */
10470 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
10471 #define I2C_OAR2_OA2MASK07_Pos       (8U)
10472 #define I2C_OAR2_OA2MASK07_Msk       (0x7U << I2C_OAR2_OA2MASK07_Pos)          /*!< 0x00000700 */
10473 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
10474 #define I2C_OAR2_OA2EN_Pos           (15U)
10475 #define I2C_OAR2_OA2EN_Msk           (0x1U << I2C_OAR2_OA2EN_Pos)              /*!< 0x00008000 */
10476 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable                           */
10477 
10478 /*******************  Bit definition for I2C_TIMINGR register *******************/
10479 #define I2C_TIMINGR_SCLL_Pos         (0U)
10480 #define I2C_TIMINGR_SCLL_Msk         (0xFFU << I2C_TIMINGR_SCLL_Pos)           /*!< 0x000000FF */
10481 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode)  */
10482 #define I2C_TIMINGR_SCLH_Pos         (8U)
10483 #define I2C_TIMINGR_SCLH_Msk         (0xFFU << I2C_TIMINGR_SCLH_Pos)           /*!< 0x0000FF00 */
10484 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
10485 #define I2C_TIMINGR_SDADEL_Pos       (16U)
10486 #define I2C_TIMINGR_SDADEL_Msk       (0xFU << I2C_TIMINGR_SDADEL_Pos)          /*!< 0x000F0000 */
10487 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time                */
10488 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
10489 #define I2C_TIMINGR_SCLDEL_Msk       (0xFU << I2C_TIMINGR_SCLDEL_Pos)          /*!< 0x00F00000 */
10490 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time               */
10491 #define I2C_TIMINGR_PRESC_Pos        (28U)
10492 #define I2C_TIMINGR_PRESC_Msk        (0xFU << I2C_TIMINGR_PRESC_Pos)           /*!< 0xF0000000 */
10493 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler             */
10494 
10495 /******************* Bit definition for I2C_TIMEOUTR register *******************/
10496 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
10497 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos)     /*!< 0x00000FFF */
10498 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A                 */
10499 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
10500 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1U << I2C_TIMEOUTR_TIDLE_Pos)          /*!< 0x00001000 */
10501 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection  */
10502 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
10503 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos)       /*!< 0x00008000 */
10504 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable          */
10505 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
10506 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos)     /*!< 0x0FFF0000 */
10507 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B                 */
10508 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
10509 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1U << I2C_TIMEOUTR_TEXTEN_Pos)         /*!< 0x80000000 */
10510 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
10511 
10512 /******************  Bit definition for I2C_ISR register  *********************/
10513 #define I2C_ISR_TXE_Pos              (0U)
10514 #define I2C_ISR_TXE_Msk              (0x1U << I2C_ISR_TXE_Pos)                 /*!< 0x00000001 */
10515 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty    */
10516 #define I2C_ISR_TXIS_Pos             (1U)
10517 #define I2C_ISR_TXIS_Msk             (0x1U << I2C_ISR_TXIS_Pos)                /*!< 0x00000002 */
10518 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status       */
10519 #define I2C_ISR_RXNE_Pos             (2U)
10520 #define I2C_ISR_RXNE_Msk             (0x1U << I2C_ISR_RXNE_Pos)                /*!< 0x00000004 */
10521 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
10522 #define I2C_ISR_ADDR_Pos             (3U)
10523 #define I2C_ISR_ADDR_Msk             (0x1U << I2C_ISR_ADDR_Pos)                /*!< 0x00000008 */
10524 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)    */
10525 #define I2C_ISR_NACKF_Pos            (4U)
10526 #define I2C_ISR_NACKF_Msk            (0x1U << I2C_ISR_NACKF_Pos)               /*!< 0x00000010 */
10527 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag              */
10528 #define I2C_ISR_STOPF_Pos            (5U)
10529 #define I2C_ISR_STOPF_Msk            (0x1U << I2C_ISR_STOPF_Pos)               /*!< 0x00000020 */
10530 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag             */
10531 #define I2C_ISR_TC_Pos               (6U)
10532 #define I2C_ISR_TC_Msk               (0x1U << I2C_ISR_TC_Pos)                  /*!< 0x00000040 */
10533 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
10534 #define I2C_ISR_TCR_Pos              (7U)
10535 #define I2C_ISR_TCR_Msk              (0x1U << I2C_ISR_TCR_Pos)                 /*!< 0x00000080 */
10536 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload        */
10537 #define I2C_ISR_BERR_Pos             (8U)
10538 #define I2C_ISR_BERR_Msk             (0x1U << I2C_ISR_BERR_Pos)                /*!< 0x00000100 */
10539 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error                       */
10540 #define I2C_ISR_ARLO_Pos             (9U)
10541 #define I2C_ISR_ARLO_Msk             (0x1U << I2C_ISR_ARLO_Pos)                /*!< 0x00000200 */
10542 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost                */
10543 #define I2C_ISR_OVR_Pos              (10U)
10544 #define I2C_ISR_OVR_Msk              (0x1U << I2C_ISR_OVR_Pos)                 /*!< 0x00000400 */
10545 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun                */
10546 #define I2C_ISR_PECERR_Pos           (11U)
10547 #define I2C_ISR_PECERR_Msk           (0x1U << I2C_ISR_PECERR_Pos)              /*!< 0x00000800 */
10548 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception          */
10549 #define I2C_ISR_TIMEOUT_Pos          (12U)
10550 #define I2C_ISR_TIMEOUT_Msk          (0x1U << I2C_ISR_TIMEOUT_Pos)             /*!< 0x00001000 */
10551 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag  */
10552 #define I2C_ISR_ALERT_Pos            (13U)
10553 #define I2C_ISR_ALERT_Msk            (0x1U << I2C_ISR_ALERT_Pos)               /*!< 0x00002000 */
10554 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert                     */
10555 #define I2C_ISR_BUSY_Pos             (15U)
10556 #define I2C_ISR_BUSY_Msk             (0x1U << I2C_ISR_BUSY_Pos)                /*!< 0x00008000 */
10557 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy                        */
10558 #define I2C_ISR_DIR_Pos              (16U)
10559 #define I2C_ISR_DIR_Msk              (0x1U << I2C_ISR_DIR_Pos)                 /*!< 0x00010000 */
10560 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
10561 #define I2C_ISR_ADDCODE_Pos          (17U)
10562 #define I2C_ISR_ADDCODE_Msk          (0x7FU << I2C_ISR_ADDCODE_Pos)            /*!< 0x00FE0000 */
10563 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
10564 
10565 /******************  Bit definition for I2C_ICR register  *********************/
10566 #define I2C_ICR_ADDRCF_Pos           (3U)
10567 #define I2C_ICR_ADDRCF_Msk           (0x1U << I2C_ICR_ADDRCF_Pos)              /*!< 0x00000008 */
10568 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag  */
10569 #define I2C_ICR_NACKCF_Pos           (4U)
10570 #define I2C_ICR_NACKCF_Msk           (0x1U << I2C_ICR_NACKCF_Pos)              /*!< 0x00000010 */
10571 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag             */
10572 #define I2C_ICR_STOPCF_Pos           (5U)
10573 #define I2C_ICR_STOPCF_Msk           (0x1U << I2C_ICR_STOPCF_Pos)              /*!< 0x00000020 */
10574 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag   */
10575 #define I2C_ICR_BERRCF_Pos           (8U)
10576 #define I2C_ICR_BERRCF_Msk           (0x1U << I2C_ICR_BERRCF_Pos)              /*!< 0x00000100 */
10577 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag        */
10578 #define I2C_ICR_ARLOCF_Pos           (9U)
10579 #define I2C_ICR_ARLOCF_Msk           (0x1U << I2C_ICR_ARLOCF_Pos)              /*!< 0x00000200 */
10580 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
10581 #define I2C_ICR_OVRCF_Pos            (10U)
10582 #define I2C_ICR_OVRCF_Msk            (0x1U << I2C_ICR_OVRCF_Pos)               /*!< 0x00000400 */
10583 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
10584 #define I2C_ICR_PECCF_Pos            (11U)
10585 #define I2C_ICR_PECCF_Msk            (0x1U << I2C_ICR_PECCF_Pos)               /*!< 0x00000800 */
10586 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag        */
10587 #define I2C_ICR_TIMOUTCF_Pos         (12U)
10588 #define I2C_ICR_TIMOUTCF_Msk         (0x1U << I2C_ICR_TIMOUTCF_Pos)            /*!< 0x00001000 */
10589 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag          */
10590 #define I2C_ICR_ALERTCF_Pos          (13U)
10591 #define I2C_ICR_ALERTCF_Msk          (0x1U << I2C_ICR_ALERTCF_Pos)             /*!< 0x00002000 */
10592 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag            */
10593 
10594 /******************  Bit definition for I2C_PECR register  *********************/
10595 #define I2C_PECR_PEC_Pos             (0U)
10596 #define I2C_PECR_PEC_Msk             (0xFFU << I2C_PECR_PEC_Pos)               /*!< 0x000000FF */
10597 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
10598 
10599 /******************  Bit definition for I2C_RXDR register  *********************/
10600 #define I2C_RXDR_RXDATA_Pos          (0U)
10601 #define I2C_RXDR_RXDATA_Msk          (0xFFU << I2C_RXDR_RXDATA_Pos)            /*!< 0x000000FF */
10602 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
10603 
10604 /******************  Bit definition for I2C_TXDR register  *********************/
10605 #define I2C_TXDR_TXDATA_Pos          (0U)
10606 #define I2C_TXDR_TXDATA_Msk          (0xFFU << I2C_TXDR_TXDATA_Pos)            /*!< 0x000000FF */
10607 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
10608 
10609 /******************************************************************************/
10610 /*                                                                            */
10611 /*                           Independent WATCHDOG                             */
10612 /*                                                                            */
10613 /******************************************************************************/
10614 /*******************  Bit definition for IWDG_KR register  ********************/
10615 #define IWDG_KR_KEY_Pos      (0U)
10616 #define IWDG_KR_KEY_Msk      (0xFFFFU << IWDG_KR_KEY_Pos)                      /*!< 0x0000FFFF */
10617 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
10618 
10619 /*******************  Bit definition for IWDG_PR register  ********************/
10620 #define IWDG_PR_PR_Pos       (0U)
10621 #define IWDG_PR_PR_Msk       (0x7U << IWDG_PR_PR_Pos)                          /*!< 0x00000007 */
10622 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
10623 #define IWDG_PR_PR_0         (0x1U << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
10624 #define IWDG_PR_PR_1         (0x2U << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
10625 #define IWDG_PR_PR_2         (0x4U << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
10626 
10627 /*******************  Bit definition for IWDG_RLR register  *******************/
10628 #define IWDG_RLR_RL_Pos      (0U)
10629 #define IWDG_RLR_RL_Msk      (0xFFFU << IWDG_RLR_RL_Pos)                       /*!< 0x00000FFF */
10630 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
10631 
10632 /*******************  Bit definition for IWDG_SR register  ********************/
10633 #define IWDG_SR_PVU_Pos      (0U)
10634 #define IWDG_SR_PVU_Msk      (0x1U << IWDG_SR_PVU_Pos)                         /*!< 0x00000001 */
10635 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
10636 #define IWDG_SR_RVU_Pos      (1U)
10637 #define IWDG_SR_RVU_Msk      (0x1U << IWDG_SR_RVU_Pos)                         /*!< 0x00000002 */
10638 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
10639 #define IWDG_SR_WVU_Pos      (2U)
10640 #define IWDG_SR_WVU_Msk      (0x1U << IWDG_SR_WVU_Pos)                         /*!< 0x00000004 */
10641 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
10642 
10643 /*******************  Bit definition for IWDG_KR register  ********************/
10644 #define IWDG_WINR_WIN_Pos    (0U)
10645 #define IWDG_WINR_WIN_Msk    (0xFFFU << IWDG_WINR_WIN_Pos)                     /*!< 0x00000FFF */
10646 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
10647 
10648 /******************************************************************************/
10649 /*                                                                            */
10650 /*                                     Firewall                               */
10651 /*                                                                            */
10652 /******************************************************************************/
10653 
10654 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register          */
10655 #define FW_CSSA_ADD_Pos      (8U)
10656 #define FW_CSSA_ADD_Msk      (0xFFFFU << FW_CSSA_ADD_Pos)                      /*!< 0x00FFFF00 */
10657 #define FW_CSSA_ADD          FW_CSSA_ADD_Msk                                   /*!< Code Segment Start Address */
10658 #define FW_CSL_LENG_Pos      (8U)
10659 #define FW_CSL_LENG_Msk      (0x3FFFU << FW_CSL_LENG_Pos)                      /*!< 0x003FFF00 */
10660 #define FW_CSL_LENG          FW_CSL_LENG_Msk                                   /*!< Code Segment Length        */
10661 #define FW_NVDSSA_ADD_Pos    (8U)
10662 #define FW_NVDSSA_ADD_Msk    (0xFFFFU << FW_NVDSSA_ADD_Pos)                    /*!< 0x00FFFF00 */
10663 #define FW_NVDSSA_ADD        FW_NVDSSA_ADD_Msk                                 /*!< Non Volatile Dat Segment Start Address */
10664 #define FW_NVDSL_LENG_Pos    (8U)
10665 #define FW_NVDSL_LENG_Msk    (0x3FFFU << FW_NVDSL_LENG_Pos)                    /*!< 0x003FFF00 */
10666 #define FW_NVDSL_LENG        FW_NVDSL_LENG_Msk                                 /*!< Non Volatile Data Segment Length */
10667 #define FW_VDSSA_ADD_Pos     (6U)
10668 #define FW_VDSSA_ADD_Msk     (0xFFFU << FW_VDSSA_ADD_Pos)                      /*!< 0x0003FFC0 */
10669 #define FW_VDSSA_ADD         FW_VDSSA_ADD_Msk                                  /*!< Volatile Data Segment Start Address */
10670 #define FW_VDSL_LENG_Pos     (6U)
10671 #define FW_VDSL_LENG_Msk     (0xFFFU << FW_VDSL_LENG_Pos)                      /*!< 0x0003FFC0 */
10672 #define FW_VDSL_LENG         FW_VDSL_LENG_Msk                                  /*!< Volatile Data Segment Length */
10673 
10674 /**************************Bit definition for CR register *********************/
10675 #define FW_CR_FPA_Pos        (0U)
10676 #define FW_CR_FPA_Msk        (0x1U << FW_CR_FPA_Pos)                           /*!< 0x00000001 */
10677 #define FW_CR_FPA            FW_CR_FPA_Msk                                     /*!< Firewall Pre Arm*/
10678 #define FW_CR_VDS_Pos        (1U)
10679 #define FW_CR_VDS_Msk        (0x1U << FW_CR_VDS_Pos)                           /*!< 0x00000002 */
10680 #define FW_CR_VDS            FW_CR_VDS_Msk                                     /*!< Volatile Data Sharing*/
10681 #define FW_CR_VDE_Pos        (2U)
10682 #define FW_CR_VDE_Msk        (0x1U << FW_CR_VDE_Pos)                           /*!< 0x00000004 */
10683 #define FW_CR_VDE            FW_CR_VDE_Msk                                     /*!< Volatile Data Execution*/
10684 
10685 /******************************************************************************/
10686 /*                                                                            */
10687 /*                             Power Control                                  */
10688 /*                                                                            */
10689 /******************************************************************************/
10690 
10691 /********************  Bit definition for PWR_CR1 register  ********************/
10692 
10693 #define PWR_CR1_LPR_Pos              (14U)
10694 #define PWR_CR1_LPR_Msk              (0x1U << PWR_CR1_LPR_Pos)                 /*!< 0x00004000 */
10695 #define PWR_CR1_LPR                  PWR_CR1_LPR_Msk                           /*!< Regulator low-power mode */
10696 #define PWR_CR1_VOS_Pos              (9U)
10697 #define PWR_CR1_VOS_Msk              (0x3U << PWR_CR1_VOS_Pos)                 /*!< 0x00000600 */
10698 #define PWR_CR1_VOS                  PWR_CR1_VOS_Msk                           /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
10699 #define PWR_CR1_VOS_0                (0x1U << PWR_CR1_VOS_Pos)                 /*!< 0x00000200 */
10700 #define PWR_CR1_VOS_1                (0x2U << PWR_CR1_VOS_Pos)                 /*!< 0x00000400 */
10701 #define PWR_CR1_DBP_Pos              (8U)
10702 #define PWR_CR1_DBP_Msk              (0x1U << PWR_CR1_DBP_Pos)                 /*!< 0x00000100 */
10703 #define PWR_CR1_DBP                  PWR_CR1_DBP_Msk                           /*!< Disable Back-up domain Protection */
10704 #define PWR_CR1_LPMS_Pos             (0U)
10705 #define PWR_CR1_LPMS_Msk             (0x7U << PWR_CR1_LPMS_Pos)                /*!< 0x00000007 */
10706 #define PWR_CR1_LPMS                 PWR_CR1_LPMS_Msk                          /*!< Low-power mode selection field */
10707 #define PWR_CR1_LPMS_STOP0           (0x00000000U)                             /*!< Stop 0 mode */
10708 #define PWR_CR1_LPMS_STOP1_Pos       (0U)
10709 #define PWR_CR1_LPMS_STOP1_Msk       (0x1U << PWR_CR1_LPMS_STOP1_Pos)          /*!< 0x00000001 */
10710 #define PWR_CR1_LPMS_STOP1           PWR_CR1_LPMS_STOP1_Msk                    /*!< Stop 1 mode */
10711 #define PWR_CR1_LPMS_STOP2_Pos       (1U)
10712 #define PWR_CR1_LPMS_STOP2_Msk       (0x1U << PWR_CR1_LPMS_STOP2_Pos)          /*!< 0x00000002 */
10713 #define PWR_CR1_LPMS_STOP2           PWR_CR1_LPMS_STOP2_Msk                    /*!< Stop 2 mode */
10714 #define PWR_CR1_LPMS_STANDBY_Pos     (0U)
10715 #define PWR_CR1_LPMS_STANDBY_Msk     (0x3U << PWR_CR1_LPMS_STANDBY_Pos)        /*!< 0x00000003 */
10716 #define PWR_CR1_LPMS_STANDBY         PWR_CR1_LPMS_STANDBY_Msk                  /*!< Stand-by mode */
10717 #define PWR_CR1_LPMS_SHUTDOWN_Pos    (2U)
10718 #define PWR_CR1_LPMS_SHUTDOWN_Msk    (0x1U << PWR_CR1_LPMS_SHUTDOWN_Pos)       /*!< 0x00000004 */
10719 #define PWR_CR1_LPMS_SHUTDOWN        PWR_CR1_LPMS_SHUTDOWN_Msk                 /*!< Shut-down mode */
10720 
10721 
10722 /********************  Bit definition for PWR_CR2 register  ********************/
10723 #define PWR_CR2_USV_Pos              (10U)
10724 #define PWR_CR2_USV_Msk              (0x1U << PWR_CR2_USV_Pos)                 /*!< 0x00000400 */
10725 #define PWR_CR2_USV                  PWR_CR2_USV_Msk                           /*!< VDD USB Supply Valid */
10726 #define PWR_CR2_IOSV_Pos             (9U)
10727 #define PWR_CR2_IOSV_Msk             (0x1U << PWR_CR2_IOSV_Pos)                /*!< 0x00000200 */
10728 #define PWR_CR2_IOSV                 PWR_CR2_IOSV_Msk                          /*!< VDD IO2 independent I/Os Supply Valid */
10729 /*!< PVME  Peripheral Voltage Monitor Enable */
10730 #define PWR_CR2_PVME_Pos             (4U)
10731 #define PWR_CR2_PVME_Msk             (0xFU << PWR_CR2_PVME_Pos)                /*!< 0x000000F0 */
10732 #define PWR_CR2_PVME                 PWR_CR2_PVME_Msk                          /*!< PVM bits field */
10733 #define PWR_CR2_PVME4_Pos            (7U)
10734 #define PWR_CR2_PVME4_Msk            (0x1U << PWR_CR2_PVME4_Pos)               /*!< 0x00000080 */
10735 #define PWR_CR2_PVME4                PWR_CR2_PVME4_Msk                         /*!< PVM 4 Enable */
10736 #define PWR_CR2_PVME3_Pos            (6U)
10737 #define PWR_CR2_PVME3_Msk            (0x1U << PWR_CR2_PVME3_Pos)               /*!< 0x00000040 */
10738 #define PWR_CR2_PVME3                PWR_CR2_PVME3_Msk                         /*!< PVM 3 Enable */
10739 #define PWR_CR2_PVME2_Pos            (5U)
10740 #define PWR_CR2_PVME2_Msk            (0x1U << PWR_CR2_PVME2_Pos)               /*!< 0x00000020 */
10741 #define PWR_CR2_PVME2                PWR_CR2_PVME2_Msk                         /*!< PVM 2 Enable */
10742 #define PWR_CR2_PVME1_Pos            (4U)
10743 #define PWR_CR2_PVME1_Msk            (0x1U << PWR_CR2_PVME1_Pos)               /*!< 0x00000010 */
10744 #define PWR_CR2_PVME1                PWR_CR2_PVME1_Msk                         /*!< PVM 1 Enable */
10745 /*!< PVD level configuration */
10746 #define PWR_CR2_PLS_Pos              (1U)
10747 #define PWR_CR2_PLS_Msk              (0x7U << PWR_CR2_PLS_Pos)                 /*!< 0x0000000E */
10748 #define PWR_CR2_PLS                  PWR_CR2_PLS_Msk                           /*!< PVD level selection */
10749 #define PWR_CR2_PLS_LEV0             (0x00000000U)                             /*!< PVD level 0 */
10750 #define PWR_CR2_PLS_LEV1_Pos         (1U)
10751 #define PWR_CR2_PLS_LEV1_Msk         (0x1U << PWR_CR2_PLS_LEV1_Pos)            /*!< 0x00000002 */
10752 #define PWR_CR2_PLS_LEV1             PWR_CR2_PLS_LEV1_Msk                      /*!< PVD level 1 */
10753 #define PWR_CR2_PLS_LEV2_Pos         (2U)
10754 #define PWR_CR2_PLS_LEV2_Msk         (0x1U << PWR_CR2_PLS_LEV2_Pos)            /*!< 0x00000004 */
10755 #define PWR_CR2_PLS_LEV2             PWR_CR2_PLS_LEV2_Msk                      /*!< PVD level 2 */
10756 #define PWR_CR2_PLS_LEV3_Pos         (1U)
10757 #define PWR_CR2_PLS_LEV3_Msk         (0x3U << PWR_CR2_PLS_LEV3_Pos)            /*!< 0x00000006 */
10758 #define PWR_CR2_PLS_LEV3             PWR_CR2_PLS_LEV3_Msk                      /*!< PVD level 3 */
10759 #define PWR_CR2_PLS_LEV4_Pos         (3U)
10760 #define PWR_CR2_PLS_LEV4_Msk         (0x1U << PWR_CR2_PLS_LEV4_Pos)            /*!< 0x00000008 */
10761 #define PWR_CR2_PLS_LEV4             PWR_CR2_PLS_LEV4_Msk                      /*!< PVD level 4 */
10762 #define PWR_CR2_PLS_LEV5_Pos         (1U)
10763 #define PWR_CR2_PLS_LEV5_Msk         (0x5U << PWR_CR2_PLS_LEV5_Pos)            /*!< 0x0000000A */
10764 #define PWR_CR2_PLS_LEV5             PWR_CR2_PLS_LEV5_Msk                      /*!< PVD level 5 */
10765 #define PWR_CR2_PLS_LEV6_Pos         (2U)
10766 #define PWR_CR2_PLS_LEV6_Msk         (0x3U << PWR_CR2_PLS_LEV6_Pos)            /*!< 0x0000000C */
10767 #define PWR_CR2_PLS_LEV6             PWR_CR2_PLS_LEV6_Msk                      /*!< PVD level 6 */
10768 #define PWR_CR2_PLS_LEV7_Pos         (1U)
10769 #define PWR_CR2_PLS_LEV7_Msk         (0x7U << PWR_CR2_PLS_LEV7_Pos)            /*!< 0x0000000E */
10770 #define PWR_CR2_PLS_LEV7             PWR_CR2_PLS_LEV7_Msk                      /*!< PVD level 7 */
10771 #define PWR_CR2_PVDE_Pos             (0U)
10772 #define PWR_CR2_PVDE_Msk             (0x1U << PWR_CR2_PVDE_Pos)                /*!< 0x00000001 */
10773 #define PWR_CR2_PVDE                 PWR_CR2_PVDE_Msk                          /*!< Power Voltage Detector Enable */
10774 
10775 /********************  Bit definition for PWR_CR3 register  ********************/
10776 #define PWR_CR3_EIWUL_Pos            (15U)
10777 #define PWR_CR3_EIWUL_Msk            (0x1U << PWR_CR3_EIWUL_Pos)               /*!< 0x00008000 */
10778 #define PWR_CR3_EIWUL                PWR_CR3_EIWUL_Msk                         /*!< Enable Internal Wake-up line */
10779 #define PWR_CR3_APC_Pos              (10U)
10780 #define PWR_CR3_APC_Msk              (0x1U << PWR_CR3_APC_Pos)                 /*!< 0x00000400 */
10781 #define PWR_CR3_APC                  PWR_CR3_APC_Msk                           /*!< Apply pull-up and pull-down configuration */
10782 #define PWR_CR3_RRS_Pos              (8U)
10783 #define PWR_CR3_RRS_Msk              (0x1U << PWR_CR3_RRS_Pos)                 /*!< 0x00000100 */
10784 #define PWR_CR3_RRS                  PWR_CR3_RRS_Msk                           /*!< SRAM2 Retention in Stand-by mode */
10785 #define PWR_CR3_EWUP5_Pos            (4U)
10786 #define PWR_CR3_EWUP5_Msk            (0x1U << PWR_CR3_EWUP5_Pos)               /*!< 0x00000010 */
10787 #define PWR_CR3_EWUP5                PWR_CR3_EWUP5_Msk                         /*!< Enable Wake-Up Pin 5 */
10788 #define PWR_CR3_EWUP4_Pos            (3U)
10789 #define PWR_CR3_EWUP4_Msk            (0x1U << PWR_CR3_EWUP4_Pos)               /*!< 0x00000008 */
10790 #define PWR_CR3_EWUP4                PWR_CR3_EWUP4_Msk                         /*!< Enable Wake-Up Pin 4 */
10791 #define PWR_CR3_EWUP3_Pos            (2U)
10792 #define PWR_CR3_EWUP3_Msk            (0x1U << PWR_CR3_EWUP3_Pos)               /*!< 0x00000004 */
10793 #define PWR_CR3_EWUP3                PWR_CR3_EWUP3_Msk                         /*!< Enable Wake-Up Pin 3 */
10794 #define PWR_CR3_EWUP2_Pos            (1U)
10795 #define PWR_CR3_EWUP2_Msk            (0x1U << PWR_CR3_EWUP2_Pos)               /*!< 0x00000002 */
10796 #define PWR_CR3_EWUP2                PWR_CR3_EWUP2_Msk                         /*!< Enable Wake-Up Pin 2 */
10797 #define PWR_CR3_EWUP1_Pos            (0U)
10798 #define PWR_CR3_EWUP1_Msk            (0x1U << PWR_CR3_EWUP1_Pos)               /*!< 0x00000001 */
10799 #define PWR_CR3_EWUP1                PWR_CR3_EWUP1_Msk                         /*!< Enable Wake-Up Pin 1 */
10800 #define PWR_CR3_EWUP_Pos             (0U)
10801 #define PWR_CR3_EWUP_Msk             (0x1FU << PWR_CR3_EWUP_Pos)               /*!< 0x0000001F */
10802 #define PWR_CR3_EWUP                 PWR_CR3_EWUP_Msk                          /*!< Enable Wake-Up Pins  */
10803 
10804 /* Legacy defines */
10805 #define PWR_CR3_EIWF_Pos             PWR_CR3_EIWUL_Pos
10806 #define PWR_CR3_EIWF_Msk             PWR_CR3_EIWUL_Msk
10807 #define PWR_CR3_EIWF                 PWR_CR3_EIWUL
10808 
10809 
10810 /********************  Bit definition for PWR_CR4 register  ********************/
10811 #define PWR_CR4_VBRS_Pos             (9U)
10812 #define PWR_CR4_VBRS_Msk             (0x1U << PWR_CR4_VBRS_Pos)                /*!< 0x00000200 */
10813 #define PWR_CR4_VBRS                 PWR_CR4_VBRS_Msk                          /*!< VBAT Battery charging Resistor Selection */
10814 #define PWR_CR4_VBE_Pos              (8U)
10815 #define PWR_CR4_VBE_Msk              (0x1U << PWR_CR4_VBE_Pos)                 /*!< 0x00000100 */
10816 #define PWR_CR4_VBE                  PWR_CR4_VBE_Msk                           /*!< VBAT Battery charging Enable  */
10817 #define PWR_CR4_WP5_Pos              (4U)
10818 #define PWR_CR4_WP5_Msk              (0x1U << PWR_CR4_WP5_Pos)                 /*!< 0x00000010 */
10819 #define PWR_CR4_WP5                  PWR_CR4_WP5_Msk                           /*!< Wake-Up Pin 5 polarity */
10820 #define PWR_CR4_WP4_Pos              (3U)
10821 #define PWR_CR4_WP4_Msk              (0x1U << PWR_CR4_WP4_Pos)                 /*!< 0x00000008 */
10822 #define PWR_CR4_WP4                  PWR_CR4_WP4_Msk                           /*!< Wake-Up Pin 4 polarity */
10823 #define PWR_CR4_WP3_Pos              (2U)
10824 #define PWR_CR4_WP3_Msk              (0x1U << PWR_CR4_WP3_Pos)                 /*!< 0x00000004 */
10825 #define PWR_CR4_WP3                  PWR_CR4_WP3_Msk                           /*!< Wake-Up Pin 3 polarity */
10826 #define PWR_CR4_WP2_Pos              (1U)
10827 #define PWR_CR4_WP2_Msk              (0x1U << PWR_CR4_WP2_Pos)                 /*!< 0x00000002 */
10828 #define PWR_CR4_WP2                  PWR_CR4_WP2_Msk                           /*!< Wake-Up Pin 2 polarity */
10829 #define PWR_CR4_WP1_Pos              (0U)
10830 #define PWR_CR4_WP1_Msk              (0x1U << PWR_CR4_WP1_Pos)                 /*!< 0x00000001 */
10831 #define PWR_CR4_WP1                  PWR_CR4_WP1_Msk                           /*!< Wake-Up Pin 1 polarity */
10832 
10833 /********************  Bit definition for PWR_SR1 register  ********************/
10834 #define PWR_SR1_WUFI_Pos             (15U)
10835 #define PWR_SR1_WUFI_Msk             (0x1U << PWR_SR1_WUFI_Pos)                /*!< 0x00008000 */
10836 #define PWR_SR1_WUFI                 PWR_SR1_WUFI_Msk                          /*!< Wake-Up Flag Internal */
10837 #define PWR_SR1_SBF_Pos              (8U)
10838 #define PWR_SR1_SBF_Msk              (0x1U << PWR_SR1_SBF_Pos)                 /*!< 0x00000100 */
10839 #define PWR_SR1_SBF                  PWR_SR1_SBF_Msk                           /*!< Stand-By Flag */
10840 #define PWR_SR1_WUF_Pos              (0U)
10841 #define PWR_SR1_WUF_Msk              (0x1FU << PWR_SR1_WUF_Pos)                /*!< 0x0000001F */
10842 #define PWR_SR1_WUF                  PWR_SR1_WUF_Msk                           /*!< Wake-up Flags */
10843 #define PWR_SR1_WUF5_Pos             (4U)
10844 #define PWR_SR1_WUF5_Msk             (0x1U << PWR_SR1_WUF5_Pos)                /*!< 0x00000010 */
10845 #define PWR_SR1_WUF5                 PWR_SR1_WUF5_Msk                          /*!< Wake-up Flag 5 */
10846 #define PWR_SR1_WUF4_Pos             (3U)
10847 #define PWR_SR1_WUF4_Msk             (0x1U << PWR_SR1_WUF4_Pos)                /*!< 0x00000008 */
10848 #define PWR_SR1_WUF4                 PWR_SR1_WUF4_Msk                          /*!< Wake-up Flag 4 */
10849 #define PWR_SR1_WUF3_Pos             (2U)
10850 #define PWR_SR1_WUF3_Msk             (0x1U << PWR_SR1_WUF3_Pos)                /*!< 0x00000004 */
10851 #define PWR_SR1_WUF3                 PWR_SR1_WUF3_Msk                          /*!< Wake-up Flag 3 */
10852 #define PWR_SR1_WUF2_Pos             (1U)
10853 #define PWR_SR1_WUF2_Msk             (0x1U << PWR_SR1_WUF2_Pos)                /*!< 0x00000002 */
10854 #define PWR_SR1_WUF2                 PWR_SR1_WUF2_Msk                          /*!< Wake-up Flag 2 */
10855 #define PWR_SR1_WUF1_Pos             (0U)
10856 #define PWR_SR1_WUF1_Msk             (0x1U << PWR_SR1_WUF1_Pos)                /*!< 0x00000001 */
10857 #define PWR_SR1_WUF1                 PWR_SR1_WUF1_Msk                          /*!< Wake-up Flag 1 */
10858 
10859 /********************  Bit definition for PWR_SR2 register  ********************/
10860 #define PWR_SR2_PVMO4_Pos            (15U)
10861 #define PWR_SR2_PVMO4_Msk            (0x1U << PWR_SR2_PVMO4_Pos)               /*!< 0x00008000 */
10862 #define PWR_SR2_PVMO4                PWR_SR2_PVMO4_Msk                         /*!< Peripheral Voltage Monitoring Output 4 */
10863 #define PWR_SR2_PVMO3_Pos            (14U)
10864 #define PWR_SR2_PVMO3_Msk            (0x1U << PWR_SR2_PVMO3_Pos)               /*!< 0x00004000 */
10865 #define PWR_SR2_PVMO3                PWR_SR2_PVMO3_Msk                         /*!< Peripheral Voltage Monitoring Output 3 */
10866 #define PWR_SR2_PVMO2_Pos            (13U)
10867 #define PWR_SR2_PVMO2_Msk            (0x1U << PWR_SR2_PVMO2_Pos)               /*!< 0x00002000 */
10868 #define PWR_SR2_PVMO2                PWR_SR2_PVMO2_Msk                         /*!< Peripheral Voltage Monitoring Output 2 */
10869 #define PWR_SR2_PVMO1_Pos            (12U)
10870 #define PWR_SR2_PVMO1_Msk            (0x1U << PWR_SR2_PVMO1_Pos)               /*!< 0x00001000 */
10871 #define PWR_SR2_PVMO1                PWR_SR2_PVMO1_Msk                         /*!< Peripheral Voltage Monitoring Output 1 */
10872 #define PWR_SR2_PVDO_Pos             (11U)
10873 #define PWR_SR2_PVDO_Msk             (0x1U << PWR_SR2_PVDO_Pos)                /*!< 0x00000800 */
10874 #define PWR_SR2_PVDO                 PWR_SR2_PVDO_Msk                          /*!< Power Voltage Detector Output */
10875 #define PWR_SR2_VOSF_Pos             (10U)
10876 #define PWR_SR2_VOSF_Msk             (0x1U << PWR_SR2_VOSF_Pos)                /*!< 0x00000400 */
10877 #define PWR_SR2_VOSF                 PWR_SR2_VOSF_Msk                          /*!< Voltage Scaling Flag */
10878 #define PWR_SR2_REGLPF_Pos           (9U)
10879 #define PWR_SR2_REGLPF_Msk           (0x1U << PWR_SR2_REGLPF_Pos)              /*!< 0x00000200 */
10880 #define PWR_SR2_REGLPF               PWR_SR2_REGLPF_Msk                        /*!< Low-power Regulator Flag */
10881 #define PWR_SR2_REGLPS_Pos           (8U)
10882 #define PWR_SR2_REGLPS_Msk           (0x1U << PWR_SR2_REGLPS_Pos)              /*!< 0x00000100 */
10883 #define PWR_SR2_REGLPS               PWR_SR2_REGLPS_Msk                        /*!< Low-power Regulator Started */
10884 
10885 /********************  Bit definition for PWR_SCR register  ********************/
10886 #define PWR_SCR_CSBF_Pos             (8U)
10887 #define PWR_SCR_CSBF_Msk             (0x1U << PWR_SCR_CSBF_Pos)                /*!< 0x00000100 */
10888 #define PWR_SCR_CSBF                 PWR_SCR_CSBF_Msk                          /*!< Clear Stand-By Flag */
10889 #define PWR_SCR_CWUF_Pos             (0U)
10890 #define PWR_SCR_CWUF_Msk             (0x1FU << PWR_SCR_CWUF_Pos)               /*!< 0x0000001F */
10891 #define PWR_SCR_CWUF                 PWR_SCR_CWUF_Msk                          /*!< Clear Wake-up Flags  */
10892 #define PWR_SCR_CWUF5_Pos            (4U)
10893 #define PWR_SCR_CWUF5_Msk            (0x1U << PWR_SCR_CWUF5_Pos)               /*!< 0x00000010 */
10894 #define PWR_SCR_CWUF5                PWR_SCR_CWUF5_Msk                         /*!< Clear Wake-up Flag 5 */
10895 #define PWR_SCR_CWUF4_Pos            (3U)
10896 #define PWR_SCR_CWUF4_Msk            (0x1U << PWR_SCR_CWUF4_Pos)               /*!< 0x00000008 */
10897 #define PWR_SCR_CWUF4                PWR_SCR_CWUF4_Msk                         /*!< Clear Wake-up Flag 4 */
10898 #define PWR_SCR_CWUF3_Pos            (2U)
10899 #define PWR_SCR_CWUF3_Msk            (0x1U << PWR_SCR_CWUF3_Pos)               /*!< 0x00000004 */
10900 #define PWR_SCR_CWUF3                PWR_SCR_CWUF3_Msk                         /*!< Clear Wake-up Flag 3 */
10901 #define PWR_SCR_CWUF2_Pos            (1U)
10902 #define PWR_SCR_CWUF2_Msk            (0x1U << PWR_SCR_CWUF2_Pos)               /*!< 0x00000002 */
10903 #define PWR_SCR_CWUF2                PWR_SCR_CWUF2_Msk                         /*!< Clear Wake-up Flag 2 */
10904 #define PWR_SCR_CWUF1_Pos            (0U)
10905 #define PWR_SCR_CWUF1_Msk            (0x1U << PWR_SCR_CWUF1_Pos)               /*!< 0x00000001 */
10906 #define PWR_SCR_CWUF1                PWR_SCR_CWUF1_Msk                         /*!< Clear Wake-up Flag 1 */
10907 
10908 /********************  Bit definition for PWR_PUCRA register  ********************/
10909 #define PWR_PUCRA_PA15_Pos           (15U)
10910 #define PWR_PUCRA_PA15_Msk           (0x1U << PWR_PUCRA_PA15_Pos)              /*!< 0x00008000 */
10911 #define PWR_PUCRA_PA15               PWR_PUCRA_PA15_Msk                        /*!< Port PA15 Pull-Up set */
10912 #define PWR_PUCRA_PA13_Pos           (13U)
10913 #define PWR_PUCRA_PA13_Msk           (0x1U << PWR_PUCRA_PA13_Pos)              /*!< 0x00002000 */
10914 #define PWR_PUCRA_PA13               PWR_PUCRA_PA13_Msk                        /*!< Port PA13 Pull-Up set */
10915 #define PWR_PUCRA_PA12_Pos           (12U)
10916 #define PWR_PUCRA_PA12_Msk           (0x1U << PWR_PUCRA_PA12_Pos)              /*!< 0x00001000 */
10917 #define PWR_PUCRA_PA12               PWR_PUCRA_PA12_Msk                        /*!< Port PA12 Pull-Up set */
10918 #define PWR_PUCRA_PA11_Pos           (11U)
10919 #define PWR_PUCRA_PA11_Msk           (0x1U << PWR_PUCRA_PA11_Pos)              /*!< 0x00000800 */
10920 #define PWR_PUCRA_PA11               PWR_PUCRA_PA11_Msk                        /*!< Port PA11 Pull-Up set */
10921 #define PWR_PUCRA_PA10_Pos           (10U)
10922 #define PWR_PUCRA_PA10_Msk           (0x1U << PWR_PUCRA_PA10_Pos)              /*!< 0x00000400 */
10923 #define PWR_PUCRA_PA10               PWR_PUCRA_PA10_Msk                        /*!< Port PA10 Pull-Up set */
10924 #define PWR_PUCRA_PA9_Pos            (9U)
10925 #define PWR_PUCRA_PA9_Msk            (0x1U << PWR_PUCRA_PA9_Pos)               /*!< 0x00000200 */
10926 #define PWR_PUCRA_PA9                PWR_PUCRA_PA9_Msk                         /*!< Port PA9 Pull-Up set  */
10927 #define PWR_PUCRA_PA8_Pos            (8U)
10928 #define PWR_PUCRA_PA8_Msk            (0x1U << PWR_PUCRA_PA8_Pos)               /*!< 0x00000100 */
10929 #define PWR_PUCRA_PA8                PWR_PUCRA_PA8_Msk                         /*!< Port PA8 Pull-Up set  */
10930 #define PWR_PUCRA_PA7_Pos            (7U)
10931 #define PWR_PUCRA_PA7_Msk            (0x1U << PWR_PUCRA_PA7_Pos)               /*!< 0x00000080 */
10932 #define PWR_PUCRA_PA7                PWR_PUCRA_PA7_Msk                         /*!< Port PA7 Pull-Up set  */
10933 #define PWR_PUCRA_PA6_Pos            (6U)
10934 #define PWR_PUCRA_PA6_Msk            (0x1U << PWR_PUCRA_PA6_Pos)               /*!< 0x00000040 */
10935 #define PWR_PUCRA_PA6                PWR_PUCRA_PA6_Msk                         /*!< Port PA6 Pull-Up set  */
10936 #define PWR_PUCRA_PA5_Pos            (5U)
10937 #define PWR_PUCRA_PA5_Msk            (0x1U << PWR_PUCRA_PA5_Pos)               /*!< 0x00000020 */
10938 #define PWR_PUCRA_PA5                PWR_PUCRA_PA5_Msk                         /*!< Port PA5 Pull-Up set  */
10939 #define PWR_PUCRA_PA4_Pos            (4U)
10940 #define PWR_PUCRA_PA4_Msk            (0x1U << PWR_PUCRA_PA4_Pos)               /*!< 0x00000010 */
10941 #define PWR_PUCRA_PA4                PWR_PUCRA_PA4_Msk                         /*!< Port PA4 Pull-Up set  */
10942 #define PWR_PUCRA_PA3_Pos            (3U)
10943 #define PWR_PUCRA_PA3_Msk            (0x1U << PWR_PUCRA_PA3_Pos)               /*!< 0x00000008 */
10944 #define PWR_PUCRA_PA3                PWR_PUCRA_PA3_Msk                         /*!< Port PA3 Pull-Up set  */
10945 #define PWR_PUCRA_PA2_Pos            (2U)
10946 #define PWR_PUCRA_PA2_Msk            (0x1U << PWR_PUCRA_PA2_Pos)               /*!< 0x00000004 */
10947 #define PWR_PUCRA_PA2                PWR_PUCRA_PA2_Msk                         /*!< Port PA2 Pull-Up set  */
10948 #define PWR_PUCRA_PA1_Pos            (1U)
10949 #define PWR_PUCRA_PA1_Msk            (0x1U << PWR_PUCRA_PA1_Pos)               /*!< 0x00000002 */
10950 #define PWR_PUCRA_PA1                PWR_PUCRA_PA1_Msk                         /*!< Port PA1 Pull-Up set  */
10951 #define PWR_PUCRA_PA0_Pos            (0U)
10952 #define PWR_PUCRA_PA0_Msk            (0x1U << PWR_PUCRA_PA0_Pos)               /*!< 0x00000001 */
10953 #define PWR_PUCRA_PA0                PWR_PUCRA_PA0_Msk                         /*!< Port PA0 Pull-Up set  */
10954 
10955 /********************  Bit definition for PWR_PDCRA register  ********************/
10956 #define PWR_PDCRA_PA14_Pos           (14U)
10957 #define PWR_PDCRA_PA14_Msk           (0x1U << PWR_PDCRA_PA14_Pos)              /*!< 0x00004000 */
10958 #define PWR_PDCRA_PA14               PWR_PDCRA_PA14_Msk                        /*!< Port PA14 Pull-Down set */
10959 #define PWR_PDCRA_PA12_Pos           (12U)
10960 #define PWR_PDCRA_PA12_Msk           (0x1U << PWR_PDCRA_PA12_Pos)              /*!< 0x00001000 */
10961 #define PWR_PDCRA_PA12               PWR_PDCRA_PA12_Msk                        /*!< Port PA12 Pull-Down set */
10962 #define PWR_PDCRA_PA11_Pos           (11U)
10963 #define PWR_PDCRA_PA11_Msk           (0x1U << PWR_PDCRA_PA11_Pos)              /*!< 0x00000800 */
10964 #define PWR_PDCRA_PA11               PWR_PDCRA_PA11_Msk                        /*!< Port PA11 Pull-Down set */
10965 #define PWR_PDCRA_PA10_Pos           (10U)
10966 #define PWR_PDCRA_PA10_Msk           (0x1U << PWR_PDCRA_PA10_Pos)              /*!< 0x00000400 */
10967 #define PWR_PDCRA_PA10               PWR_PDCRA_PA10_Msk                        /*!< Port PA10 Pull-Down set */
10968 #define PWR_PDCRA_PA9_Pos            (9U)
10969 #define PWR_PDCRA_PA9_Msk            (0x1U << PWR_PDCRA_PA9_Pos)               /*!< 0x00000200 */
10970 #define PWR_PDCRA_PA9                PWR_PDCRA_PA9_Msk                         /*!< Port PA9 Pull-Down set  */
10971 #define PWR_PDCRA_PA8_Pos            (8U)
10972 #define PWR_PDCRA_PA8_Msk            (0x1U << PWR_PDCRA_PA8_Pos)               /*!< 0x00000100 */
10973 #define PWR_PDCRA_PA8                PWR_PDCRA_PA8_Msk                         /*!< Port PA8 Pull-Down set  */
10974 #define PWR_PDCRA_PA7_Pos            (7U)
10975 #define PWR_PDCRA_PA7_Msk            (0x1U << PWR_PDCRA_PA7_Pos)               /*!< 0x00000080 */
10976 #define PWR_PDCRA_PA7                PWR_PDCRA_PA7_Msk                         /*!< Port PA7 Pull-Down set  */
10977 #define PWR_PDCRA_PA6_Pos            (6U)
10978 #define PWR_PDCRA_PA6_Msk            (0x1U << PWR_PDCRA_PA6_Pos)               /*!< 0x00000040 */
10979 #define PWR_PDCRA_PA6                PWR_PDCRA_PA6_Msk                         /*!< Port PA6 Pull-Down set  */
10980 #define PWR_PDCRA_PA5_Pos            (5U)
10981 #define PWR_PDCRA_PA5_Msk            (0x1U << PWR_PDCRA_PA5_Pos)               /*!< 0x00000020 */
10982 #define PWR_PDCRA_PA5                PWR_PDCRA_PA5_Msk                         /*!< Port PA5 Pull-Down set  */
10983 #define PWR_PDCRA_PA4_Pos            (4U)
10984 #define PWR_PDCRA_PA4_Msk            (0x1U << PWR_PDCRA_PA4_Pos)               /*!< 0x00000010 */
10985 #define PWR_PDCRA_PA4                PWR_PDCRA_PA4_Msk                         /*!< Port PA4 Pull-Down set  */
10986 #define PWR_PDCRA_PA3_Pos            (3U)
10987 #define PWR_PDCRA_PA3_Msk            (0x1U << PWR_PDCRA_PA3_Pos)               /*!< 0x00000008 */
10988 #define PWR_PDCRA_PA3                PWR_PDCRA_PA3_Msk                         /*!< Port PA3 Pull-Down set  */
10989 #define PWR_PDCRA_PA2_Pos            (2U)
10990 #define PWR_PDCRA_PA2_Msk            (0x1U << PWR_PDCRA_PA2_Pos)               /*!< 0x00000004 */
10991 #define PWR_PDCRA_PA2                PWR_PDCRA_PA2_Msk                         /*!< Port PA2 Pull-Down set  */
10992 #define PWR_PDCRA_PA1_Pos            (1U)
10993 #define PWR_PDCRA_PA1_Msk            (0x1U << PWR_PDCRA_PA1_Pos)               /*!< 0x00000002 */
10994 #define PWR_PDCRA_PA1                PWR_PDCRA_PA1_Msk                         /*!< Port PA1 Pull-Down set  */
10995 #define PWR_PDCRA_PA0_Pos            (0U)
10996 #define PWR_PDCRA_PA0_Msk            (0x1U << PWR_PDCRA_PA0_Pos)               /*!< 0x00000001 */
10997 #define PWR_PDCRA_PA0                PWR_PDCRA_PA0_Msk                         /*!< Port PA0 Pull-Down set  */
10998 
10999 /********************  Bit definition for PWR_PUCRB register  ********************/
11000 #define PWR_PUCRB_PB15_Pos           (15U)
11001 #define PWR_PUCRB_PB15_Msk           (0x1U << PWR_PUCRB_PB15_Pos)              /*!< 0x00008000 */
11002 #define PWR_PUCRB_PB15               PWR_PUCRB_PB15_Msk                        /*!< Port PB15 Pull-Up set */
11003 #define PWR_PUCRB_PB14_Pos           (14U)
11004 #define PWR_PUCRB_PB14_Msk           (0x1U << PWR_PUCRB_PB14_Pos)              /*!< 0x00004000 */
11005 #define PWR_PUCRB_PB14               PWR_PUCRB_PB14_Msk                        /*!< Port PB14 Pull-Up set */
11006 #define PWR_PUCRB_PB13_Pos           (13U)
11007 #define PWR_PUCRB_PB13_Msk           (0x1U << PWR_PUCRB_PB13_Pos)              /*!< 0x00002000 */
11008 #define PWR_PUCRB_PB13               PWR_PUCRB_PB13_Msk                        /*!< Port PB13 Pull-Up set */
11009 #define PWR_PUCRB_PB12_Pos           (12U)
11010 #define PWR_PUCRB_PB12_Msk           (0x1U << PWR_PUCRB_PB12_Pos)              /*!< 0x00001000 */
11011 #define PWR_PUCRB_PB12               PWR_PUCRB_PB12_Msk                        /*!< Port PB12 Pull-Up set */
11012 #define PWR_PUCRB_PB11_Pos           (11U)
11013 #define PWR_PUCRB_PB11_Msk           (0x1U << PWR_PUCRB_PB11_Pos)              /*!< 0x00000800 */
11014 #define PWR_PUCRB_PB11               PWR_PUCRB_PB11_Msk                        /*!< Port PB11 Pull-Up set */
11015 #define PWR_PUCRB_PB10_Pos           (10U)
11016 #define PWR_PUCRB_PB10_Msk           (0x1U << PWR_PUCRB_PB10_Pos)              /*!< 0x00000400 */
11017 #define PWR_PUCRB_PB10               PWR_PUCRB_PB10_Msk                        /*!< Port PB10 Pull-Up set */
11018 #define PWR_PUCRB_PB9_Pos            (9U)
11019 #define PWR_PUCRB_PB9_Msk            (0x1U << PWR_PUCRB_PB9_Pos)               /*!< 0x00000200 */
11020 #define PWR_PUCRB_PB9                PWR_PUCRB_PB9_Msk                         /*!< Port PB9 Pull-Up set  */
11021 #define PWR_PUCRB_PB8_Pos            (8U)
11022 #define PWR_PUCRB_PB8_Msk            (0x1U << PWR_PUCRB_PB8_Pos)               /*!< 0x00000100 */
11023 #define PWR_PUCRB_PB8                PWR_PUCRB_PB8_Msk                         /*!< Port PB8 Pull-Up set  */
11024 #define PWR_PUCRB_PB7_Pos            (7U)
11025 #define PWR_PUCRB_PB7_Msk            (0x1U << PWR_PUCRB_PB7_Pos)               /*!< 0x00000080 */
11026 #define PWR_PUCRB_PB7                PWR_PUCRB_PB7_Msk                         /*!< Port PB7 Pull-Up set  */
11027 #define PWR_PUCRB_PB6_Pos            (6U)
11028 #define PWR_PUCRB_PB6_Msk            (0x1U << PWR_PUCRB_PB6_Pos)               /*!< 0x00000040 */
11029 #define PWR_PUCRB_PB6                PWR_PUCRB_PB6_Msk                         /*!< Port PB6 Pull-Up set  */
11030 #define PWR_PUCRB_PB5_Pos            (5U)
11031 #define PWR_PUCRB_PB5_Msk            (0x1U << PWR_PUCRB_PB5_Pos)               /*!< 0x00000020 */
11032 #define PWR_PUCRB_PB5                PWR_PUCRB_PB5_Msk                         /*!< Port PB5 Pull-Up set  */
11033 #define PWR_PUCRB_PB4_Pos            (4U)
11034 #define PWR_PUCRB_PB4_Msk            (0x1U << PWR_PUCRB_PB4_Pos)               /*!< 0x00000010 */
11035 #define PWR_PUCRB_PB4                PWR_PUCRB_PB4_Msk                         /*!< Port PB4 Pull-Up set  */
11036 #define PWR_PUCRB_PB3_Pos            (3U)
11037 #define PWR_PUCRB_PB3_Msk            (0x1U << PWR_PUCRB_PB3_Pos)               /*!< 0x00000008 */
11038 #define PWR_PUCRB_PB3                PWR_PUCRB_PB3_Msk                         /*!< Port PB3 Pull-Up set  */
11039 #define PWR_PUCRB_PB2_Pos            (2U)
11040 #define PWR_PUCRB_PB2_Msk            (0x1U << PWR_PUCRB_PB2_Pos)               /*!< 0x00000004 */
11041 #define PWR_PUCRB_PB2                PWR_PUCRB_PB2_Msk                         /*!< Port PB2 Pull-Up set  */
11042 #define PWR_PUCRB_PB1_Pos            (1U)
11043 #define PWR_PUCRB_PB1_Msk            (0x1U << PWR_PUCRB_PB1_Pos)               /*!< 0x00000002 */
11044 #define PWR_PUCRB_PB1                PWR_PUCRB_PB1_Msk                         /*!< Port PB1 Pull-Up set  */
11045 #define PWR_PUCRB_PB0_Pos            (0U)
11046 #define PWR_PUCRB_PB0_Msk            (0x1U << PWR_PUCRB_PB0_Pos)               /*!< 0x00000001 */
11047 #define PWR_PUCRB_PB0                PWR_PUCRB_PB0_Msk                         /*!< Port PB0 Pull-Up set  */
11048 
11049 /********************  Bit definition for PWR_PDCRB register  ********************/
11050 #define PWR_PDCRB_PB15_Pos           (15U)
11051 #define PWR_PDCRB_PB15_Msk           (0x1U << PWR_PDCRB_PB15_Pos)              /*!< 0x00008000 */
11052 #define PWR_PDCRB_PB15               PWR_PDCRB_PB15_Msk                        /*!< Port PB15 Pull-Down set */
11053 #define PWR_PDCRB_PB14_Pos           (14U)
11054 #define PWR_PDCRB_PB14_Msk           (0x1U << PWR_PDCRB_PB14_Pos)              /*!< 0x00004000 */
11055 #define PWR_PDCRB_PB14               PWR_PDCRB_PB14_Msk                        /*!< Port PB14 Pull-Down set */
11056 #define PWR_PDCRB_PB13_Pos           (13U)
11057 #define PWR_PDCRB_PB13_Msk           (0x1U << PWR_PDCRB_PB13_Pos)              /*!< 0x00002000 */
11058 #define PWR_PDCRB_PB13               PWR_PDCRB_PB13_Msk                        /*!< Port PB13 Pull-Down set */
11059 #define PWR_PDCRB_PB12_Pos           (12U)
11060 #define PWR_PDCRB_PB12_Msk           (0x1U << PWR_PDCRB_PB12_Pos)              /*!< 0x00001000 */
11061 #define PWR_PDCRB_PB12               PWR_PDCRB_PB12_Msk                        /*!< Port PB12 Pull-Down set */
11062 #define PWR_PDCRB_PB11_Pos           (11U)
11063 #define PWR_PDCRB_PB11_Msk           (0x1U << PWR_PDCRB_PB11_Pos)              /*!< 0x00000800 */
11064 #define PWR_PDCRB_PB11               PWR_PDCRB_PB11_Msk                        /*!< Port PB11 Pull-Down set */
11065 #define PWR_PDCRB_PB10_Pos           (10U)
11066 #define PWR_PDCRB_PB10_Msk           (0x1U << PWR_PDCRB_PB10_Pos)              /*!< 0x00000400 */
11067 #define PWR_PDCRB_PB10               PWR_PDCRB_PB10_Msk                        /*!< Port PB10 Pull-Down set */
11068 #define PWR_PDCRB_PB9_Pos            (9U)
11069 #define PWR_PDCRB_PB9_Msk            (0x1U << PWR_PDCRB_PB9_Pos)               /*!< 0x00000200 */
11070 #define PWR_PDCRB_PB9                PWR_PDCRB_PB9_Msk                         /*!< Port PB9 Pull-Down set  */
11071 #define PWR_PDCRB_PB8_Pos            (8U)
11072 #define PWR_PDCRB_PB8_Msk            (0x1U << PWR_PDCRB_PB8_Pos)               /*!< 0x00000100 */
11073 #define PWR_PDCRB_PB8                PWR_PDCRB_PB8_Msk                         /*!< Port PB8 Pull-Down set  */
11074 #define PWR_PDCRB_PB7_Pos            (7U)
11075 #define PWR_PDCRB_PB7_Msk            (0x1U << PWR_PDCRB_PB7_Pos)               /*!< 0x00000080 */
11076 #define PWR_PDCRB_PB7                PWR_PDCRB_PB7_Msk                         /*!< Port PB7 Pull-Down set  */
11077 #define PWR_PDCRB_PB6_Pos            (6U)
11078 #define PWR_PDCRB_PB6_Msk            (0x1U << PWR_PDCRB_PB6_Pos)               /*!< 0x00000040 */
11079 #define PWR_PDCRB_PB6                PWR_PDCRB_PB6_Msk                         /*!< Port PB6 Pull-Down set  */
11080 #define PWR_PDCRB_PB5_Pos            (5U)
11081 #define PWR_PDCRB_PB5_Msk            (0x1U << PWR_PDCRB_PB5_Pos)               /*!< 0x00000020 */
11082 #define PWR_PDCRB_PB5                PWR_PDCRB_PB5_Msk                         /*!< Port PB5 Pull-Down set  */
11083 #define PWR_PDCRB_PB3_Pos            (3U)
11084 #define PWR_PDCRB_PB3_Msk            (0x1U << PWR_PDCRB_PB3_Pos)               /*!< 0x00000008 */
11085 #define PWR_PDCRB_PB3                PWR_PDCRB_PB3_Msk                         /*!< Port PB3 Pull-Down set  */
11086 #define PWR_PDCRB_PB2_Pos            (2U)
11087 #define PWR_PDCRB_PB2_Msk            (0x1U << PWR_PDCRB_PB2_Pos)               /*!< 0x00000004 */
11088 #define PWR_PDCRB_PB2                PWR_PDCRB_PB2_Msk                         /*!< Port PB2 Pull-Down set  */
11089 #define PWR_PDCRB_PB1_Pos            (1U)
11090 #define PWR_PDCRB_PB1_Msk            (0x1U << PWR_PDCRB_PB1_Pos)               /*!< 0x00000002 */
11091 #define PWR_PDCRB_PB1                PWR_PDCRB_PB1_Msk                         /*!< Port PB1 Pull-Down set  */
11092 #define PWR_PDCRB_PB0_Pos            (0U)
11093 #define PWR_PDCRB_PB0_Msk            (0x1U << PWR_PDCRB_PB0_Pos)               /*!< 0x00000001 */
11094 #define PWR_PDCRB_PB0                PWR_PDCRB_PB0_Msk                         /*!< Port PB0 Pull-Down set  */
11095 
11096 /********************  Bit definition for PWR_PUCRC register  ********************/
11097 #define PWR_PUCRC_PC15_Pos           (15U)
11098 #define PWR_PUCRC_PC15_Msk           (0x1U << PWR_PUCRC_PC15_Pos)              /*!< 0x00008000 */
11099 #define PWR_PUCRC_PC15               PWR_PUCRC_PC15_Msk                        /*!< Port PC15 Pull-Up set */
11100 #define PWR_PUCRC_PC14_Pos           (14U)
11101 #define PWR_PUCRC_PC14_Msk           (0x1U << PWR_PUCRC_PC14_Pos)              /*!< 0x00004000 */
11102 #define PWR_PUCRC_PC14               PWR_PUCRC_PC14_Msk                        /*!< Port PC14 Pull-Up set */
11103 #define PWR_PUCRC_PC13_Pos           (13U)
11104 #define PWR_PUCRC_PC13_Msk           (0x1U << PWR_PUCRC_PC13_Pos)              /*!< 0x00002000 */
11105 #define PWR_PUCRC_PC13               PWR_PUCRC_PC13_Msk                        /*!< Port PC13 Pull-Up set */
11106 #define PWR_PUCRC_PC12_Pos           (12U)
11107 #define PWR_PUCRC_PC12_Msk           (0x1U << PWR_PUCRC_PC12_Pos)              /*!< 0x00001000 */
11108 #define PWR_PUCRC_PC12               PWR_PUCRC_PC12_Msk                        /*!< Port PC12 Pull-Up set */
11109 #define PWR_PUCRC_PC11_Pos           (11U)
11110 #define PWR_PUCRC_PC11_Msk           (0x1U << PWR_PUCRC_PC11_Pos)              /*!< 0x00000800 */
11111 #define PWR_PUCRC_PC11               PWR_PUCRC_PC11_Msk                        /*!< Port PC11 Pull-Up set */
11112 #define PWR_PUCRC_PC10_Pos           (10U)
11113 #define PWR_PUCRC_PC10_Msk           (0x1U << PWR_PUCRC_PC10_Pos)              /*!< 0x00000400 */
11114 #define PWR_PUCRC_PC10               PWR_PUCRC_PC10_Msk                        /*!< Port PC10 Pull-Up set */
11115 #define PWR_PUCRC_PC9_Pos            (9U)
11116 #define PWR_PUCRC_PC9_Msk            (0x1U << PWR_PUCRC_PC9_Pos)               /*!< 0x00000200 */
11117 #define PWR_PUCRC_PC9                PWR_PUCRC_PC9_Msk                         /*!< Port PC9 Pull-Up set  */
11118 #define PWR_PUCRC_PC8_Pos            (8U)
11119 #define PWR_PUCRC_PC8_Msk            (0x1U << PWR_PUCRC_PC8_Pos)               /*!< 0x00000100 */
11120 #define PWR_PUCRC_PC8                PWR_PUCRC_PC8_Msk                         /*!< Port PC8 Pull-Up set  */
11121 #define PWR_PUCRC_PC7_Pos            (7U)
11122 #define PWR_PUCRC_PC7_Msk            (0x1U << PWR_PUCRC_PC7_Pos)               /*!< 0x00000080 */
11123 #define PWR_PUCRC_PC7                PWR_PUCRC_PC7_Msk                         /*!< Port PC7 Pull-Up set  */
11124 #define PWR_PUCRC_PC6_Pos            (6U)
11125 #define PWR_PUCRC_PC6_Msk            (0x1U << PWR_PUCRC_PC6_Pos)               /*!< 0x00000040 */
11126 #define PWR_PUCRC_PC6                PWR_PUCRC_PC6_Msk                         /*!< Port PC6 Pull-Up set  */
11127 #define PWR_PUCRC_PC5_Pos            (5U)
11128 #define PWR_PUCRC_PC5_Msk            (0x1U << PWR_PUCRC_PC5_Pos)               /*!< 0x00000020 */
11129 #define PWR_PUCRC_PC5                PWR_PUCRC_PC5_Msk                         /*!< Port PC5 Pull-Up set  */
11130 #define PWR_PUCRC_PC4_Pos            (4U)
11131 #define PWR_PUCRC_PC4_Msk            (0x1U << PWR_PUCRC_PC4_Pos)               /*!< 0x00000010 */
11132 #define PWR_PUCRC_PC4                PWR_PUCRC_PC4_Msk                         /*!< Port PC4 Pull-Up set  */
11133 #define PWR_PUCRC_PC3_Pos            (3U)
11134 #define PWR_PUCRC_PC3_Msk            (0x1U << PWR_PUCRC_PC3_Pos)               /*!< 0x00000008 */
11135 #define PWR_PUCRC_PC3                PWR_PUCRC_PC3_Msk                         /*!< Port PC3 Pull-Up set  */
11136 #define PWR_PUCRC_PC2_Pos            (2U)
11137 #define PWR_PUCRC_PC2_Msk            (0x1U << PWR_PUCRC_PC2_Pos)               /*!< 0x00000004 */
11138 #define PWR_PUCRC_PC2                PWR_PUCRC_PC2_Msk                         /*!< Port PC2 Pull-Up set  */
11139 #define PWR_PUCRC_PC1_Pos            (1U)
11140 #define PWR_PUCRC_PC1_Msk            (0x1U << PWR_PUCRC_PC1_Pos)               /*!< 0x00000002 */
11141 #define PWR_PUCRC_PC1                PWR_PUCRC_PC1_Msk                         /*!< Port PC1 Pull-Up set  */
11142 #define PWR_PUCRC_PC0_Pos            (0U)
11143 #define PWR_PUCRC_PC0_Msk            (0x1U << PWR_PUCRC_PC0_Pos)               /*!< 0x00000001 */
11144 #define PWR_PUCRC_PC0                PWR_PUCRC_PC0_Msk                         /*!< Port PC0 Pull-Up set  */
11145 
11146 /********************  Bit definition for PWR_PDCRC register  ********************/
11147 #define PWR_PDCRC_PC15_Pos           (15U)
11148 #define PWR_PDCRC_PC15_Msk           (0x1U << PWR_PDCRC_PC15_Pos)              /*!< 0x00008000 */
11149 #define PWR_PDCRC_PC15               PWR_PDCRC_PC15_Msk                        /*!< Port PC15 Pull-Down set */
11150 #define PWR_PDCRC_PC14_Pos           (14U)
11151 #define PWR_PDCRC_PC14_Msk           (0x1U << PWR_PDCRC_PC14_Pos)              /*!< 0x00004000 */
11152 #define PWR_PDCRC_PC14               PWR_PDCRC_PC14_Msk                        /*!< Port PC14 Pull-Down set */
11153 #define PWR_PDCRC_PC13_Pos           (13U)
11154 #define PWR_PDCRC_PC13_Msk           (0x1U << PWR_PDCRC_PC13_Pos)              /*!< 0x00002000 */
11155 #define PWR_PDCRC_PC13               PWR_PDCRC_PC13_Msk                        /*!< Port PC13 Pull-Down set */
11156 #define PWR_PDCRC_PC12_Pos           (12U)
11157 #define PWR_PDCRC_PC12_Msk           (0x1U << PWR_PDCRC_PC12_Pos)              /*!< 0x00001000 */
11158 #define PWR_PDCRC_PC12               PWR_PDCRC_PC12_Msk                        /*!< Port PC12 Pull-Down set */
11159 #define PWR_PDCRC_PC11_Pos           (11U)
11160 #define PWR_PDCRC_PC11_Msk           (0x1U << PWR_PDCRC_PC11_Pos)              /*!< 0x00000800 */
11161 #define PWR_PDCRC_PC11               PWR_PDCRC_PC11_Msk                        /*!< Port PC11 Pull-Down set */
11162 #define PWR_PDCRC_PC10_Pos           (10U)
11163 #define PWR_PDCRC_PC10_Msk           (0x1U << PWR_PDCRC_PC10_Pos)              /*!< 0x00000400 */
11164 #define PWR_PDCRC_PC10               PWR_PDCRC_PC10_Msk                        /*!< Port PC10 Pull-Down set */
11165 #define PWR_PDCRC_PC9_Pos            (9U)
11166 #define PWR_PDCRC_PC9_Msk            (0x1U << PWR_PDCRC_PC9_Pos)               /*!< 0x00000200 */
11167 #define PWR_PDCRC_PC9                PWR_PDCRC_PC9_Msk                         /*!< Port PC9 Pull-Down set  */
11168 #define PWR_PDCRC_PC8_Pos            (8U)
11169 #define PWR_PDCRC_PC8_Msk            (0x1U << PWR_PDCRC_PC8_Pos)               /*!< 0x00000100 */
11170 #define PWR_PDCRC_PC8                PWR_PDCRC_PC8_Msk                         /*!< Port PC8 Pull-Down set  */
11171 #define PWR_PDCRC_PC7_Pos            (7U)
11172 #define PWR_PDCRC_PC7_Msk            (0x1U << PWR_PDCRC_PC7_Pos)               /*!< 0x00000080 */
11173 #define PWR_PDCRC_PC7                PWR_PDCRC_PC7_Msk                         /*!< Port PC7 Pull-Down set  */
11174 #define PWR_PDCRC_PC6_Pos            (6U)
11175 #define PWR_PDCRC_PC6_Msk            (0x1U << PWR_PDCRC_PC6_Pos)               /*!< 0x00000040 */
11176 #define PWR_PDCRC_PC6                PWR_PDCRC_PC6_Msk                         /*!< Port PC6 Pull-Down set  */
11177 #define PWR_PDCRC_PC5_Pos            (5U)
11178 #define PWR_PDCRC_PC5_Msk            (0x1U << PWR_PDCRC_PC5_Pos)               /*!< 0x00000020 */
11179 #define PWR_PDCRC_PC5                PWR_PDCRC_PC5_Msk                         /*!< Port PC5 Pull-Down set  */
11180 #define PWR_PDCRC_PC4_Pos            (4U)
11181 #define PWR_PDCRC_PC4_Msk            (0x1U << PWR_PDCRC_PC4_Pos)               /*!< 0x00000010 */
11182 #define PWR_PDCRC_PC4                PWR_PDCRC_PC4_Msk                         /*!< Port PC4 Pull-Down set  */
11183 #define PWR_PDCRC_PC3_Pos            (3U)
11184 #define PWR_PDCRC_PC3_Msk            (0x1U << PWR_PDCRC_PC3_Pos)               /*!< 0x00000008 */
11185 #define PWR_PDCRC_PC3                PWR_PDCRC_PC3_Msk                         /*!< Port PC3 Pull-Down set  */
11186 #define PWR_PDCRC_PC2_Pos            (2U)
11187 #define PWR_PDCRC_PC2_Msk            (0x1U << PWR_PDCRC_PC2_Pos)               /*!< 0x00000004 */
11188 #define PWR_PDCRC_PC2                PWR_PDCRC_PC2_Msk                         /*!< Port PC2 Pull-Down set  */
11189 #define PWR_PDCRC_PC1_Pos            (1U)
11190 #define PWR_PDCRC_PC1_Msk            (0x1U << PWR_PDCRC_PC1_Pos)               /*!< 0x00000002 */
11191 #define PWR_PDCRC_PC1                PWR_PDCRC_PC1_Msk                         /*!< Port PC1 Pull-Down set  */
11192 #define PWR_PDCRC_PC0_Pos            (0U)
11193 #define PWR_PDCRC_PC0_Msk            (0x1U << PWR_PDCRC_PC0_Pos)               /*!< 0x00000001 */
11194 #define PWR_PDCRC_PC0                PWR_PDCRC_PC0_Msk                         /*!< Port PC0 Pull-Down set  */
11195 
11196 /********************  Bit definition for PWR_PUCRD register  ********************/
11197 #define PWR_PUCRD_PD15_Pos           (15U)
11198 #define PWR_PUCRD_PD15_Msk           (0x1U << PWR_PUCRD_PD15_Pos)              /*!< 0x00008000 */
11199 #define PWR_PUCRD_PD15               PWR_PUCRD_PD15_Msk                        /*!< Port PD15 Pull-Up set */
11200 #define PWR_PUCRD_PD14_Pos           (14U)
11201 #define PWR_PUCRD_PD14_Msk           (0x1U << PWR_PUCRD_PD14_Pos)              /*!< 0x00004000 */
11202 #define PWR_PUCRD_PD14               PWR_PUCRD_PD14_Msk                        /*!< Port PD14 Pull-Up set */
11203 #define PWR_PUCRD_PD13_Pos           (13U)
11204 #define PWR_PUCRD_PD13_Msk           (0x1U << PWR_PUCRD_PD13_Pos)              /*!< 0x00002000 */
11205 #define PWR_PUCRD_PD13               PWR_PUCRD_PD13_Msk                        /*!< Port PD13 Pull-Up set */
11206 #define PWR_PUCRD_PD12_Pos           (12U)
11207 #define PWR_PUCRD_PD12_Msk           (0x1U << PWR_PUCRD_PD12_Pos)              /*!< 0x00001000 */
11208 #define PWR_PUCRD_PD12               PWR_PUCRD_PD12_Msk                        /*!< Port PD12 Pull-Up set */
11209 #define PWR_PUCRD_PD11_Pos           (11U)
11210 #define PWR_PUCRD_PD11_Msk           (0x1U << PWR_PUCRD_PD11_Pos)              /*!< 0x00000800 */
11211 #define PWR_PUCRD_PD11               PWR_PUCRD_PD11_Msk                        /*!< Port PD11 Pull-Up set */
11212 #define PWR_PUCRD_PD10_Pos           (10U)
11213 #define PWR_PUCRD_PD10_Msk           (0x1U << PWR_PUCRD_PD10_Pos)              /*!< 0x00000400 */
11214 #define PWR_PUCRD_PD10               PWR_PUCRD_PD10_Msk                        /*!< Port PD10 Pull-Up set */
11215 #define PWR_PUCRD_PD9_Pos            (9U)
11216 #define PWR_PUCRD_PD9_Msk            (0x1U << PWR_PUCRD_PD9_Pos)               /*!< 0x00000200 */
11217 #define PWR_PUCRD_PD9                PWR_PUCRD_PD9_Msk                         /*!< Port PD9 Pull-Up set  */
11218 #define PWR_PUCRD_PD8_Pos            (8U)
11219 #define PWR_PUCRD_PD8_Msk            (0x1U << PWR_PUCRD_PD8_Pos)               /*!< 0x00000100 */
11220 #define PWR_PUCRD_PD8                PWR_PUCRD_PD8_Msk                         /*!< Port PD8 Pull-Up set  */
11221 #define PWR_PUCRD_PD7_Pos            (7U)
11222 #define PWR_PUCRD_PD7_Msk            (0x1U << PWR_PUCRD_PD7_Pos)               /*!< 0x00000080 */
11223 #define PWR_PUCRD_PD7                PWR_PUCRD_PD7_Msk                         /*!< Port PD7 Pull-Up set  */
11224 #define PWR_PUCRD_PD6_Pos            (6U)
11225 #define PWR_PUCRD_PD6_Msk            (0x1U << PWR_PUCRD_PD6_Pos)               /*!< 0x00000040 */
11226 #define PWR_PUCRD_PD6                PWR_PUCRD_PD6_Msk                         /*!< Port PD6 Pull-Up set  */
11227 #define PWR_PUCRD_PD5_Pos            (5U)
11228 #define PWR_PUCRD_PD5_Msk            (0x1U << PWR_PUCRD_PD5_Pos)               /*!< 0x00000020 */
11229 #define PWR_PUCRD_PD5                PWR_PUCRD_PD5_Msk                         /*!< Port PD5 Pull-Up set  */
11230 #define PWR_PUCRD_PD4_Pos            (4U)
11231 #define PWR_PUCRD_PD4_Msk            (0x1U << PWR_PUCRD_PD4_Pos)               /*!< 0x00000010 */
11232 #define PWR_PUCRD_PD4                PWR_PUCRD_PD4_Msk                         /*!< Port PD4 Pull-Up set  */
11233 #define PWR_PUCRD_PD3_Pos            (3U)
11234 #define PWR_PUCRD_PD3_Msk            (0x1U << PWR_PUCRD_PD3_Pos)               /*!< 0x00000008 */
11235 #define PWR_PUCRD_PD3                PWR_PUCRD_PD3_Msk                         /*!< Port PD3 Pull-Up set  */
11236 #define PWR_PUCRD_PD2_Pos            (2U)
11237 #define PWR_PUCRD_PD2_Msk            (0x1U << PWR_PUCRD_PD2_Pos)               /*!< 0x00000004 */
11238 #define PWR_PUCRD_PD2                PWR_PUCRD_PD2_Msk                         /*!< Port PD2 Pull-Up set  */
11239 #define PWR_PUCRD_PD1_Pos            (1U)
11240 #define PWR_PUCRD_PD1_Msk            (0x1U << PWR_PUCRD_PD1_Pos)               /*!< 0x00000002 */
11241 #define PWR_PUCRD_PD1                PWR_PUCRD_PD1_Msk                         /*!< Port PD1 Pull-Up set  */
11242 #define PWR_PUCRD_PD0_Pos            (0U)
11243 #define PWR_PUCRD_PD0_Msk            (0x1U << PWR_PUCRD_PD0_Pos)               /*!< 0x00000001 */
11244 #define PWR_PUCRD_PD0                PWR_PUCRD_PD0_Msk                         /*!< Port PD0 Pull-Up set  */
11245 
11246 /********************  Bit definition for PWR_PDCRD register  ********************/
11247 #define PWR_PDCRD_PD15_Pos           (15U)
11248 #define PWR_PDCRD_PD15_Msk           (0x1U << PWR_PDCRD_PD15_Pos)              /*!< 0x00008000 */
11249 #define PWR_PDCRD_PD15               PWR_PDCRD_PD15_Msk                        /*!< Port PD15 Pull-Down set */
11250 #define PWR_PDCRD_PD14_Pos           (14U)
11251 #define PWR_PDCRD_PD14_Msk           (0x1U << PWR_PDCRD_PD14_Pos)              /*!< 0x00004000 */
11252 #define PWR_PDCRD_PD14               PWR_PDCRD_PD14_Msk                        /*!< Port PD14 Pull-Down set */
11253 #define PWR_PDCRD_PD13_Pos           (13U)
11254 #define PWR_PDCRD_PD13_Msk           (0x1U << PWR_PDCRD_PD13_Pos)              /*!< 0x00002000 */
11255 #define PWR_PDCRD_PD13               PWR_PDCRD_PD13_Msk                        /*!< Port PD13 Pull-Down set */
11256 #define PWR_PDCRD_PD12_Pos           (12U)
11257 #define PWR_PDCRD_PD12_Msk           (0x1U << PWR_PDCRD_PD12_Pos)              /*!< 0x00001000 */
11258 #define PWR_PDCRD_PD12               PWR_PDCRD_PD12_Msk                        /*!< Port PD12 Pull-Down set */
11259 #define PWR_PDCRD_PD11_Pos           (11U)
11260 #define PWR_PDCRD_PD11_Msk           (0x1U << PWR_PDCRD_PD11_Pos)              /*!< 0x00000800 */
11261 #define PWR_PDCRD_PD11               PWR_PDCRD_PD11_Msk                        /*!< Port PD11 Pull-Down set */
11262 #define PWR_PDCRD_PD10_Pos           (10U)
11263 #define PWR_PDCRD_PD10_Msk           (0x1U << PWR_PDCRD_PD10_Pos)              /*!< 0x00000400 */
11264 #define PWR_PDCRD_PD10               PWR_PDCRD_PD10_Msk                        /*!< Port PD10 Pull-Down set */
11265 #define PWR_PDCRD_PD9_Pos            (9U)
11266 #define PWR_PDCRD_PD9_Msk            (0x1U << PWR_PDCRD_PD9_Pos)               /*!< 0x00000200 */
11267 #define PWR_PDCRD_PD9                PWR_PDCRD_PD9_Msk                         /*!< Port PD9 Pull-Down set  */
11268 #define PWR_PDCRD_PD8_Pos            (8U)
11269 #define PWR_PDCRD_PD8_Msk            (0x1U << PWR_PDCRD_PD8_Pos)               /*!< 0x00000100 */
11270 #define PWR_PDCRD_PD8                PWR_PDCRD_PD8_Msk                         /*!< Port PD8 Pull-Down set  */
11271 #define PWR_PDCRD_PD7_Pos            (7U)
11272 #define PWR_PDCRD_PD7_Msk            (0x1U << PWR_PDCRD_PD7_Pos)               /*!< 0x00000080 */
11273 #define PWR_PDCRD_PD7                PWR_PDCRD_PD7_Msk                         /*!< Port PD7 Pull-Down set  */
11274 #define PWR_PDCRD_PD6_Pos            (6U)
11275 #define PWR_PDCRD_PD6_Msk            (0x1U << PWR_PDCRD_PD6_Pos)               /*!< 0x00000040 */
11276 #define PWR_PDCRD_PD6                PWR_PDCRD_PD6_Msk                         /*!< Port PD6 Pull-Down set  */
11277 #define PWR_PDCRD_PD5_Pos            (5U)
11278 #define PWR_PDCRD_PD5_Msk            (0x1U << PWR_PDCRD_PD5_Pos)               /*!< 0x00000020 */
11279 #define PWR_PDCRD_PD5                PWR_PDCRD_PD5_Msk                         /*!< Port PD5 Pull-Down set  */
11280 #define PWR_PDCRD_PD4_Pos            (4U)
11281 #define PWR_PDCRD_PD4_Msk            (0x1U << PWR_PDCRD_PD4_Pos)               /*!< 0x00000010 */
11282 #define PWR_PDCRD_PD4                PWR_PDCRD_PD4_Msk                         /*!< Port PD4 Pull-Down set  */
11283 #define PWR_PDCRD_PD3_Pos            (3U)
11284 #define PWR_PDCRD_PD3_Msk            (0x1U << PWR_PDCRD_PD3_Pos)               /*!< 0x00000008 */
11285 #define PWR_PDCRD_PD3                PWR_PDCRD_PD3_Msk                         /*!< Port PD3 Pull-Down set  */
11286 #define PWR_PDCRD_PD2_Pos            (2U)
11287 #define PWR_PDCRD_PD2_Msk            (0x1U << PWR_PDCRD_PD2_Pos)               /*!< 0x00000004 */
11288 #define PWR_PDCRD_PD2                PWR_PDCRD_PD2_Msk                         /*!< Port PD2 Pull-Down set  */
11289 #define PWR_PDCRD_PD1_Pos            (1U)
11290 #define PWR_PDCRD_PD1_Msk            (0x1U << PWR_PDCRD_PD1_Pos)               /*!< 0x00000002 */
11291 #define PWR_PDCRD_PD1                PWR_PDCRD_PD1_Msk                         /*!< Port PD1 Pull-Down set  */
11292 #define PWR_PDCRD_PD0_Pos            (0U)
11293 #define PWR_PDCRD_PD0_Msk            (0x1U << PWR_PDCRD_PD0_Pos)               /*!< 0x00000001 */
11294 #define PWR_PDCRD_PD0                PWR_PDCRD_PD0_Msk                         /*!< Port PD0 Pull-Down set  */
11295 
11296 /********************  Bit definition for PWR_PUCRE register  ********************/
11297 #define PWR_PUCRE_PE15_Pos           (15U)
11298 #define PWR_PUCRE_PE15_Msk           (0x1U << PWR_PUCRE_PE15_Pos)              /*!< 0x00008000 */
11299 #define PWR_PUCRE_PE15               PWR_PUCRE_PE15_Msk                        /*!< Port PE15 Pull-Up set */
11300 #define PWR_PUCRE_PE14_Pos           (14U)
11301 #define PWR_PUCRE_PE14_Msk           (0x1U << PWR_PUCRE_PE14_Pos)              /*!< 0x00004000 */
11302 #define PWR_PUCRE_PE14               PWR_PUCRE_PE14_Msk                        /*!< Port PE14 Pull-Up set */
11303 #define PWR_PUCRE_PE13_Pos           (13U)
11304 #define PWR_PUCRE_PE13_Msk           (0x1U << PWR_PUCRE_PE13_Pos)              /*!< 0x00002000 */
11305 #define PWR_PUCRE_PE13               PWR_PUCRE_PE13_Msk                        /*!< Port PE13 Pull-Up set */
11306 #define PWR_PUCRE_PE12_Pos           (12U)
11307 #define PWR_PUCRE_PE12_Msk           (0x1U << PWR_PUCRE_PE12_Pos)              /*!< 0x00001000 */
11308 #define PWR_PUCRE_PE12               PWR_PUCRE_PE12_Msk                        /*!< Port PE12 Pull-Up set */
11309 #define PWR_PUCRE_PE11_Pos           (11U)
11310 #define PWR_PUCRE_PE11_Msk           (0x1U << PWR_PUCRE_PE11_Pos)              /*!< 0x00000800 */
11311 #define PWR_PUCRE_PE11               PWR_PUCRE_PE11_Msk                        /*!< Port PE11 Pull-Up set */
11312 #define PWR_PUCRE_PE10_Pos           (10U)
11313 #define PWR_PUCRE_PE10_Msk           (0x1U << PWR_PUCRE_PE10_Pos)              /*!< 0x00000400 */
11314 #define PWR_PUCRE_PE10               PWR_PUCRE_PE10_Msk                        /*!< Port PE10 Pull-Up set */
11315 #define PWR_PUCRE_PE9_Pos            (9U)
11316 #define PWR_PUCRE_PE9_Msk            (0x1U << PWR_PUCRE_PE9_Pos)               /*!< 0x00000200 */
11317 #define PWR_PUCRE_PE9                PWR_PUCRE_PE9_Msk                         /*!< Port PE9 Pull-Up set  */
11318 #define PWR_PUCRE_PE8_Pos            (8U)
11319 #define PWR_PUCRE_PE8_Msk            (0x1U << PWR_PUCRE_PE8_Pos)               /*!< 0x00000100 */
11320 #define PWR_PUCRE_PE8                PWR_PUCRE_PE8_Msk                         /*!< Port PE8 Pull-Up set  */
11321 #define PWR_PUCRE_PE7_Pos            (7U)
11322 #define PWR_PUCRE_PE7_Msk            (0x1U << PWR_PUCRE_PE7_Pos)               /*!< 0x00000080 */
11323 #define PWR_PUCRE_PE7                PWR_PUCRE_PE7_Msk                         /*!< Port PE7 Pull-Up set  */
11324 #define PWR_PUCRE_PE6_Pos            (6U)
11325 #define PWR_PUCRE_PE6_Msk            (0x1U << PWR_PUCRE_PE6_Pos)               /*!< 0x00000040 */
11326 #define PWR_PUCRE_PE6                PWR_PUCRE_PE6_Msk                         /*!< Port PE6 Pull-Up set  */
11327 #define PWR_PUCRE_PE5_Pos            (5U)
11328 #define PWR_PUCRE_PE5_Msk            (0x1U << PWR_PUCRE_PE5_Pos)               /*!< 0x00000020 */
11329 #define PWR_PUCRE_PE5                PWR_PUCRE_PE5_Msk                         /*!< Port PE5 Pull-Up set  */
11330 #define PWR_PUCRE_PE4_Pos            (4U)
11331 #define PWR_PUCRE_PE4_Msk            (0x1U << PWR_PUCRE_PE4_Pos)               /*!< 0x00000010 */
11332 #define PWR_PUCRE_PE4                PWR_PUCRE_PE4_Msk                         /*!< Port PE4 Pull-Up set  */
11333 #define PWR_PUCRE_PE3_Pos            (3U)
11334 #define PWR_PUCRE_PE3_Msk            (0x1U << PWR_PUCRE_PE3_Pos)               /*!< 0x00000008 */
11335 #define PWR_PUCRE_PE3                PWR_PUCRE_PE3_Msk                         /*!< Port PE3 Pull-Up set  */
11336 #define PWR_PUCRE_PE2_Pos            (2U)
11337 #define PWR_PUCRE_PE2_Msk            (0x1U << PWR_PUCRE_PE2_Pos)               /*!< 0x00000004 */
11338 #define PWR_PUCRE_PE2                PWR_PUCRE_PE2_Msk                         /*!< Port PE2 Pull-Up set  */
11339 #define PWR_PUCRE_PE1_Pos            (1U)
11340 #define PWR_PUCRE_PE1_Msk            (0x1U << PWR_PUCRE_PE1_Pos)               /*!< 0x00000002 */
11341 #define PWR_PUCRE_PE1                PWR_PUCRE_PE1_Msk                         /*!< Port PE1 Pull-Up set  */
11342 #define PWR_PUCRE_PE0_Pos            (0U)
11343 #define PWR_PUCRE_PE0_Msk            (0x1U << PWR_PUCRE_PE0_Pos)               /*!< 0x00000001 */
11344 #define PWR_PUCRE_PE0                PWR_PUCRE_PE0_Msk                         /*!< Port PE0 Pull-Up set  */
11345 
11346 /********************  Bit definition for PWR_PDCRE register  ********************/
11347 #define PWR_PDCRE_PE15_Pos           (15U)
11348 #define PWR_PDCRE_PE15_Msk           (0x1U << PWR_PDCRE_PE15_Pos)              /*!< 0x00008000 */
11349 #define PWR_PDCRE_PE15               PWR_PDCRE_PE15_Msk                        /*!< Port PE15 Pull-Down set */
11350 #define PWR_PDCRE_PE14_Pos           (14U)
11351 #define PWR_PDCRE_PE14_Msk           (0x1U << PWR_PDCRE_PE14_Pos)              /*!< 0x00004000 */
11352 #define PWR_PDCRE_PE14               PWR_PDCRE_PE14_Msk                        /*!< Port PE14 Pull-Down set */
11353 #define PWR_PDCRE_PE13_Pos           (13U)
11354 #define PWR_PDCRE_PE13_Msk           (0x1U << PWR_PDCRE_PE13_Pos)              /*!< 0x00002000 */
11355 #define PWR_PDCRE_PE13               PWR_PDCRE_PE13_Msk                        /*!< Port PE13 Pull-Down set */
11356 #define PWR_PDCRE_PE12_Pos           (12U)
11357 #define PWR_PDCRE_PE12_Msk           (0x1U << PWR_PDCRE_PE12_Pos)              /*!< 0x00001000 */
11358 #define PWR_PDCRE_PE12               PWR_PDCRE_PE12_Msk                        /*!< Port PE12 Pull-Down set */
11359 #define PWR_PDCRE_PE11_Pos           (11U)
11360 #define PWR_PDCRE_PE11_Msk           (0x1U << PWR_PDCRE_PE11_Pos)              /*!< 0x00000800 */
11361 #define PWR_PDCRE_PE11               PWR_PDCRE_PE11_Msk                        /*!< Port PE11 Pull-Down set */
11362 #define PWR_PDCRE_PE10_Pos           (10U)
11363 #define PWR_PDCRE_PE10_Msk           (0x1U << PWR_PDCRE_PE10_Pos)              /*!< 0x00000400 */
11364 #define PWR_PDCRE_PE10               PWR_PDCRE_PE10_Msk                        /*!< Port PE10 Pull-Down set */
11365 #define PWR_PDCRE_PE9_Pos            (9U)
11366 #define PWR_PDCRE_PE9_Msk            (0x1U << PWR_PDCRE_PE9_Pos)               /*!< 0x00000200 */
11367 #define PWR_PDCRE_PE9                PWR_PDCRE_PE9_Msk                         /*!< Port PE9 Pull-Down set  */
11368 #define PWR_PDCRE_PE8_Pos            (8U)
11369 #define PWR_PDCRE_PE8_Msk            (0x1U << PWR_PDCRE_PE8_Pos)               /*!< 0x00000100 */
11370 #define PWR_PDCRE_PE8                PWR_PDCRE_PE8_Msk                         /*!< Port PE8 Pull-Down set  */
11371 #define PWR_PDCRE_PE7_Pos            (7U)
11372 #define PWR_PDCRE_PE7_Msk            (0x1U << PWR_PDCRE_PE7_Pos)               /*!< 0x00000080 */
11373 #define PWR_PDCRE_PE7                PWR_PDCRE_PE7_Msk                         /*!< Port PE7 Pull-Down set  */
11374 #define PWR_PDCRE_PE6_Pos            (6U)
11375 #define PWR_PDCRE_PE6_Msk            (0x1U << PWR_PDCRE_PE6_Pos)               /*!< 0x00000040 */
11376 #define PWR_PDCRE_PE6                PWR_PDCRE_PE6_Msk                         /*!< Port PE6 Pull-Down set  */
11377 #define PWR_PDCRE_PE5_Pos            (5U)
11378 #define PWR_PDCRE_PE5_Msk            (0x1U << PWR_PDCRE_PE5_Pos)               /*!< 0x00000020 */
11379 #define PWR_PDCRE_PE5                PWR_PDCRE_PE5_Msk                         /*!< Port PE5 Pull-Down set  */
11380 #define PWR_PDCRE_PE4_Pos            (4U)
11381 #define PWR_PDCRE_PE4_Msk            (0x1U << PWR_PDCRE_PE4_Pos)               /*!< 0x00000010 */
11382 #define PWR_PDCRE_PE4                PWR_PDCRE_PE4_Msk                         /*!< Port PE4 Pull-Down set  */
11383 #define PWR_PDCRE_PE3_Pos            (3U)
11384 #define PWR_PDCRE_PE3_Msk            (0x1U << PWR_PDCRE_PE3_Pos)               /*!< 0x00000008 */
11385 #define PWR_PDCRE_PE3                PWR_PDCRE_PE3_Msk                         /*!< Port PE3 Pull-Down set  */
11386 #define PWR_PDCRE_PE2_Pos            (2U)
11387 #define PWR_PDCRE_PE2_Msk            (0x1U << PWR_PDCRE_PE2_Pos)               /*!< 0x00000004 */
11388 #define PWR_PDCRE_PE2                PWR_PDCRE_PE2_Msk                         /*!< Port PE2 Pull-Down set  */
11389 #define PWR_PDCRE_PE1_Pos            (1U)
11390 #define PWR_PDCRE_PE1_Msk            (0x1U << PWR_PDCRE_PE1_Pos)               /*!< 0x00000002 */
11391 #define PWR_PDCRE_PE1                PWR_PDCRE_PE1_Msk                         /*!< Port PE1 Pull-Down set  */
11392 #define PWR_PDCRE_PE0_Pos            (0U)
11393 #define PWR_PDCRE_PE0_Msk            (0x1U << PWR_PDCRE_PE0_Pos)               /*!< 0x00000001 */
11394 #define PWR_PDCRE_PE0                PWR_PDCRE_PE0_Msk                         /*!< Port PE0 Pull-Down set  */
11395 
11396 /********************  Bit definition for PWR_PUCRF register  ********************/
11397 #define PWR_PUCRF_PF15_Pos           (15U)
11398 #define PWR_PUCRF_PF15_Msk           (0x1U << PWR_PUCRF_PF15_Pos)              /*!< 0x00008000 */
11399 #define PWR_PUCRF_PF15               PWR_PUCRF_PF15_Msk                        /*!< Port PF15 Pull-Up set */
11400 #define PWR_PUCRF_PF14_Pos           (14U)
11401 #define PWR_PUCRF_PF14_Msk           (0x1U << PWR_PUCRF_PF14_Pos)              /*!< 0x00004000 */
11402 #define PWR_PUCRF_PF14               PWR_PUCRF_PF14_Msk                        /*!< Port PF14 Pull-Up set */
11403 #define PWR_PUCRF_PF13_Pos           (13U)
11404 #define PWR_PUCRF_PF13_Msk           (0x1U << PWR_PUCRF_PF13_Pos)              /*!< 0x00002000 */
11405 #define PWR_PUCRF_PF13               PWR_PUCRF_PF13_Msk                        /*!< Port PF13 Pull-Up set */
11406 #define PWR_PUCRF_PF12_Pos           (12U)
11407 #define PWR_PUCRF_PF12_Msk           (0x1U << PWR_PUCRF_PF12_Pos)              /*!< 0x00001000 */
11408 #define PWR_PUCRF_PF12               PWR_PUCRF_PF12_Msk                        /*!< Port PF12 Pull-Up set */
11409 #define PWR_PUCRF_PF11_Pos           (11U)
11410 #define PWR_PUCRF_PF11_Msk           (0x1U << PWR_PUCRF_PF11_Pos)              /*!< 0x00000800 */
11411 #define PWR_PUCRF_PF11               PWR_PUCRF_PF11_Msk                        /*!< Port PF11 Pull-Up set */
11412 #define PWR_PUCRF_PF10_Pos           (10U)
11413 #define PWR_PUCRF_PF10_Msk           (0x1U << PWR_PUCRF_PF10_Pos)              /*!< 0x00000400 */
11414 #define PWR_PUCRF_PF10               PWR_PUCRF_PF10_Msk                        /*!< Port PF10 Pull-Up set */
11415 #define PWR_PUCRF_PF9_Pos            (9U)
11416 #define PWR_PUCRF_PF9_Msk            (0x1U << PWR_PUCRF_PF9_Pos)               /*!< 0x00000200 */
11417 #define PWR_PUCRF_PF9                PWR_PUCRF_PF9_Msk                         /*!< Port PF9 Pull-Up set  */
11418 #define PWR_PUCRF_PF8_Pos            (8U)
11419 #define PWR_PUCRF_PF8_Msk            (0x1U << PWR_PUCRF_PF8_Pos)               /*!< 0x00000100 */
11420 #define PWR_PUCRF_PF8                PWR_PUCRF_PF8_Msk                         /*!< Port PF8 Pull-Up set  */
11421 #define PWR_PUCRF_PF7_Pos            (7U)
11422 #define PWR_PUCRF_PF7_Msk            (0x1U << PWR_PUCRF_PF7_Pos)               /*!< 0x00000080 */
11423 #define PWR_PUCRF_PF7                PWR_PUCRF_PF7_Msk                         /*!< Port PF7 Pull-Up set  */
11424 #define PWR_PUCRF_PF6_Pos            (6U)
11425 #define PWR_PUCRF_PF6_Msk            (0x1U << PWR_PUCRF_PF6_Pos)               /*!< 0x00000040 */
11426 #define PWR_PUCRF_PF6                PWR_PUCRF_PF6_Msk                         /*!< Port PF6 Pull-Up set  */
11427 #define PWR_PUCRF_PF5_Pos            (5U)
11428 #define PWR_PUCRF_PF5_Msk            (0x1U << PWR_PUCRF_PF5_Pos)               /*!< 0x00000020 */
11429 #define PWR_PUCRF_PF5                PWR_PUCRF_PF5_Msk                         /*!< Port PF5 Pull-Up set  */
11430 #define PWR_PUCRF_PF4_Pos            (4U)
11431 #define PWR_PUCRF_PF4_Msk            (0x1U << PWR_PUCRF_PF4_Pos)               /*!< 0x00000010 */
11432 #define PWR_PUCRF_PF4                PWR_PUCRF_PF4_Msk                         /*!< Port PF4 Pull-Up set  */
11433 #define PWR_PUCRF_PF3_Pos            (3U)
11434 #define PWR_PUCRF_PF3_Msk            (0x1U << PWR_PUCRF_PF3_Pos)               /*!< 0x00000008 */
11435 #define PWR_PUCRF_PF3                PWR_PUCRF_PF3_Msk                         /*!< Port PF3 Pull-Up set  */
11436 #define PWR_PUCRF_PF2_Pos            (2U)
11437 #define PWR_PUCRF_PF2_Msk            (0x1U << PWR_PUCRF_PF2_Pos)               /*!< 0x00000004 */
11438 #define PWR_PUCRF_PF2                PWR_PUCRF_PF2_Msk                         /*!< Port PF2 Pull-Up set  */
11439 #define PWR_PUCRF_PF1_Pos            (1U)
11440 #define PWR_PUCRF_PF1_Msk            (0x1U << PWR_PUCRF_PF1_Pos)               /*!< 0x00000002 */
11441 #define PWR_PUCRF_PF1                PWR_PUCRF_PF1_Msk                         /*!< Port PF1 Pull-Up set  */
11442 #define PWR_PUCRF_PF0_Pos            (0U)
11443 #define PWR_PUCRF_PF0_Msk            (0x1U << PWR_PUCRF_PF0_Pos)               /*!< 0x00000001 */
11444 #define PWR_PUCRF_PF0                PWR_PUCRF_PF0_Msk                         /*!< Port PF0 Pull-Up set  */
11445 
11446 /********************  Bit definition for PWR_PDCRF register  ********************/
11447 #define PWR_PDCRF_PF15_Pos           (15U)
11448 #define PWR_PDCRF_PF15_Msk           (0x1U << PWR_PDCRF_PF15_Pos)              /*!< 0x00008000 */
11449 #define PWR_PDCRF_PF15               PWR_PDCRF_PF15_Msk                        /*!< Port PF15 Pull-Down set */
11450 #define PWR_PDCRF_PF14_Pos           (14U)
11451 #define PWR_PDCRF_PF14_Msk           (0x1U << PWR_PDCRF_PF14_Pos)              /*!< 0x00004000 */
11452 #define PWR_PDCRF_PF14               PWR_PDCRF_PF14_Msk                        /*!< Port PF14 Pull-Down set */
11453 #define PWR_PDCRF_PF13_Pos           (13U)
11454 #define PWR_PDCRF_PF13_Msk           (0x1U << PWR_PDCRF_PF13_Pos)              /*!< 0x00002000 */
11455 #define PWR_PDCRF_PF13               PWR_PDCRF_PF13_Msk                        /*!< Port PF13 Pull-Down set */
11456 #define PWR_PDCRF_PF12_Pos           (12U)
11457 #define PWR_PDCRF_PF12_Msk           (0x1U << PWR_PDCRF_PF12_Pos)              /*!< 0x00001000 */
11458 #define PWR_PDCRF_PF12               PWR_PDCRF_PF12_Msk                        /*!< Port PF12 Pull-Down set */
11459 #define PWR_PDCRF_PF11_Pos           (11U)
11460 #define PWR_PDCRF_PF11_Msk           (0x1U << PWR_PDCRF_PF11_Pos)              /*!< 0x00000800 */
11461 #define PWR_PDCRF_PF11               PWR_PDCRF_PF11_Msk                        /*!< Port PF11 Pull-Down set */
11462 #define PWR_PDCRF_PF10_Pos           (10U)
11463 #define PWR_PDCRF_PF10_Msk           (0x1U << PWR_PDCRF_PF10_Pos)              /*!< 0x00000400 */
11464 #define PWR_PDCRF_PF10               PWR_PDCRF_PF10_Msk                        /*!< Port PF10 Pull-Down set */
11465 #define PWR_PDCRF_PF9_Pos            (9U)
11466 #define PWR_PDCRF_PF9_Msk            (0x1U << PWR_PDCRF_PF9_Pos)               /*!< 0x00000200 */
11467 #define PWR_PDCRF_PF9                PWR_PDCRF_PF9_Msk                         /*!< Port PF9 Pull-Down set  */
11468 #define PWR_PDCRF_PF8_Pos            (8U)
11469 #define PWR_PDCRF_PF8_Msk            (0x1U << PWR_PDCRF_PF8_Pos)               /*!< 0x00000100 */
11470 #define PWR_PDCRF_PF8                PWR_PDCRF_PF8_Msk                         /*!< Port PF8 Pull-Down set  */
11471 #define PWR_PDCRF_PF7_Pos            (7U)
11472 #define PWR_PDCRF_PF7_Msk            (0x1U << PWR_PDCRF_PF7_Pos)               /*!< 0x00000080 */
11473 #define PWR_PDCRF_PF7                PWR_PDCRF_PF7_Msk                         /*!< Port PF7 Pull-Down set  */
11474 #define PWR_PDCRF_PF6_Pos            (6U)
11475 #define PWR_PDCRF_PF6_Msk            (0x1U << PWR_PDCRF_PF6_Pos)               /*!< 0x00000040 */
11476 #define PWR_PDCRF_PF6                PWR_PDCRF_PF6_Msk                         /*!< Port PF6 Pull-Down set  */
11477 #define PWR_PDCRF_PF5_Pos            (5U)
11478 #define PWR_PDCRF_PF5_Msk            (0x1U << PWR_PDCRF_PF5_Pos)               /*!< 0x00000020 */
11479 #define PWR_PDCRF_PF5                PWR_PDCRF_PF5_Msk                         /*!< Port PF5 Pull-Down set  */
11480 #define PWR_PDCRF_PF4_Pos            (4U)
11481 #define PWR_PDCRF_PF4_Msk            (0x1U << PWR_PDCRF_PF4_Pos)               /*!< 0x00000010 */
11482 #define PWR_PDCRF_PF4                PWR_PDCRF_PF4_Msk                         /*!< Port PF4 Pull-Down set  */
11483 #define PWR_PDCRF_PF3_Pos            (3U)
11484 #define PWR_PDCRF_PF3_Msk            (0x1U << PWR_PDCRF_PF3_Pos)               /*!< 0x00000008 */
11485 #define PWR_PDCRF_PF3                PWR_PDCRF_PF3_Msk                         /*!< Port PF3 Pull-Down set  */
11486 #define PWR_PDCRF_PF2_Pos            (2U)
11487 #define PWR_PDCRF_PF2_Msk            (0x1U << PWR_PDCRF_PF2_Pos)               /*!< 0x00000004 */
11488 #define PWR_PDCRF_PF2                PWR_PDCRF_PF2_Msk                         /*!< Port PF2 Pull-Down set  */
11489 #define PWR_PDCRF_PF1_Pos            (1U)
11490 #define PWR_PDCRF_PF1_Msk            (0x1U << PWR_PDCRF_PF1_Pos)               /*!< 0x00000002 */
11491 #define PWR_PDCRF_PF1                PWR_PDCRF_PF1_Msk                         /*!< Port PF1 Pull-Down set  */
11492 #define PWR_PDCRF_PF0_Pos            (0U)
11493 #define PWR_PDCRF_PF0_Msk            (0x1U << PWR_PDCRF_PF0_Pos)               /*!< 0x00000001 */
11494 #define PWR_PDCRF_PF0                PWR_PDCRF_PF0_Msk                         /*!< Port PF0 Pull-Down set  */
11495 
11496 /********************  Bit definition for PWR_PUCRG register  ********************/
11497 #define PWR_PUCRG_PG15_Pos           (15U)
11498 #define PWR_PUCRG_PG15_Msk           (0x1U << PWR_PUCRG_PG15_Pos)              /*!< 0x00008000 */
11499 #define PWR_PUCRG_PG15               PWR_PUCRG_PG15_Msk                        /*!< Port PG15 Pull-Up set */
11500 #define PWR_PUCRG_PG14_Pos           (14U)
11501 #define PWR_PUCRG_PG14_Msk           (0x1U << PWR_PUCRG_PG14_Pos)              /*!< 0x00004000 */
11502 #define PWR_PUCRG_PG14               PWR_PUCRG_PG14_Msk                        /*!< Port PG14 Pull-Up set */
11503 #define PWR_PUCRG_PG13_Pos           (13U)
11504 #define PWR_PUCRG_PG13_Msk           (0x1U << PWR_PUCRG_PG13_Pos)              /*!< 0x00002000 */
11505 #define PWR_PUCRG_PG13               PWR_PUCRG_PG13_Msk                        /*!< Port PG13 Pull-Up set */
11506 #define PWR_PUCRG_PG12_Pos           (12U)
11507 #define PWR_PUCRG_PG12_Msk           (0x1U << PWR_PUCRG_PG12_Pos)              /*!< 0x00001000 */
11508 #define PWR_PUCRG_PG12               PWR_PUCRG_PG12_Msk                        /*!< Port PG12 Pull-Up set */
11509 #define PWR_PUCRG_PG11_Pos           (11U)
11510 #define PWR_PUCRG_PG11_Msk           (0x1U << PWR_PUCRG_PG11_Pos)              /*!< 0x00000800 */
11511 #define PWR_PUCRG_PG11               PWR_PUCRG_PG11_Msk                        /*!< Port PG11 Pull-Up set */
11512 #define PWR_PUCRG_PG10_Pos           (10U)
11513 #define PWR_PUCRG_PG10_Msk           (0x1U << PWR_PUCRG_PG10_Pos)              /*!< 0x00000400 */
11514 #define PWR_PUCRG_PG10               PWR_PUCRG_PG10_Msk                        /*!< Port PG10 Pull-Up set */
11515 #define PWR_PUCRG_PG9_Pos            (9U)
11516 #define PWR_PUCRG_PG9_Msk            (0x1U << PWR_PUCRG_PG9_Pos)               /*!< 0x00000200 */
11517 #define PWR_PUCRG_PG9                PWR_PUCRG_PG9_Msk                         /*!< Port PG9 Pull-Up set  */
11518 #define PWR_PUCRG_PG8_Pos            (8U)
11519 #define PWR_PUCRG_PG8_Msk            (0x1U << PWR_PUCRG_PG8_Pos)               /*!< 0x00000100 */
11520 #define PWR_PUCRG_PG8                PWR_PUCRG_PG8_Msk                         /*!< Port PG8 Pull-Up set  */
11521 #define PWR_PUCRG_PG7_Pos            (7U)
11522 #define PWR_PUCRG_PG7_Msk            (0x1U << PWR_PUCRG_PG7_Pos)               /*!< 0x00000080 */
11523 #define PWR_PUCRG_PG7                PWR_PUCRG_PG7_Msk                         /*!< Port PG7 Pull-Up set  */
11524 #define PWR_PUCRG_PG6_Pos            (6U)
11525 #define PWR_PUCRG_PG6_Msk            (0x1U << PWR_PUCRG_PG6_Pos)               /*!< 0x00000040 */
11526 #define PWR_PUCRG_PG6                PWR_PUCRG_PG6_Msk                         /*!< Port PG6 Pull-Up set  */
11527 #define PWR_PUCRG_PG5_Pos            (5U)
11528 #define PWR_PUCRG_PG5_Msk            (0x1U << PWR_PUCRG_PG5_Pos)               /*!< 0x00000020 */
11529 #define PWR_PUCRG_PG5                PWR_PUCRG_PG5_Msk                         /*!< Port PG5 Pull-Up set  */
11530 #define PWR_PUCRG_PG4_Pos            (4U)
11531 #define PWR_PUCRG_PG4_Msk            (0x1U << PWR_PUCRG_PG4_Pos)               /*!< 0x00000010 */
11532 #define PWR_PUCRG_PG4                PWR_PUCRG_PG4_Msk                         /*!< Port PG4 Pull-Up set  */
11533 #define PWR_PUCRG_PG3_Pos            (3U)
11534 #define PWR_PUCRG_PG3_Msk            (0x1U << PWR_PUCRG_PG3_Pos)               /*!< 0x00000008 */
11535 #define PWR_PUCRG_PG3                PWR_PUCRG_PG3_Msk                         /*!< Port PG3 Pull-Up set  */
11536 #define PWR_PUCRG_PG2_Pos            (2U)
11537 #define PWR_PUCRG_PG2_Msk            (0x1U << PWR_PUCRG_PG2_Pos)               /*!< 0x00000004 */
11538 #define PWR_PUCRG_PG2                PWR_PUCRG_PG2_Msk                         /*!< Port PG2 Pull-Up set  */
11539 #define PWR_PUCRG_PG1_Pos            (1U)
11540 #define PWR_PUCRG_PG1_Msk            (0x1U << PWR_PUCRG_PG1_Pos)               /*!< 0x00000002 */
11541 #define PWR_PUCRG_PG1                PWR_PUCRG_PG1_Msk                         /*!< Port PG1 Pull-Up set  */
11542 #define PWR_PUCRG_PG0_Pos            (0U)
11543 #define PWR_PUCRG_PG0_Msk            (0x1U << PWR_PUCRG_PG0_Pos)               /*!< 0x00000001 */
11544 #define PWR_PUCRG_PG0                PWR_PUCRG_PG0_Msk                         /*!< Port PG0 Pull-Up set  */
11545 
11546 /********************  Bit definition for PWR_PDCRG register  ********************/
11547 #define PWR_PDCRG_PG15_Pos           (15U)
11548 #define PWR_PDCRG_PG15_Msk           (0x1U << PWR_PDCRG_PG15_Pos)              /*!< 0x00008000 */
11549 #define PWR_PDCRG_PG15               PWR_PDCRG_PG15_Msk                        /*!< Port PG15 Pull-Down set */
11550 #define PWR_PDCRG_PG14_Pos           (14U)
11551 #define PWR_PDCRG_PG14_Msk           (0x1U << PWR_PDCRG_PG14_Pos)              /*!< 0x00004000 */
11552 #define PWR_PDCRG_PG14               PWR_PDCRG_PG14_Msk                        /*!< Port PG14 Pull-Down set */
11553 #define PWR_PDCRG_PG13_Pos           (13U)
11554 #define PWR_PDCRG_PG13_Msk           (0x1U << PWR_PDCRG_PG13_Pos)              /*!< 0x00002000 */
11555 #define PWR_PDCRG_PG13               PWR_PDCRG_PG13_Msk                        /*!< Port PG13 Pull-Down set */
11556 #define PWR_PDCRG_PG12_Pos           (12U)
11557 #define PWR_PDCRG_PG12_Msk           (0x1U << PWR_PDCRG_PG12_Pos)              /*!< 0x00001000 */
11558 #define PWR_PDCRG_PG12               PWR_PDCRG_PG12_Msk                        /*!< Port PG12 Pull-Down set */
11559 #define PWR_PDCRG_PG11_Pos           (11U)
11560 #define PWR_PDCRG_PG11_Msk           (0x1U << PWR_PDCRG_PG11_Pos)              /*!< 0x00000800 */
11561 #define PWR_PDCRG_PG11               PWR_PDCRG_PG11_Msk                        /*!< Port PG11 Pull-Down set */
11562 #define PWR_PDCRG_PG10_Pos           (10U)
11563 #define PWR_PDCRG_PG10_Msk           (0x1U << PWR_PDCRG_PG10_Pos)              /*!< 0x00000400 */
11564 #define PWR_PDCRG_PG10               PWR_PDCRG_PG10_Msk                        /*!< Port PG10 Pull-Down set */
11565 #define PWR_PDCRG_PG9_Pos            (9U)
11566 #define PWR_PDCRG_PG9_Msk            (0x1U << PWR_PDCRG_PG9_Pos)               /*!< 0x00000200 */
11567 #define PWR_PDCRG_PG9                PWR_PDCRG_PG9_Msk                         /*!< Port PG9 Pull-Down set  */
11568 #define PWR_PDCRG_PG8_Pos            (8U)
11569 #define PWR_PDCRG_PG8_Msk            (0x1U << PWR_PDCRG_PG8_Pos)               /*!< 0x00000100 */
11570 #define PWR_PDCRG_PG8                PWR_PDCRG_PG8_Msk                         /*!< Port PG8 Pull-Down set  */
11571 #define PWR_PDCRG_PG7_Pos            (7U)
11572 #define PWR_PDCRG_PG7_Msk            (0x1U << PWR_PDCRG_PG7_Pos)               /*!< 0x00000080 */
11573 #define PWR_PDCRG_PG7                PWR_PDCRG_PG7_Msk                         /*!< Port PG7 Pull-Down set  */
11574 #define PWR_PDCRG_PG6_Pos            (6U)
11575 #define PWR_PDCRG_PG6_Msk            (0x1U << PWR_PDCRG_PG6_Pos)               /*!< 0x00000040 */
11576 #define PWR_PDCRG_PG6                PWR_PDCRG_PG6_Msk                         /*!< Port PG6 Pull-Down set  */
11577 #define PWR_PDCRG_PG5_Pos            (5U)
11578 #define PWR_PDCRG_PG5_Msk            (0x1U << PWR_PDCRG_PG5_Pos)               /*!< 0x00000020 */
11579 #define PWR_PDCRG_PG5                PWR_PDCRG_PG5_Msk                         /*!< Port PG5 Pull-Down set  */
11580 #define PWR_PDCRG_PG4_Pos            (4U)
11581 #define PWR_PDCRG_PG4_Msk            (0x1U << PWR_PDCRG_PG4_Pos)               /*!< 0x00000010 */
11582 #define PWR_PDCRG_PG4                PWR_PDCRG_PG4_Msk                         /*!< Port PG4 Pull-Down set  */
11583 #define PWR_PDCRG_PG3_Pos            (3U)
11584 #define PWR_PDCRG_PG3_Msk            (0x1U << PWR_PDCRG_PG3_Pos)               /*!< 0x00000008 */
11585 #define PWR_PDCRG_PG3                PWR_PDCRG_PG3_Msk                         /*!< Port PG3 Pull-Down set  */
11586 #define PWR_PDCRG_PG2_Pos            (2U)
11587 #define PWR_PDCRG_PG2_Msk            (0x1U << PWR_PDCRG_PG2_Pos)               /*!< 0x00000004 */
11588 #define PWR_PDCRG_PG2                PWR_PDCRG_PG2_Msk                         /*!< Port PG2 Pull-Down set  */
11589 #define PWR_PDCRG_PG1_Pos            (1U)
11590 #define PWR_PDCRG_PG1_Msk            (0x1U << PWR_PDCRG_PG1_Pos)               /*!< 0x00000002 */
11591 #define PWR_PDCRG_PG1                PWR_PDCRG_PG1_Msk                         /*!< Port PG1 Pull-Down set  */
11592 #define PWR_PDCRG_PG0_Pos            (0U)
11593 #define PWR_PDCRG_PG0_Msk            (0x1U << PWR_PDCRG_PG0_Pos)               /*!< 0x00000001 */
11594 #define PWR_PDCRG_PG0                PWR_PDCRG_PG0_Msk                         /*!< Port PG0 Pull-Down set  */
11595 
11596 /********************  Bit definition for PWR_PUCRH register  ********************/
11597 #define PWR_PUCRH_PH15_Pos           (15U)
11598 #define PWR_PUCRH_PH15_Msk           (0x1U << PWR_PUCRH_PH15_Pos)              /*!< 0x00008000 */
11599 #define PWR_PUCRH_PH15               PWR_PUCRH_PH15_Msk                        /*!< Port PH15 Pull-Up set  */
11600 #define PWR_PUCRH_PH14_Pos           (14U)
11601 #define PWR_PUCRH_PH14_Msk           (0x1U << PWR_PUCRH_PH14_Pos)              /*!< 0x00004000 */
11602 #define PWR_PUCRH_PH14               PWR_PUCRH_PH14_Msk                        /*!< Port PH14 Pull-Up set  */
11603 #define PWR_PUCRH_PH13_Pos           (13U)
11604 #define PWR_PUCRH_PH13_Msk           (0x1U << PWR_PUCRH_PH13_Pos)              /*!< 0x00002000 */
11605 #define PWR_PUCRH_PH13               PWR_PUCRH_PH13_Msk                        /*!< Port PH13 Pull-Up set  */
11606 #define PWR_PUCRH_PH12_Pos           (12U)
11607 #define PWR_PUCRH_PH12_Msk           (0x1U << PWR_PUCRH_PH12_Pos)              /*!< 0x00001000 */
11608 #define PWR_PUCRH_PH12               PWR_PUCRH_PH12_Msk                        /*!< Port PH12 Pull-Up set  */
11609 #define PWR_PUCRH_PH11_Pos           (11U)
11610 #define PWR_PUCRH_PH11_Msk           (0x1U << PWR_PUCRH_PH11_Pos)              /*!< 0x00000800 */
11611 #define PWR_PUCRH_PH11               PWR_PUCRH_PH11_Msk                        /*!< Port PH11 Pull-Up set  */
11612 #define PWR_PUCRH_PH10_Pos           (10U)
11613 #define PWR_PUCRH_PH10_Msk           (0x1U << PWR_PUCRH_PH10_Pos)              /*!< 0x00000400 */
11614 #define PWR_PUCRH_PH10               PWR_PUCRH_PH10_Msk                        /*!< Port PH10 Pull-Up set  */
11615 #define PWR_PUCRH_PH9_Pos            (9U)
11616 #define PWR_PUCRH_PH9_Msk            (0x1U << PWR_PUCRH_PH9_Pos)               /*!< 0x00000200 */
11617 #define PWR_PUCRH_PH9                PWR_PUCRH_PH9_Msk                         /*!< Port PH9 Pull-Up set  */
11618 #define PWR_PUCRH_PH8_Pos            (8U)
11619 #define PWR_PUCRH_PH8_Msk            (0x1U << PWR_PUCRH_PH8_Pos)               /*!< 0x00000100 */
11620 #define PWR_PUCRH_PH8                PWR_PUCRH_PH8_Msk                         /*!< Port PH8 Pull-Up set  */
11621 #define PWR_PUCRH_PH7_Pos            (7U)
11622 #define PWR_PUCRH_PH7_Msk            (0x1U << PWR_PUCRH_PH7_Pos)               /*!< 0x00000080 */
11623 #define PWR_PUCRH_PH7                PWR_PUCRH_PH7_Msk                         /*!< Port PH7 Pull-Up set  */
11624 #define PWR_PUCRH_PH6_Pos            (6U)
11625 #define PWR_PUCRH_PH6_Msk            (0x1U << PWR_PUCRH_PH6_Pos)               /*!< 0x00000040 */
11626 #define PWR_PUCRH_PH6                PWR_PUCRH_PH6_Msk                         /*!< Port PH6 Pull-Up set  */
11627 #define PWR_PUCRH_PH5_Pos            (5U)
11628 #define PWR_PUCRH_PH5_Msk            (0x1U << PWR_PUCRH_PH5_Pos)               /*!< 0x00000020 */
11629 #define PWR_PUCRH_PH5                PWR_PUCRH_PH5_Msk                         /*!< Port PH5 Pull-Up set  */
11630 #define PWR_PUCRH_PH4_Pos            (4U)
11631 #define PWR_PUCRH_PH4_Msk            (0x1U << PWR_PUCRH_PH4_Pos)               /*!< 0x00000010 */
11632 #define PWR_PUCRH_PH4                PWR_PUCRH_PH4_Msk                         /*!< Port PH4 Pull-Up set  */
11633 #define PWR_PUCRH_PH3_Pos            (3U)
11634 #define PWR_PUCRH_PH3_Msk            (0x1U << PWR_PUCRH_PH3_Pos)               /*!< 0x00000008 */
11635 #define PWR_PUCRH_PH3                PWR_PUCRH_PH3_Msk                         /*!< Port PH3 Pull-Up set  */
11636 #define PWR_PUCRH_PH2_Pos            (2U)
11637 #define PWR_PUCRH_PH2_Msk            (0x1U << PWR_PUCRH_PH2_Pos)               /*!< 0x00000004 */
11638 #define PWR_PUCRH_PH2                PWR_PUCRH_PH2_Msk                         /*!< Port PH2 Pull-Up set  */
11639 #define PWR_PUCRH_PH1_Pos            (1U)
11640 #define PWR_PUCRH_PH1_Msk            (0x1U << PWR_PUCRH_PH1_Pos)               /*!< 0x00000002 */
11641 #define PWR_PUCRH_PH1                PWR_PUCRH_PH1_Msk                         /*!< Port PH1 Pull-Up set  */
11642 #define PWR_PUCRH_PH0_Pos            (0U)
11643 #define PWR_PUCRH_PH0_Msk            (0x1U << PWR_PUCRH_PH0_Pos)               /*!< 0x00000001 */
11644 #define PWR_PUCRH_PH0                PWR_PUCRH_PH0_Msk                         /*!< Port PH0 Pull-Up set  */
11645 
11646 /********************  Bit definition for PWR_PDCRH register  ********************/
11647 #define PWR_PDCRH_PH15_Pos           (15U)
11648 #define PWR_PDCRH_PH15_Msk           (0x1U << PWR_PDCRH_PH15_Pos)              /*!< 0x00008000 */
11649 #define PWR_PDCRH_PH15               PWR_PDCRH_PH15_Msk                        /*!< Port PH15 Pull-Down set  */
11650 #define PWR_PDCRH_PH14_Pos           (14U)
11651 #define PWR_PDCRH_PH14_Msk           (0x1U << PWR_PDCRH_PH14_Pos)              /*!< 0x00004000 */
11652 #define PWR_PDCRH_PH14               PWR_PDCRH_PH14_Msk                        /*!< Port PH14 Pull-Down set  */
11653 #define PWR_PDCRH_PH13_Pos           (13U)
11654 #define PWR_PDCRH_PH13_Msk           (0x1U << PWR_PDCRH_PH13_Pos)              /*!< 0x00002000 */
11655 #define PWR_PDCRH_PH13               PWR_PDCRH_PH13_Msk                        /*!< Port PH13 Pull-Down set  */
11656 #define PWR_PDCRH_PH12_Pos           (12U)
11657 #define PWR_PDCRH_PH12_Msk           (0x1U << PWR_PDCRH_PH12_Pos)              /*!< 0x00001000 */
11658 #define PWR_PDCRH_PH12               PWR_PDCRH_PH12_Msk                        /*!< Port PH12 Pull-Down set  */
11659 #define PWR_PDCRH_PH11_Pos           (11U)
11660 #define PWR_PDCRH_PH11_Msk           (0x1U << PWR_PDCRH_PH11_Pos)              /*!< 0x00000800 */
11661 #define PWR_PDCRH_PH11               PWR_PDCRH_PH11_Msk                        /*!< Port PH11 Pull-Down set  */
11662 #define PWR_PDCRH_PH10_Pos           (10U)
11663 #define PWR_PDCRH_PH10_Msk           (0x1U << PWR_PDCRH_PH10_Pos)              /*!< 0x00000400 */
11664 #define PWR_PDCRH_PH10               PWR_PDCRH_PH10_Msk                        /*!< Port PH10 Pull-Down set  */
11665 #define PWR_PDCRH_PH9_Pos            (9U)
11666 #define PWR_PDCRH_PH9_Msk            (0x1U << PWR_PDCRH_PH9_Pos)               /*!< 0x00000200 */
11667 #define PWR_PDCRH_PH9                PWR_PDCRH_PH9_Msk                         /*!< Port PH9 Pull-Down set  */
11668 #define PWR_PDCRH_PH8_Pos            (8U)
11669 #define PWR_PDCRH_PH8_Msk            (0x1U << PWR_PDCRH_PH8_Pos)               /*!< 0x00000100 */
11670 #define PWR_PDCRH_PH8                PWR_PDCRH_PH8_Msk                         /*!< Port PH8 Pull-Down set  */
11671 #define PWR_PDCRH_PH7_Pos            (7U)
11672 #define PWR_PDCRH_PH7_Msk            (0x1U << PWR_PDCRH_PH7_Pos)               /*!< 0x00000080 */
11673 #define PWR_PDCRH_PH7                PWR_PDCRH_PH7_Msk                         /*!< Port PH7 Pull-Down set  */
11674 #define PWR_PDCRH_PH6_Pos            (6U)
11675 #define PWR_PDCRH_PH6_Msk            (0x1U << PWR_PDCRH_PH6_Pos)               /*!< 0x00000040 */
11676 #define PWR_PDCRH_PH6                PWR_PDCRH_PH6_Msk                         /*!< Port PH6 Pull-Down set  */
11677 #define PWR_PDCRH_PH5_Pos            (5U)
11678 #define PWR_PDCRH_PH5_Msk            (0x1U << PWR_PDCRH_PH5_Pos)               /*!< 0x00000020 */
11679 #define PWR_PDCRH_PH5                PWR_PDCRH_PH5_Msk                         /*!< Port PH5 Pull-Down set  */
11680 #define PWR_PDCRH_PH4_Pos            (4U)
11681 #define PWR_PDCRH_PH4_Msk            (0x1U << PWR_PDCRH_PH4_Pos)               /*!< 0x00000010 */
11682 #define PWR_PDCRH_PH4                PWR_PDCRH_PH4_Msk                         /*!< Port PH4 Pull-Down set  */
11683 #define PWR_PDCRH_PH3_Pos            (3U)
11684 #define PWR_PDCRH_PH3_Msk            (0x1U << PWR_PDCRH_PH3_Pos)               /*!< 0x00000008 */
11685 #define PWR_PDCRH_PH3                PWR_PDCRH_PH3_Msk                         /*!< Port PH3 Pull-Down set  */
11686 #define PWR_PDCRH_PH2_Pos            (2U)
11687 #define PWR_PDCRH_PH2_Msk            (0x1U << PWR_PDCRH_PH2_Pos)               /*!< 0x00000004 */
11688 #define PWR_PDCRH_PH2                PWR_PDCRH_PH2_Msk                         /*!< Port PH1 Pull-Down set  */
11689 #define PWR_PDCRH_PH1_Pos            (1U)
11690 #define PWR_PDCRH_PH1_Msk            (0x1U << PWR_PDCRH_PH1_Pos)               /*!< 0x00000002 */
11691 #define PWR_PDCRH_PH1                PWR_PDCRH_PH1_Msk                         /*!< Port PH1 Pull-Down set  */
11692 #define PWR_PDCRH_PH0_Pos            (0U)
11693 #define PWR_PDCRH_PH0_Msk            (0x1U << PWR_PDCRH_PH0_Pos)               /*!< 0x00000001 */
11694 #define PWR_PDCRH_PH0                PWR_PDCRH_PH0_Msk                         /*!< Port PH0 Pull-Down set  */
11695 
11696 /********************  Bit definition for PWR_PUCRI register  ********************/
11697 #define PWR_PUCRI_PI11_Pos           (11U)
11698 #define PWR_PUCRI_PI11_Msk           (0x1U << PWR_PUCRI_PI11_Pos)              /*!< 0x00000800 */
11699 #define PWR_PUCRI_PI11               PWR_PUCRI_PI11_Msk                        /*!< Port PI11 Pull-Up set */
11700 #define PWR_PUCRI_PI10_Pos           (10U)
11701 #define PWR_PUCRI_PI10_Msk           (0x1U << PWR_PUCRI_PI10_Pos)              /*!< 0x00000400 */
11702 #define PWR_PUCRI_PI10               PWR_PUCRI_PI10_Msk                        /*!< Port PI10 Pull-Up set */
11703 #define PWR_PUCRI_PI9_Pos            (9U)
11704 #define PWR_PUCRI_PI9_Msk            (0x1U << PWR_PUCRI_PI9_Pos)               /*!< 0x00000200 */
11705 #define PWR_PUCRI_PI9                PWR_PUCRI_PI9_Msk                         /*!< Port PI9 Pull-Up set  */
11706 #define PWR_PUCRI_PI8_Pos            (8U)
11707 #define PWR_PUCRI_PI8_Msk            (0x1U << PWR_PUCRI_PI8_Pos)               /*!< 0x00000100 */
11708 #define PWR_PUCRI_PI8                PWR_PUCRI_PI8_Msk                         /*!< Port PI8 Pull-Up set  */
11709 #define PWR_PUCRI_PI7_Pos            (7U)
11710 #define PWR_PUCRI_PI7_Msk            (0x1U << PWR_PUCRI_PI7_Pos)               /*!< 0x00000080 */
11711 #define PWR_PUCRI_PI7                PWR_PUCRI_PI7_Msk                         /*!< Port PI7 Pull-Up set  */
11712 #define PWR_PUCRI_PI6_Pos            (6U)
11713 #define PWR_PUCRI_PI6_Msk            (0x1U << PWR_PUCRI_PI6_Pos)               /*!< 0x00000040 */
11714 #define PWR_PUCRI_PI6                PWR_PUCRI_PI6_Msk                         /*!< Port PI6 Pull-Up set  */
11715 #define PWR_PUCRI_PI5_Pos            (5U)
11716 #define PWR_PUCRI_PI5_Msk            (0x1U << PWR_PUCRI_PI5_Pos)               /*!< 0x00000020 */
11717 #define PWR_PUCRI_PI5                PWR_PUCRI_PI5_Msk                         /*!< Port PI5 Pull-Up set  */
11718 #define PWR_PUCRI_PI4_Pos            (4U)
11719 #define PWR_PUCRI_PI4_Msk            (0x1U << PWR_PUCRI_PI4_Pos)               /*!< 0x00000010 */
11720 #define PWR_PUCRI_PI4                PWR_PUCRI_PI4_Msk                         /*!< Port PI4 Pull-Up set  */
11721 #define PWR_PUCRI_PI3_Pos            (3U)
11722 #define PWR_PUCRI_PI3_Msk            (0x1U << PWR_PUCRI_PI3_Pos)               /*!< 0x00000008 */
11723 #define PWR_PUCRI_PI3                PWR_PUCRI_PI3_Msk                         /*!< Port PI3 Pull-Up set  */
11724 #define PWR_PUCRI_PI2_Pos            (2U)
11725 #define PWR_PUCRI_PI2_Msk            (0x1U << PWR_PUCRI_PI2_Pos)               /*!< 0x00000004 */
11726 #define PWR_PUCRI_PI2                PWR_PUCRI_PI2_Msk                         /*!< Port PI2 Pull-Up set  */
11727 #define PWR_PUCRI_PI1_Pos            (1U)
11728 #define PWR_PUCRI_PI1_Msk            (0x1U << PWR_PUCRI_PI1_Pos)               /*!< 0x00000002 */
11729 #define PWR_PUCRI_PI1                PWR_PUCRI_PI1_Msk                         /*!< Port PI1 Pull-Up set  */
11730 #define PWR_PUCRI_PI0_Pos            (0U)
11731 #define PWR_PUCRI_PI0_Msk            (0x1U << PWR_PUCRI_PI0_Pos)               /*!< 0x00000001 */
11732 #define PWR_PUCRI_PI0                PWR_PUCRI_PI0_Msk                         /*!< Port PI0 Pull-Up set  */
11733 
11734 /********************  Bit definition for PWR_PDCRI register  ********************/
11735 #define PWR_PDCRI_PI11_Pos           (11U)
11736 #define PWR_PDCRI_PI11_Msk           (0x1U << PWR_PDCRI_PI11_Pos)              /*!< 0x00000800 */
11737 #define PWR_PDCRI_PI11               PWR_PDCRI_PI11_Msk                        /*!< Port PI11 Pull-Down set */
11738 #define PWR_PDCRI_PI10_Pos           (10U)
11739 #define PWR_PDCRI_PI10_Msk           (0x1U << PWR_PDCRI_PI10_Pos)              /*!< 0x00000400 */
11740 #define PWR_PDCRI_PI10               PWR_PDCRI_PI10_Msk                        /*!< Port PI10 Pull-Down set */
11741 #define PWR_PDCRI_PI9_Pos            (9U)
11742 #define PWR_PDCRI_PI9_Msk            (0x1U << PWR_PDCRI_PI9_Pos)               /*!< 0x00000200 */
11743 #define PWR_PDCRI_PI9                PWR_PDCRI_PI9_Msk                         /*!< Port PI9 Pull-Down set  */
11744 #define PWR_PDCRI_PI8_Pos            (8U)
11745 #define PWR_PDCRI_PI8_Msk            (0x1U << PWR_PDCRI_PI8_Pos)               /*!< 0x00000100 */
11746 #define PWR_PDCRI_PI8                PWR_PDCRI_PI8_Msk                         /*!< Port PI8 Pull-Down set  */
11747 #define PWR_PDCRI_PI7_Pos            (7U)
11748 #define PWR_PDCRI_PI7_Msk            (0x1U << PWR_PDCRI_PI7_Pos)               /*!< 0x00000080 */
11749 #define PWR_PDCRI_PI7                PWR_PDCRI_PI7_Msk                         /*!< Port PI7 Pull-Down set  */
11750 #define PWR_PDCRI_PI6_Pos            (6U)
11751 #define PWR_PDCRI_PI6_Msk            (0x1U << PWR_PDCRI_PI6_Pos)               /*!< 0x00000040 */
11752 #define PWR_PDCRI_PI6                PWR_PDCRI_PI6_Msk                         /*!< Port PI6 Pull-Down set  */
11753 #define PWR_PDCRI_PI5_Pos            (5U)
11754 #define PWR_PDCRI_PI5_Msk            (0x1U << PWR_PDCRI_PI5_Pos)               /*!< 0x00000020 */
11755 #define PWR_PDCRI_PI5                PWR_PDCRI_PI5_Msk                         /*!< Port PI5 Pull-Down set  */
11756 #define PWR_PDCRI_PI4_Pos            (4U)
11757 #define PWR_PDCRI_PI4_Msk            (0x1U << PWR_PDCRI_PI4_Pos)               /*!< 0x00000010 */
11758 #define PWR_PDCRI_PI4                PWR_PDCRI_PI4_Msk                         /*!< Port PI4 Pull-Down set  */
11759 #define PWR_PDCRI_PI3_Pos            (3U)
11760 #define PWR_PDCRI_PI3_Msk            (0x1U << PWR_PDCRI_PI3_Pos)               /*!< 0x00000008 */
11761 #define PWR_PDCRI_PI3                PWR_PDCRI_PI3_Msk                         /*!< Port PI3 Pull-Down set  */
11762 #define PWR_PDCRI_PI2_Pos            (2U)
11763 #define PWR_PDCRI_PI2_Msk            (0x1U << PWR_PDCRI_PI2_Pos)               /*!< 0x00000004 */
11764 #define PWR_PDCRI_PI2                PWR_PDCRI_PI2_Msk                         /*!< Port PI2 Pull-Down set  */
11765 #define PWR_PDCRI_PI1_Pos            (1U)
11766 #define PWR_PDCRI_PI1_Msk            (0x1U << PWR_PDCRI_PI1_Pos)               /*!< 0x00000002 */
11767 #define PWR_PDCRI_PI1                PWR_PDCRI_PI1_Msk                         /*!< Port PI1 Pull-Down set  */
11768 #define PWR_PDCRI_PI0_Pos            (0U)
11769 #define PWR_PDCRI_PI0_Msk            (0x1U << PWR_PDCRI_PI0_Pos)               /*!< 0x00000001 */
11770 #define PWR_PDCRI_PI0                PWR_PDCRI_PI0_Msk                         /*!< Port PI0 Pull-Down set  */
11771 
11772 
11773 /******************************************************************************/
11774 /*                                                                            */
11775 /*                         Reset and Clock Control                            */
11776 /*                                                                            */
11777 /******************************************************************************/
11778 /*
11779 * @brief Specific device feature definitions  (not present on all devices in the STM32L4 serie)
11780 */
11781 #define RCC_HSI48_SUPPORT
11782 #define RCC_PLLP_DIV_2_31_SUPPORT
11783 #define RCC_PLLSAI1P_DIV_2_31_SUPPORT
11784 #define RCC_PLLSAI2_SUPPORT
11785 #define RCC_PLLSAI2P_DIV_2_31_SUPPORT
11786 
11787 /********************  Bit definition for RCC_CR register  ********************/
11788 #define RCC_CR_MSION_Pos                     (0U)
11789 #define RCC_CR_MSION_Msk                     (0x1U << RCC_CR_MSION_Pos)        /*!< 0x00000001 */
11790 #define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
11791 #define RCC_CR_MSIRDY_Pos                    (1U)
11792 #define RCC_CR_MSIRDY_Msk                    (0x1U << RCC_CR_MSIRDY_Pos)       /*!< 0x00000002 */
11793 #define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
11794 #define RCC_CR_MSIPLLEN_Pos                  (2U)
11795 #define RCC_CR_MSIPLLEN_Msk                  (0x1U << RCC_CR_MSIPLLEN_Pos)     /*!< 0x00000004 */
11796 #define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
11797 #define RCC_CR_MSIRGSEL_Pos                  (3U)
11798 #define RCC_CR_MSIRGSEL_Msk                  (0x1U << RCC_CR_MSIRGSEL_Pos)     /*!< 0x00000008 */
11799 #define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
11800 
11801 /*!< MSIRANGE configuration : 12 frequency ranges available */
11802 #define RCC_CR_MSIRANGE_Pos                  (4U)
11803 #define RCC_CR_MSIRANGE_Msk                  (0xFU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000F0 */
11804 #define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
11805 #define RCC_CR_MSIRANGE_0                    (0x0U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000000 */
11806 #define RCC_CR_MSIRANGE_1                    (0x1U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000010 */
11807 #define RCC_CR_MSIRANGE_2                    (0x2U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000020 */
11808 #define RCC_CR_MSIRANGE_3                    (0x3U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000030 */
11809 #define RCC_CR_MSIRANGE_4                    (0x4U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000040 */
11810 #define RCC_CR_MSIRANGE_5                    (0x5U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000050 */
11811 #define RCC_CR_MSIRANGE_6                    (0x6U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000060 */
11812 #define RCC_CR_MSIRANGE_7                    (0x7U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000070 */
11813 #define RCC_CR_MSIRANGE_8                    (0x8U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000080 */
11814 #define RCC_CR_MSIRANGE_9                    (0x9U << RCC_CR_MSIRANGE_Pos)     /*!< 0x00000090 */
11815 #define RCC_CR_MSIRANGE_10                   (0xAU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000A0 */
11816 #define RCC_CR_MSIRANGE_11                   (0xBU << RCC_CR_MSIRANGE_Pos)     /*!< 0x000000B0 */
11817 
11818 #define RCC_CR_HSION_Pos                     (8U)
11819 #define RCC_CR_HSION_Msk                     (0x1U << RCC_CR_HSION_Pos)        /*!< 0x00000100 */
11820 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
11821 #define RCC_CR_HSIKERON_Pos                  (9U)
11822 #define RCC_CR_HSIKERON_Msk                  (0x1U << RCC_CR_HSIKERON_Pos)     /*!< 0x00000200 */
11823 #define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
11824 #define RCC_CR_HSIRDY_Pos                    (10U)
11825 #define RCC_CR_HSIRDY_Msk                    (0x1U << RCC_CR_HSIRDY_Pos)       /*!< 0x00000400 */
11826 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
11827 #define RCC_CR_HSIASFS_Pos                   (11U)
11828 #define RCC_CR_HSIASFS_Msk                   (0x1U << RCC_CR_HSIASFS_Pos)      /*!< 0x00000800 */
11829 #define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
11830 
11831 #define RCC_CR_HSEON_Pos                     (16U)
11832 #define RCC_CR_HSEON_Msk                     (0x1U << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
11833 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
11834 #define RCC_CR_HSERDY_Pos                    (17U)
11835 #define RCC_CR_HSERDY_Msk                    (0x1U << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
11836 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
11837 #define RCC_CR_HSEBYP_Pos                    (18U)
11838 #define RCC_CR_HSEBYP_Msk                    (0x1U << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
11839 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed oscillator (HSE) clock bypass */
11840 #define RCC_CR_CSSON_Pos                     (19U)
11841 #define RCC_CR_CSSON_Msk                     (0x1U << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
11842 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
11843 
11844 #define RCC_CR_PLLON_Pos                     (24U)
11845 #define RCC_CR_PLLON_Msk                     (0x1U << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
11846 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
11847 #define RCC_CR_PLLRDY_Pos                    (25U)
11848 #define RCC_CR_PLLRDY_Msk                    (0x1U << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
11849 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
11850 #define RCC_CR_PLLSAI1ON_Pos                 (26U)
11851 #define RCC_CR_PLLSAI1ON_Msk                 (0x1U << RCC_CR_PLLSAI1ON_Pos)    /*!< 0x04000000 */
11852 #define RCC_CR_PLLSAI1ON                     RCC_CR_PLLSAI1ON_Msk              /*!< SAI1 PLL enable */
11853 #define RCC_CR_PLLSAI1RDY_Pos                (27U)
11854 #define RCC_CR_PLLSAI1RDY_Msk                (0x1U << RCC_CR_PLLSAI1RDY_Pos)   /*!< 0x08000000 */
11855 #define RCC_CR_PLLSAI1RDY                    RCC_CR_PLLSAI1RDY_Msk             /*!< SAI1 PLL ready */
11856 #define RCC_CR_PLLSAI2ON_Pos                 (28U)
11857 #define RCC_CR_PLLSAI2ON_Msk                 (0x1U << RCC_CR_PLLSAI2ON_Pos)    /*!< 0x10000000 */
11858 #define RCC_CR_PLLSAI2ON                     RCC_CR_PLLSAI2ON_Msk              /*!< SAI2 PLL enable */
11859 #define RCC_CR_PLLSAI2RDY_Pos                (29U)
11860 #define RCC_CR_PLLSAI2RDY_Msk                (0x1U << RCC_CR_PLLSAI2RDY_Pos)   /*!< 0x20000000 */
11861 #define RCC_CR_PLLSAI2RDY                    RCC_CR_PLLSAI2RDY_Msk             /*!< SAI2 PLL ready */
11862 
11863 /********************  Bit definition for RCC_ICSCR register  ***************/
11864 /*!< MSICAL configuration */
11865 #define RCC_ICSCR_MSICAL_Pos                 (0U)
11866 #define RCC_ICSCR_MSICAL_Msk                 (0xFFU << RCC_ICSCR_MSICAL_Pos)   /*!< 0x000000FF */
11867 #define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
11868 #define RCC_ICSCR_MSICAL_0                   (0x01U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000001 */
11869 #define RCC_ICSCR_MSICAL_1                   (0x02U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000002 */
11870 #define RCC_ICSCR_MSICAL_2                   (0x04U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000004 */
11871 #define RCC_ICSCR_MSICAL_3                   (0x08U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000008 */
11872 #define RCC_ICSCR_MSICAL_4                   (0x10U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000010 */
11873 #define RCC_ICSCR_MSICAL_5                   (0x20U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000020 */
11874 #define RCC_ICSCR_MSICAL_6                   (0x40U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000040 */
11875 #define RCC_ICSCR_MSICAL_7                   (0x80U << RCC_ICSCR_MSICAL_Pos)   /*!< 0x00000080 */
11876 
11877 /*!< MSITRIM configuration */
11878 #define RCC_ICSCR_MSITRIM_Pos                (8U)
11879 #define RCC_ICSCR_MSITRIM_Msk                (0xFFU << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x0000FF00 */
11880 #define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
11881 #define RCC_ICSCR_MSITRIM_0                  (0x01U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000100 */
11882 #define RCC_ICSCR_MSITRIM_1                  (0x02U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000200 */
11883 #define RCC_ICSCR_MSITRIM_2                  (0x04U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000400 */
11884 #define RCC_ICSCR_MSITRIM_3                  (0x08U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00000800 */
11885 #define RCC_ICSCR_MSITRIM_4                  (0x10U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00001000 */
11886 #define RCC_ICSCR_MSITRIM_5                  (0x20U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00002000 */
11887 #define RCC_ICSCR_MSITRIM_6                  (0x40U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00004000 */
11888 #define RCC_ICSCR_MSITRIM_7                  (0x80U << RCC_ICSCR_MSITRIM_Pos)  /*!< 0x00008000 */
11889 
11890 /*!< HSICAL configuration */
11891 #define RCC_ICSCR_HSICAL_Pos                 (16U)
11892 #define RCC_ICSCR_HSICAL_Msk                 (0xFFU << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00FF0000 */
11893 #define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
11894 #define RCC_ICSCR_HSICAL_0                   (0x01U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00010000 */
11895 #define RCC_ICSCR_HSICAL_1                   (0x02U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00020000 */
11896 #define RCC_ICSCR_HSICAL_2                   (0x04U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00040000 */
11897 #define RCC_ICSCR_HSICAL_3                   (0x08U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00080000 */
11898 #define RCC_ICSCR_HSICAL_4                   (0x10U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00100000 */
11899 #define RCC_ICSCR_HSICAL_5                   (0x20U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00200000 */
11900 #define RCC_ICSCR_HSICAL_6                   (0x40U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00400000 */
11901 #define RCC_ICSCR_HSICAL_7                   (0x80U << RCC_ICSCR_HSICAL_Pos)   /*!< 0x00800000 */
11902 
11903 /*!< HSITRIM configuration */
11904 #define RCC_ICSCR_HSITRIM_Pos                (24U)
11905 #define RCC_ICSCR_HSITRIM_Msk                (0x7FU << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x7F000000 */
11906 #define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
11907 #define RCC_ICSCR_HSITRIM_0                  (0x01U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x01000000 */
11908 #define RCC_ICSCR_HSITRIM_1                  (0x02U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x02000000 */
11909 #define RCC_ICSCR_HSITRIM_2                  (0x04U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x04000000 */
11910 #define RCC_ICSCR_HSITRIM_3                  (0x08U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x08000000 */
11911 #define RCC_ICSCR_HSITRIM_4                  (0x10U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x10000000 */
11912 #define RCC_ICSCR_HSITRIM_5                  (0x20U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x20000000 */
11913 #define RCC_ICSCR_HSITRIM_6                  (0x40U << RCC_ICSCR_HSITRIM_Pos)  /*!< 0x40000000 */
11914 
11915 /********************  Bit definition for RCC_CFGR register  ******************/
11916 /*!< SW configuration */
11917 #define RCC_CFGR_SW_Pos                      (0U)
11918 #define RCC_CFGR_SW_Msk                      (0x3U << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
11919 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
11920 #define RCC_CFGR_SW_0                        (0x1U << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
11921 #define RCC_CFGR_SW_1                        (0x2U << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
11922 
11923 #define RCC_CFGR_SW_MSI                      (0x00000000U)                     /*!< MSI oscillator selection as system clock */
11924 #define RCC_CFGR_SW_HSI                      (0x00000001U)                     /*!< HSI16 oscillator selection as system clock */
11925 #define RCC_CFGR_SW_HSE                      (0x00000002U)                     /*!< HSE oscillator selection as system clock */
11926 #define RCC_CFGR_SW_PLL                      (0x00000003U)                     /*!< PLL selection as system clock */
11927 
11928 /*!< SWS configuration */
11929 #define RCC_CFGR_SWS_Pos                     (2U)
11930 #define RCC_CFGR_SWS_Msk                     (0x3U << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
11931 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
11932 #define RCC_CFGR_SWS_0                       (0x1U << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
11933 #define RCC_CFGR_SWS_1                       (0x2U << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
11934 
11935 #define RCC_CFGR_SWS_MSI                     (0x00000000U)                     /*!< MSI oscillator used as system clock */
11936 #define RCC_CFGR_SWS_HSI                     (0x00000004U)                     /*!< HSI16 oscillator used as system clock */
11937 #define RCC_CFGR_SWS_HSE                     (0x00000008U)                     /*!< HSE oscillator used as system clock */
11938 #define RCC_CFGR_SWS_PLL                     (0x0000000CU)                     /*!< PLL used as system clock */
11939 
11940 /*!< HPRE configuration */
11941 #define RCC_CFGR_HPRE_Pos                    (4U)
11942 #define RCC_CFGR_HPRE_Msk                    (0xFU << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
11943 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
11944 #define RCC_CFGR_HPRE_0                      (0x1U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
11945 #define RCC_CFGR_HPRE_1                      (0x2U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
11946 #define RCC_CFGR_HPRE_2                      (0x4U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
11947 #define RCC_CFGR_HPRE_3                      (0x8U << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
11948 
11949 #define RCC_CFGR_HPRE_DIV1                   (0x00000000U)                     /*!< SYSCLK not divided */
11950 #define RCC_CFGR_HPRE_DIV2                   (0x00000080U)                     /*!< SYSCLK divided by 2 */
11951 #define RCC_CFGR_HPRE_DIV4                   (0x00000090U)                     /*!< SYSCLK divided by 4 */
11952 #define RCC_CFGR_HPRE_DIV8                   (0x000000A0U)                     /*!< SYSCLK divided by 8 */
11953 #define RCC_CFGR_HPRE_DIV16                  (0x000000B0U)                     /*!< SYSCLK divided by 16 */
11954 #define RCC_CFGR_HPRE_DIV64                  (0x000000C0U)                     /*!< SYSCLK divided by 64 */
11955 #define RCC_CFGR_HPRE_DIV128                 (0x000000D0U)                     /*!< SYSCLK divided by 128 */
11956 #define RCC_CFGR_HPRE_DIV256                 (0x000000E0U)                     /*!< SYSCLK divided by 256 */
11957 #define RCC_CFGR_HPRE_DIV512                 (0x000000F0U)                     /*!< SYSCLK divided by 512 */
11958 
11959 /*!< PPRE1 configuration */
11960 #define RCC_CFGR_PPRE1_Pos                   (8U)
11961 #define RCC_CFGR_PPRE1_Msk                   (0x7U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
11962 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB2 prescaler) */
11963 #define RCC_CFGR_PPRE1_0                     (0x1U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
11964 #define RCC_CFGR_PPRE1_1                     (0x2U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
11965 #define RCC_CFGR_PPRE1_2                     (0x4U << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
11966 
11967 #define RCC_CFGR_PPRE1_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
11968 #define RCC_CFGR_PPRE1_DIV2                  (0x00000400U)                     /*!< HCLK divided by 2 */
11969 #define RCC_CFGR_PPRE1_DIV4                  (0x00000500U)                     /*!< HCLK divided by 4 */
11970 #define RCC_CFGR_PPRE1_DIV8                  (0x00000600U)                     /*!< HCLK divided by 8 */
11971 #define RCC_CFGR_PPRE1_DIV16                 (0x00000700U)                     /*!< HCLK divided by 16 */
11972 
11973 /*!< PPRE2 configuration */
11974 #define RCC_CFGR_PPRE2_Pos                   (11U)
11975 #define RCC_CFGR_PPRE2_Msk                   (0x7U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
11976 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
11977 #define RCC_CFGR_PPRE2_0                     (0x1U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
11978 #define RCC_CFGR_PPRE2_1                     (0x2U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
11979 #define RCC_CFGR_PPRE2_2                     (0x4U << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
11980 
11981 #define RCC_CFGR_PPRE2_DIV1                  (0x00000000U)                     /*!< HCLK not divided */
11982 #define RCC_CFGR_PPRE2_DIV2                  (0x00002000U)                     /*!< HCLK divided by 2 */
11983 #define RCC_CFGR_PPRE2_DIV4                  (0x00002800U)                     /*!< HCLK divided by 4 */
11984 #define RCC_CFGR_PPRE2_DIV8                  (0x00003000U)                     /*!< HCLK divided by 8 */
11985 #define RCC_CFGR_PPRE2_DIV16                 (0x00003800U)                     /*!< HCLK divided by 16 */
11986 
11987 #define RCC_CFGR_STOPWUCK_Pos                (15U)
11988 #define RCC_CFGR_STOPWUCK_Msk                (0x1U << RCC_CFGR_STOPWUCK_Pos)   /*!< 0x00008000 */
11989 #define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
11990 
11991 /*!< MCOSEL configuration */
11992 #define RCC_CFGR_MCOSEL_Pos                  (24U)
11993 #define RCC_CFGR_MCOSEL_Msk                  (0xFU << RCC_CFGR_MCOSEL_Pos)     /*!< 0x0F000000 */
11994 #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
11995 #define RCC_CFGR_MCOSEL_0                    (0x1U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x01000000 */
11996 #define RCC_CFGR_MCOSEL_1                    (0x2U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x02000000 */
11997 #define RCC_CFGR_MCOSEL_2                    (0x4U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x04000000 */
11998 #define RCC_CFGR_MCOSEL_3                    (0x8U << RCC_CFGR_MCOSEL_Pos)     /*!< 0x08000000 */
11999 
12000 #define RCC_CFGR_MCOPRE_Pos                  (28U)
12001 #define RCC_CFGR_MCOPRE_Msk                  (0x7U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x70000000 */
12002 #define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
12003 #define RCC_CFGR_MCOPRE_0                    (0x1U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x10000000 */
12004 #define RCC_CFGR_MCOPRE_1                    (0x2U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x20000000 */
12005 #define RCC_CFGR_MCOPRE_2                    (0x4U << RCC_CFGR_MCOPRE_Pos)     /*!< 0x40000000 */
12006 
12007 #define RCC_CFGR_MCOPRE_DIV1                 (0x00000000U)                     /*!< MCO is divided by 1 */
12008 #define RCC_CFGR_MCOPRE_DIV2                 (0x10000000U)                     /*!< MCO is divided by 2 */
12009 #define RCC_CFGR_MCOPRE_DIV4                 (0x20000000U)                     /*!< MCO is divided by 4 */
12010 #define RCC_CFGR_MCOPRE_DIV8                 (0x30000000U)                     /*!< MCO is divided by 8 */
12011 #define RCC_CFGR_MCOPRE_DIV16                (0x40000000U)                     /*!< MCO is divided by 16 */
12012 
12013 /* Legacy aliases */
12014 #define RCC_CFGR_MCO_PRE                     RCC_CFGR_MCOPRE
12015 #define RCC_CFGR_MCO_PRE_1                   RCC_CFGR_MCOPRE_DIV1
12016 #define RCC_CFGR_MCO_PRE_2                   RCC_CFGR_MCOPRE_DIV2
12017 #define RCC_CFGR_MCO_PRE_4                   RCC_CFGR_MCOPRE_DIV4
12018 #define RCC_CFGR_MCO_PRE_8                   RCC_CFGR_MCOPRE_DIV8
12019 #define RCC_CFGR_MCO_PRE_16                  RCC_CFGR_MCOPRE_DIV16
12020 
12021 /********************  Bit definition for RCC_PLLCFGR register  ***************/
12022 #define RCC_PLLCFGR_PLLSRC_Pos               (0U)
12023 #define RCC_PLLCFGR_PLLSRC_Msk               (0x3U << RCC_PLLCFGR_PLLSRC_Pos)  /*!< 0x00000003 */
12024 #define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
12025 
12026 #define RCC_PLLCFGR_PLLSRC_MSI_Pos           (0U)
12027 #define RCC_PLLCFGR_PLLSRC_MSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_MSI_Pos) /*!< 0x00000001 */
12028 #define RCC_PLLCFGR_PLLSRC_MSI               RCC_PLLCFGR_PLLSRC_MSI_Msk        /*!< MSI oscillator source clock selected */
12029 #define RCC_PLLCFGR_PLLSRC_HSI_Pos           (1U)
12030 #define RCC_PLLCFGR_PLLSRC_HSI_Msk           (0x1U << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
12031 #define RCC_PLLCFGR_PLLSRC_HSI               RCC_PLLCFGR_PLLSRC_HSI_Msk        /*!< HSI16 oscillator source clock selected */
12032 #define RCC_PLLCFGR_PLLSRC_HSE_Pos           (0U)
12033 #define RCC_PLLCFGR_PLLSRC_HSE_Msk           (0x3U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
12034 #define RCC_PLLCFGR_PLLSRC_HSE               RCC_PLLCFGR_PLLSRC_HSE_Msk        /*!< HSE oscillator source clock selected */
12035 
12036 #define RCC_PLLCFGR_PLLM_Pos                 (4U)
12037 #define RCC_PLLCFGR_PLLM_Msk                 (0x7U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000070 */
12038 #define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
12039 #define RCC_PLLCFGR_PLLM_0                   (0x1U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000010 */
12040 #define RCC_PLLCFGR_PLLM_1                   (0x2U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000020 */
12041 #define RCC_PLLCFGR_PLLM_2                   (0x4U << RCC_PLLCFGR_PLLM_Pos)    /*!< 0x00000040 */
12042 
12043 #define RCC_PLLCFGR_PLLN_Pos                 (8U)
12044 #define RCC_PLLCFGR_PLLN_Msk                 (0x7FU << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00007F00 */
12045 #define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
12046 #define RCC_PLLCFGR_PLLN_0                   (0x01U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000100 */
12047 #define RCC_PLLCFGR_PLLN_1                   (0x02U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000200 */
12048 #define RCC_PLLCFGR_PLLN_2                   (0x04U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000400 */
12049 #define RCC_PLLCFGR_PLLN_3                   (0x08U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00000800 */
12050 #define RCC_PLLCFGR_PLLN_4                   (0x10U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00001000 */
12051 #define RCC_PLLCFGR_PLLN_5                   (0x20U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00002000 */
12052 #define RCC_PLLCFGR_PLLN_6                   (0x40U << RCC_PLLCFGR_PLLN_Pos)   /*!< 0x00004000 */
12053 
12054 #define RCC_PLLCFGR_PLLPEN_Pos               (16U)
12055 #define RCC_PLLCFGR_PLLPEN_Msk               (0x1U << RCC_PLLCFGR_PLLPEN_Pos)  /*!< 0x00010000 */
12056 #define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
12057 #define RCC_PLLCFGR_PLLP_Pos                 (17U)
12058 #define RCC_PLLCFGR_PLLP_Msk                 (0x1U << RCC_PLLCFGR_PLLP_Pos)    /*!< 0x00020000 */
12059 #define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
12060 #define RCC_PLLCFGR_PLLQEN_Pos               (20U)
12061 #define RCC_PLLCFGR_PLLQEN_Msk               (0x1U << RCC_PLLCFGR_PLLQEN_Pos)  /*!< 0x00100000 */
12062 #define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
12063 
12064 #define RCC_PLLCFGR_PLLQ_Pos                 (21U)
12065 #define RCC_PLLCFGR_PLLQ_Msk                 (0x3U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00600000 */
12066 #define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
12067 #define RCC_PLLCFGR_PLLQ_0                   (0x1U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00200000 */
12068 #define RCC_PLLCFGR_PLLQ_1                   (0x2U << RCC_PLLCFGR_PLLQ_Pos)    /*!< 0x00400000 */
12069 
12070 #define RCC_PLLCFGR_PLLREN_Pos               (24U)
12071 #define RCC_PLLCFGR_PLLREN_Msk               (0x1U << RCC_PLLCFGR_PLLREN_Pos)  /*!< 0x01000000 */
12072 #define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
12073 #define RCC_PLLCFGR_PLLR_Pos                 (25U)
12074 #define RCC_PLLCFGR_PLLR_Msk                 (0x3U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x06000000 */
12075 #define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
12076 #define RCC_PLLCFGR_PLLR_0                   (0x1U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x02000000 */
12077 #define RCC_PLLCFGR_PLLR_1                   (0x2U << RCC_PLLCFGR_PLLR_Pos)    /*!< 0x04000000 */
12078 
12079 #define RCC_PLLCFGR_PLLPDIV_Pos              (27U)
12080 #define RCC_PLLCFGR_PLLPDIV_Msk              (0x1FU << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0xF8000000 */
12081 #define RCC_PLLCFGR_PLLPDIV                  RCC_PLLCFGR_PLLPDIV_Msk
12082 #define RCC_PLLCFGR_PLLPDIV_0                (0x01U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x08000000 */
12083 #define RCC_PLLCFGR_PLLPDIV_1                (0x02U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x10000000 */
12084 #define RCC_PLLCFGR_PLLPDIV_2                (0x04U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x20000000 */
12085 #define RCC_PLLCFGR_PLLPDIV_3                (0x08U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x40000000 */
12086 #define RCC_PLLCFGR_PLLPDIV_4                (0x10U << RCC_PLLCFGR_PLLPDIV_Pos) /*!< 0x80000000 */
12087 
12088 /********************  Bit definition for RCC_PLLSAI1CFGR register  ************/
12089 #define RCC_PLLSAI1CFGR_PLLSAI1N_Pos         (8U)
12090 #define RCC_PLLSAI1CFGR_PLLSAI1N_Msk         (0x7FU << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00007F00 */
12091 #define RCC_PLLSAI1CFGR_PLLSAI1N             RCC_PLLSAI1CFGR_PLLSAI1N_Msk
12092 #define RCC_PLLSAI1CFGR_PLLSAI1N_0           (0x01U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000100 */
12093 #define RCC_PLLSAI1CFGR_PLLSAI1N_1           (0x02U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000200 */
12094 #define RCC_PLLSAI1CFGR_PLLSAI1N_2           (0x04U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000400 */
12095 #define RCC_PLLSAI1CFGR_PLLSAI1N_3           (0x08U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00000800 */
12096 #define RCC_PLLSAI1CFGR_PLLSAI1N_4           (0x10U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00001000 */
12097 #define RCC_PLLSAI1CFGR_PLLSAI1N_5           (0x20U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00002000 */
12098 #define RCC_PLLSAI1CFGR_PLLSAI1N_6           (0x40U << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /*!< 0x00004000 */
12099 
12100 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos       (16U)
12101 #define RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1PEN_Pos) /*!< 0x00010000 */
12102 #define RCC_PLLSAI1CFGR_PLLSAI1PEN           RCC_PLLSAI1CFGR_PLLSAI1PEN_Msk
12103 #define RCC_PLLSAI1CFGR_PLLSAI1P_Pos         (17U)
12104 #define RCC_PLLSAI1CFGR_PLLSAI1P_Msk         (0x1U << RCC_PLLSAI1CFGR_PLLSAI1P_Pos) /*!< 0x00020000 */
12105 #define RCC_PLLSAI1CFGR_PLLSAI1P             RCC_PLLSAI1CFGR_PLLSAI1P_Msk
12106 
12107 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos       (20U)
12108 #define RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1QEN_Pos) /*!< 0x00100000 */
12109 #define RCC_PLLSAI1CFGR_PLLSAI1QEN           RCC_PLLSAI1CFGR_PLLSAI1QEN_Msk
12110 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Pos         (21U)
12111 #define RCC_PLLSAI1CFGR_PLLSAI1Q_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00600000 */
12112 #define RCC_PLLSAI1CFGR_PLLSAI1Q             RCC_PLLSAI1CFGR_PLLSAI1Q_Msk
12113 #define RCC_PLLSAI1CFGR_PLLSAI1Q_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00200000 */
12114 #define RCC_PLLSAI1CFGR_PLLSAI1Q_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /*!< 0x00400000 */
12115 
12116 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Pos       (24U)
12117 #define RCC_PLLSAI1CFGR_PLLSAI1REN_Msk       (0x1U << RCC_PLLSAI1CFGR_PLLSAI1REN_Pos) /*!< 0x01000000 */
12118 #define RCC_PLLSAI1CFGR_PLLSAI1REN           RCC_PLLSAI1CFGR_PLLSAI1REN_Msk
12119 #define RCC_PLLSAI1CFGR_PLLSAI1R_Pos         (25U)
12120 #define RCC_PLLSAI1CFGR_PLLSAI1R_Msk         (0x3U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x06000000 */
12121 #define RCC_PLLSAI1CFGR_PLLSAI1R             RCC_PLLSAI1CFGR_PLLSAI1R_Msk
12122 #define RCC_PLLSAI1CFGR_PLLSAI1R_0           (0x1U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x02000000 */
12123 #define RCC_PLLSAI1CFGR_PLLSAI1R_1           (0x2U << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /*!< 0x04000000 */
12124 
12125 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos      (27U)
12126 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk      (0x1FU << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0xF8000000 */
12127 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV          RCC_PLLSAI1CFGR_PLLSAI1PDIV_Msk
12128 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_0        (0x01U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x08000000 */
12129 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_1        (0x02U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x10000000 */
12130 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_2        (0x04U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x20000000 */
12131 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_3        (0x08U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x40000000 */
12132 #define RCC_PLLSAI1CFGR_PLLSAI1PDIV_4        (0x10U << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /*!< 0x80000000 */
12133 
12134 /********************  Bit definition for RCC_PLLSAI2CFGR register  ************/
12135 #define RCC_PLLSAI2CFGR_PLLSAI2N_Pos         (8U)
12136 #define RCC_PLLSAI2CFGR_PLLSAI2N_Msk         (0x7FU << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00007F00 */
12137 #define RCC_PLLSAI2CFGR_PLLSAI2N             RCC_PLLSAI2CFGR_PLLSAI2N_Msk
12138 #define RCC_PLLSAI2CFGR_PLLSAI2N_0           (0x01U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000100 */
12139 #define RCC_PLLSAI2CFGR_PLLSAI2N_1           (0x02U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000200 */
12140 #define RCC_PLLSAI2CFGR_PLLSAI2N_2           (0x04U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000400 */
12141 #define RCC_PLLSAI2CFGR_PLLSAI2N_3           (0x08U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00000800 */
12142 #define RCC_PLLSAI2CFGR_PLLSAI2N_4           (0x10U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00001000 */
12143 #define RCC_PLLSAI2CFGR_PLLSAI2N_5           (0x20U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00002000 */
12144 #define RCC_PLLSAI2CFGR_PLLSAI2N_6           (0x40U << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /*!< 0x00004000 */
12145 
12146 #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos       (16U)
12147 #define RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2PEN_Pos) /*!< 0x00010000 */
12148 #define RCC_PLLSAI2CFGR_PLLSAI2PEN           RCC_PLLSAI2CFGR_PLLSAI2PEN_Msk
12149 #define RCC_PLLSAI2CFGR_PLLSAI2P_Pos         (17U)
12150 #define RCC_PLLSAI2CFGR_PLLSAI2P_Msk         (0x1U << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /*!< 0x00020000 */
12151 #define RCC_PLLSAI2CFGR_PLLSAI2P             RCC_PLLSAI2CFGR_PLLSAI2P_Msk
12152 
12153 #define RCC_PLLSAI2CFGR_PLLSAI2REN_Pos       (24U)
12154 #define RCC_PLLSAI2CFGR_PLLSAI2REN_Msk       (0x1U << RCC_PLLSAI2CFGR_PLLSAI2REN_Pos) /*!< 0x01000000 */
12155 #define RCC_PLLSAI2CFGR_PLLSAI2REN           RCC_PLLSAI2CFGR_PLLSAI2REN_Msk
12156 #define RCC_PLLSAI2CFGR_PLLSAI2R_Pos         (25U)
12157 #define RCC_PLLSAI2CFGR_PLLSAI2R_Msk         (0x3U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x06000000 */
12158 #define RCC_PLLSAI2CFGR_PLLSAI2R             RCC_PLLSAI2CFGR_PLLSAI2R_Msk
12159 #define RCC_PLLSAI2CFGR_PLLSAI2R_0           (0x1U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x02000000 */
12160 #define RCC_PLLSAI2CFGR_PLLSAI2R_1           (0x2U << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) /*!< 0x04000000 */
12161 
12162 #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos      (27U)
12163 #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk      (0x1FU << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0xF8000000 */
12164 #define RCC_PLLSAI2CFGR_PLLSAI2PDIV          RCC_PLLSAI2CFGR_PLLSAI2PDIV_Msk
12165 #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_0        (0x01U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x08000000 */
12166 #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_1        (0x02U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x10000000 */
12167 #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_2        (0x04U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x20000000 */
12168 #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_3        (0x08U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x40000000 */
12169 #define RCC_PLLSAI2CFGR_PLLSAI2PDIV_4        (0x10U << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos) /*!< 0x80000000 */
12170 
12171 /********************  Bit definition for RCC_CIER register  ******************/
12172 #define RCC_CIER_LSIRDYIE_Pos                (0U)
12173 #define RCC_CIER_LSIRDYIE_Msk                (0x1U << RCC_CIER_LSIRDYIE_Pos)   /*!< 0x00000001 */
12174 #define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
12175 #define RCC_CIER_LSERDYIE_Pos                (1U)
12176 #define RCC_CIER_LSERDYIE_Msk                (0x1U << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
12177 #define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
12178 #define RCC_CIER_MSIRDYIE_Pos                (2U)
12179 #define RCC_CIER_MSIRDYIE_Msk                (0x1U << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
12180 #define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk
12181 #define RCC_CIER_HSIRDYIE_Pos                (3U)
12182 #define RCC_CIER_HSIRDYIE_Msk                (0x1U << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
12183 #define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
12184 #define RCC_CIER_HSERDYIE_Pos                (4U)
12185 #define RCC_CIER_HSERDYIE_Msk                (0x1U << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
12186 #define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
12187 #define RCC_CIER_PLLRDYIE_Pos                (5U)
12188 #define RCC_CIER_PLLRDYIE_Msk                (0x1U << RCC_CIER_PLLRDYIE_Pos)   /*!< 0x00000020 */
12189 #define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
12190 #define RCC_CIER_PLLSAI1RDYIE_Pos            (6U)
12191 #define RCC_CIER_PLLSAI1RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI1RDYIE_Pos) /*!< 0x00000040 */
12192 #define RCC_CIER_PLLSAI1RDYIE                RCC_CIER_PLLSAI1RDYIE_Msk
12193 #define RCC_CIER_PLLSAI2RDYIE_Pos            (7U)
12194 #define RCC_CIER_PLLSAI2RDYIE_Msk            (0x1U << RCC_CIER_PLLSAI2RDYIE_Pos) /*!< 0x00000080 */
12195 #define RCC_CIER_PLLSAI2RDYIE                RCC_CIER_PLLSAI2RDYIE_Msk
12196 #define RCC_CIER_LSECSSIE_Pos                (9U)
12197 #define RCC_CIER_LSECSSIE_Msk                (0x1U << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
12198 #define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
12199 #define RCC_CIER_HSI48RDYIE_Pos              (10U)
12200 #define RCC_CIER_HSI48RDYIE_Msk              (0x1U << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000400 */
12201 #define RCC_CIER_HSI48RDYIE                  RCC_CIER_HSI48RDYIE_Msk
12202 
12203 /********************  Bit definition for RCC_CIFR register  ******************/
12204 #define RCC_CIFR_LSIRDYF_Pos                 (0U)
12205 #define RCC_CIFR_LSIRDYF_Msk                 (0x1U << RCC_CIFR_LSIRDYF_Pos)    /*!< 0x00000001 */
12206 #define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
12207 #define RCC_CIFR_LSERDYF_Pos                 (1U)
12208 #define RCC_CIFR_LSERDYF_Msk                 (0x1U << RCC_CIFR_LSERDYF_Pos)    /*!< 0x00000002 */
12209 #define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
12210 #define RCC_CIFR_MSIRDYF_Pos                 (2U)
12211 #define RCC_CIFR_MSIRDYF_Msk                 (0x1U << RCC_CIFR_MSIRDYF_Pos)    /*!< 0x00000004 */
12212 #define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk
12213 #define RCC_CIFR_HSIRDYF_Pos                 (3U)
12214 #define RCC_CIFR_HSIRDYF_Msk                 (0x1U << RCC_CIFR_HSIRDYF_Pos)    /*!< 0x00000008 */
12215 #define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
12216 #define RCC_CIFR_HSERDYF_Pos                 (4U)
12217 #define RCC_CIFR_HSERDYF_Msk                 (0x1U << RCC_CIFR_HSERDYF_Pos)    /*!< 0x00000010 */
12218 #define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
12219 #define RCC_CIFR_PLLRDYF_Pos                 (5U)
12220 #define RCC_CIFR_PLLRDYF_Msk                 (0x1U << RCC_CIFR_PLLRDYF_Pos)    /*!< 0x00000020 */
12221 #define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
12222 #define RCC_CIFR_PLLSAI1RDYF_Pos             (6U)
12223 #define RCC_CIFR_PLLSAI1RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI1RDYF_Pos) /*!< 0x00000040 */
12224 #define RCC_CIFR_PLLSAI1RDYF                 RCC_CIFR_PLLSAI1RDYF_Msk
12225 #define RCC_CIFR_PLLSAI2RDYF_Pos             (7U)
12226 #define RCC_CIFR_PLLSAI2RDYF_Msk             (0x1U << RCC_CIFR_PLLSAI2RDYF_Pos) /*!< 0x00000080 */
12227 #define RCC_CIFR_PLLSAI2RDYF                 RCC_CIFR_PLLSAI2RDYF_Msk
12228 #define RCC_CIFR_CSSF_Pos                    (8U)
12229 #define RCC_CIFR_CSSF_Msk                    (0x1U << RCC_CIFR_CSSF_Pos)       /*!< 0x00000100 */
12230 #define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
12231 #define RCC_CIFR_LSECSSF_Pos                 (9U)
12232 #define RCC_CIFR_LSECSSF_Msk                 (0x1U << RCC_CIFR_LSECSSF_Pos)    /*!< 0x00000200 */
12233 #define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
12234 #define RCC_CIFR_HSI48RDYF_Pos               (10U)
12235 #define RCC_CIFR_HSI48RDYF_Msk               (0x1U << RCC_CIFR_HSI48RDYF_Pos)  /*!< 0x00000400 */
12236 #define RCC_CIFR_HSI48RDYF                   RCC_CIFR_HSI48RDYF_Msk
12237 
12238 /********************  Bit definition for RCC_CICR register  ******************/
12239 #define RCC_CICR_LSIRDYC_Pos                 (0U)
12240 #define RCC_CICR_LSIRDYC_Msk                 (0x1U << RCC_CICR_LSIRDYC_Pos)    /*!< 0x00000001 */
12241 #define RCC_CICR_LSIRDYC                     RCC_CICR_LSIRDYC_Msk
12242 #define RCC_CICR_LSERDYC_Pos                 (1U)
12243 #define RCC_CICR_LSERDYC_Msk                 (0x1U << RCC_CICR_LSERDYC_Pos)    /*!< 0x00000002 */
12244 #define RCC_CICR_LSERDYC                     RCC_CICR_LSERDYC_Msk
12245 #define RCC_CICR_MSIRDYC_Pos                 (2U)
12246 #define RCC_CICR_MSIRDYC_Msk                 (0x1U << RCC_CICR_MSIRDYC_Pos)    /*!< 0x00000004 */
12247 #define RCC_CICR_MSIRDYC                     RCC_CICR_MSIRDYC_Msk
12248 #define RCC_CICR_HSIRDYC_Pos                 (3U)
12249 #define RCC_CICR_HSIRDYC_Msk                 (0x1U << RCC_CICR_HSIRDYC_Pos)    /*!< 0x00000008 */
12250 #define RCC_CICR_HSIRDYC                     RCC_CICR_HSIRDYC_Msk
12251 #define RCC_CICR_HSERDYC_Pos                 (4U)
12252 #define RCC_CICR_HSERDYC_Msk                 (0x1U << RCC_CICR_HSERDYC_Pos)    /*!< 0x00000010 */
12253 #define RCC_CICR_HSERDYC                     RCC_CICR_HSERDYC_Msk
12254 #define RCC_CICR_PLLRDYC_Pos                 (5U)
12255 #define RCC_CICR_PLLRDYC_Msk                 (0x1U << RCC_CICR_PLLRDYC_Pos)    /*!< 0x00000020 */
12256 #define RCC_CICR_PLLRDYC                     RCC_CICR_PLLRDYC_Msk
12257 #define RCC_CICR_PLLSAI1RDYC_Pos             (6U)
12258 #define RCC_CICR_PLLSAI1RDYC_Msk             (0x1U << RCC_CICR_PLLSAI1RDYC_Pos) /*!< 0x00000040 */
12259 #define RCC_CICR_PLLSAI1RDYC                 RCC_CICR_PLLSAI1RDYC_Msk
12260 #define RCC_CICR_PLLSAI2RDYC_Pos             (7U)
12261 #define RCC_CICR_PLLSAI2RDYC_Msk             (0x1U << RCC_CICR_PLLSAI2RDYC_Pos) /*!< 0x00000080 */
12262 #define RCC_CICR_PLLSAI2RDYC                 RCC_CICR_PLLSAI2RDYC_Msk
12263 #define RCC_CICR_CSSC_Pos                    (8U)
12264 #define RCC_CICR_CSSC_Msk                    (0x1U << RCC_CICR_CSSC_Pos)       /*!< 0x00000100 */
12265 #define RCC_CICR_CSSC                        RCC_CICR_CSSC_Msk
12266 #define RCC_CICR_LSECSSC_Pos                 (9U)
12267 #define RCC_CICR_LSECSSC_Msk                 (0x1U << RCC_CICR_LSECSSC_Pos)    /*!< 0x00000200 */
12268 #define RCC_CICR_LSECSSC                     RCC_CICR_LSECSSC_Msk
12269 #define RCC_CICR_HSI48RDYC_Pos               (10U)
12270 #define RCC_CICR_HSI48RDYC_Msk               (0x1U << RCC_CICR_HSI48RDYC_Pos)  /*!< 0x00000400 */
12271 #define RCC_CICR_HSI48RDYC                   RCC_CICR_HSI48RDYC_Msk
12272 
12273 /********************  Bit definition for RCC_AHB1RSTR register  **************/
12274 #define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
12275 #define RCC_AHB1RSTR_DMA1RST_Msk             (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
12276 #define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
12277 #define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
12278 #define RCC_AHB1RSTR_DMA2RST_Msk             (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
12279 #define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
12280 #define RCC_AHB1RSTR_FLASHRST_Pos            (8U)
12281 #define RCC_AHB1RSTR_FLASHRST_Msk            (0x1U << RCC_AHB1RSTR_FLASHRST_Pos) /*!< 0x00000100 */
12282 #define RCC_AHB1RSTR_FLASHRST                RCC_AHB1RSTR_FLASHRST_Msk
12283 #define RCC_AHB1RSTR_CRCRST_Pos              (12U)
12284 #define RCC_AHB1RSTR_CRCRST_Msk              (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
12285 #define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
12286 #define RCC_AHB1RSTR_TSCRST_Pos              (16U)
12287 #define RCC_AHB1RSTR_TSCRST_Msk              (0x1U << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */
12288 #define RCC_AHB1RSTR_TSCRST                  RCC_AHB1RSTR_TSCRST_Msk
12289 #define RCC_AHB1RSTR_DMA2DRST_Pos            (17U)
12290 #define RCC_AHB1RSTR_DMA2DRST_Msk            (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00020000 */
12291 #define RCC_AHB1RSTR_DMA2DRST                RCC_AHB1RSTR_DMA2DRST_Msk
12292 
12293 /********************  Bit definition for RCC_AHB2RSTR register  **************/
12294 #define RCC_AHB2RSTR_GPIOARST_Pos            (0U)
12295 #define RCC_AHB2RSTR_GPIOARST_Msk            (0x1U << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */
12296 #define RCC_AHB2RSTR_GPIOARST                RCC_AHB2RSTR_GPIOARST_Msk
12297 #define RCC_AHB2RSTR_GPIOBRST_Pos            (1U)
12298 #define RCC_AHB2RSTR_GPIOBRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
12299 #define RCC_AHB2RSTR_GPIOBRST                RCC_AHB2RSTR_GPIOBRST_Msk
12300 #define RCC_AHB2RSTR_GPIOCRST_Pos            (2U)
12301 #define RCC_AHB2RSTR_GPIOCRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
12302 #define RCC_AHB2RSTR_GPIOCRST                RCC_AHB2RSTR_GPIOCRST_Msk
12303 #define RCC_AHB2RSTR_GPIODRST_Pos            (3U)
12304 #define RCC_AHB2RSTR_GPIODRST_Msk            (0x1U << RCC_AHB2RSTR_GPIODRST_Pos) /*!< 0x00000008 */
12305 #define RCC_AHB2RSTR_GPIODRST                RCC_AHB2RSTR_GPIODRST_Msk
12306 #define RCC_AHB2RSTR_GPIOERST_Pos            (4U)
12307 #define RCC_AHB2RSTR_GPIOERST_Msk            (0x1U << RCC_AHB2RSTR_GPIOERST_Pos) /*!< 0x00000010 */
12308 #define RCC_AHB2RSTR_GPIOERST                RCC_AHB2RSTR_GPIOERST_Msk
12309 #define RCC_AHB2RSTR_GPIOFRST_Pos            (5U)
12310 #define RCC_AHB2RSTR_GPIOFRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
12311 #define RCC_AHB2RSTR_GPIOFRST                RCC_AHB2RSTR_GPIOFRST_Msk
12312 #define RCC_AHB2RSTR_GPIOGRST_Pos            (6U)
12313 #define RCC_AHB2RSTR_GPIOGRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
12314 #define RCC_AHB2RSTR_GPIOGRST                RCC_AHB2RSTR_GPIOGRST_Msk
12315 #define RCC_AHB2RSTR_GPIOHRST_Pos            (7U)
12316 #define RCC_AHB2RSTR_GPIOHRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
12317 #define RCC_AHB2RSTR_GPIOHRST                RCC_AHB2RSTR_GPIOHRST_Msk
12318 #define RCC_AHB2RSTR_GPIOIRST_Pos            (8U)
12319 #define RCC_AHB2RSTR_GPIOIRST_Msk            (0x1U << RCC_AHB2RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
12320 #define RCC_AHB2RSTR_GPIOIRST                RCC_AHB2RSTR_GPIOIRST_Msk
12321 #define RCC_AHB2RSTR_OTGFSRST_Pos            (12U)
12322 #define RCC_AHB2RSTR_OTGFSRST_Msk            (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00001000 */
12323 #define RCC_AHB2RSTR_OTGFSRST                RCC_AHB2RSTR_OTGFSRST_Msk
12324 #define RCC_AHB2RSTR_ADCRST_Pos              (13U)
12325 #define RCC_AHB2RSTR_ADCRST_Msk              (0x1U << RCC_AHB2RSTR_ADCRST_Pos) /*!< 0x00002000 */
12326 #define RCC_AHB2RSTR_ADCRST                  RCC_AHB2RSTR_ADCRST_Msk
12327 #define RCC_AHB2RSTR_DCMIRST_Pos             (14U)
12328 #define RCC_AHB2RSTR_DCMIRST_Msk             (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00004000 */
12329 #define RCC_AHB2RSTR_DCMIRST                 RCC_AHB2RSTR_DCMIRST_Msk
12330 #define RCC_AHB2RSTR_AESRST_Pos              (16U)
12331 #define RCC_AHB2RSTR_AESRST_Msk              (0x1U << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */
12332 #define RCC_AHB2RSTR_AESRST                  RCC_AHB2RSTR_AESRST_Msk
12333 #define RCC_AHB2RSTR_HASHRST_Pos             (17U)
12334 #define RCC_AHB2RSTR_HASHRST_Msk             (0x1U << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */
12335 #define RCC_AHB2RSTR_HASHRST                 RCC_AHB2RSTR_HASHRST_Msk
12336 #define RCC_AHB2RSTR_RNGRST_Pos              (18U)
12337 #define RCC_AHB2RSTR_RNGRST_Msk              (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */
12338 #define RCC_AHB2RSTR_RNGRST                  RCC_AHB2RSTR_RNGRST_Msk
12339 
12340 /********************  Bit definition for RCC_AHB3RSTR register  **************/
12341 #define RCC_AHB3RSTR_FMCRST_Pos              (0U)
12342 #define RCC_AHB3RSTR_FMCRST_Msk              (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
12343 #define RCC_AHB3RSTR_FMCRST                  RCC_AHB3RSTR_FMCRST_Msk
12344 #define RCC_AHB3RSTR_QSPIRST_Pos             (8U)
12345 #define RCC_AHB3RSTR_QSPIRST_Msk             (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000100 */
12346 #define RCC_AHB3RSTR_QSPIRST                 RCC_AHB3RSTR_QSPIRST_Msk
12347 
12348 /********************  Bit definition for RCC_APB1RSTR1 register  **************/
12349 #define RCC_APB1RSTR1_TIM2RST_Pos            (0U)
12350 #define RCC_APB1RSTR1_TIM2RST_Msk            (0x1U << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
12351 #define RCC_APB1RSTR1_TIM2RST                RCC_APB1RSTR1_TIM2RST_Msk
12352 #define RCC_APB1RSTR1_TIM3RST_Pos            (1U)
12353 #define RCC_APB1RSTR1_TIM3RST_Msk            (0x1U << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
12354 #define RCC_APB1RSTR1_TIM3RST                RCC_APB1RSTR1_TIM3RST_Msk
12355 #define RCC_APB1RSTR1_TIM4RST_Pos            (2U)
12356 #define RCC_APB1RSTR1_TIM4RST_Msk            (0x1U << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
12357 #define RCC_APB1RSTR1_TIM4RST                RCC_APB1RSTR1_TIM4RST_Msk
12358 #define RCC_APB1RSTR1_TIM5RST_Pos            (3U)
12359 #define RCC_APB1RSTR1_TIM5RST_Msk            (0x1U << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
12360 #define RCC_APB1RSTR1_TIM5RST                RCC_APB1RSTR1_TIM5RST_Msk
12361 #define RCC_APB1RSTR1_TIM6RST_Pos            (4U)
12362 #define RCC_APB1RSTR1_TIM6RST_Msk            (0x1U << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
12363 #define RCC_APB1RSTR1_TIM6RST                RCC_APB1RSTR1_TIM6RST_Msk
12364 #define RCC_APB1RSTR1_TIM7RST_Pos            (5U)
12365 #define RCC_APB1RSTR1_TIM7RST_Msk            (0x1U << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
12366 #define RCC_APB1RSTR1_TIM7RST                RCC_APB1RSTR1_TIM7RST_Msk
12367 #define RCC_APB1RSTR1_LCDRST_Pos             (9U)
12368 #define RCC_APB1RSTR1_LCDRST_Msk             (0x1U << RCC_APB1RSTR1_LCDRST_Pos) /*!< 0x00000200 */
12369 #define RCC_APB1RSTR1_LCDRST                 RCC_APB1RSTR1_LCDRST_Msk
12370 #define RCC_APB1RSTR1_SPI2RST_Pos            (14U)
12371 #define RCC_APB1RSTR1_SPI2RST_Msk            (0x1U << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
12372 #define RCC_APB1RSTR1_SPI2RST                RCC_APB1RSTR1_SPI2RST_Msk
12373 #define RCC_APB1RSTR1_SPI3RST_Pos            (15U)
12374 #define RCC_APB1RSTR1_SPI3RST_Msk            (0x1U << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
12375 #define RCC_APB1RSTR1_SPI3RST                RCC_APB1RSTR1_SPI3RST_Msk
12376 #define RCC_APB1RSTR1_USART2RST_Pos          (17U)
12377 #define RCC_APB1RSTR1_USART2RST_Msk          (0x1U << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */
12378 #define RCC_APB1RSTR1_USART2RST              RCC_APB1RSTR1_USART2RST_Msk
12379 #define RCC_APB1RSTR1_USART3RST_Pos          (18U)
12380 #define RCC_APB1RSTR1_USART3RST_Msk          (0x1U << RCC_APB1RSTR1_USART3RST_Pos) /*!< 0x00040000 */
12381 #define RCC_APB1RSTR1_USART3RST              RCC_APB1RSTR1_USART3RST_Msk
12382 #define RCC_APB1RSTR1_UART4RST_Pos           (19U)
12383 #define RCC_APB1RSTR1_UART4RST_Msk           (0x1U << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
12384 #define RCC_APB1RSTR1_UART4RST               RCC_APB1RSTR1_UART4RST_Msk
12385 #define RCC_APB1RSTR1_UART5RST_Pos           (20U)
12386 #define RCC_APB1RSTR1_UART5RST_Msk           (0x1U << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
12387 #define RCC_APB1RSTR1_UART5RST               RCC_APB1RSTR1_UART5RST_Msk
12388 #define RCC_APB1RSTR1_I2C1RST_Pos            (21U)
12389 #define RCC_APB1RSTR1_I2C1RST_Msk            (0x1U << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
12390 #define RCC_APB1RSTR1_I2C1RST                RCC_APB1RSTR1_I2C1RST_Msk
12391 #define RCC_APB1RSTR1_I2C2RST_Pos            (22U)
12392 #define RCC_APB1RSTR1_I2C2RST_Msk            (0x1U << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
12393 #define RCC_APB1RSTR1_I2C2RST                RCC_APB1RSTR1_I2C2RST_Msk
12394 #define RCC_APB1RSTR1_I2C3RST_Pos            (23U)
12395 #define RCC_APB1RSTR1_I2C3RST_Msk            (0x1U << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
12396 #define RCC_APB1RSTR1_I2C3RST                RCC_APB1RSTR1_I2C3RST_Msk
12397 #define RCC_APB1RSTR1_CRSRST_Pos             (24U)
12398 #define RCC_APB1RSTR1_CRSRST_Msk             (0x1U << RCC_APB1RSTR1_CRSRST_Pos) /*!< 0x01000000 */
12399 #define RCC_APB1RSTR1_CRSRST                 RCC_APB1RSTR1_CRSRST_Msk
12400 #define RCC_APB1RSTR1_CAN1RST_Pos            (25U)
12401 #define RCC_APB1RSTR1_CAN1RST_Msk            (0x1U << RCC_APB1RSTR1_CAN1RST_Pos) /*!< 0x02000000 */
12402 #define RCC_APB1RSTR1_CAN1RST                RCC_APB1RSTR1_CAN1RST_Msk
12403 #define RCC_APB1RSTR1_CAN2RST_Pos            (26U)
12404 #define RCC_APB1RSTR1_CAN2RST_Msk            (0x1U << RCC_APB1RSTR1_CAN2RST_Pos) /*!< 0x04000000 */
12405 #define RCC_APB1RSTR1_CAN2RST                RCC_APB1RSTR1_CAN2RST_Msk
12406 #define RCC_APB1RSTR1_PWRRST_Pos             (28U)
12407 #define RCC_APB1RSTR1_PWRRST_Msk             (0x1U << RCC_APB1RSTR1_PWRRST_Pos) /*!< 0x10000000 */
12408 #define RCC_APB1RSTR1_PWRRST                 RCC_APB1RSTR1_PWRRST_Msk
12409 #define RCC_APB1RSTR1_DAC1RST_Pos            (29U)
12410 #define RCC_APB1RSTR1_DAC1RST_Msk            (0x1U << RCC_APB1RSTR1_DAC1RST_Pos) /*!< 0x20000000 */
12411 #define RCC_APB1RSTR1_DAC1RST                RCC_APB1RSTR1_DAC1RST_Msk
12412 #define RCC_APB1RSTR1_OPAMPRST_Pos           (30U)
12413 #define RCC_APB1RSTR1_OPAMPRST_Msk           (0x1U << RCC_APB1RSTR1_OPAMPRST_Pos) /*!< 0x40000000 */
12414 #define RCC_APB1RSTR1_OPAMPRST               RCC_APB1RSTR1_OPAMPRST_Msk
12415 #define RCC_APB1RSTR1_LPTIM1RST_Pos          (31U)
12416 #define RCC_APB1RSTR1_LPTIM1RST_Msk          (0x1U << RCC_APB1RSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
12417 #define RCC_APB1RSTR1_LPTIM1RST              RCC_APB1RSTR1_LPTIM1RST_Msk
12418 
12419 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
12420 #define RCC_APB1RSTR2_LPUART1RST_Pos         (0U)
12421 #define RCC_APB1RSTR2_LPUART1RST_Msk         (0x1U << RCC_APB1RSTR2_LPUART1RST_Pos) /*!< 0x00000001 */
12422 #define RCC_APB1RSTR2_LPUART1RST             RCC_APB1RSTR2_LPUART1RST_Msk
12423 #define RCC_APB1RSTR2_I2C4RST_Pos            (1U)
12424 #define RCC_APB1RSTR2_I2C4RST_Msk            (0x1U << RCC_APB1RSTR2_I2C4RST_Pos) /*!< 0x00000002 */
12425 #define RCC_APB1RSTR2_I2C4RST                RCC_APB1RSTR2_I2C4RST_Msk
12426 #define RCC_APB1RSTR2_SWPMI1RST_Pos          (2U)
12427 #define RCC_APB1RSTR2_SWPMI1RST_Msk          (0x1U << RCC_APB1RSTR2_SWPMI1RST_Pos) /*!< 0x00000004 */
12428 #define RCC_APB1RSTR2_SWPMI1RST              RCC_APB1RSTR2_SWPMI1RST_Msk
12429 #define RCC_APB1RSTR2_LPTIM2RST_Pos          (5U)
12430 #define RCC_APB1RSTR2_LPTIM2RST_Msk          (0x1U << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */
12431 #define RCC_APB1RSTR2_LPTIM2RST              RCC_APB1RSTR2_LPTIM2RST_Msk
12432 
12433 /********************  Bit definition for RCC_APB2RSTR register  **************/
12434 #define RCC_APB2RSTR_SYSCFGRST_Pos           (0U)
12435 #define RCC_APB2RSTR_SYSCFGRST_Msk           (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
12436 #define RCC_APB2RSTR_SYSCFGRST               RCC_APB2RSTR_SYSCFGRST_Msk
12437 #define RCC_APB2RSTR_SDMMC1RST_Pos           (10U)
12438 #define RCC_APB2RSTR_SDMMC1RST_Msk           (0x1U << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000400 */
12439 #define RCC_APB2RSTR_SDMMC1RST               RCC_APB2RSTR_SDMMC1RST_Msk
12440 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
12441 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
12442 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk
12443 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
12444 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
12445 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk
12446 #define RCC_APB2RSTR_TIM8RST_Pos             (13U)
12447 #define RCC_APB2RSTR_TIM8RST_Msk             (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */
12448 #define RCC_APB2RSTR_TIM8RST                 RCC_APB2RSTR_TIM8RST_Msk
12449 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
12450 #define RCC_APB2RSTR_USART1RST_Msk           (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
12451 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk
12452 #define RCC_APB2RSTR_TIM15RST_Pos            (16U)
12453 #define RCC_APB2RSTR_TIM15RST_Msk            (0x1U << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
12454 #define RCC_APB2RSTR_TIM15RST                RCC_APB2RSTR_TIM15RST_Msk
12455 #define RCC_APB2RSTR_TIM16RST_Pos            (17U)
12456 #define RCC_APB2RSTR_TIM16RST_Msk            (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
12457 #define RCC_APB2RSTR_TIM16RST                RCC_APB2RSTR_TIM16RST_Msk
12458 #define RCC_APB2RSTR_TIM17RST_Pos            (18U)
12459 #define RCC_APB2RSTR_TIM17RST_Msk            (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
12460 #define RCC_APB2RSTR_TIM17RST                RCC_APB2RSTR_TIM17RST_Msk
12461 #define RCC_APB2RSTR_SAI1RST_Pos             (21U)
12462 #define RCC_APB2RSTR_SAI1RST_Msk             (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
12463 #define RCC_APB2RSTR_SAI1RST                 RCC_APB2RSTR_SAI1RST_Msk
12464 #define RCC_APB2RSTR_SAI2RST_Pos             (22U)
12465 #define RCC_APB2RSTR_SAI2RST_Msk             (0x1U << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
12466 #define RCC_APB2RSTR_SAI2RST                 RCC_APB2RSTR_SAI2RST_Msk
12467 #define RCC_APB2RSTR_DFSDM1RST_Pos           (24U)
12468 #define RCC_APB2RSTR_DFSDM1RST_Msk           (0x1U << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x01000000 */
12469 #define RCC_APB2RSTR_DFSDM1RST               RCC_APB2RSTR_DFSDM1RST_Msk
12470 
12471 /********************  Bit definition for RCC_AHB1ENR register  ***************/
12472 #define RCC_AHB1ENR_DMA1EN_Pos               (0U)
12473 #define RCC_AHB1ENR_DMA1EN_Msk               (0x1U << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
12474 #define RCC_AHB1ENR_DMA1EN                   RCC_AHB1ENR_DMA1EN_Msk
12475 #define RCC_AHB1ENR_DMA2EN_Pos               (1U)
12476 #define RCC_AHB1ENR_DMA2EN_Msk               (0x1U << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
12477 #define RCC_AHB1ENR_DMA2EN                   RCC_AHB1ENR_DMA2EN_Msk
12478 #define RCC_AHB1ENR_FLASHEN_Pos              (8U)
12479 #define RCC_AHB1ENR_FLASHEN_Msk              (0x1U << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */
12480 #define RCC_AHB1ENR_FLASHEN                  RCC_AHB1ENR_FLASHEN_Msk
12481 #define RCC_AHB1ENR_CRCEN_Pos                (12U)
12482 #define RCC_AHB1ENR_CRCEN_Msk                (0x1U << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
12483 #define RCC_AHB1ENR_CRCEN                    RCC_AHB1ENR_CRCEN_Msk
12484 #define RCC_AHB1ENR_TSCEN_Pos                (16U)
12485 #define RCC_AHB1ENR_TSCEN_Msk                (0x1U << RCC_AHB1ENR_TSCEN_Pos)   /*!< 0x00010000 */
12486 #define RCC_AHB1ENR_TSCEN                    RCC_AHB1ENR_TSCEN_Msk
12487 #define RCC_AHB1ENR_DMA2DEN_Pos              (17U)
12488 #define RCC_AHB1ENR_DMA2DEN_Msk              (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00020000 */
12489 #define RCC_AHB1ENR_DMA2DEN                  RCC_AHB1ENR_DMA2DEN_Msk
12490 
12491 /********************  Bit definition for RCC_AHB2ENR register  ***************/
12492 #define RCC_AHB2ENR_GPIOAEN_Pos              (0U)
12493 #define RCC_AHB2ENR_GPIOAEN_Msk              (0x1U << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
12494 #define RCC_AHB2ENR_GPIOAEN                  RCC_AHB2ENR_GPIOAEN_Msk
12495 #define RCC_AHB2ENR_GPIOBEN_Pos              (1U)
12496 #define RCC_AHB2ENR_GPIOBEN_Msk              (0x1U << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
12497 #define RCC_AHB2ENR_GPIOBEN                  RCC_AHB2ENR_GPIOBEN_Msk
12498 #define RCC_AHB2ENR_GPIOCEN_Pos              (2U)
12499 #define RCC_AHB2ENR_GPIOCEN_Msk              (0x1U << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
12500 #define RCC_AHB2ENR_GPIOCEN                  RCC_AHB2ENR_GPIOCEN_Msk
12501 #define RCC_AHB2ENR_GPIODEN_Pos              (3U)
12502 #define RCC_AHB2ENR_GPIODEN_Msk              (0x1U << RCC_AHB2ENR_GPIODEN_Pos) /*!< 0x00000008 */
12503 #define RCC_AHB2ENR_GPIODEN                  RCC_AHB2ENR_GPIODEN_Msk
12504 #define RCC_AHB2ENR_GPIOEEN_Pos              (4U)
12505 #define RCC_AHB2ENR_GPIOEEN_Msk              (0x1U << RCC_AHB2ENR_GPIOEEN_Pos) /*!< 0x00000010 */
12506 #define RCC_AHB2ENR_GPIOEEN                  RCC_AHB2ENR_GPIOEEN_Msk
12507 #define RCC_AHB2ENR_GPIOFEN_Pos              (5U)
12508 #define RCC_AHB2ENR_GPIOFEN_Msk              (0x1U << RCC_AHB2ENR_GPIOFEN_Pos) /*!< 0x00000020 */
12509 #define RCC_AHB2ENR_GPIOFEN                  RCC_AHB2ENR_GPIOFEN_Msk
12510 #define RCC_AHB2ENR_GPIOGEN_Pos              (6U)
12511 #define RCC_AHB2ENR_GPIOGEN_Msk              (0x1U << RCC_AHB2ENR_GPIOGEN_Pos) /*!< 0x00000040 */
12512 #define RCC_AHB2ENR_GPIOGEN                  RCC_AHB2ENR_GPIOGEN_Msk
12513 #define RCC_AHB2ENR_GPIOHEN_Pos              (7U)
12514 #define RCC_AHB2ENR_GPIOHEN_Msk              (0x1U << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
12515 #define RCC_AHB2ENR_GPIOHEN                  RCC_AHB2ENR_GPIOHEN_Msk
12516 #define RCC_AHB2ENR_GPIOIEN_Pos              (8U)
12517 #define RCC_AHB2ENR_GPIOIEN_Msk              (0x1U << RCC_AHB2ENR_GPIOIEN_Pos) /*!< 0x00000100 */
12518 #define RCC_AHB2ENR_GPIOIEN                  RCC_AHB2ENR_GPIOIEN_Msk
12519 #define RCC_AHB2ENR_OTGFSEN_Pos              (12U)
12520 #define RCC_AHB2ENR_OTGFSEN_Msk              (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00001000 */
12521 #define RCC_AHB2ENR_OTGFSEN                  RCC_AHB2ENR_OTGFSEN_Msk
12522 #define RCC_AHB2ENR_ADCEN_Pos                (13U)
12523 #define RCC_AHB2ENR_ADCEN_Msk                (0x1U << RCC_AHB2ENR_ADCEN_Pos)   /*!< 0x00002000 */
12524 #define RCC_AHB2ENR_ADCEN                    RCC_AHB2ENR_ADCEN_Msk
12525 #define RCC_AHB2ENR_DCMIEN_Pos               (14U)
12526 #define RCC_AHB2ENR_DCMIEN_Msk               (0x1U << RCC_AHB2ENR_DCMIEN_Pos)  /*!< 0x00004000 */
12527 #define RCC_AHB2ENR_DCMIEN                   RCC_AHB2ENR_DCMIEN_Msk
12528 #define RCC_AHB2ENR_AESEN_Pos                (16U)
12529 #define RCC_AHB2ENR_AESEN_Msk                (0x1U << RCC_AHB2ENR_AESEN_Pos)   /*!< 0x00010000 */
12530 #define RCC_AHB2ENR_AESEN                    RCC_AHB2ENR_AESEN_Msk
12531 #define RCC_AHB2ENR_HASHEN_Pos               (17U)
12532 #define RCC_AHB2ENR_HASHEN_Msk               (0x1U << RCC_AHB2ENR_HASHEN_Pos)  /*!< 0x00020000 */
12533 #define RCC_AHB2ENR_HASHEN                   RCC_AHB2ENR_HASHEN_Msk
12534 #define RCC_AHB2ENR_RNGEN_Pos                (18U)
12535 #define RCC_AHB2ENR_RNGEN_Msk                (0x1U << RCC_AHB2ENR_RNGEN_Pos)   /*!< 0x00040000 */
12536 #define RCC_AHB2ENR_RNGEN                    RCC_AHB2ENR_RNGEN_Msk
12537 
12538 /********************  Bit definition for RCC_AHB3ENR register  ***************/
12539 #define RCC_AHB3ENR_FMCEN_Pos                (0U)
12540 #define RCC_AHB3ENR_FMCEN_Msk                (0x1U << RCC_AHB3ENR_FMCEN_Pos)   /*!< 0x00000001 */
12541 #define RCC_AHB3ENR_FMCEN                    RCC_AHB3ENR_FMCEN_Msk
12542 #define RCC_AHB3ENR_QSPIEN_Pos               (8U)
12543 #define RCC_AHB3ENR_QSPIEN_Msk               (0x1U << RCC_AHB3ENR_QSPIEN_Pos)  /*!< 0x00000100 */
12544 #define RCC_AHB3ENR_QSPIEN                   RCC_AHB3ENR_QSPIEN_Msk
12545 
12546 /********************  Bit definition for RCC_APB1ENR1 register  ***************/
12547 #define RCC_APB1ENR1_TIM2EN_Pos              (0U)
12548 #define RCC_APB1ENR1_TIM2EN_Msk              (0x1U << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
12549 #define RCC_APB1ENR1_TIM2EN                  RCC_APB1ENR1_TIM2EN_Msk
12550 #define RCC_APB1ENR1_TIM3EN_Pos              (1U)
12551 #define RCC_APB1ENR1_TIM3EN_Msk              (0x1U << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
12552 #define RCC_APB1ENR1_TIM3EN                  RCC_APB1ENR1_TIM3EN_Msk
12553 #define RCC_APB1ENR1_TIM4EN_Pos              (2U)
12554 #define RCC_APB1ENR1_TIM4EN_Msk              (0x1U << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
12555 #define RCC_APB1ENR1_TIM4EN                  RCC_APB1ENR1_TIM4EN_Msk
12556 #define RCC_APB1ENR1_TIM5EN_Pos              (3U)
12557 #define RCC_APB1ENR1_TIM5EN_Msk              (0x1U << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
12558 #define RCC_APB1ENR1_TIM5EN                  RCC_APB1ENR1_TIM5EN_Msk
12559 #define RCC_APB1ENR1_TIM6EN_Pos              (4U)
12560 #define RCC_APB1ENR1_TIM6EN_Msk              (0x1U << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
12561 #define RCC_APB1ENR1_TIM6EN                  RCC_APB1ENR1_TIM6EN_Msk
12562 #define RCC_APB1ENR1_TIM7EN_Pos              (5U)
12563 #define RCC_APB1ENR1_TIM7EN_Msk              (0x1U << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
12564 #define RCC_APB1ENR1_TIM7EN                  RCC_APB1ENR1_TIM7EN_Msk
12565 #define RCC_APB1ENR1_LCDEN_Pos               (9U)
12566 #define RCC_APB1ENR1_LCDEN_Msk               (0x1U << RCC_APB1ENR1_LCDEN_Pos)  /*!< 0x00000200 */
12567 #define RCC_APB1ENR1_LCDEN                   RCC_APB1ENR1_LCDEN_Msk
12568 #define RCC_APB1ENR1_RTCAPBEN_Pos            (10U)
12569 #define RCC_APB1ENR1_RTCAPBEN_Msk            (0x1U << RCC_APB1ENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
12570 #define RCC_APB1ENR1_RTCAPBEN                RCC_APB1ENR1_RTCAPBEN_Msk
12571 #define RCC_APB1ENR1_WWDGEN_Pos              (11U)
12572 #define RCC_APB1ENR1_WWDGEN_Msk              (0x1U << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
12573 #define RCC_APB1ENR1_WWDGEN                  RCC_APB1ENR1_WWDGEN_Msk
12574 #define RCC_APB1ENR1_SPI2EN_Pos              (14U)
12575 #define RCC_APB1ENR1_SPI2EN_Msk              (0x1U << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
12576 #define RCC_APB1ENR1_SPI2EN                  RCC_APB1ENR1_SPI2EN_Msk
12577 #define RCC_APB1ENR1_SPI3EN_Pos              (15U)
12578 #define RCC_APB1ENR1_SPI3EN_Msk              (0x1U << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
12579 #define RCC_APB1ENR1_SPI3EN                  RCC_APB1ENR1_SPI3EN_Msk
12580 #define RCC_APB1ENR1_USART2EN_Pos            (17U)
12581 #define RCC_APB1ENR1_USART2EN_Msk            (0x1U << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
12582 #define RCC_APB1ENR1_USART2EN                RCC_APB1ENR1_USART2EN_Msk
12583 #define RCC_APB1ENR1_USART3EN_Pos            (18U)
12584 #define RCC_APB1ENR1_USART3EN_Msk            (0x1U << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
12585 #define RCC_APB1ENR1_USART3EN                RCC_APB1ENR1_USART3EN_Msk
12586 #define RCC_APB1ENR1_UART4EN_Pos             (19U)
12587 #define RCC_APB1ENR1_UART4EN_Msk             (0x1U << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
12588 #define RCC_APB1ENR1_UART4EN                 RCC_APB1ENR1_UART4EN_Msk
12589 #define RCC_APB1ENR1_UART5EN_Pos             (20U)
12590 #define RCC_APB1ENR1_UART5EN_Msk             (0x1U << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
12591 #define RCC_APB1ENR1_UART5EN                 RCC_APB1ENR1_UART5EN_Msk
12592 #define RCC_APB1ENR1_I2C1EN_Pos              (21U)
12593 #define RCC_APB1ENR1_I2C1EN_Msk              (0x1U << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
12594 #define RCC_APB1ENR1_I2C1EN                  RCC_APB1ENR1_I2C1EN_Msk
12595 #define RCC_APB1ENR1_I2C2EN_Pos              (22U)
12596 #define RCC_APB1ENR1_I2C2EN_Msk              (0x1U << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
12597 #define RCC_APB1ENR1_I2C2EN                  RCC_APB1ENR1_I2C2EN_Msk
12598 #define RCC_APB1ENR1_I2C3EN_Pos              (23U)
12599 #define RCC_APB1ENR1_I2C3EN_Msk              (0x1U << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
12600 #define RCC_APB1ENR1_I2C3EN                  RCC_APB1ENR1_I2C3EN_Msk
12601 #define RCC_APB1ENR1_CRSEN_Pos               (24U)
12602 #define RCC_APB1ENR1_CRSEN_Msk               (0x1U << RCC_APB1ENR1_CRSEN_Pos)  /*!< 0x01000000 */
12603 #define RCC_APB1ENR1_CRSEN                   RCC_APB1ENR1_CRSEN_Msk
12604 #define RCC_APB1ENR1_CAN1EN_Pos              (25U)
12605 #define RCC_APB1ENR1_CAN1EN_Msk              (0x1U << RCC_APB1ENR1_CAN1EN_Pos) /*!< 0x02000000 */
12606 #define RCC_APB1ENR1_CAN1EN                  RCC_APB1ENR1_CAN1EN_Msk
12607 #define RCC_APB1ENR1_CAN2EN_Pos              (26U)
12608 #define RCC_APB1ENR1_CAN2EN_Msk              (0x1U << RCC_APB1ENR1_CAN2EN_Pos) /*!< 0x04000000 */
12609 #define RCC_APB1ENR1_CAN2EN                  RCC_APB1ENR1_CAN2EN_Msk
12610 #define RCC_APB1ENR1_PWREN_Pos               (28U)
12611 #define RCC_APB1ENR1_PWREN_Msk               (0x1U << RCC_APB1ENR1_PWREN_Pos)  /*!< 0x10000000 */
12612 #define RCC_APB1ENR1_PWREN                   RCC_APB1ENR1_PWREN_Msk
12613 #define RCC_APB1ENR1_DAC1EN_Pos              (29U)
12614 #define RCC_APB1ENR1_DAC1EN_Msk              (0x1U << RCC_APB1ENR1_DAC1EN_Pos) /*!< 0x20000000 */
12615 #define RCC_APB1ENR1_DAC1EN                  RCC_APB1ENR1_DAC1EN_Msk
12616 #define RCC_APB1ENR1_OPAMPEN_Pos             (30U)
12617 #define RCC_APB1ENR1_OPAMPEN_Msk             (0x1U << RCC_APB1ENR1_OPAMPEN_Pos) /*!< 0x40000000 */
12618 #define RCC_APB1ENR1_OPAMPEN                 RCC_APB1ENR1_OPAMPEN_Msk
12619 #define RCC_APB1ENR1_LPTIM1EN_Pos            (31U)
12620 #define RCC_APB1ENR1_LPTIM1EN_Msk            (0x1U << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
12621 #define RCC_APB1ENR1_LPTIM1EN                RCC_APB1ENR1_LPTIM1EN_Msk
12622 
12623 /********************  Bit definition for RCC_APB1RSTR2 register  **************/
12624 #define RCC_APB1ENR2_LPUART1EN_Pos           (0U)
12625 #define RCC_APB1ENR2_LPUART1EN_Msk           (0x1U << RCC_APB1ENR2_LPUART1EN_Pos) /*!< 0x00000001 */
12626 #define RCC_APB1ENR2_LPUART1EN               RCC_APB1ENR2_LPUART1EN_Msk
12627 #define RCC_APB1ENR2_I2C4EN_Pos              (1U)
12628 #define RCC_APB1ENR2_I2C4EN_Msk              (0x1U << RCC_APB1ENR2_I2C4EN_Pos) /*!< 0x00000002 */
12629 #define RCC_APB1ENR2_I2C4EN                  RCC_APB1ENR2_I2C4EN_Msk
12630 #define RCC_APB1ENR2_SWPMI1EN_Pos            (2U)
12631 #define RCC_APB1ENR2_SWPMI1EN_Msk            (0x1U << RCC_APB1ENR2_SWPMI1EN_Pos) /*!< 0x00000004 */
12632 #define RCC_APB1ENR2_SWPMI1EN                RCC_APB1ENR2_SWPMI1EN_Msk
12633 #define RCC_APB1ENR2_LPTIM2EN_Pos            (5U)
12634 #define RCC_APB1ENR2_LPTIM2EN_Msk            (0x1U << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */
12635 #define RCC_APB1ENR2_LPTIM2EN                RCC_APB1ENR2_LPTIM2EN_Msk
12636 
12637 /********************  Bit definition for RCC_APB2ENR register  ***************/
12638 #define RCC_APB2ENR_SYSCFGEN_Pos             (0U)
12639 #define RCC_APB2ENR_SYSCFGEN_Msk             (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
12640 #define RCC_APB2ENR_SYSCFGEN                 RCC_APB2ENR_SYSCFGEN_Msk
12641 #define RCC_APB2ENR_FWEN_Pos                 (7U)
12642 #define RCC_APB2ENR_FWEN_Msk                 (0x1U << RCC_APB2ENR_FWEN_Pos)    /*!< 0x00000080 */
12643 #define RCC_APB2ENR_FWEN                     RCC_APB2ENR_FWEN_Msk
12644 #define RCC_APB2ENR_SDMMC1EN_Pos             (10U)
12645 #define RCC_APB2ENR_SDMMC1EN_Msk             (0x1U << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000400 */
12646 #define RCC_APB2ENR_SDMMC1EN                 RCC_APB2ENR_SDMMC1EN_Msk
12647 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
12648 #define RCC_APB2ENR_TIM1EN_Msk               (0x1U << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
12649 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk
12650 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
12651 #define RCC_APB2ENR_SPI1EN_Msk               (0x1U << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
12652 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk
12653 #define RCC_APB2ENR_TIM8EN_Pos               (13U)
12654 #define RCC_APB2ENR_TIM8EN_Msk               (0x1U << RCC_APB2ENR_TIM8EN_Pos)  /*!< 0x00002000 */
12655 #define RCC_APB2ENR_TIM8EN                   RCC_APB2ENR_TIM8EN_Msk
12656 #define RCC_APB2ENR_USART1EN_Pos             (14U)
12657 #define RCC_APB2ENR_USART1EN_Msk             (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
12658 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk
12659 #define RCC_APB2ENR_TIM15EN_Pos              (16U)
12660 #define RCC_APB2ENR_TIM15EN_Msk              (0x1U << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
12661 #define RCC_APB2ENR_TIM15EN                  RCC_APB2ENR_TIM15EN_Msk
12662 #define RCC_APB2ENR_TIM16EN_Pos              (17U)
12663 #define RCC_APB2ENR_TIM16EN_Msk              (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
12664 #define RCC_APB2ENR_TIM16EN                  RCC_APB2ENR_TIM16EN_Msk
12665 #define RCC_APB2ENR_TIM17EN_Pos              (18U)
12666 #define RCC_APB2ENR_TIM17EN_Msk              (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
12667 #define RCC_APB2ENR_TIM17EN                  RCC_APB2ENR_TIM17EN_Msk
12668 #define RCC_APB2ENR_SAI1EN_Pos               (21U)
12669 #define RCC_APB2ENR_SAI1EN_Msk               (0x1U << RCC_APB2ENR_SAI1EN_Pos)  /*!< 0x00200000 */
12670 #define RCC_APB2ENR_SAI1EN                   RCC_APB2ENR_SAI1EN_Msk
12671 #define RCC_APB2ENR_SAI2EN_Pos               (22U)
12672 #define RCC_APB2ENR_SAI2EN_Msk               (0x1U << RCC_APB2ENR_SAI2EN_Pos)  /*!< 0x00400000 */
12673 #define RCC_APB2ENR_SAI2EN                   RCC_APB2ENR_SAI2EN_Msk
12674 #define RCC_APB2ENR_DFSDM1EN_Pos             (24U)
12675 #define RCC_APB2ENR_DFSDM1EN_Msk             (0x1U << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x01000000 */
12676 #define RCC_APB2ENR_DFSDM1EN                 RCC_APB2ENR_DFSDM1EN_Msk
12677 
12678 /********************  Bit definition for RCC_AHB1SMENR register  ***************/
12679 #define RCC_AHB1SMENR_DMA1SMEN_Pos           (0U)
12680 #define RCC_AHB1SMENR_DMA1SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
12681 #define RCC_AHB1SMENR_DMA1SMEN               RCC_AHB1SMENR_DMA1SMEN_Msk
12682 #define RCC_AHB1SMENR_DMA2SMEN_Pos           (1U)
12683 #define RCC_AHB1SMENR_DMA2SMEN_Msk           (0x1U << RCC_AHB1SMENR_DMA2SMEN_Pos) /*!< 0x00000002 */
12684 #define RCC_AHB1SMENR_DMA2SMEN               RCC_AHB1SMENR_DMA2SMEN_Msk
12685 #define RCC_AHB1SMENR_FLASHSMEN_Pos          (8U)
12686 #define RCC_AHB1SMENR_FLASHSMEN_Msk          (0x1U << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
12687 #define RCC_AHB1SMENR_FLASHSMEN              RCC_AHB1SMENR_FLASHSMEN_Msk
12688 #define RCC_AHB1SMENR_SRAM1SMEN_Pos          (9U)
12689 #define RCC_AHB1SMENR_SRAM1SMEN_Msk          (0x1U << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x00000200 */
12690 #define RCC_AHB1SMENR_SRAM1SMEN              RCC_AHB1SMENR_SRAM1SMEN_Msk
12691 #define RCC_AHB1SMENR_CRCSMEN_Pos            (12U)
12692 #define RCC_AHB1SMENR_CRCSMEN_Msk            (0x1U << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */
12693 #define RCC_AHB1SMENR_CRCSMEN                RCC_AHB1SMENR_CRCSMEN_Msk
12694 #define RCC_AHB1SMENR_TSCSMEN_Pos            (16U)
12695 #define RCC_AHB1SMENR_TSCSMEN_Msk            (0x1U << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */
12696 #define RCC_AHB1SMENR_TSCSMEN                RCC_AHB1SMENR_TSCSMEN_Msk
12697 #define RCC_AHB1SMENR_DMA2DSMEN_Pos          (17U)
12698 #define RCC_AHB1SMENR_DMA2DSMEN_Msk          (0x1U << RCC_AHB1SMENR_DMA2DSMEN_Pos) /*!< 0x00020000 */
12699 #define RCC_AHB1SMENR_DMA2DSMEN              RCC_AHB1SMENR_DMA2DSMEN_Msk
12700 
12701 /********************  Bit definition for RCC_AHB2SMENR register  *************/
12702 #define RCC_AHB2SMENR_GPIOASMEN_Pos          (0U)
12703 #define RCC_AHB2SMENR_GPIOASMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
12704 #define RCC_AHB2SMENR_GPIOASMEN              RCC_AHB2SMENR_GPIOASMEN_Msk
12705 #define RCC_AHB2SMENR_GPIOBSMEN_Pos          (1U)
12706 #define RCC_AHB2SMENR_GPIOBSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
12707 #define RCC_AHB2SMENR_GPIOBSMEN              RCC_AHB2SMENR_GPIOBSMEN_Msk
12708 #define RCC_AHB2SMENR_GPIOCSMEN_Pos          (2U)
12709 #define RCC_AHB2SMENR_GPIOCSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
12710 #define RCC_AHB2SMENR_GPIOCSMEN              RCC_AHB2SMENR_GPIOCSMEN_Msk
12711 #define RCC_AHB2SMENR_GPIODSMEN_Pos          (3U)
12712 #define RCC_AHB2SMENR_GPIODSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
12713 #define RCC_AHB2SMENR_GPIODSMEN              RCC_AHB2SMENR_GPIODSMEN_Msk
12714 #define RCC_AHB2SMENR_GPIOESMEN_Pos          (4U)
12715 #define RCC_AHB2SMENR_GPIOESMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOESMEN_Pos) /*!< 0x00000010 */
12716 #define RCC_AHB2SMENR_GPIOESMEN              RCC_AHB2SMENR_GPIOESMEN_Msk
12717 #define RCC_AHB2SMENR_GPIOFSMEN_Pos          (5U)
12718 #define RCC_AHB2SMENR_GPIOFSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
12719 #define RCC_AHB2SMENR_GPIOFSMEN              RCC_AHB2SMENR_GPIOFSMEN_Msk
12720 #define RCC_AHB2SMENR_GPIOGSMEN_Pos          (6U)
12721 #define RCC_AHB2SMENR_GPIOGSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOGSMEN_Pos) /*!< 0x00000040 */
12722 #define RCC_AHB2SMENR_GPIOGSMEN              RCC_AHB2SMENR_GPIOGSMEN_Msk
12723 #define RCC_AHB2SMENR_GPIOHSMEN_Pos          (7U)
12724 #define RCC_AHB2SMENR_GPIOHSMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */
12725 #define RCC_AHB2SMENR_GPIOHSMEN              RCC_AHB2SMENR_GPIOHSMEN_Msk
12726 #define RCC_AHB2SMENR_GPIOISMEN_Pos          (8U)
12727 #define RCC_AHB2SMENR_GPIOISMEN_Msk          (0x1U << RCC_AHB2SMENR_GPIOISMEN_Pos) /*!< 0x00000100 */
12728 #define RCC_AHB2SMENR_GPIOISMEN              RCC_AHB2SMENR_GPIOISMEN_Msk
12729 #define RCC_AHB2SMENR_SRAM2SMEN_Pos          (9U)
12730 #define RCC_AHB2SMENR_SRAM2SMEN_Msk          (0x1U << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x00000200 */
12731 #define RCC_AHB2SMENR_SRAM2SMEN              RCC_AHB2SMENR_SRAM2SMEN_Msk
12732 #define RCC_AHB2SMENR_OTGFSSMEN_Pos          (12U)
12733 #define RCC_AHB2SMENR_OTGFSSMEN_Msk          (0x1U << RCC_AHB2SMENR_OTGFSSMEN_Pos) /*!< 0x00001000 */
12734 #define RCC_AHB2SMENR_OTGFSSMEN              RCC_AHB2SMENR_OTGFSSMEN_Msk
12735 #define RCC_AHB2SMENR_ADCSMEN_Pos            (13U)
12736 #define RCC_AHB2SMENR_ADCSMEN_Msk            (0x1U << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
12737 #define RCC_AHB2SMENR_ADCSMEN                RCC_AHB2SMENR_ADCSMEN_Msk
12738 #define RCC_AHB2SMENR_DCMISMEN_Pos           (14U)
12739 #define RCC_AHB2SMENR_DCMISMEN_Msk           (0x1U << RCC_AHB2SMENR_DCMISMEN_Pos) /*!< 0x00004000 */
12740 #define RCC_AHB2SMENR_DCMISMEN               RCC_AHB2SMENR_DCMISMEN_Msk
12741 #define RCC_AHB2SMENR_AESSMEN_Pos            (16U)
12742 #define RCC_AHB2SMENR_AESSMEN_Msk            (0x1U << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */
12743 #define RCC_AHB2SMENR_AESSMEN                RCC_AHB2SMENR_AESSMEN_Msk
12744 #define RCC_AHB2SMENR_HASHSMEN_Pos           (17U)
12745 #define RCC_AHB2SMENR_HASHSMEN_Msk           (0x1U << RCC_AHB2SMENR_HASHSMEN_Pos) /*!< 0x00020000 */
12746 #define RCC_AHB2SMENR_HASHSMEN               RCC_AHB2SMENR_HASHSMEN_Msk
12747 #define RCC_AHB2SMENR_RNGSMEN_Pos            (18U)
12748 #define RCC_AHB2SMENR_RNGSMEN_Msk            (0x1U << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */
12749 #define RCC_AHB2SMENR_RNGSMEN                RCC_AHB2SMENR_RNGSMEN_Msk
12750 
12751 /********************  Bit definition for RCC_AHB3SMENR register  *************/
12752 #define RCC_AHB3SMENR_FMCSMEN_Pos            (0U)
12753 #define RCC_AHB3SMENR_FMCSMEN_Msk            (0x1U << RCC_AHB3SMENR_FMCSMEN_Pos) /*!< 0x00000001 */
12754 #define RCC_AHB3SMENR_FMCSMEN                RCC_AHB3SMENR_FMCSMEN_Msk
12755 #define RCC_AHB3SMENR_QSPISMEN_Pos           (8U)
12756 #define RCC_AHB3SMENR_QSPISMEN_Msk           (0x1U << RCC_AHB3SMENR_QSPISMEN_Pos) /*!< 0x00000100 */
12757 #define RCC_AHB3SMENR_QSPISMEN               RCC_AHB3SMENR_QSPISMEN_Msk
12758 
12759 /********************  Bit definition for RCC_APB1SMENR1 register  *************/
12760 #define RCC_APB1SMENR1_TIM2SMEN_Pos          (0U)
12761 #define RCC_APB1SMENR1_TIM2SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
12762 #define RCC_APB1SMENR1_TIM2SMEN              RCC_APB1SMENR1_TIM2SMEN_Msk
12763 #define RCC_APB1SMENR1_TIM3SMEN_Pos          (1U)
12764 #define RCC_APB1SMENR1_TIM3SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
12765 #define RCC_APB1SMENR1_TIM3SMEN              RCC_APB1SMENR1_TIM3SMEN_Msk
12766 #define RCC_APB1SMENR1_TIM4SMEN_Pos          (2U)
12767 #define RCC_APB1SMENR1_TIM4SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM4SMEN_Pos) /*!< 0x00000004 */
12768 #define RCC_APB1SMENR1_TIM4SMEN              RCC_APB1SMENR1_TIM4SMEN_Msk
12769 #define RCC_APB1SMENR1_TIM5SMEN_Pos          (3U)
12770 #define RCC_APB1SMENR1_TIM5SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM5SMEN_Pos) /*!< 0x00000008 */
12771 #define RCC_APB1SMENR1_TIM5SMEN              RCC_APB1SMENR1_TIM5SMEN_Msk
12772 #define RCC_APB1SMENR1_TIM6SMEN_Pos          (4U)
12773 #define RCC_APB1SMENR1_TIM6SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM6SMEN_Pos) /*!< 0x00000010 */
12774 #define RCC_APB1SMENR1_TIM6SMEN              RCC_APB1SMENR1_TIM6SMEN_Msk
12775 #define RCC_APB1SMENR1_TIM7SMEN_Pos          (5U)
12776 #define RCC_APB1SMENR1_TIM7SMEN_Msk          (0x1U << RCC_APB1SMENR1_TIM7SMEN_Pos) /*!< 0x00000020 */
12777 #define RCC_APB1SMENR1_TIM7SMEN              RCC_APB1SMENR1_TIM7SMEN_Msk
12778 #define RCC_APB1SMENR1_LCDSMEN_Pos           (9U)
12779 #define RCC_APB1SMENR1_LCDSMEN_Msk           (0x1U << RCC_APB1SMENR1_LCDSMEN_Pos) /*!< 0x00000200 */
12780 #define RCC_APB1SMENR1_LCDSMEN               RCC_APB1SMENR1_LCDSMEN_Msk
12781 #define RCC_APB1SMENR1_RTCAPBSMEN_Pos        (10U)
12782 #define RCC_APB1SMENR1_RTCAPBSMEN_Msk        (0x1U << RCC_APB1SMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
12783 #define RCC_APB1SMENR1_RTCAPBSMEN            RCC_APB1SMENR1_RTCAPBSMEN_Msk
12784 #define RCC_APB1SMENR1_WWDGSMEN_Pos          (11U)
12785 #define RCC_APB1SMENR1_WWDGSMEN_Msk          (0x1U << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
12786 #define RCC_APB1SMENR1_WWDGSMEN              RCC_APB1SMENR1_WWDGSMEN_Msk
12787 #define RCC_APB1SMENR1_SPI2SMEN_Pos          (14U)
12788 #define RCC_APB1SMENR1_SPI2SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
12789 #define RCC_APB1SMENR1_SPI2SMEN              RCC_APB1SMENR1_SPI2SMEN_Msk
12790 #define RCC_APB1SMENR1_SPI3SMEN_Pos          (15U)
12791 #define RCC_APB1SMENR1_SPI3SMEN_Msk          (0x1U << RCC_APB1SMENR1_SPI3SMEN_Pos) /*!< 0x00008000 */
12792 #define RCC_APB1SMENR1_SPI3SMEN              RCC_APB1SMENR1_SPI3SMEN_Msk
12793 #define RCC_APB1SMENR1_USART2SMEN_Pos        (17U)
12794 #define RCC_APB1SMENR1_USART2SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
12795 #define RCC_APB1SMENR1_USART2SMEN            RCC_APB1SMENR1_USART2SMEN_Msk
12796 #define RCC_APB1SMENR1_USART3SMEN_Pos        (18U)
12797 #define RCC_APB1SMENR1_USART3SMEN_Msk        (0x1U << RCC_APB1SMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
12798 #define RCC_APB1SMENR1_USART3SMEN            RCC_APB1SMENR1_USART3SMEN_Msk
12799 #define RCC_APB1SMENR1_UART4SMEN_Pos         (19U)
12800 #define RCC_APB1SMENR1_UART4SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART4SMEN_Pos) /*!< 0x00080000 */
12801 #define RCC_APB1SMENR1_UART4SMEN             RCC_APB1SMENR1_UART4SMEN_Msk
12802 #define RCC_APB1SMENR1_UART5SMEN_Pos         (20U)
12803 #define RCC_APB1SMENR1_UART5SMEN_Msk         (0x1U << RCC_APB1SMENR1_UART5SMEN_Pos) /*!< 0x00100000 */
12804 #define RCC_APB1SMENR1_UART5SMEN             RCC_APB1SMENR1_UART5SMEN_Msk
12805 #define RCC_APB1SMENR1_I2C1SMEN_Pos          (21U)
12806 #define RCC_APB1SMENR1_I2C1SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
12807 #define RCC_APB1SMENR1_I2C1SMEN              RCC_APB1SMENR1_I2C1SMEN_Msk
12808 #define RCC_APB1SMENR1_I2C2SMEN_Pos          (22U)
12809 #define RCC_APB1SMENR1_I2C2SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
12810 #define RCC_APB1SMENR1_I2C2SMEN              RCC_APB1SMENR1_I2C2SMEN_Msk
12811 #define RCC_APB1SMENR1_I2C3SMEN_Pos          (23U)
12812 #define RCC_APB1SMENR1_I2C3SMEN_Msk          (0x1U << RCC_APB1SMENR1_I2C3SMEN_Pos) /*!< 0x00800000 */
12813 #define RCC_APB1SMENR1_I2C3SMEN              RCC_APB1SMENR1_I2C3SMEN_Msk
12814 #define RCC_APB1SMENR1_CRSSMEN_Pos           (24U)
12815 #define RCC_APB1SMENR1_CRSSMEN_Msk           (0x1U << RCC_APB1SMENR1_CRSSMEN_Pos) /*!< 0x01000000 */
12816 #define RCC_APB1SMENR1_CRSSMEN               RCC_APB1SMENR1_CRSSMEN_Msk
12817 #define RCC_APB1SMENR1_CAN1SMEN_Pos          (25U)
12818 #define RCC_APB1SMENR1_CAN1SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN1SMEN_Pos) /*!< 0x02000000 */
12819 #define RCC_APB1SMENR1_CAN1SMEN              RCC_APB1SMENR1_CAN1SMEN_Msk
12820 #define RCC_APB1SMENR1_CAN2SMEN_Pos          (26U)
12821 #define RCC_APB1SMENR1_CAN2SMEN_Msk          (0x1U << RCC_APB1SMENR1_CAN2SMEN_Pos) /*!< 0x04000000 */
12822 #define RCC_APB1SMENR1_CAN2SMEN              RCC_APB1SMENR1_CAN2SMEN_Msk
12823 #define RCC_APB1SMENR1_PWRSMEN_Pos           (28U)
12824 #define RCC_APB1SMENR1_PWRSMEN_Msk           (0x1U << RCC_APB1SMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
12825 #define RCC_APB1SMENR1_PWRSMEN               RCC_APB1SMENR1_PWRSMEN_Msk
12826 #define RCC_APB1SMENR1_DAC1SMEN_Pos          (29U)
12827 #define RCC_APB1SMENR1_DAC1SMEN_Msk          (0x1U << RCC_APB1SMENR1_DAC1SMEN_Pos) /*!< 0x20000000 */
12828 #define RCC_APB1SMENR1_DAC1SMEN              RCC_APB1SMENR1_DAC1SMEN_Msk
12829 #define RCC_APB1SMENR1_OPAMPSMEN_Pos         (30U)
12830 #define RCC_APB1SMENR1_OPAMPSMEN_Msk         (0x1U << RCC_APB1SMENR1_OPAMPSMEN_Pos) /*!< 0x40000000 */
12831 #define RCC_APB1SMENR1_OPAMPSMEN             RCC_APB1SMENR1_OPAMPSMEN_Msk
12832 #define RCC_APB1SMENR1_LPTIM1SMEN_Pos        (31U)
12833 #define RCC_APB1SMENR1_LPTIM1SMEN_Msk        (0x1U << RCC_APB1SMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
12834 #define RCC_APB1SMENR1_LPTIM1SMEN            RCC_APB1SMENR1_LPTIM1SMEN_Msk
12835 
12836 /********************  Bit definition for RCC_APB1SMENR2 register  *************/
12837 #define RCC_APB1SMENR2_LPUART1SMEN_Pos       (0U)
12838 #define RCC_APB1SMENR2_LPUART1SMEN_Msk       (0x1U << RCC_APB1SMENR2_LPUART1SMEN_Pos) /*!< 0x00000001 */
12839 #define RCC_APB1SMENR2_LPUART1SMEN           RCC_APB1SMENR2_LPUART1SMEN_Msk
12840 #define RCC_APB1SMENR2_I2C4SMEN_Pos          (1U)
12841 #define RCC_APB1SMENR2_I2C4SMEN_Msk          (0x1U << RCC_APB1SMENR2_I2C4SMEN_Pos) /*!< 0x00000002 */
12842 #define RCC_APB1SMENR2_I2C4SMEN              RCC_APB1SMENR2_I2C4SMEN_Msk
12843 #define RCC_APB1SMENR2_SWPMI1SMEN_Pos        (2U)
12844 #define RCC_APB1SMENR2_SWPMI1SMEN_Msk        (0x1U << RCC_APB1SMENR2_SWPMI1SMEN_Pos) /*!< 0x00000004 */
12845 #define RCC_APB1SMENR2_SWPMI1SMEN            RCC_APB1SMENR2_SWPMI1SMEN_Msk
12846 #define RCC_APB1SMENR2_LPTIM2SMEN_Pos        (5U)
12847 #define RCC_APB1SMENR2_LPTIM2SMEN_Msk        (0x1U << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */
12848 #define RCC_APB1SMENR2_LPTIM2SMEN            RCC_APB1SMENR2_LPTIM2SMEN_Msk
12849 
12850 /********************  Bit definition for RCC_APB2SMENR register  *************/
12851 #define RCC_APB2SMENR_SYSCFGSMEN_Pos         (0U)
12852 #define RCC_APB2SMENR_SYSCFGSMEN_Msk         (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */
12853 #define RCC_APB2SMENR_SYSCFGSMEN             RCC_APB2SMENR_SYSCFGSMEN_Msk
12854 #define RCC_APB2SMENR_SDMMC1SMEN_Pos         (10U)
12855 #define RCC_APB2SMENR_SDMMC1SMEN_Msk         (0x1U << RCC_APB2SMENR_SDMMC1SMEN_Pos) /*!< 0x00000400 */
12856 #define RCC_APB2SMENR_SDMMC1SMEN             RCC_APB2SMENR_SDMMC1SMEN_Msk
12857 #define RCC_APB2SMENR_TIM1SMEN_Pos           (11U)
12858 #define RCC_APB2SMENR_TIM1SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */
12859 #define RCC_APB2SMENR_TIM1SMEN               RCC_APB2SMENR_TIM1SMEN_Msk
12860 #define RCC_APB2SMENR_SPI1SMEN_Pos           (12U)
12861 #define RCC_APB2SMENR_SPI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */
12862 #define RCC_APB2SMENR_SPI1SMEN               RCC_APB2SMENR_SPI1SMEN_Msk
12863 #define RCC_APB2SMENR_TIM8SMEN_Pos           (13U)
12864 #define RCC_APB2SMENR_TIM8SMEN_Msk           (0x1U << RCC_APB2SMENR_TIM8SMEN_Pos) /*!< 0x00002000 */
12865 #define RCC_APB2SMENR_TIM8SMEN               RCC_APB2SMENR_TIM8SMEN_Msk
12866 #define RCC_APB2SMENR_USART1SMEN_Pos         (14U)
12867 #define RCC_APB2SMENR_USART1SMEN_Msk         (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */
12868 #define RCC_APB2SMENR_USART1SMEN             RCC_APB2SMENR_USART1SMEN_Msk
12869 #define RCC_APB2SMENR_TIM15SMEN_Pos          (16U)
12870 #define RCC_APB2SMENR_TIM15SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM15SMEN_Pos) /*!< 0x00010000 */
12871 #define RCC_APB2SMENR_TIM15SMEN              RCC_APB2SMENR_TIM15SMEN_Msk
12872 #define RCC_APB2SMENR_TIM16SMEN_Pos          (17U)
12873 #define RCC_APB2SMENR_TIM16SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */
12874 #define RCC_APB2SMENR_TIM16SMEN              RCC_APB2SMENR_TIM16SMEN_Msk
12875 #define RCC_APB2SMENR_TIM17SMEN_Pos          (18U)
12876 #define RCC_APB2SMENR_TIM17SMEN_Msk          (0x1U << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */
12877 #define RCC_APB2SMENR_TIM17SMEN              RCC_APB2SMENR_TIM17SMEN_Msk
12878 #define RCC_APB2SMENR_SAI1SMEN_Pos           (21U)
12879 #define RCC_APB2SMENR_SAI1SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */
12880 #define RCC_APB2SMENR_SAI1SMEN               RCC_APB2SMENR_SAI1SMEN_Msk
12881 #define RCC_APB2SMENR_SAI2SMEN_Pos           (22U)
12882 #define RCC_APB2SMENR_SAI2SMEN_Msk           (0x1U << RCC_APB2SMENR_SAI2SMEN_Pos) /*!< 0x00400000 */
12883 #define RCC_APB2SMENR_SAI2SMEN               RCC_APB2SMENR_SAI2SMEN_Msk
12884 #define RCC_APB2SMENR_DFSDM1SMEN_Pos         (24U)
12885 #define RCC_APB2SMENR_DFSDM1SMEN_Msk         (0x1U << RCC_APB2SMENR_DFSDM1SMEN_Pos) /*!< 0x01000000 */
12886 #define RCC_APB2SMENR_DFSDM1SMEN             RCC_APB2SMENR_DFSDM1SMEN_Msk
12887 
12888 /********************  Bit definition for RCC_CCIPR register  ******************/
12889 #define RCC_CCIPR_USART1SEL_Pos              (0U)
12890 #define RCC_CCIPR_USART1SEL_Msk              (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
12891 #define RCC_CCIPR_USART1SEL                  RCC_CCIPR_USART1SEL_Msk
12892 #define RCC_CCIPR_USART1SEL_0                (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
12893 #define RCC_CCIPR_USART1SEL_1                (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
12894 
12895 #define RCC_CCIPR_USART2SEL_Pos              (2U)
12896 #define RCC_CCIPR_USART2SEL_Msk              (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
12897 #define RCC_CCIPR_USART2SEL                  RCC_CCIPR_USART2SEL_Msk
12898 #define RCC_CCIPR_USART2SEL_0                (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
12899 #define RCC_CCIPR_USART2SEL_1                (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
12900 
12901 #define RCC_CCIPR_USART3SEL_Pos              (4U)
12902 #define RCC_CCIPR_USART3SEL_Msk              (0x3U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000030 */
12903 #define RCC_CCIPR_USART3SEL                  RCC_CCIPR_USART3SEL_Msk
12904 #define RCC_CCIPR_USART3SEL_0                (0x1U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000010 */
12905 #define RCC_CCIPR_USART3SEL_1                (0x2U << RCC_CCIPR_USART3SEL_Pos) /*!< 0x00000020 */
12906 
12907 #define RCC_CCIPR_UART4SEL_Pos               (6U)
12908 #define RCC_CCIPR_UART4SEL_Msk               (0x3U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x000000C0 */
12909 #define RCC_CCIPR_UART4SEL                   RCC_CCIPR_UART4SEL_Msk
12910 #define RCC_CCIPR_UART4SEL_0                 (0x1U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000040 */
12911 #define RCC_CCIPR_UART4SEL_1                 (0x2U << RCC_CCIPR_UART4SEL_Pos)  /*!< 0x00000080 */
12912 
12913 #define RCC_CCIPR_UART5SEL_Pos               (8U)
12914 #define RCC_CCIPR_UART5SEL_Msk               (0x3U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000300 */
12915 #define RCC_CCIPR_UART5SEL                   RCC_CCIPR_UART5SEL_Msk
12916 #define RCC_CCIPR_UART5SEL_0                 (0x1U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000100 */
12917 #define RCC_CCIPR_UART5SEL_1                 (0x2U << RCC_CCIPR_UART5SEL_Pos)  /*!< 0x00000200 */
12918 
12919 #define RCC_CCIPR_LPUART1SEL_Pos             (10U)
12920 #define RCC_CCIPR_LPUART1SEL_Msk             (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
12921 #define RCC_CCIPR_LPUART1SEL                 RCC_CCIPR_LPUART1SEL_Msk
12922 #define RCC_CCIPR_LPUART1SEL_0               (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
12923 #define RCC_CCIPR_LPUART1SEL_1               (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
12924 
12925 #define RCC_CCIPR_I2C1SEL_Pos                (12U)
12926 #define RCC_CCIPR_I2C1SEL_Msk                (0x3U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
12927 #define RCC_CCIPR_I2C1SEL                    RCC_CCIPR_I2C1SEL_Msk
12928 #define RCC_CCIPR_I2C1SEL_0                  (0x1U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
12929 #define RCC_CCIPR_I2C1SEL_1                  (0x2U << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
12930 
12931 #define RCC_CCIPR_I2C2SEL_Pos                (14U)
12932 #define RCC_CCIPR_I2C2SEL_Msk                (0x3U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */
12933 #define RCC_CCIPR_I2C2SEL                    RCC_CCIPR_I2C2SEL_Msk
12934 #define RCC_CCIPR_I2C2SEL_0                  (0x1U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */
12935 #define RCC_CCIPR_I2C2SEL_1                  (0x2U << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */
12936 
12937 #define RCC_CCIPR_I2C3SEL_Pos                (16U)
12938 #define RCC_CCIPR_I2C3SEL_Msk                (0x3U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
12939 #define RCC_CCIPR_I2C3SEL                    RCC_CCIPR_I2C3SEL_Msk
12940 #define RCC_CCIPR_I2C3SEL_0                  (0x1U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
12941 #define RCC_CCIPR_I2C3SEL_1                  (0x2U << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
12942 
12943 #define RCC_CCIPR_LPTIM1SEL_Pos              (18U)
12944 #define RCC_CCIPR_LPTIM1SEL_Msk              (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
12945 #define RCC_CCIPR_LPTIM1SEL                  RCC_CCIPR_LPTIM1SEL_Msk
12946 #define RCC_CCIPR_LPTIM1SEL_0                (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
12947 #define RCC_CCIPR_LPTIM1SEL_1                (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
12948 
12949 #define RCC_CCIPR_LPTIM2SEL_Pos              (20U)
12950 #define RCC_CCIPR_LPTIM2SEL_Msk              (0x3U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
12951 #define RCC_CCIPR_LPTIM2SEL                  RCC_CCIPR_LPTIM2SEL_Msk
12952 #define RCC_CCIPR_LPTIM2SEL_0                (0x1U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
12953 #define RCC_CCIPR_LPTIM2SEL_1                (0x2U << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
12954 
12955 #define RCC_CCIPR_SAI1SEL_Pos                (22U)
12956 #define RCC_CCIPR_SAI1SEL_Msk                (0x3U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00C00000 */
12957 #define RCC_CCIPR_SAI1SEL                    RCC_CCIPR_SAI1SEL_Msk
12958 #define RCC_CCIPR_SAI1SEL_0                  (0x1U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00400000 */
12959 #define RCC_CCIPR_SAI1SEL_1                  (0x2U << RCC_CCIPR_SAI1SEL_Pos)   /*!< 0x00800000 */
12960 
12961 #define RCC_CCIPR_SAI2SEL_Pos                (24U)
12962 #define RCC_CCIPR_SAI2SEL_Msk                (0x3U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x03000000 */
12963 #define RCC_CCIPR_SAI2SEL                    RCC_CCIPR_SAI2SEL_Msk
12964 #define RCC_CCIPR_SAI2SEL_0                  (0x1U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x01000000 */
12965 #define RCC_CCIPR_SAI2SEL_1                  (0x2U << RCC_CCIPR_SAI2SEL_Pos)   /*!< 0x02000000 */
12966 
12967 #define RCC_CCIPR_CLK48SEL_Pos               (26U)
12968 #define RCC_CCIPR_CLK48SEL_Msk               (0x3U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x0C000000 */
12969 #define RCC_CCIPR_CLK48SEL                   RCC_CCIPR_CLK48SEL_Msk
12970 #define RCC_CCIPR_CLK48SEL_0                 (0x1U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x04000000 */
12971 #define RCC_CCIPR_CLK48SEL_1                 (0x2U << RCC_CCIPR_CLK48SEL_Pos)  /*!< 0x08000000 */
12972 
12973 #define RCC_CCIPR_ADCSEL_Pos                 (28U)
12974 #define RCC_CCIPR_ADCSEL_Msk                 (0x3U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
12975 #define RCC_CCIPR_ADCSEL                     RCC_CCIPR_ADCSEL_Msk
12976 #define RCC_CCIPR_ADCSEL_0                   (0x1U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
12977 #define RCC_CCIPR_ADCSEL_1                   (0x2U << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
12978 
12979 #define RCC_CCIPR_SWPMI1SEL_Pos              (30U)
12980 #define RCC_CCIPR_SWPMI1SEL_Msk              (0x1U << RCC_CCIPR_SWPMI1SEL_Pos) /*!< 0x40000000 */
12981 #define RCC_CCIPR_SWPMI1SEL                  RCC_CCIPR_SWPMI1SEL_Msk
12982 
12983 #define RCC_CCIPR_DFSDM1SEL_Pos              (31U)
12984 #define RCC_CCIPR_DFSDM1SEL_Msk              (0x1U << RCC_CCIPR_DFSDM1SEL_Pos) /*!< 0x80000000 */
12985 #define RCC_CCIPR_DFSDM1SEL                  RCC_CCIPR_DFSDM1SEL_Msk
12986 
12987 /********************  Bit definition for RCC_BDCR register  ******************/
12988 #define RCC_BDCR_LSEON_Pos                   (0U)
12989 #define RCC_BDCR_LSEON_Msk                   (0x1U << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
12990 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk
12991 #define RCC_BDCR_LSERDY_Pos                  (1U)
12992 #define RCC_BDCR_LSERDY_Msk                  (0x1U << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
12993 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk
12994 #define RCC_BDCR_LSEBYP_Pos                  (2U)
12995 #define RCC_BDCR_LSEBYP_Msk                  (0x1U << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
12996 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk
12997 
12998 #define RCC_BDCR_LSEDRV_Pos                  (3U)
12999 #define RCC_BDCR_LSEDRV_Msk                  (0x3U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
13000 #define RCC_BDCR_LSEDRV                      RCC_BDCR_LSEDRV_Msk
13001 #define RCC_BDCR_LSEDRV_0                    (0x1U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
13002 #define RCC_BDCR_LSEDRV_1                    (0x2U << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
13003 
13004 #define RCC_BDCR_LSECSSON_Pos                (5U)
13005 #define RCC_BDCR_LSECSSON_Msk                (0x1U << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
13006 #define RCC_BDCR_LSECSSON                    RCC_BDCR_LSECSSON_Msk
13007 #define RCC_BDCR_LSECSSD_Pos                 (6U)
13008 #define RCC_BDCR_LSECSSD_Msk                 (0x1U << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
13009 #define RCC_BDCR_LSECSSD                     RCC_BDCR_LSECSSD_Msk
13010 
13011 #define RCC_BDCR_RTCSEL_Pos                  (8U)
13012 #define RCC_BDCR_RTCSEL_Msk                  (0x3U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
13013 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk
13014 #define RCC_BDCR_RTCSEL_0                    (0x1U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
13015 #define RCC_BDCR_RTCSEL_1                    (0x2U << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
13016 
13017 #define RCC_BDCR_RTCEN_Pos                   (15U)
13018 #define RCC_BDCR_RTCEN_Msk                   (0x1U << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
13019 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk
13020 #define RCC_BDCR_BDRST_Pos                   (16U)
13021 #define RCC_BDCR_BDRST_Msk                   (0x1U << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
13022 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk
13023 #define RCC_BDCR_LSCOEN_Pos                  (24U)
13024 #define RCC_BDCR_LSCOEN_Msk                  (0x1U << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
13025 #define RCC_BDCR_LSCOEN                      RCC_BDCR_LSCOEN_Msk
13026 #define RCC_BDCR_LSCOSEL_Pos                 (25U)
13027 #define RCC_BDCR_LSCOSEL_Msk                 (0x1U << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
13028 #define RCC_BDCR_LSCOSEL                     RCC_BDCR_LSCOSEL_Msk
13029 
13030 /********************  Bit definition for RCC_CSR register  *******************/
13031 #define RCC_CSR_LSION_Pos                    (0U)
13032 #define RCC_CSR_LSION_Msk                    (0x1U << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
13033 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk
13034 #define RCC_CSR_LSIRDY_Pos                   (1U)
13035 #define RCC_CSR_LSIRDY_Msk                   (0x1U << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
13036 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk
13037 
13038 #define RCC_CSR_MSISRANGE_Pos                (8U)
13039 #define RCC_CSR_MSISRANGE_Msk                (0xFU << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000F00 */
13040 #define RCC_CSR_MSISRANGE                    RCC_CSR_MSISRANGE_Msk
13041 #define RCC_CSR_MSISRANGE_1                  (0x4U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000400 */
13042 #define RCC_CSR_MSISRANGE_2                  (0x5U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000500 */
13043 #define RCC_CSR_MSISRANGE_4                  (0x6U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000600 */
13044 #define RCC_CSR_MSISRANGE_8                  (0x7U << RCC_CSR_MSISRANGE_Pos)   /*!< 0x00000700 */
13045 
13046 #define RCC_CSR_RMVF_Pos                     (23U)
13047 #define RCC_CSR_RMVF_Msk                     (0x1U << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
13048 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk
13049 #define RCC_CSR_FWRSTF_Pos                   (24U)
13050 #define RCC_CSR_FWRSTF_Msk                   (0x1U << RCC_CSR_FWRSTF_Pos)      /*!< 0x01000000 */
13051 #define RCC_CSR_FWRSTF                       RCC_CSR_FWRSTF_Msk
13052 #define RCC_CSR_OBLRSTF_Pos                  (25U)
13053 #define RCC_CSR_OBLRSTF_Msk                  (0x1U << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
13054 #define RCC_CSR_OBLRSTF                      RCC_CSR_OBLRSTF_Msk
13055 #define RCC_CSR_PINRSTF_Pos                  (26U)
13056 #define RCC_CSR_PINRSTF_Msk                  (0x1U << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
13057 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk
13058 #define RCC_CSR_BORRSTF_Pos                  (27U)
13059 #define RCC_CSR_BORRSTF_Msk                  (0x1U << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
13060 #define RCC_CSR_BORRSTF                      RCC_CSR_BORRSTF_Msk
13061 #define RCC_CSR_SFTRSTF_Pos                  (28U)
13062 #define RCC_CSR_SFTRSTF_Msk                  (0x1U << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
13063 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk
13064 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
13065 #define RCC_CSR_IWDGRSTF_Msk                 (0x1U << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
13066 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk
13067 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
13068 #define RCC_CSR_WWDGRSTF_Msk                 (0x1U << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
13069 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk
13070 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
13071 #define RCC_CSR_LPWRRSTF_Msk                 (0x1U << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
13072 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk
13073 
13074 /********************  Bit definition for RCC_CRRCR register  *****************/
13075 #define RCC_CRRCR_HSI48ON_Pos                (0U)
13076 #define RCC_CRRCR_HSI48ON_Msk                (0x1U << RCC_CRRCR_HSI48ON_Pos)   /*!< 0x00000001 */
13077 #define RCC_CRRCR_HSI48ON                    RCC_CRRCR_HSI48ON_Msk
13078 #define RCC_CRRCR_HSI48RDY_Pos               (1U)
13079 #define RCC_CRRCR_HSI48RDY_Msk               (0x1U << RCC_CRRCR_HSI48RDY_Pos)  /*!< 0x00000002 */
13080 #define RCC_CRRCR_HSI48RDY                   RCC_CRRCR_HSI48RDY_Msk
13081 
13082 /*!< HSI48CAL configuration */
13083 #define RCC_CRRCR_HSI48CAL_Pos               (7U)
13084 #define RCC_CRRCR_HSI48CAL_Msk               (0x1FFU << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x0000FF80 */
13085 #define RCC_CRRCR_HSI48CAL                   RCC_CRRCR_HSI48CAL_Msk             /*!< HSI48CAL[8:0] bits */
13086 #define RCC_CRRCR_HSI48CAL_0                 (0x001U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
13087 #define RCC_CRRCR_HSI48CAL_1                 (0x002U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
13088 #define RCC_CRRCR_HSI48CAL_2                 (0x004U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
13089 #define RCC_CRRCR_HSI48CAL_3                 (0x008U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000400 */
13090 #define RCC_CRRCR_HSI48CAL_4                 (0x010U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000800 */
13091 #define RCC_CRRCR_HSI48CAL_5                 (0x020U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00001000 */
13092 #define RCC_CRRCR_HSI48CAL_6                 (0x040U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00002000 */
13093 #define RCC_CRRCR_HSI48CAL_7                 (0x080U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00004000 */
13094 #define RCC_CRRCR_HSI48CAL_8                 (0x100U << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00008000 */
13095 
13096 /********************  Bit definition for RCC_CCIPR2 register  ******************/
13097 #define RCC_CCIPR2_I2C4SEL_Pos               (0U)
13098 #define RCC_CCIPR2_I2C4SEL_Msk               (0x3U << RCC_CCIPR2_I2C4SEL_Pos)  /*!< 0x00000003 */
13099 #define RCC_CCIPR2_I2C4SEL                   RCC_CCIPR2_I2C4SEL_Msk
13100 #define RCC_CCIPR2_I2C4SEL_0                 (0x1U << RCC_CCIPR2_I2C4SEL_Pos)  /*!< 0x00000001 */
13101 #define RCC_CCIPR2_I2C4SEL_1                 (0x2U << RCC_CCIPR2_I2C4SEL_Pos)  /*!< 0x00000002 */
13102 
13103 /******************************************************************************/
13104 /*                                                                            */
13105 /*                                    RNG                                     */
13106 /*                                                                            */
13107 /******************************************************************************/
13108 /********************  Bits definition for RNG_CR register  *******************/
13109 #define RNG_CR_RNGEN_Pos    (2U)
13110 #define RNG_CR_RNGEN_Msk    (0x1U << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
13111 #define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
13112 #define RNG_CR_IE_Pos       (3U)
13113 #define RNG_CR_IE_Msk       (0x1U << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
13114 #define RNG_CR_IE           RNG_CR_IE_Msk
13115 
13116 /********************  Bits definition for RNG_SR register  *******************/
13117 #define RNG_SR_DRDY_Pos     (0U)
13118 #define RNG_SR_DRDY_Msk     (0x1U << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
13119 #define RNG_SR_DRDY         RNG_SR_DRDY_Msk
13120 #define RNG_SR_CECS_Pos     (1U)
13121 #define RNG_SR_CECS_Msk     (0x1U << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
13122 #define RNG_SR_CECS         RNG_SR_CECS_Msk
13123 #define RNG_SR_SECS_Pos     (2U)
13124 #define RNG_SR_SECS_Msk     (0x1U << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
13125 #define RNG_SR_SECS         RNG_SR_SECS_Msk
13126 #define RNG_SR_CEIS_Pos     (5U)
13127 #define RNG_SR_CEIS_Msk     (0x1U << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
13128 #define RNG_SR_CEIS         RNG_SR_CEIS_Msk
13129 #define RNG_SR_SEIS_Pos     (6U)
13130 #define RNG_SR_SEIS_Msk     (0x1U << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
13131 #define RNG_SR_SEIS         RNG_SR_SEIS_Msk
13132 
13133 /******************************************************************************/
13134 /*                                                                            */
13135 /*                           Real-Time Clock (RTC)                            */
13136 /*                                                                            */
13137 /******************************************************************************/
13138 /*
13139 * @brief Specific device feature definitions
13140 */
13141 #define RTC_TAMPER1_SUPPORT
13142 #define RTC_TAMPER2_SUPPORT
13143 #define RTC_TAMPER3_SUPPORT
13144 #define RTC_WAKEUP_SUPPORT
13145 #define RTC_BACKUP_SUPPORT
13146 
13147 /********************  Bits definition for RTC_TR register  *******************/
13148 #define RTC_TR_PM_Pos                  (22U)
13149 #define RTC_TR_PM_Msk                  (0x1U << RTC_TR_PM_Pos)                 /*!< 0x00400000 */
13150 #define RTC_TR_PM                      RTC_TR_PM_Msk
13151 #define RTC_TR_HT_Pos                  (20U)
13152 #define RTC_TR_HT_Msk                  (0x3U << RTC_TR_HT_Pos)                 /*!< 0x00300000 */
13153 #define RTC_TR_HT                      RTC_TR_HT_Msk
13154 #define RTC_TR_HT_0                    (0x1U << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
13155 #define RTC_TR_HT_1                    (0x2U << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
13156 #define RTC_TR_HU_Pos                  (16U)
13157 #define RTC_TR_HU_Msk                  (0xFU << RTC_TR_HU_Pos)                 /*!< 0x000F0000 */
13158 #define RTC_TR_HU                      RTC_TR_HU_Msk
13159 #define RTC_TR_HU_0                    (0x1U << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
13160 #define RTC_TR_HU_1                    (0x2U << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
13161 #define RTC_TR_HU_2                    (0x4U << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
13162 #define RTC_TR_HU_3                    (0x8U << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
13163 #define RTC_TR_MNT_Pos                 (12U)
13164 #define RTC_TR_MNT_Msk                 (0x7U << RTC_TR_MNT_Pos)                /*!< 0x00007000 */
13165 #define RTC_TR_MNT                     RTC_TR_MNT_Msk
13166 #define RTC_TR_MNT_0                   (0x1U << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
13167 #define RTC_TR_MNT_1                   (0x2U << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
13168 #define RTC_TR_MNT_2                   (0x4U << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
13169 #define RTC_TR_MNU_Pos                 (8U)
13170 #define RTC_TR_MNU_Msk                 (0xFU << RTC_TR_MNU_Pos)                /*!< 0x00000F00 */
13171 #define RTC_TR_MNU                     RTC_TR_MNU_Msk
13172 #define RTC_TR_MNU_0                   (0x1U << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
13173 #define RTC_TR_MNU_1                   (0x2U << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
13174 #define RTC_TR_MNU_2                   (0x4U << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
13175 #define RTC_TR_MNU_3                   (0x8U << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
13176 #define RTC_TR_ST_Pos                  (4U)
13177 #define RTC_TR_ST_Msk                  (0x7U << RTC_TR_ST_Pos)                 /*!< 0x00000070 */
13178 #define RTC_TR_ST                      RTC_TR_ST_Msk
13179 #define RTC_TR_ST_0                    (0x1U << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
13180 #define RTC_TR_ST_1                    (0x2U << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
13181 #define RTC_TR_ST_2                    (0x4U << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
13182 #define RTC_TR_SU_Pos                  (0U)
13183 #define RTC_TR_SU_Msk                  (0xFU << RTC_TR_SU_Pos)                 /*!< 0x0000000F */
13184 #define RTC_TR_SU                      RTC_TR_SU_Msk
13185 #define RTC_TR_SU_0                    (0x1U << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
13186 #define RTC_TR_SU_1                    (0x2U << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
13187 #define RTC_TR_SU_2                    (0x4U << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
13188 #define RTC_TR_SU_3                    (0x8U << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
13189 
13190 /********************  Bits definition for RTC_DR register  *******************/
13191 #define RTC_DR_YT_Pos                  (20U)
13192 #define RTC_DR_YT_Msk                  (0xFU << RTC_DR_YT_Pos)                 /*!< 0x00F00000 */
13193 #define RTC_DR_YT                      RTC_DR_YT_Msk
13194 #define RTC_DR_YT_0                    (0x1U << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
13195 #define RTC_DR_YT_1                    (0x2U << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
13196 #define RTC_DR_YT_2                    (0x4U << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
13197 #define RTC_DR_YT_3                    (0x8U << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
13198 #define RTC_DR_YU_Pos                  (16U)
13199 #define RTC_DR_YU_Msk                  (0xFU << RTC_DR_YU_Pos)                 /*!< 0x000F0000 */
13200 #define RTC_DR_YU                      RTC_DR_YU_Msk
13201 #define RTC_DR_YU_0                    (0x1U << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
13202 #define RTC_DR_YU_1                    (0x2U << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
13203 #define RTC_DR_YU_2                    (0x4U << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
13204 #define RTC_DR_YU_3                    (0x8U << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
13205 #define RTC_DR_WDU_Pos                 (13U)
13206 #define RTC_DR_WDU_Msk                 (0x7U << RTC_DR_WDU_Pos)                /*!< 0x0000E000 */
13207 #define RTC_DR_WDU                     RTC_DR_WDU_Msk
13208 #define RTC_DR_WDU_0                   (0x1U << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
13209 #define RTC_DR_WDU_1                   (0x2U << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
13210 #define RTC_DR_WDU_2                   (0x4U << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
13211 #define RTC_DR_MT_Pos                  (12U)
13212 #define RTC_DR_MT_Msk                  (0x1U << RTC_DR_MT_Pos)                 /*!< 0x00001000 */
13213 #define RTC_DR_MT                      RTC_DR_MT_Msk
13214 #define RTC_DR_MU_Pos                  (8U)
13215 #define RTC_DR_MU_Msk                  (0xFU << RTC_DR_MU_Pos)                 /*!< 0x00000F00 */
13216 #define RTC_DR_MU                      RTC_DR_MU_Msk
13217 #define RTC_DR_MU_0                    (0x1U << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
13218 #define RTC_DR_MU_1                    (0x2U << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
13219 #define RTC_DR_MU_2                    (0x4U << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
13220 #define RTC_DR_MU_3                    (0x8U << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
13221 #define RTC_DR_DT_Pos                  (4U)
13222 #define RTC_DR_DT_Msk                  (0x3U << RTC_DR_DT_Pos)                 /*!< 0x00000030 */
13223 #define RTC_DR_DT                      RTC_DR_DT_Msk
13224 #define RTC_DR_DT_0                    (0x1U << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
13225 #define RTC_DR_DT_1                    (0x2U << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
13226 #define RTC_DR_DU_Pos                  (0U)
13227 #define RTC_DR_DU_Msk                  (0xFU << RTC_DR_DU_Pos)                 /*!< 0x0000000F */
13228 #define RTC_DR_DU                      RTC_DR_DU_Msk
13229 #define RTC_DR_DU_0                    (0x1U << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
13230 #define RTC_DR_DU_1                    (0x2U << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
13231 #define RTC_DR_DU_2                    (0x4U << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
13232 #define RTC_DR_DU_3                    (0x8U << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
13233 
13234 /********************  Bits definition for RTC_CR register  *******************/
13235 #define RTC_CR_ITSE_Pos                (24U)
13236 #define RTC_CR_ITSE_Msk                (0x1U << RTC_CR_ITSE_Pos)               /*!< 0x01000000 */
13237 #define RTC_CR_ITSE                    RTC_CR_ITSE_Msk
13238 #define RTC_CR_COE_Pos                 (23U)
13239 #define RTC_CR_COE_Msk                 (0x1U << RTC_CR_COE_Pos)                /*!< 0x00800000 */
13240 #define RTC_CR_COE                     RTC_CR_COE_Msk
13241 #define RTC_CR_OSEL_Pos                (21U)
13242 #define RTC_CR_OSEL_Msk                (0x3U << RTC_CR_OSEL_Pos)               /*!< 0x00600000 */
13243 #define RTC_CR_OSEL                    RTC_CR_OSEL_Msk
13244 #define RTC_CR_OSEL_0                  (0x1U << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
13245 #define RTC_CR_OSEL_1                  (0x2U << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
13246 #define RTC_CR_POL_Pos                 (20U)
13247 #define RTC_CR_POL_Msk                 (0x1U << RTC_CR_POL_Pos)                /*!< 0x00100000 */
13248 #define RTC_CR_POL                     RTC_CR_POL_Msk
13249 #define RTC_CR_COSEL_Pos               (19U)
13250 #define RTC_CR_COSEL_Msk               (0x1U << RTC_CR_COSEL_Pos)              /*!< 0x00080000 */
13251 #define RTC_CR_COSEL                   RTC_CR_COSEL_Msk
13252 #define RTC_CR_BKP_Pos                 (18U)
13253 #define RTC_CR_BKP_Msk                 (0x1U << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
13254 #define RTC_CR_BKP                     RTC_CR_BKP_Msk
13255 #define RTC_CR_SUB1H_Pos               (17U)
13256 #define RTC_CR_SUB1H_Msk               (0x1U << RTC_CR_SUB1H_Pos)              /*!< 0x00020000 */
13257 #define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk
13258 #define RTC_CR_ADD1H_Pos               (16U)
13259 #define RTC_CR_ADD1H_Msk               (0x1U << RTC_CR_ADD1H_Pos)              /*!< 0x00010000 */
13260 #define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk
13261 #define RTC_CR_TSIE_Pos                (15U)
13262 #define RTC_CR_TSIE_Msk                (0x1U << RTC_CR_TSIE_Pos)               /*!< 0x00008000 */
13263 #define RTC_CR_TSIE                    RTC_CR_TSIE_Msk
13264 #define RTC_CR_WUTIE_Pos               (14U)
13265 #define RTC_CR_WUTIE_Msk               (0x1U << RTC_CR_WUTIE_Pos)              /*!< 0x00004000 */
13266 #define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk
13267 #define RTC_CR_ALRBIE_Pos              (13U)
13268 #define RTC_CR_ALRBIE_Msk              (0x1U << RTC_CR_ALRBIE_Pos)             /*!< 0x00002000 */
13269 #define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk
13270 #define RTC_CR_ALRAIE_Pos              (12U)
13271 #define RTC_CR_ALRAIE_Msk              (0x1U << RTC_CR_ALRAIE_Pos)             /*!< 0x00001000 */
13272 #define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk
13273 #define RTC_CR_TSE_Pos                 (11U)
13274 #define RTC_CR_TSE_Msk                 (0x1U << RTC_CR_TSE_Pos)                /*!< 0x00000800 */
13275 #define RTC_CR_TSE                     RTC_CR_TSE_Msk
13276 #define RTC_CR_WUTE_Pos                (10U)
13277 #define RTC_CR_WUTE_Msk                (0x1U << RTC_CR_WUTE_Pos)               /*!< 0x00000400 */
13278 #define RTC_CR_WUTE                    RTC_CR_WUTE_Msk
13279 #define RTC_CR_ALRBE_Pos               (9U)
13280 #define RTC_CR_ALRBE_Msk               (0x1U << RTC_CR_ALRBE_Pos)              /*!< 0x00000200 */
13281 #define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk
13282 #define RTC_CR_ALRAE_Pos               (8U)
13283 #define RTC_CR_ALRAE_Msk               (0x1U << RTC_CR_ALRAE_Pos)              /*!< 0x00000100 */
13284 #define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk
13285 #define RTC_CR_FMT_Pos                 (6U)
13286 #define RTC_CR_FMT_Msk                 (0x1U << RTC_CR_FMT_Pos)                /*!< 0x00000040 */
13287 #define RTC_CR_FMT                     RTC_CR_FMT_Msk
13288 #define RTC_CR_BYPSHAD_Pos             (5U)
13289 #define RTC_CR_BYPSHAD_Msk             (0x1U << RTC_CR_BYPSHAD_Pos)            /*!< 0x00000020 */
13290 #define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk
13291 #define RTC_CR_REFCKON_Pos             (4U)
13292 #define RTC_CR_REFCKON_Msk             (0x1U << RTC_CR_REFCKON_Pos)            /*!< 0x00000010 */
13293 #define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk
13294 #define RTC_CR_TSEDGE_Pos              (3U)
13295 #define RTC_CR_TSEDGE_Msk              (0x1U << RTC_CR_TSEDGE_Pos)             /*!< 0x00000008 */
13296 #define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk
13297 #define RTC_CR_WUCKSEL_Pos             (0U)
13298 #define RTC_CR_WUCKSEL_Msk             (0x7U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000007 */
13299 #define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk
13300 #define RTC_CR_WUCKSEL_0               (0x1U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
13301 #define RTC_CR_WUCKSEL_1               (0x2U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
13302 #define RTC_CR_WUCKSEL_2               (0x4U << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
13303 
13304 /* Legacy defines */
13305 #define RTC_CR_BCK_Pos                 RTC_CR_BKP_Pos
13306 #define RTC_CR_BCK_Msk                 RTC_CR_BKP_Msk
13307 #define RTC_CR_BCK                     RTC_CR_BKP
13308 
13309 /********************  Bits definition for RTC_ISR register  ******************/
13310 #define RTC_ISR_ITSF_Pos               (17U)
13311 #define RTC_ISR_ITSF_Msk               (0x1U << RTC_ISR_ITSF_Pos)              /*!< 0x00020000 */
13312 #define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk
13313 #define RTC_ISR_RECALPF_Pos            (16U)
13314 #define RTC_ISR_RECALPF_Msk            (0x1U << RTC_ISR_RECALPF_Pos)           /*!< 0x00010000 */
13315 #define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk
13316 #define RTC_ISR_TAMP3F_Pos             (15U)
13317 #define RTC_ISR_TAMP3F_Msk             (0x1U << RTC_ISR_TAMP3F_Pos)            /*!< 0x00008000 */
13318 #define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk
13319 #define RTC_ISR_TAMP2F_Pos             (14U)
13320 #define RTC_ISR_TAMP2F_Msk             (0x1U << RTC_ISR_TAMP2F_Pos)            /*!< 0x00004000 */
13321 #define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk
13322 #define RTC_ISR_TAMP1F_Pos             (13U)
13323 #define RTC_ISR_TAMP1F_Msk             (0x1U << RTC_ISR_TAMP1F_Pos)            /*!< 0x00002000 */
13324 #define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk
13325 #define RTC_ISR_TSOVF_Pos              (12U)
13326 #define RTC_ISR_TSOVF_Msk              (0x1U << RTC_ISR_TSOVF_Pos)             /*!< 0x00001000 */
13327 #define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk
13328 #define RTC_ISR_TSF_Pos                (11U)
13329 #define RTC_ISR_TSF_Msk                (0x1U << RTC_ISR_TSF_Pos)               /*!< 0x00000800 */
13330 #define RTC_ISR_TSF                    RTC_ISR_TSF_Msk
13331 #define RTC_ISR_WUTF_Pos               (10U)
13332 #define RTC_ISR_WUTF_Msk               (0x1U << RTC_ISR_WUTF_Pos)              /*!< 0x00000400 */
13333 #define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk
13334 #define RTC_ISR_ALRBF_Pos              (9U)
13335 #define RTC_ISR_ALRBF_Msk              (0x1U << RTC_ISR_ALRBF_Pos)             /*!< 0x00000200 */
13336 #define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk
13337 #define RTC_ISR_ALRAF_Pos              (8U)
13338 #define RTC_ISR_ALRAF_Msk              (0x1U << RTC_ISR_ALRAF_Pos)             /*!< 0x00000100 */
13339 #define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk
13340 #define RTC_ISR_INIT_Pos               (7U)
13341 #define RTC_ISR_INIT_Msk               (0x1U << RTC_ISR_INIT_Pos)              /*!< 0x00000080 */
13342 #define RTC_ISR_INIT                   RTC_ISR_INIT_Msk
13343 #define RTC_ISR_INITF_Pos              (6U)
13344 #define RTC_ISR_INITF_Msk              (0x1U << RTC_ISR_INITF_Pos)             /*!< 0x00000040 */
13345 #define RTC_ISR_INITF                  RTC_ISR_INITF_Msk
13346 #define RTC_ISR_RSF_Pos                (5U)
13347 #define RTC_ISR_RSF_Msk                (0x1U << RTC_ISR_RSF_Pos)               /*!< 0x00000020 */
13348 #define RTC_ISR_RSF                    RTC_ISR_RSF_Msk
13349 #define RTC_ISR_INITS_Pos              (4U)
13350 #define RTC_ISR_INITS_Msk              (0x1U << RTC_ISR_INITS_Pos)             /*!< 0x00000010 */
13351 #define RTC_ISR_INITS                  RTC_ISR_INITS_Msk
13352 #define RTC_ISR_SHPF_Pos               (3U)
13353 #define RTC_ISR_SHPF_Msk               (0x1U << RTC_ISR_SHPF_Pos)              /*!< 0x00000008 */
13354 #define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk
13355 #define RTC_ISR_WUTWF_Pos              (2U)
13356 #define RTC_ISR_WUTWF_Msk              (0x1U << RTC_ISR_WUTWF_Pos)             /*!< 0x00000004 */
13357 #define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk
13358 #define RTC_ISR_ALRBWF_Pos             (1U)
13359 #define RTC_ISR_ALRBWF_Msk             (0x1U << RTC_ISR_ALRBWF_Pos)            /*!< 0x00000002 */
13360 #define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk
13361 #define RTC_ISR_ALRAWF_Pos             (0U)
13362 #define RTC_ISR_ALRAWF_Msk             (0x1U << RTC_ISR_ALRAWF_Pos)            /*!< 0x00000001 */
13363 #define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk
13364 
13365 /********************  Bits definition for RTC_PRER register  *****************/
13366 #define RTC_PRER_PREDIV_A_Pos          (16U)
13367 #define RTC_PRER_PREDIV_A_Msk          (0x7FU << RTC_PRER_PREDIV_A_Pos)        /*!< 0x007F0000 */
13368 #define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk
13369 #define RTC_PRER_PREDIV_S_Pos          (0U)
13370 #define RTC_PRER_PREDIV_S_Msk          (0x7FFFU << RTC_PRER_PREDIV_S_Pos)      /*!< 0x00007FFF */
13371 #define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk
13372 
13373 /********************  Bits definition for RTC_WUTR register  *****************/
13374 #define RTC_WUTR_WUT_Pos               (0U)
13375 #define RTC_WUTR_WUT_Msk               (0xFFFFU << RTC_WUTR_WUT_Pos)           /*!< 0x0000FFFF */
13376 #define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
13377 
13378 /********************  Bits definition for RTC_ALRMAR register  ***************/
13379 #define RTC_ALRMAR_MSK4_Pos            (31U)
13380 #define RTC_ALRMAR_MSK4_Msk            (0x1U << RTC_ALRMAR_MSK4_Pos)           /*!< 0x80000000 */
13381 #define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk
13382 #define RTC_ALRMAR_WDSEL_Pos           (30U)
13383 #define RTC_ALRMAR_WDSEL_Msk           (0x1U << RTC_ALRMAR_WDSEL_Pos)          /*!< 0x40000000 */
13384 #define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk
13385 #define RTC_ALRMAR_DT_Pos              (28U)
13386 #define RTC_ALRMAR_DT_Msk              (0x3U << RTC_ALRMAR_DT_Pos)             /*!< 0x30000000 */
13387 #define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk
13388 #define RTC_ALRMAR_DT_0                (0x1U << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
13389 #define RTC_ALRMAR_DT_1                (0x2U << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
13390 #define RTC_ALRMAR_DU_Pos              (24U)
13391 #define RTC_ALRMAR_DU_Msk              (0xFU << RTC_ALRMAR_DU_Pos)             /*!< 0x0F000000 */
13392 #define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk
13393 #define RTC_ALRMAR_DU_0                (0x1U << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
13394 #define RTC_ALRMAR_DU_1                (0x2U << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
13395 #define RTC_ALRMAR_DU_2                (0x4U << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
13396 #define RTC_ALRMAR_DU_3                (0x8U << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
13397 #define RTC_ALRMAR_MSK3_Pos            (23U)
13398 #define RTC_ALRMAR_MSK3_Msk            (0x1U << RTC_ALRMAR_MSK3_Pos)           /*!< 0x00800000 */
13399 #define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk
13400 #define RTC_ALRMAR_PM_Pos              (22U)
13401 #define RTC_ALRMAR_PM_Msk              (0x1U << RTC_ALRMAR_PM_Pos)             /*!< 0x00400000 */
13402 #define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk
13403 #define RTC_ALRMAR_HT_Pos              (20U)
13404 #define RTC_ALRMAR_HT_Msk              (0x3U << RTC_ALRMAR_HT_Pos)             /*!< 0x00300000 */
13405 #define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk
13406 #define RTC_ALRMAR_HT_0                (0x1U << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
13407 #define RTC_ALRMAR_HT_1                (0x2U << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
13408 #define RTC_ALRMAR_HU_Pos              (16U)
13409 #define RTC_ALRMAR_HU_Msk              (0xFU << RTC_ALRMAR_HU_Pos)             /*!< 0x000F0000 */
13410 #define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk
13411 #define RTC_ALRMAR_HU_0                (0x1U << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
13412 #define RTC_ALRMAR_HU_1                (0x2U << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
13413 #define RTC_ALRMAR_HU_2                (0x4U << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
13414 #define RTC_ALRMAR_HU_3                (0x8U << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
13415 #define RTC_ALRMAR_MSK2_Pos            (15U)
13416 #define RTC_ALRMAR_MSK2_Msk            (0x1U << RTC_ALRMAR_MSK2_Pos)           /*!< 0x00008000 */
13417 #define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk
13418 #define RTC_ALRMAR_MNT_Pos             (12U)
13419 #define RTC_ALRMAR_MNT_Msk             (0x7U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00007000 */
13420 #define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk
13421 #define RTC_ALRMAR_MNT_0               (0x1U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
13422 #define RTC_ALRMAR_MNT_1               (0x2U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
13423 #define RTC_ALRMAR_MNT_2               (0x4U << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
13424 #define RTC_ALRMAR_MNU_Pos             (8U)
13425 #define RTC_ALRMAR_MNU_Msk             (0xFU << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000F00 */
13426 #define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk
13427 #define RTC_ALRMAR_MNU_0               (0x1U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
13428 #define RTC_ALRMAR_MNU_1               (0x2U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
13429 #define RTC_ALRMAR_MNU_2               (0x4U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
13430 #define RTC_ALRMAR_MNU_3               (0x8U << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
13431 #define RTC_ALRMAR_MSK1_Pos            (7U)
13432 #define RTC_ALRMAR_MSK1_Msk            (0x1U << RTC_ALRMAR_MSK1_Pos)           /*!< 0x00000080 */
13433 #define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk
13434 #define RTC_ALRMAR_ST_Pos              (4U)
13435 #define RTC_ALRMAR_ST_Msk              (0x7U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000070 */
13436 #define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk
13437 #define RTC_ALRMAR_ST_0                (0x1U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
13438 #define RTC_ALRMAR_ST_1                (0x2U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
13439 #define RTC_ALRMAR_ST_2                (0x4U << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
13440 #define RTC_ALRMAR_SU_Pos              (0U)
13441 #define RTC_ALRMAR_SU_Msk              (0xFU << RTC_ALRMAR_SU_Pos)             /*!< 0x0000000F */
13442 #define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk
13443 #define RTC_ALRMAR_SU_0                (0x1U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
13444 #define RTC_ALRMAR_SU_1                (0x2U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
13445 #define RTC_ALRMAR_SU_2                (0x4U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
13446 #define RTC_ALRMAR_SU_3                (0x8U << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
13447 
13448 /********************  Bits definition for RTC_ALRMBR register  ***************/
13449 #define RTC_ALRMBR_MSK4_Pos            (31U)
13450 #define RTC_ALRMBR_MSK4_Msk            (0x1U << RTC_ALRMBR_MSK4_Pos)           /*!< 0x80000000 */
13451 #define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk
13452 #define RTC_ALRMBR_WDSEL_Pos           (30U)
13453 #define RTC_ALRMBR_WDSEL_Msk           (0x1U << RTC_ALRMBR_WDSEL_Pos)          /*!< 0x40000000 */
13454 #define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk
13455 #define RTC_ALRMBR_DT_Pos              (28U)
13456 #define RTC_ALRMBR_DT_Msk              (0x3U << RTC_ALRMBR_DT_Pos)             /*!< 0x30000000 */
13457 #define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk
13458 #define RTC_ALRMBR_DT_0                (0x1U << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
13459 #define RTC_ALRMBR_DT_1                (0x2U << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
13460 #define RTC_ALRMBR_DU_Pos              (24U)
13461 #define RTC_ALRMBR_DU_Msk              (0xFU << RTC_ALRMBR_DU_Pos)             /*!< 0x0F000000 */
13462 #define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk
13463 #define RTC_ALRMBR_DU_0                (0x1U << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
13464 #define RTC_ALRMBR_DU_1                (0x2U << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
13465 #define RTC_ALRMBR_DU_2                (0x4U << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
13466 #define RTC_ALRMBR_DU_3                (0x8U << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
13467 #define RTC_ALRMBR_MSK3_Pos            (23U)
13468 #define RTC_ALRMBR_MSK3_Msk            (0x1U << RTC_ALRMBR_MSK3_Pos)           /*!< 0x00800000 */
13469 #define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk
13470 #define RTC_ALRMBR_PM_Pos              (22U)
13471 #define RTC_ALRMBR_PM_Msk              (0x1U << RTC_ALRMBR_PM_Pos)             /*!< 0x00400000 */
13472 #define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk
13473 #define RTC_ALRMBR_HT_Pos              (20U)
13474 #define RTC_ALRMBR_HT_Msk              (0x3U << RTC_ALRMBR_HT_Pos)             /*!< 0x00300000 */
13475 #define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk
13476 #define RTC_ALRMBR_HT_0                (0x1U << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
13477 #define RTC_ALRMBR_HT_1                (0x2U << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
13478 #define RTC_ALRMBR_HU_Pos              (16U)
13479 #define RTC_ALRMBR_HU_Msk              (0xFU << RTC_ALRMBR_HU_Pos)             /*!< 0x000F0000 */
13480 #define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk
13481 #define RTC_ALRMBR_HU_0                (0x1U << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
13482 #define RTC_ALRMBR_HU_1                (0x2U << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
13483 #define RTC_ALRMBR_HU_2                (0x4U << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
13484 #define RTC_ALRMBR_HU_3                (0x8U << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
13485 #define RTC_ALRMBR_MSK2_Pos            (15U)
13486 #define RTC_ALRMBR_MSK2_Msk            (0x1U << RTC_ALRMBR_MSK2_Pos)           /*!< 0x00008000 */
13487 #define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk
13488 #define RTC_ALRMBR_MNT_Pos             (12U)
13489 #define RTC_ALRMBR_MNT_Msk             (0x7U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00007000 */
13490 #define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk
13491 #define RTC_ALRMBR_MNT_0               (0x1U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
13492 #define RTC_ALRMBR_MNT_1               (0x2U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
13493 #define RTC_ALRMBR_MNT_2               (0x4U << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
13494 #define RTC_ALRMBR_MNU_Pos             (8U)
13495 #define RTC_ALRMBR_MNU_Msk             (0xFU << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000F00 */
13496 #define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk
13497 #define RTC_ALRMBR_MNU_0               (0x1U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
13498 #define RTC_ALRMBR_MNU_1               (0x2U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
13499 #define RTC_ALRMBR_MNU_2               (0x4U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
13500 #define RTC_ALRMBR_MNU_3               (0x8U << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
13501 #define RTC_ALRMBR_MSK1_Pos            (7U)
13502 #define RTC_ALRMBR_MSK1_Msk            (0x1U << RTC_ALRMBR_MSK1_Pos)           /*!< 0x00000080 */
13503 #define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk
13504 #define RTC_ALRMBR_ST_Pos              (4U)
13505 #define RTC_ALRMBR_ST_Msk              (0x7U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000070 */
13506 #define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk
13507 #define RTC_ALRMBR_ST_0                (0x1U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
13508 #define RTC_ALRMBR_ST_1                (0x2U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
13509 #define RTC_ALRMBR_ST_2                (0x4U << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
13510 #define RTC_ALRMBR_SU_Pos              (0U)
13511 #define RTC_ALRMBR_SU_Msk              (0xFU << RTC_ALRMBR_SU_Pos)             /*!< 0x0000000F */
13512 #define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk
13513 #define RTC_ALRMBR_SU_0                (0x1U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
13514 #define RTC_ALRMBR_SU_1                (0x2U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
13515 #define RTC_ALRMBR_SU_2                (0x4U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
13516 #define RTC_ALRMBR_SU_3                (0x8U << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
13517 
13518 /********************  Bits definition for RTC_WPR register  ******************/
13519 #define RTC_WPR_KEY_Pos                (0U)
13520 #define RTC_WPR_KEY_Msk                (0xFFU << RTC_WPR_KEY_Pos)              /*!< 0x000000FF */
13521 #define RTC_WPR_KEY                    RTC_WPR_KEY_Msk
13522 
13523 /********************  Bits definition for RTC_SSR register  ******************/
13524 #define RTC_SSR_SS_Pos                 (0U)
13525 #define RTC_SSR_SS_Msk                 (0xFFFFU << RTC_SSR_SS_Pos)             /*!< 0x0000FFFF */
13526 #define RTC_SSR_SS                     RTC_SSR_SS_Msk
13527 
13528 /********************  Bits definition for RTC_SHIFTR register  ***************/
13529 #define RTC_SHIFTR_SUBFS_Pos           (0U)
13530 #define RTC_SHIFTR_SUBFS_Msk           (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)       /*!< 0x00007FFF */
13531 #define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk
13532 #define RTC_SHIFTR_ADD1S_Pos           (31U)
13533 #define RTC_SHIFTR_ADD1S_Msk           (0x1U << RTC_SHIFTR_ADD1S_Pos)          /*!< 0x80000000 */
13534 #define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk
13535 
13536 /********************  Bits definition for RTC_TSTR register  *****************/
13537 #define RTC_TSTR_PM_Pos                (22U)
13538 #define RTC_TSTR_PM_Msk                (0x1U << RTC_TSTR_PM_Pos)               /*!< 0x00400000 */
13539 #define RTC_TSTR_PM                    RTC_TSTR_PM_Msk
13540 #define RTC_TSTR_HT_Pos                (20U)
13541 #define RTC_TSTR_HT_Msk                (0x3U << RTC_TSTR_HT_Pos)               /*!< 0x00300000 */
13542 #define RTC_TSTR_HT                    RTC_TSTR_HT_Msk
13543 #define RTC_TSTR_HT_0                  (0x1U << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
13544 #define RTC_TSTR_HT_1                  (0x2U << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
13545 #define RTC_TSTR_HU_Pos                (16U)
13546 #define RTC_TSTR_HU_Msk                (0xFU << RTC_TSTR_HU_Pos)               /*!< 0x000F0000 */
13547 #define RTC_TSTR_HU                    RTC_TSTR_HU_Msk
13548 #define RTC_TSTR_HU_0                  (0x1U << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
13549 #define RTC_TSTR_HU_1                  (0x2U << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
13550 #define RTC_TSTR_HU_2                  (0x4U << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
13551 #define RTC_TSTR_HU_3                  (0x8U << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
13552 #define RTC_TSTR_MNT_Pos               (12U)
13553 #define RTC_TSTR_MNT_Msk               (0x7U << RTC_TSTR_MNT_Pos)              /*!< 0x00007000 */
13554 #define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk
13555 #define RTC_TSTR_MNT_0                 (0x1U << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
13556 #define RTC_TSTR_MNT_1                 (0x2U << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
13557 #define RTC_TSTR_MNT_2                 (0x4U << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
13558 #define RTC_TSTR_MNU_Pos               (8U)
13559 #define RTC_TSTR_MNU_Msk               (0xFU << RTC_TSTR_MNU_Pos)              /*!< 0x00000F00 */
13560 #define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk
13561 #define RTC_TSTR_MNU_0                 (0x1U << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
13562 #define RTC_TSTR_MNU_1                 (0x2U << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
13563 #define RTC_TSTR_MNU_2                 (0x4U << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
13564 #define RTC_TSTR_MNU_3                 (0x8U << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
13565 #define RTC_TSTR_ST_Pos                (4U)
13566 #define RTC_TSTR_ST_Msk                (0x7U << RTC_TSTR_ST_Pos)               /*!< 0x00000070 */
13567 #define RTC_TSTR_ST                    RTC_TSTR_ST_Msk
13568 #define RTC_TSTR_ST_0                  (0x1U << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
13569 #define RTC_TSTR_ST_1                  (0x2U << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
13570 #define RTC_TSTR_ST_2                  (0x4U << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
13571 #define RTC_TSTR_SU_Pos                (0U)
13572 #define RTC_TSTR_SU_Msk                (0xFU << RTC_TSTR_SU_Pos)               /*!< 0x0000000F */
13573 #define RTC_TSTR_SU                    RTC_TSTR_SU_Msk
13574 #define RTC_TSTR_SU_0                  (0x1U << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
13575 #define RTC_TSTR_SU_1                  (0x2U << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
13576 #define RTC_TSTR_SU_2                  (0x4U << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
13577 #define RTC_TSTR_SU_3                  (0x8U << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
13578 
13579 /********************  Bits definition for RTC_TSDR register  *****************/
13580 #define RTC_TSDR_WDU_Pos               (13U)
13581 #define RTC_TSDR_WDU_Msk               (0x7U << RTC_TSDR_WDU_Pos)              /*!< 0x0000E000 */
13582 #define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk
13583 #define RTC_TSDR_WDU_0                 (0x1U << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
13584 #define RTC_TSDR_WDU_1                 (0x2U << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
13585 #define RTC_TSDR_WDU_2                 (0x4U << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
13586 #define RTC_TSDR_MT_Pos                (12U)
13587 #define RTC_TSDR_MT_Msk                (0x1U << RTC_TSDR_MT_Pos)               /*!< 0x00001000 */
13588 #define RTC_TSDR_MT                    RTC_TSDR_MT_Msk
13589 #define RTC_TSDR_MU_Pos                (8U)
13590 #define RTC_TSDR_MU_Msk                (0xFU << RTC_TSDR_MU_Pos)               /*!< 0x00000F00 */
13591 #define RTC_TSDR_MU                    RTC_TSDR_MU_Msk
13592 #define RTC_TSDR_MU_0                  (0x1U << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
13593 #define RTC_TSDR_MU_1                  (0x2U << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
13594 #define RTC_TSDR_MU_2                  (0x4U << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
13595 #define RTC_TSDR_MU_3                  (0x8U << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
13596 #define RTC_TSDR_DT_Pos                (4U)
13597 #define RTC_TSDR_DT_Msk                (0x3U << RTC_TSDR_DT_Pos)               /*!< 0x00000030 */
13598 #define RTC_TSDR_DT                    RTC_TSDR_DT_Msk
13599 #define RTC_TSDR_DT_0                  (0x1U << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
13600 #define RTC_TSDR_DT_1                  (0x2U << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
13601 #define RTC_TSDR_DU_Pos                (0U)
13602 #define RTC_TSDR_DU_Msk                (0xFU << RTC_TSDR_DU_Pos)               /*!< 0x0000000F */
13603 #define RTC_TSDR_DU                    RTC_TSDR_DU_Msk
13604 #define RTC_TSDR_DU_0                  (0x1U << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
13605 #define RTC_TSDR_DU_1                  (0x2U << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
13606 #define RTC_TSDR_DU_2                  (0x4U << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
13607 #define RTC_TSDR_DU_3                  (0x8U << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
13608 
13609 /********************  Bits definition for RTC_TSSSR register  ****************/
13610 #define RTC_TSSSR_SS_Pos               (0U)
13611 #define RTC_TSSSR_SS_Msk               (0xFFFFU << RTC_TSSSR_SS_Pos)           /*!< 0x0000FFFF */
13612 #define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
13613 
13614 /********************  Bits definition for RTC_CAL register  *****************/
13615 #define RTC_CALR_CALP_Pos              (15U)
13616 #define RTC_CALR_CALP_Msk              (0x1U << RTC_CALR_CALP_Pos)             /*!< 0x00008000 */
13617 #define RTC_CALR_CALP                  RTC_CALR_CALP_Msk
13618 #define RTC_CALR_CALW8_Pos             (14U)
13619 #define RTC_CALR_CALW8_Msk             (0x1U << RTC_CALR_CALW8_Pos)            /*!< 0x00004000 */
13620 #define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk
13621 #define RTC_CALR_CALW16_Pos            (13U)
13622 #define RTC_CALR_CALW16_Msk            (0x1U << RTC_CALR_CALW16_Pos)           /*!< 0x00002000 */
13623 #define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk
13624 #define RTC_CALR_CALM_Pos              (0U)
13625 #define RTC_CALR_CALM_Msk              (0x1FFU << RTC_CALR_CALM_Pos)           /*!< 0x000001FF */
13626 #define RTC_CALR_CALM                  RTC_CALR_CALM_Msk
13627 #define RTC_CALR_CALM_0                (0x001U << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
13628 #define RTC_CALR_CALM_1                (0x002U << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
13629 #define RTC_CALR_CALM_2                (0x004U << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
13630 #define RTC_CALR_CALM_3                (0x008U << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
13631 #define RTC_CALR_CALM_4                (0x010U << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
13632 #define RTC_CALR_CALM_5                (0x020U << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
13633 #define RTC_CALR_CALM_6                (0x040U << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
13634 #define RTC_CALR_CALM_7                (0x080U << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
13635 #define RTC_CALR_CALM_8                (0x100U << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
13636 
13637 /********************  Bits definition for RTC_TAMPCR register  ***************/
13638 #define RTC_TAMPCR_TAMP3MF_Pos         (24U)
13639 #define RTC_TAMPCR_TAMP3MF_Msk         (0x1U << RTC_TAMPCR_TAMP3MF_Pos)        /*!< 0x01000000 */
13640 #define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk
13641 #define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)
13642 #define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos)   /*!< 0x00800000 */
13643 #define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk
13644 #define RTC_TAMPCR_TAMP3IE_Pos         (22U)
13645 #define RTC_TAMPCR_TAMP3IE_Msk         (0x1U << RTC_TAMPCR_TAMP3IE_Pos)        /*!< 0x00400000 */
13646 #define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk
13647 #define RTC_TAMPCR_TAMP2MF_Pos         (21U)
13648 #define RTC_TAMPCR_TAMP2MF_Msk         (0x1U << RTC_TAMPCR_TAMP2MF_Pos)        /*!< 0x00200000 */
13649 #define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk
13650 #define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
13651 #define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos)   /*!< 0x00100000 */
13652 #define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk
13653 #define RTC_TAMPCR_TAMP2IE_Pos         (19U)
13654 #define RTC_TAMPCR_TAMP2IE_Msk         (0x1U << RTC_TAMPCR_TAMP2IE_Pos)        /*!< 0x00080000 */
13655 #define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk
13656 #define RTC_TAMPCR_TAMP1MF_Pos         (18U)
13657 #define RTC_TAMPCR_TAMP1MF_Msk         (0x1U << RTC_TAMPCR_TAMP1MF_Pos)        /*!< 0x00040000 */
13658 #define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk
13659 #define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)
13660 #define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos)   /*!< 0x00020000 */
13661 #define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk
13662 #define RTC_TAMPCR_TAMP1IE_Pos         (16U)
13663 #define RTC_TAMPCR_TAMP1IE_Msk         (0x1U << RTC_TAMPCR_TAMP1IE_Pos)        /*!< 0x00010000 */
13664 #define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk
13665 #define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
13666 #define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos)      /*!< 0x00008000 */
13667 #define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk
13668 #define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
13669 #define RTC_TAMPCR_TAMPPRCH_Msk        (0x3U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00006000 */
13670 #define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk
13671 #define RTC_TAMPCR_TAMPPRCH_0          (0x1U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
13672 #define RTC_TAMPCR_TAMPPRCH_1          (0x2U << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
13673 #define RTC_TAMPCR_TAMPFLT_Pos         (11U)
13674 #define RTC_TAMPCR_TAMPFLT_Msk         (0x3U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001800 */
13675 #define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk
13676 #define RTC_TAMPCR_TAMPFLT_0           (0x1U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
13677 #define RTC_TAMPCR_TAMPFLT_1           (0x2U << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
13678 #define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
13679 #define RTC_TAMPCR_TAMPFREQ_Msk        (0x7U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000700 */
13680 #define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk
13681 #define RTC_TAMPCR_TAMPFREQ_0          (0x1U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
13682 #define RTC_TAMPCR_TAMPFREQ_1          (0x2U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
13683 #define RTC_TAMPCR_TAMPFREQ_2          (0x4U << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
13684 #define RTC_TAMPCR_TAMPTS_Pos          (7U)
13685 #define RTC_TAMPCR_TAMPTS_Msk          (0x1U << RTC_TAMPCR_TAMPTS_Pos)         /*!< 0x00000080 */
13686 #define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk
13687 #define RTC_TAMPCR_TAMP3TRG_Pos        (6U)
13688 #define RTC_TAMPCR_TAMP3TRG_Msk        (0x1U << RTC_TAMPCR_TAMP3TRG_Pos)       /*!< 0x00000040 */
13689 #define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk
13690 #define RTC_TAMPCR_TAMP3E_Pos          (5U)
13691 #define RTC_TAMPCR_TAMP3E_Msk          (0x1U << RTC_TAMPCR_TAMP3E_Pos)         /*!< 0x00000020 */
13692 #define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk
13693 #define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
13694 #define RTC_TAMPCR_TAMP2TRG_Msk        (0x1U << RTC_TAMPCR_TAMP2TRG_Pos)       /*!< 0x00000010 */
13695 #define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk
13696 #define RTC_TAMPCR_TAMP2E_Pos          (3U)
13697 #define RTC_TAMPCR_TAMP2E_Msk          (0x1U << RTC_TAMPCR_TAMP2E_Pos)         /*!< 0x00000008 */
13698 #define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk
13699 #define RTC_TAMPCR_TAMPIE_Pos          (2U)
13700 #define RTC_TAMPCR_TAMPIE_Msk          (0x1U << RTC_TAMPCR_TAMPIE_Pos)         /*!< 0x00000004 */
13701 #define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk
13702 #define RTC_TAMPCR_TAMP1TRG_Pos        (1U)
13703 #define RTC_TAMPCR_TAMP1TRG_Msk        (0x1U << RTC_TAMPCR_TAMP1TRG_Pos)       /*!< 0x00000002 */
13704 #define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk
13705 #define RTC_TAMPCR_TAMP1E_Pos          (0U)
13706 #define RTC_TAMPCR_TAMP1E_Msk          (0x1U << RTC_TAMPCR_TAMP1E_Pos)         /*!< 0x00000001 */
13707 #define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk
13708 
13709 /********************  Bits definition for RTC_ALRMASSR register  *************/
13710 #define RTC_ALRMASSR_MASKSS_Pos        (24U)
13711 #define RTC_ALRMASSR_MASKSS_Msk        (0xFU << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x0F000000 */
13712 #define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
13713 #define RTC_ALRMASSR_MASKSS_0          (0x1U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
13714 #define RTC_ALRMASSR_MASKSS_1          (0x2U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
13715 #define RTC_ALRMASSR_MASKSS_2          (0x4U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
13716 #define RTC_ALRMASSR_MASKSS_3          (0x8U << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
13717 #define RTC_ALRMASSR_SS_Pos            (0U)
13718 #define RTC_ALRMASSR_SS_Msk            (0x7FFFU << RTC_ALRMASSR_SS_Pos)        /*!< 0x00007FFF */
13719 #define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
13720 
13721 /********************  Bits definition for RTC_ALRMBSSR register  *************/
13722 #define RTC_ALRMBSSR_MASKSS_Pos        (24U)
13723 #define RTC_ALRMBSSR_MASKSS_Msk        (0xFU << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
13724 #define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
13725 #define RTC_ALRMBSSR_MASKSS_0          (0x1U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
13726 #define RTC_ALRMBSSR_MASKSS_1          (0x2U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
13727 #define RTC_ALRMBSSR_MASKSS_2          (0x4U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
13728 #define RTC_ALRMBSSR_MASKSS_3          (0x8U << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
13729 #define RTC_ALRMBSSR_SS_Pos            (0U)
13730 #define RTC_ALRMBSSR_SS_Msk            (0x7FFFU << RTC_ALRMBSSR_SS_Pos)        /*!< 0x00007FFF */
13731 #define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
13732 
13733 /********************  Bits definition for RTC_0R register  *******************/
13734 #define RTC_OR_OUT_RMP_Pos             (1U)
13735 #define RTC_OR_OUT_RMP_Msk             (0x1U << RTC_OR_OUT_RMP_Pos)            /*!< 0x00000002 */
13736 #define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk
13737 #define RTC_OR_ALARMOUTTYPE_Pos        (0U)
13738 #define RTC_OR_ALARMOUTTYPE_Msk        (0x1U << RTC_OR_ALARMOUTTYPE_Pos)       /*!< 0x00000001 */
13739 #define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk
13740 
13741 
13742 /********************  Bits definition for RTC_BKP0R register  ****************/
13743 #define RTC_BKP0R_Pos                  (0U)
13744 #define RTC_BKP0R_Msk                  (0xFFFFFFFFU << RTC_BKP0R_Pos)          /*!< 0xFFFFFFFF */
13745 #define RTC_BKP0R                      RTC_BKP0R_Msk
13746 
13747 /********************  Bits definition for RTC_BKP1R register  ****************/
13748 #define RTC_BKP1R_Pos                  (0U)
13749 #define RTC_BKP1R_Msk                  (0xFFFFFFFFU << RTC_BKP1R_Pos)          /*!< 0xFFFFFFFF */
13750 #define RTC_BKP1R                      RTC_BKP1R_Msk
13751 
13752 /********************  Bits definition for RTC_BKP2R register  ****************/
13753 #define RTC_BKP2R_Pos                  (0U)
13754 #define RTC_BKP2R_Msk                  (0xFFFFFFFFU << RTC_BKP2R_Pos)          /*!< 0xFFFFFFFF */
13755 #define RTC_BKP2R                      RTC_BKP2R_Msk
13756 
13757 /********************  Bits definition for RTC_BKP3R register  ****************/
13758 #define RTC_BKP3R_Pos                  (0U)
13759 #define RTC_BKP3R_Msk                  (0xFFFFFFFFU << RTC_BKP3R_Pos)          /*!< 0xFFFFFFFF */
13760 #define RTC_BKP3R                      RTC_BKP3R_Msk
13761 
13762 /********************  Bits definition for RTC_BKP4R register  ****************/
13763 #define RTC_BKP4R_Pos                  (0U)
13764 #define RTC_BKP4R_Msk                  (0xFFFFFFFFU << RTC_BKP4R_Pos)          /*!< 0xFFFFFFFF */
13765 #define RTC_BKP4R                      RTC_BKP4R_Msk
13766 
13767 /********************  Bits definition for RTC_BKP5R register  ****************/
13768 #define RTC_BKP5R_Pos                  (0U)
13769 #define RTC_BKP5R_Msk                  (0xFFFFFFFFU << RTC_BKP5R_Pos)          /*!< 0xFFFFFFFF */
13770 #define RTC_BKP5R                      RTC_BKP5R_Msk
13771 
13772 /********************  Bits definition for RTC_BKP6R register  ****************/
13773 #define RTC_BKP6R_Pos                  (0U)
13774 #define RTC_BKP6R_Msk                  (0xFFFFFFFFU << RTC_BKP6R_Pos)          /*!< 0xFFFFFFFF */
13775 #define RTC_BKP6R                      RTC_BKP6R_Msk
13776 
13777 /********************  Bits definition for RTC_BKP7R register  ****************/
13778 #define RTC_BKP7R_Pos                  (0U)
13779 #define RTC_BKP7R_Msk                  (0xFFFFFFFFU << RTC_BKP7R_Pos)          /*!< 0xFFFFFFFF */
13780 #define RTC_BKP7R                      RTC_BKP7R_Msk
13781 
13782 /********************  Bits definition for RTC_BKP8R register  ****************/
13783 #define RTC_BKP8R_Pos                  (0U)
13784 #define RTC_BKP8R_Msk                  (0xFFFFFFFFU << RTC_BKP8R_Pos)          /*!< 0xFFFFFFFF */
13785 #define RTC_BKP8R                      RTC_BKP8R_Msk
13786 
13787 /********************  Bits definition for RTC_BKP9R register  ****************/
13788 #define RTC_BKP9R_Pos                  (0U)
13789 #define RTC_BKP9R_Msk                  (0xFFFFFFFFU << RTC_BKP9R_Pos)          /*!< 0xFFFFFFFF */
13790 #define RTC_BKP9R                      RTC_BKP9R_Msk
13791 
13792 /********************  Bits definition for RTC_BKP10R register  ***************/
13793 #define RTC_BKP10R_Pos                 (0U)
13794 #define RTC_BKP10R_Msk                 (0xFFFFFFFFU << RTC_BKP10R_Pos)         /*!< 0xFFFFFFFF */
13795 #define RTC_BKP10R                     RTC_BKP10R_Msk
13796 
13797 /********************  Bits definition for RTC_BKP11R register  ***************/
13798 #define RTC_BKP11R_Pos                 (0U)
13799 #define RTC_BKP11R_Msk                 (0xFFFFFFFFU << RTC_BKP11R_Pos)         /*!< 0xFFFFFFFF */
13800 #define RTC_BKP11R                     RTC_BKP11R_Msk
13801 
13802 /********************  Bits definition for RTC_BKP12R register  ***************/
13803 #define RTC_BKP12R_Pos                 (0U)
13804 #define RTC_BKP12R_Msk                 (0xFFFFFFFFU << RTC_BKP12R_Pos)         /*!< 0xFFFFFFFF */
13805 #define RTC_BKP12R                     RTC_BKP12R_Msk
13806 
13807 /********************  Bits definition for RTC_BKP13R register  ***************/
13808 #define RTC_BKP13R_Pos                 (0U)
13809 #define RTC_BKP13R_Msk                 (0xFFFFFFFFU << RTC_BKP13R_Pos)         /*!< 0xFFFFFFFF */
13810 #define RTC_BKP13R                     RTC_BKP13R_Msk
13811 
13812 /********************  Bits definition for RTC_BKP14R register  ***************/
13813 #define RTC_BKP14R_Pos                 (0U)
13814 #define RTC_BKP14R_Msk                 (0xFFFFFFFFU << RTC_BKP14R_Pos)         /*!< 0xFFFFFFFF */
13815 #define RTC_BKP14R                     RTC_BKP14R_Msk
13816 
13817 /********************  Bits definition for RTC_BKP15R register  ***************/
13818 #define RTC_BKP15R_Pos                 (0U)
13819 #define RTC_BKP15R_Msk                 (0xFFFFFFFFU << RTC_BKP15R_Pos)         /*!< 0xFFFFFFFF */
13820 #define RTC_BKP15R                     RTC_BKP15R_Msk
13821 
13822 /********************  Bits definition for RTC_BKP16R register  ***************/
13823 #define RTC_BKP16R_Pos                 (0U)
13824 #define RTC_BKP16R_Msk                 (0xFFFFFFFFU << RTC_BKP16R_Pos)         /*!< 0xFFFFFFFF */
13825 #define RTC_BKP16R                     RTC_BKP16R_Msk
13826 
13827 /********************  Bits definition for RTC_BKP17R register  ***************/
13828 #define RTC_BKP17R_Pos                 (0U)
13829 #define RTC_BKP17R_Msk                 (0xFFFFFFFFU << RTC_BKP17R_Pos)         /*!< 0xFFFFFFFF */
13830 #define RTC_BKP17R                     RTC_BKP17R_Msk
13831 
13832 /********************  Bits definition for RTC_BKP18R register  ***************/
13833 #define RTC_BKP18R_Pos                 (0U)
13834 #define RTC_BKP18R_Msk                 (0xFFFFFFFFU << RTC_BKP18R_Pos)         /*!< 0xFFFFFFFF */
13835 #define RTC_BKP18R                     RTC_BKP18R_Msk
13836 
13837 /********************  Bits definition for RTC_BKP19R register  ***************/
13838 #define RTC_BKP19R_Pos                 (0U)
13839 #define RTC_BKP19R_Msk                 (0xFFFFFFFFU << RTC_BKP19R_Pos)         /*!< 0xFFFFFFFF */
13840 #define RTC_BKP19R                     RTC_BKP19R_Msk
13841 
13842 /********************  Bits definition for RTC_BKP20R register  ***************/
13843 #define RTC_BKP20R_Pos                 (0U)
13844 #define RTC_BKP20R_Msk                 (0xFFFFFFFFU << RTC_BKP20R_Pos)         /*!< 0xFFFFFFFF */
13845 #define RTC_BKP20R                     RTC_BKP20R_Msk
13846 
13847 /********************  Bits definition for RTC_BKP21R register  ***************/
13848 #define RTC_BKP21R_Pos                 (0U)
13849 #define RTC_BKP21R_Msk                 (0xFFFFFFFFU << RTC_BKP21R_Pos)         /*!< 0xFFFFFFFF */
13850 #define RTC_BKP21R                     RTC_BKP21R_Msk
13851 
13852 /********************  Bits definition for RTC_BKP22R register  ***************/
13853 #define RTC_BKP22R_Pos                 (0U)
13854 #define RTC_BKP22R_Msk                 (0xFFFFFFFFU << RTC_BKP22R_Pos)         /*!< 0xFFFFFFFF */
13855 #define RTC_BKP22R                     RTC_BKP22R_Msk
13856 
13857 /********************  Bits definition for RTC_BKP23R register  ***************/
13858 #define RTC_BKP23R_Pos                 (0U)
13859 #define RTC_BKP23R_Msk                 (0xFFFFFFFFU << RTC_BKP23R_Pos)         /*!< 0xFFFFFFFF */
13860 #define RTC_BKP23R                     RTC_BKP23R_Msk
13861 
13862 /********************  Bits definition for RTC_BKP24R register  ***************/
13863 #define RTC_BKP24R_Pos                 (0U)
13864 #define RTC_BKP24R_Msk                 (0xFFFFFFFFU << RTC_BKP24R_Pos)         /*!< 0xFFFFFFFF */
13865 #define RTC_BKP24R                     RTC_BKP24R_Msk
13866 
13867 /********************  Bits definition for RTC_BKP25R register  ***************/
13868 #define RTC_BKP25R_Pos                 (0U)
13869 #define RTC_BKP25R_Msk                 (0xFFFFFFFFU << RTC_BKP25R_Pos)         /*!< 0xFFFFFFFF */
13870 #define RTC_BKP25R                     RTC_BKP25R_Msk
13871 
13872 /********************  Bits definition for RTC_BKP26R register  ***************/
13873 #define RTC_BKP26R_Pos                 (0U)
13874 #define RTC_BKP26R_Msk                 (0xFFFFFFFFU << RTC_BKP26R_Pos)         /*!< 0xFFFFFFFF */
13875 #define RTC_BKP26R                     RTC_BKP26R_Msk
13876 
13877 /********************  Bits definition for RTC_BKP27R register  ***************/
13878 #define RTC_BKP27R_Pos                 (0U)
13879 #define RTC_BKP27R_Msk                 (0xFFFFFFFFU << RTC_BKP27R_Pos)         /*!< 0xFFFFFFFF */
13880 #define RTC_BKP27R                     RTC_BKP27R_Msk
13881 
13882 /********************  Bits definition for RTC_BKP28R register  ***************/
13883 #define RTC_BKP28R_Pos                 (0U)
13884 #define RTC_BKP28R_Msk                 (0xFFFFFFFFU << RTC_BKP28R_Pos)         /*!< 0xFFFFFFFF */
13885 #define RTC_BKP28R                     RTC_BKP28R_Msk
13886 
13887 /********************  Bits definition for RTC_BKP29R register  ***************/
13888 #define RTC_BKP29R_Pos                 (0U)
13889 #define RTC_BKP29R_Msk                 (0xFFFFFFFFU << RTC_BKP29R_Pos)         /*!< 0xFFFFFFFF */
13890 #define RTC_BKP29R                     RTC_BKP29R_Msk
13891 
13892 /********************  Bits definition for RTC_BKP30R register  ***************/
13893 #define RTC_BKP30R_Pos                 (0U)
13894 #define RTC_BKP30R_Msk                 (0xFFFFFFFFU << RTC_BKP30R_Pos)         /*!< 0xFFFFFFFF */
13895 #define RTC_BKP30R                     RTC_BKP30R_Msk
13896 
13897 /********************  Bits definition for RTC_BKP31R register  ***************/
13898 #define RTC_BKP31R_Pos                 (0U)
13899 #define RTC_BKP31R_Msk                 (0xFFFFFFFFU << RTC_BKP31R_Pos)         /*!< 0xFFFFFFFF */
13900 #define RTC_BKP31R                     RTC_BKP31R_Msk
13901 
13902 /******************** Number of backup registers ******************************/
13903 #define RTC_BKP_NUMBER                       32U
13904 
13905 /******************************************************************************/
13906 /*                                                                            */
13907 /*                          Serial Audio Interface                            */
13908 /*                                                                            */
13909 /******************************************************************************/
13910 /********************  Bit definition for SAI_GCR register  *******************/
13911 #define SAI_GCR_SYNCIN_Pos         (0U)
13912 #define SAI_GCR_SYNCIN_Msk         (0x3U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000003 */
13913 #define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
13914 #define SAI_GCR_SYNCIN_0           (0x1U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
13915 #define SAI_GCR_SYNCIN_1           (0x2U << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
13916 
13917 #define SAI_GCR_SYNCOUT_Pos        (4U)
13918 #define SAI_GCR_SYNCOUT_Msk        (0x3U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000030 */
13919 #define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
13920 #define SAI_GCR_SYNCOUT_0          (0x1U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
13921 #define SAI_GCR_SYNCOUT_1          (0x2U << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
13922 
13923 /*******************  Bit definition for SAI_xCR1 register  *******************/
13924 #define SAI_xCR1_MODE_Pos          (0U)
13925 #define SAI_xCR1_MODE_Msk          (0x3U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000003 */
13926 #define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
13927 #define SAI_xCR1_MODE_0            (0x1U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
13928 #define SAI_xCR1_MODE_1            (0x2U << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
13929 
13930 #define SAI_xCR1_PRTCFG_Pos        (2U)
13931 #define SAI_xCR1_PRTCFG_Msk        (0x3U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x0000000C */
13932 #define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
13933 #define SAI_xCR1_PRTCFG_0          (0x1U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
13934 #define SAI_xCR1_PRTCFG_1          (0x2U << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
13935 
13936 #define SAI_xCR1_DS_Pos            (5U)
13937 #define SAI_xCR1_DS_Msk            (0x7U << SAI_xCR1_DS_Pos)                   /*!< 0x000000E0 */
13938 #define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
13939 #define SAI_xCR1_DS_0              (0x1U << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
13940 #define SAI_xCR1_DS_1              (0x2U << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
13941 #define SAI_xCR1_DS_2              (0x4U << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
13942 
13943 #define SAI_xCR1_LSBFIRST_Pos      (8U)
13944 #define SAI_xCR1_LSBFIRST_Msk      (0x1U << SAI_xCR1_LSBFIRST_Pos)             /*!< 0x00000100 */
13945 #define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
13946 #define SAI_xCR1_CKSTR_Pos         (9U)
13947 #define SAI_xCR1_CKSTR_Msk         (0x1U << SAI_xCR1_CKSTR_Pos)                /*!< 0x00000200 */
13948 #define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
13949 
13950 #define SAI_xCR1_SYNCEN_Pos        (10U)
13951 #define SAI_xCR1_SYNCEN_Msk        (0x3U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000C00 */
13952 #define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
13953 #define SAI_xCR1_SYNCEN_0          (0x1U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
13954 #define SAI_xCR1_SYNCEN_1          (0x2U << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
13955 
13956 #define SAI_xCR1_MONO_Pos          (12U)
13957 #define SAI_xCR1_MONO_Msk          (0x1U << SAI_xCR1_MONO_Pos)                 /*!< 0x00001000 */
13958 #define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
13959 #define SAI_xCR1_OUTDRIV_Pos       (13U)
13960 #define SAI_xCR1_OUTDRIV_Msk       (0x1U << SAI_xCR1_OUTDRIV_Pos)              /*!< 0x00002000 */
13961 #define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
13962 #define SAI_xCR1_SAIEN_Pos         (16U)
13963 #define SAI_xCR1_SAIEN_Msk         (0x1U << SAI_xCR1_SAIEN_Pos)                /*!< 0x00010000 */
13964 #define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
13965 #define SAI_xCR1_DMAEN_Pos         (17U)
13966 #define SAI_xCR1_DMAEN_Msk         (0x1U << SAI_xCR1_DMAEN_Pos)                /*!< 0x00020000 */
13967 #define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
13968 #define SAI_xCR1_NODIV_Pos         (19U)
13969 #define SAI_xCR1_NODIV_Msk         (0x1U << SAI_xCR1_NODIV_Pos)                /*!< 0x00080000 */
13970 #define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
13971 
13972 #define SAI_xCR1_MCKDIV_Pos        (20U)
13973 #define SAI_xCR1_MCKDIV_Msk        (0xFU << SAI_xCR1_MCKDIV_Pos)               /*!< 0x00F00000 */
13974 #define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[3:0] (Master ClocK Divider)  */
13975 #define SAI_xCR1_MCKDIV_0          (0x00100000U)                               /*!<Bit 0  */
13976 #define SAI_xCR1_MCKDIV_1          (0x00200000U)                               /*!<Bit 1  */
13977 #define SAI_xCR1_MCKDIV_2          (0x00400000U)                               /*!<Bit 2  */
13978 #define SAI_xCR1_MCKDIV_3          (0x00800000U)                               /*!<Bit 3  */
13979 
13980 /*******************  Bit definition for SAI_xCR2 register  *******************/
13981 #define SAI_xCR2_FTH_Pos           (0U)
13982 #define SAI_xCR2_FTH_Msk           (0x7U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000007 */
13983 #define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
13984 #define SAI_xCR2_FTH_0             (0x1U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
13985 #define SAI_xCR2_FTH_1             (0x2U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
13986 #define SAI_xCR2_FTH_2             (0x4U << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
13987 
13988 #define SAI_xCR2_FFLUSH_Pos        (3U)
13989 #define SAI_xCR2_FFLUSH_Msk        (0x1U << SAI_xCR2_FFLUSH_Pos)               /*!< 0x00000008 */
13990 #define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
13991 #define SAI_xCR2_TRIS_Pos          (4U)
13992 #define SAI_xCR2_TRIS_Msk          (0x1U << SAI_xCR2_TRIS_Pos)                 /*!< 0x00000010 */
13993 #define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
13994 #define SAI_xCR2_MUTE_Pos          (5U)
13995 #define SAI_xCR2_MUTE_Msk          (0x1U << SAI_xCR2_MUTE_Pos)                 /*!< 0x00000020 */
13996 #define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
13997 #define SAI_xCR2_MUTEVAL_Pos       (6U)
13998 #define SAI_xCR2_MUTEVAL_Msk       (0x1U << SAI_xCR2_MUTEVAL_Pos)              /*!< 0x00000040 */
13999 #define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
14000 
14001 
14002 #define SAI_xCR2_MUTECNT_Pos       (7U)
14003 #define SAI_xCR2_MUTECNT_Msk       (0x3FU << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001F80 */
14004 #define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
14005 #define SAI_xCR2_MUTECNT_0         (0x01U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
14006 #define SAI_xCR2_MUTECNT_1         (0x02U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
14007 #define SAI_xCR2_MUTECNT_2         (0x04U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
14008 #define SAI_xCR2_MUTECNT_3         (0x08U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
14009 #define SAI_xCR2_MUTECNT_4         (0x10U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
14010 #define SAI_xCR2_MUTECNT_5         (0x20U << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
14011 
14012 #define SAI_xCR2_CPL_Pos           (13U)
14013 #define SAI_xCR2_CPL_Msk           (0x1U << SAI_xCR2_CPL_Pos)                  /*!< 0x00002000 */
14014 #define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!<CPL mode                    */
14015 #define SAI_xCR2_COMP_Pos          (14U)
14016 #define SAI_xCR2_COMP_Msk          (0x3U << SAI_xCR2_COMP_Pos)                 /*!< 0x0000C000 */
14017 #define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
14018 #define SAI_xCR2_COMP_0            (0x1U << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
14019 #define SAI_xCR2_COMP_1            (0x2U << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
14020 
14021 
14022 /******************  Bit definition for SAI_xFRCR register  *******************/
14023 #define SAI_xFRCR_FRL_Pos          (0U)
14024 #define SAI_xFRCR_FRL_Msk          (0xFFU << SAI_xFRCR_FRL_Pos)                /*!< 0x000000FF */
14025 #define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](Frame length)  */
14026 #define SAI_xFRCR_FRL_0            (0x01U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
14027 #define SAI_xFRCR_FRL_1            (0x02U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
14028 #define SAI_xFRCR_FRL_2            (0x04U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
14029 #define SAI_xFRCR_FRL_3            (0x08U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
14030 #define SAI_xFRCR_FRL_4            (0x10U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
14031 #define SAI_xFRCR_FRL_5            (0x20U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
14032 #define SAI_xFRCR_FRL_6            (0x40U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
14033 #define SAI_xFRCR_FRL_7            (0x80U << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
14034 
14035 #define SAI_xFRCR_FSALL_Pos        (8U)
14036 #define SAI_xFRCR_FSALL_Msk        (0x7FU << SAI_xFRCR_FSALL_Pos)              /*!< 0x00007F00 */
14037 #define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FRL[6:0] (Frame synchronization active level length)  */
14038 #define SAI_xFRCR_FSALL_0          (0x01U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
14039 #define SAI_xFRCR_FSALL_1          (0x02U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
14040 #define SAI_xFRCR_FSALL_2          (0x04U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
14041 #define SAI_xFRCR_FSALL_3          (0x08U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
14042 #define SAI_xFRCR_FSALL_4          (0x10U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
14043 #define SAI_xFRCR_FSALL_5          (0x20U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
14044 #define SAI_xFRCR_FSALL_6          (0x40U << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
14045 
14046 #define SAI_xFRCR_FSDEF_Pos        (16U)
14047 #define SAI_xFRCR_FSDEF_Msk        (0x1U << SAI_xFRCR_FSDEF_Pos)               /*!< 0x00010000 */
14048 #define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!< Frame Synchronization Definition */
14049 #define SAI_xFRCR_FSPOL_Pos        (17U)
14050 #define SAI_xFRCR_FSPOL_Msk        (0x1U << SAI_xFRCR_FSPOL_Pos)               /*!< 0x00020000 */
14051 #define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
14052 #define SAI_xFRCR_FSOFF_Pos        (18U)
14053 #define SAI_xFRCR_FSOFF_Msk        (0x1U << SAI_xFRCR_FSOFF_Pos)               /*!< 0x00040000 */
14054 #define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
14055 
14056 /******************  Bit definition for SAI_xSLOTR register  *******************/
14057 #define SAI_xSLOTR_FBOFF_Pos       (0U)
14058 #define SAI_xSLOTR_FBOFF_Msk       (0x1FU << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x0000001F */
14059 #define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FRL[4:0](First Bit Offset)  */
14060 #define SAI_xSLOTR_FBOFF_0         (0x01U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
14061 #define SAI_xSLOTR_FBOFF_1         (0x02U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
14062 #define SAI_xSLOTR_FBOFF_2         (0x04U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
14063 #define SAI_xSLOTR_FBOFF_3         (0x08U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
14064 #define SAI_xSLOTR_FBOFF_4         (0x10U << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
14065 
14066 #define SAI_xSLOTR_SLOTSZ_Pos      (6U)
14067 #define SAI_xSLOTR_SLOTSZ_Msk      (0x3U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x000000C0 */
14068 #define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
14069 #define SAI_xSLOTR_SLOTSZ_0        (0x1U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
14070 #define SAI_xSLOTR_SLOTSZ_1        (0x2U << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
14071 
14072 #define SAI_xSLOTR_NBSLOT_Pos      (8U)
14073 #define SAI_xSLOTR_NBSLOT_Msk      (0xFU << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000F00 */
14074 #define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
14075 #define SAI_xSLOTR_NBSLOT_0        (0x1U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
14076 #define SAI_xSLOTR_NBSLOT_1        (0x2U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
14077 #define SAI_xSLOTR_NBSLOT_2        (0x4U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
14078 #define SAI_xSLOTR_NBSLOT_3        (0x8U << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
14079 
14080 #define SAI_xSLOTR_SLOTEN_Pos      (16U)
14081 #define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos)          /*!< 0xFFFF0000 */
14082 #define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
14083 
14084 /*******************  Bit definition for SAI_xIMR register  *******************/
14085 #define SAI_xIMR_OVRUDRIE_Pos      (0U)
14086 #define SAI_xIMR_OVRUDRIE_Msk      (0x1U << SAI_xIMR_OVRUDRIE_Pos)             /*!< 0x00000001 */
14087 #define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
14088 #define SAI_xIMR_MUTEDETIE_Pos     (1U)
14089 #define SAI_xIMR_MUTEDETIE_Msk     (0x1U << SAI_xIMR_MUTEDETIE_Pos)            /*!< 0x00000002 */
14090 #define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
14091 #define SAI_xIMR_WCKCFGIE_Pos      (2U)
14092 #define SAI_xIMR_WCKCFGIE_Msk      (0x1U << SAI_xIMR_WCKCFGIE_Pos)             /*!< 0x00000004 */
14093 #define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
14094 #define SAI_xIMR_FREQIE_Pos        (3U)
14095 #define SAI_xIMR_FREQIE_Msk        (0x1U << SAI_xIMR_FREQIE_Pos)               /*!< 0x00000008 */
14096 #define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
14097 #define SAI_xIMR_CNRDYIE_Pos       (4U)
14098 #define SAI_xIMR_CNRDYIE_Msk       (0x1U << SAI_xIMR_CNRDYIE_Pos)              /*!< 0x00000010 */
14099 #define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
14100 #define SAI_xIMR_AFSDETIE_Pos      (5U)
14101 #define SAI_xIMR_AFSDETIE_Msk      (0x1U << SAI_xIMR_AFSDETIE_Pos)             /*!< 0x00000020 */
14102 #define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
14103 #define SAI_xIMR_LFSDETIE_Pos      (6U)
14104 #define SAI_xIMR_LFSDETIE_Msk      (0x1U << SAI_xIMR_LFSDETIE_Pos)             /*!< 0x00000040 */
14105 #define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
14106 
14107 /********************  Bit definition for SAI_xSR register  *******************/
14108 #define SAI_xSR_OVRUDR_Pos         (0U)
14109 #define SAI_xSR_OVRUDR_Msk         (0x1U << SAI_xSR_OVRUDR_Pos)                /*!< 0x00000001 */
14110 #define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
14111 #define SAI_xSR_MUTEDET_Pos        (1U)
14112 #define SAI_xSR_MUTEDET_Msk        (0x1U << SAI_xSR_MUTEDET_Pos)               /*!< 0x00000002 */
14113 #define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
14114 #define SAI_xSR_WCKCFG_Pos         (2U)
14115 #define SAI_xSR_WCKCFG_Msk         (0x1U << SAI_xSR_WCKCFG_Pos)                /*!< 0x00000004 */
14116 #define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
14117 #define SAI_xSR_FREQ_Pos           (3U)
14118 #define SAI_xSR_FREQ_Msk           (0x1U << SAI_xSR_FREQ_Pos)                  /*!< 0x00000008 */
14119 #define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
14120 #define SAI_xSR_CNRDY_Pos          (4U)
14121 #define SAI_xSR_CNRDY_Msk          (0x1U << SAI_xSR_CNRDY_Pos)                 /*!< 0x00000010 */
14122 #define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
14123 #define SAI_xSR_AFSDET_Pos         (5U)
14124 #define SAI_xSR_AFSDET_Msk         (0x1U << SAI_xSR_AFSDET_Pos)                /*!< 0x00000020 */
14125 #define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
14126 #define SAI_xSR_LFSDET_Pos         (6U)
14127 #define SAI_xSR_LFSDET_Msk         (0x1U << SAI_xSR_LFSDET_Pos)                /*!< 0x00000040 */
14128 #define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
14129 
14130 #define SAI_xSR_FLVL_Pos           (16U)
14131 #define SAI_xSR_FLVL_Msk           (0x7U << SAI_xSR_FLVL_Pos)                  /*!< 0x00070000 */
14132 #define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
14133 #define SAI_xSR_FLVL_0             (0x1U << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
14134 #define SAI_xSR_FLVL_1             (0x2U << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
14135 #define SAI_xSR_FLVL_2             (0x4U << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
14136 
14137 /******************  Bit definition for SAI_xCLRFR register  ******************/
14138 #define SAI_xCLRFR_COVRUDR_Pos     (0U)
14139 #define SAI_xCLRFR_COVRUDR_Msk     (0x1U << SAI_xCLRFR_COVRUDR_Pos)            /*!< 0x00000001 */
14140 #define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
14141 #define SAI_xCLRFR_CMUTEDET_Pos    (1U)
14142 #define SAI_xCLRFR_CMUTEDET_Msk    (0x1U << SAI_xCLRFR_CMUTEDET_Pos)           /*!< 0x00000002 */
14143 #define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
14144 #define SAI_xCLRFR_CWCKCFG_Pos     (2U)
14145 #define SAI_xCLRFR_CWCKCFG_Msk     (0x1U << SAI_xCLRFR_CWCKCFG_Pos)            /*!< 0x00000004 */
14146 #define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
14147 #define SAI_xCLRFR_CFREQ_Pos       (3U)
14148 #define SAI_xCLRFR_CFREQ_Msk       (0x1U << SAI_xCLRFR_CFREQ_Pos)              /*!< 0x00000008 */
14149 #define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
14150 #define SAI_xCLRFR_CCNRDY_Pos      (4U)
14151 #define SAI_xCLRFR_CCNRDY_Msk      (0x1U << SAI_xCLRFR_CCNRDY_Pos)             /*!< 0x00000010 */
14152 #define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
14153 #define SAI_xCLRFR_CAFSDET_Pos     (5U)
14154 #define SAI_xCLRFR_CAFSDET_Msk     (0x1U << SAI_xCLRFR_CAFSDET_Pos)            /*!< 0x00000020 */
14155 #define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
14156 #define SAI_xCLRFR_CLFSDET_Pos     (6U)
14157 #define SAI_xCLRFR_CLFSDET_Msk     (0x1U << SAI_xCLRFR_CLFSDET_Pos)            /*!< 0x00000040 */
14158 #define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
14159 
14160 /******************  Bit definition for SAI_xDR register  ******************/
14161 #define SAI_xDR_DATA_Pos           (0U)
14162 #define SAI_xDR_DATA_Msk           (0xFFFFFFFFU << SAI_xDR_DATA_Pos)           /*!< 0xFFFFFFFF */
14163 #define SAI_xDR_DATA               SAI_xDR_DATA_Msk
14164 
14165 /******************************************************************************/
14166 /*                                                                            */
14167 /*                          LCD Controller (LCD)                              */
14168 /*                                                                            */
14169 /******************************************************************************/
14170 
14171 /*******************  Bit definition for LCD_CR register  *********************/
14172 #define LCD_CR_LCDEN_Pos            (0U)
14173 #define LCD_CR_LCDEN_Msk            (0x1U << LCD_CR_LCDEN_Pos)                 /*!< 0x00000001 */
14174 #define LCD_CR_LCDEN                LCD_CR_LCDEN_Msk                           /*!< LCD Enable Bit */
14175 #define LCD_CR_VSEL_Pos             (1U)
14176 #define LCD_CR_VSEL_Msk             (0x1U << LCD_CR_VSEL_Pos)                  /*!< 0x00000002 */
14177 #define LCD_CR_VSEL                 LCD_CR_VSEL_Msk                            /*!< Voltage source selector Bit */
14178 
14179 #define LCD_CR_DUTY_Pos             (2U)
14180 #define LCD_CR_DUTY_Msk             (0x7U << LCD_CR_DUTY_Pos)                  /*!< 0x0000001C */
14181 #define LCD_CR_DUTY                 LCD_CR_DUTY_Msk                            /*!< DUTY[2:0] bits (Duty selector) */
14182 #define LCD_CR_DUTY_0               (0x1U << LCD_CR_DUTY_Pos)                  /*!< 0x00000004 */
14183 #define LCD_CR_DUTY_1               (0x2U << LCD_CR_DUTY_Pos)                  /*!< 0x00000008 */
14184 #define LCD_CR_DUTY_2               (0x4U << LCD_CR_DUTY_Pos)                  /*!< 0x00000010 */
14185 
14186 #define LCD_CR_BIAS_Pos             (5U)
14187 #define LCD_CR_BIAS_Msk             (0x3U << LCD_CR_BIAS_Pos)                  /*!< 0x00000060 */
14188 #define LCD_CR_BIAS                 LCD_CR_BIAS_Msk                            /*!< BIAS[1:0] bits (Bias selector) */
14189 #define LCD_CR_BIAS_0               (0x1U << LCD_CR_BIAS_Pos)                  /*!< 0x00000020 */
14190 #define LCD_CR_BIAS_1               (0x2U << LCD_CR_BIAS_Pos)                  /*!< 0x00000040 */
14191 
14192 #define LCD_CR_MUX_SEG_Pos          (7U)
14193 #define LCD_CR_MUX_SEG_Msk          (0x1U << LCD_CR_MUX_SEG_Pos)               /*!< 0x00000080 */
14194 #define LCD_CR_MUX_SEG              LCD_CR_MUX_SEG_Msk                         /*!< Mux Segment Enable Bit */
14195 #define LCD_CR_BUFEN_Pos            (8U)
14196 #define LCD_CR_BUFEN_Msk            (0x1U << LCD_CR_BUFEN_Pos)                 /*!< 0x00000100 */
14197 #define LCD_CR_BUFEN                LCD_CR_BUFEN_Msk                           /*!< Voltage output buffer enable */
14198 
14199 /*******************  Bit definition for LCD_FCR register  ********************/
14200 #define LCD_FCR_HD_Pos              (0U)
14201 #define LCD_FCR_HD_Msk              (0x1U << LCD_FCR_HD_Pos)                   /*!< 0x00000001 */
14202 #define LCD_FCR_HD                  LCD_FCR_HD_Msk                             /*!< High Drive Enable Bit */
14203 #define LCD_FCR_SOFIE_Pos           (1U)
14204 #define LCD_FCR_SOFIE_Msk           (0x1U << LCD_FCR_SOFIE_Pos)                /*!< 0x00000002 */
14205 #define LCD_FCR_SOFIE               LCD_FCR_SOFIE_Msk                          /*!< Start of Frame Interrupt Enable Bit */
14206 #define LCD_FCR_UDDIE_Pos           (3U)
14207 #define LCD_FCR_UDDIE_Msk           (0x1U << LCD_FCR_UDDIE_Pos)                /*!< 0x00000008 */
14208 #define LCD_FCR_UDDIE               LCD_FCR_UDDIE_Msk                          /*!< Update Display Done Interrupt Enable Bit */
14209 
14210 #define LCD_FCR_PON_Pos             (4U)
14211 #define LCD_FCR_PON_Msk             (0x7U << LCD_FCR_PON_Pos)                  /*!< 0x00000070 */
14212 #define LCD_FCR_PON                 LCD_FCR_PON_Msk                            /*!< PON[2:0] bits (Pulse ON Duration) */
14213 #define LCD_FCR_PON_0               (0x1U << LCD_FCR_PON_Pos)                  /*!< 0x00000010 */
14214 #define LCD_FCR_PON_1               (0x2U << LCD_FCR_PON_Pos)                  /*!< 0x00000020 */
14215 #define LCD_FCR_PON_2               (0x4U << LCD_FCR_PON_Pos)                  /*!< 0x00000040 */
14216 
14217 #define LCD_FCR_DEAD_Pos            (7U)
14218 #define LCD_FCR_DEAD_Msk            (0x7U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000380 */
14219 #define LCD_FCR_DEAD                LCD_FCR_DEAD_Msk                           /*!< DEAD[2:0] bits (DEAD Time) */
14220 #define LCD_FCR_DEAD_0              (0x1U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000080 */
14221 #define LCD_FCR_DEAD_1              (0x2U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000100 */
14222 #define LCD_FCR_DEAD_2              (0x4U << LCD_FCR_DEAD_Pos)                 /*!< 0x00000200 */
14223 
14224 #define LCD_FCR_CC_Pos              (10U)
14225 #define LCD_FCR_CC_Msk              (0x7U << LCD_FCR_CC_Pos)                   /*!< 0x00001C00 */
14226 #define LCD_FCR_CC                  LCD_FCR_CC_Msk                             /*!< CC[2:0] bits (Contrast Control) */
14227 #define LCD_FCR_CC_0                (0x1U << LCD_FCR_CC_Pos)                   /*!< 0x00000400 */
14228 #define LCD_FCR_CC_1                (0x2U << LCD_FCR_CC_Pos)                   /*!< 0x00000800 */
14229 #define LCD_FCR_CC_2                (0x4U << LCD_FCR_CC_Pos)                   /*!< 0x00001000 */
14230 
14231 #define LCD_FCR_BLINKF_Pos          (13U)
14232 #define LCD_FCR_BLINKF_Msk          (0x7U << LCD_FCR_BLINKF_Pos)               /*!< 0x0000E000 */
14233 #define LCD_FCR_BLINKF              LCD_FCR_BLINKF_Msk                         /*!< BLINKF[2:0] bits (Blink Frequency) */
14234 #define LCD_FCR_BLINKF_0            (0x1U << LCD_FCR_BLINKF_Pos)               /*!< 0x00002000 */
14235 #define LCD_FCR_BLINKF_1            (0x2U << LCD_FCR_BLINKF_Pos)               /*!< 0x00004000 */
14236 #define LCD_FCR_BLINKF_2            (0x4U << LCD_FCR_BLINKF_Pos)               /*!< 0x00008000 */
14237 
14238 #define LCD_FCR_BLINK_Pos           (16U)
14239 #define LCD_FCR_BLINK_Msk           (0x3U << LCD_FCR_BLINK_Pos)                /*!< 0x00030000 */
14240 #define LCD_FCR_BLINK               LCD_FCR_BLINK_Msk                          /*!< BLINK[1:0] bits (Blink Enable) */
14241 #define LCD_FCR_BLINK_0             (0x1U << LCD_FCR_BLINK_Pos)                /*!< 0x00010000 */
14242 #define LCD_FCR_BLINK_1             (0x2U << LCD_FCR_BLINK_Pos)                /*!< 0x00020000 */
14243 
14244 #define LCD_FCR_DIV_Pos             (18U)
14245 #define LCD_FCR_DIV_Msk             (0xFU << LCD_FCR_DIV_Pos)                  /*!< 0x003C0000 */
14246 #define LCD_FCR_DIV                 LCD_FCR_DIV_Msk                            /*!< DIV[3:0] bits (Divider) */
14247 #define LCD_FCR_PS_Pos              (22U)
14248 #define LCD_FCR_PS_Msk              (0xFU << LCD_FCR_PS_Pos)                   /*!< 0x03C00000 */
14249 #define LCD_FCR_PS                  LCD_FCR_PS_Msk                             /*!< PS[3:0] bits (Prescaler) */
14250 
14251 /*******************  Bit definition for LCD_SR register  *********************/
14252 #define LCD_SR_ENS_Pos              (0U)
14253 #define LCD_SR_ENS_Msk              (0x1U << LCD_SR_ENS_Pos)                   /*!< 0x00000001 */
14254 #define LCD_SR_ENS                  LCD_SR_ENS_Msk                             /*!< LCD Enabled Bit */
14255 #define LCD_SR_SOF_Pos              (1U)
14256 #define LCD_SR_SOF_Msk              (0x1U << LCD_SR_SOF_Pos)                   /*!< 0x00000002 */
14257 #define LCD_SR_SOF                  LCD_SR_SOF_Msk                             /*!< Start Of Frame Flag Bit */
14258 #define LCD_SR_UDR_Pos              (2U)
14259 #define LCD_SR_UDR_Msk              (0x1U << LCD_SR_UDR_Pos)                   /*!< 0x00000004 */
14260 #define LCD_SR_UDR                  LCD_SR_UDR_Msk                             /*!< Update Display Request Bit */
14261 #define LCD_SR_UDD_Pos              (3U)
14262 #define LCD_SR_UDD_Msk              (0x1U << LCD_SR_UDD_Pos)                   /*!< 0x00000008 */
14263 #define LCD_SR_UDD                  LCD_SR_UDD_Msk                             /*!< Update Display Done Flag Bit */
14264 #define LCD_SR_RDY_Pos              (4U)
14265 #define LCD_SR_RDY_Msk              (0x1U << LCD_SR_RDY_Pos)                   /*!< 0x00000010 */
14266 #define LCD_SR_RDY                  LCD_SR_RDY_Msk                             /*!< Ready Flag Bit */
14267 #define LCD_SR_FCRSR_Pos            (5U)
14268 #define LCD_SR_FCRSR_Msk            (0x1U << LCD_SR_FCRSR_Pos)                 /*!< 0x00000020 */
14269 #define LCD_SR_FCRSR                LCD_SR_FCRSR_Msk                           /*!< LCD FCR Register Synchronization Flag Bit */
14270 
14271 /*******************  Bit definition for LCD_CLR register  ********************/
14272 #define LCD_CLR_SOFC_Pos            (1U)
14273 #define LCD_CLR_SOFC_Msk            (0x1U << LCD_CLR_SOFC_Pos)                 /*!< 0x00000002 */
14274 #define LCD_CLR_SOFC                LCD_CLR_SOFC_Msk                           /*!< Start Of Frame Flag Clear Bit */
14275 #define LCD_CLR_UDDC_Pos            (3U)
14276 #define LCD_CLR_UDDC_Msk            (0x1U << LCD_CLR_UDDC_Pos)                 /*!< 0x00000008 */
14277 #define LCD_CLR_UDDC                LCD_CLR_UDDC_Msk                           /*!< Update Display Done Flag Clear Bit */
14278 
14279 /*******************  Bit definition for LCD_RAM register  ********************/
14280 #define LCD_RAM_SEGMENT_DATA_Pos    (0U)
14281 #define LCD_RAM_SEGMENT_DATA_Msk    (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)  /*!< 0xFFFFFFFF */
14282 #define LCD_RAM_SEGMENT_DATA        LCD_RAM_SEGMENT_DATA_Msk                   /*!< Segment Data Bits */
14283 
14284 /******************************************************************************/
14285 /*                                                                            */
14286 /*                           SDMMC Interface                                  */
14287 /*                                                                            */
14288 /******************************************************************************/
14289 /******************  Bit definition for SDMMC_POWER register  ******************/
14290 #define SDMMC_POWER_PWRCTRL_Pos         (0U)
14291 #define SDMMC_POWER_PWRCTRL_Msk         (0x3U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000003 */
14292 #define SDMMC_POWER_PWRCTRL             SDMMC_POWER_PWRCTRL_Msk                /*!<PWRCTRL[1:0] bits (Power supply control bits) */
14293 #define SDMMC_POWER_PWRCTRL_0           (0x1U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000001 */
14294 #define SDMMC_POWER_PWRCTRL_1           (0x2U << SDMMC_POWER_PWRCTRL_Pos)      /*!< 0x00000002 */
14295 
14296 /******************  Bit definition for SDMMC_CLKCR register  ******************/
14297 #define SDMMC_CLKCR_CLKDIV_Pos          (0U)
14298 #define SDMMC_CLKCR_CLKDIV_Msk          (0xFFU << SDMMC_CLKCR_CLKDIV_Pos)      /*!< 0x000000FF */
14299 #define SDMMC_CLKCR_CLKDIV              SDMMC_CLKCR_CLKDIV_Msk                 /*!<Clock divide factor             */
14300 #define SDMMC_CLKCR_CLKEN_Pos           (8U)
14301 #define SDMMC_CLKCR_CLKEN_Msk           (0x1U << SDMMC_CLKCR_CLKEN_Pos)        /*!< 0x00000100 */
14302 #define SDMMC_CLKCR_CLKEN               SDMMC_CLKCR_CLKEN_Msk                  /*!<Clock enable bit                */
14303 #define SDMMC_CLKCR_PWRSAV_Pos          (9U)
14304 #define SDMMC_CLKCR_PWRSAV_Msk          (0x1U << SDMMC_CLKCR_PWRSAV_Pos)       /*!< 0x00000200 */
14305 #define SDMMC_CLKCR_PWRSAV              SDMMC_CLKCR_PWRSAV_Msk                 /*!<Power saving configuration bit  */
14306 #define SDMMC_CLKCR_BYPASS_Pos          (10U)
14307 #define SDMMC_CLKCR_BYPASS_Msk          (0x1U << SDMMC_CLKCR_BYPASS_Pos)       /*!< 0x00000400 */
14308 #define SDMMC_CLKCR_BYPASS              SDMMC_CLKCR_BYPASS_Msk                 /*!<Clock divider bypass enable bit */
14309 
14310 #define SDMMC_CLKCR_WIDBUS_Pos          (11U)
14311 #define SDMMC_CLKCR_WIDBUS_Msk          (0x3U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001800 */
14312 #define SDMMC_CLKCR_WIDBUS              SDMMC_CLKCR_WIDBUS_Msk                 /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
14313 #define SDMMC_CLKCR_WIDBUS_0            (0x1U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00000800 */
14314 #define SDMMC_CLKCR_WIDBUS_1            (0x2U << SDMMC_CLKCR_WIDBUS_Pos)       /*!< 0x00001000 */
14315 
14316 #define SDMMC_CLKCR_NEGEDGE_Pos         (13U)
14317 #define SDMMC_CLKCR_NEGEDGE_Msk         (0x1U << SDMMC_CLKCR_NEGEDGE_Pos)      /*!< 0x00002000 */
14318 #define SDMMC_CLKCR_NEGEDGE             SDMMC_CLKCR_NEGEDGE_Msk                /*!<SDMMC_CK dephasing selection bit */
14319 #define SDMMC_CLKCR_HWFC_EN_Pos         (14U)
14320 #define SDMMC_CLKCR_HWFC_EN_Msk         (0x1U << SDMMC_CLKCR_HWFC_EN_Pos)      /*!< 0x00004000 */
14321 #define SDMMC_CLKCR_HWFC_EN             SDMMC_CLKCR_HWFC_EN_Msk                /*!<HW Flow Control enable          */
14322 
14323 /*******************  Bit definition for SDMMC_ARG register  *******************/
14324 #define SDMMC_ARG_CMDARG_Pos            (0U)
14325 #define SDMMC_ARG_CMDARG_Msk            (0xFFFFFFFFU << SDMMC_ARG_CMDARG_Pos)  /*!< 0xFFFFFFFF */
14326 #define SDMMC_ARG_CMDARG                SDMMC_ARG_CMDARG_Msk                   /*!<Command argument */
14327 
14328 /*******************  Bit definition for SDMMC_CMD register  *******************/
14329 #define SDMMC_CMD_CMDINDEX_Pos          (0U)
14330 #define SDMMC_CMD_CMDINDEX_Msk          (0x3FU << SDMMC_CMD_CMDINDEX_Pos)      /*!< 0x0000003F */
14331 #define SDMMC_CMD_CMDINDEX              SDMMC_CMD_CMDINDEX_Msk                 /*!<Command Index                               */
14332 
14333 #define SDMMC_CMD_WAITRESP_Pos          (6U)
14334 #define SDMMC_CMD_WAITRESP_Msk          (0x3U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x000000C0 */
14335 #define SDMMC_CMD_WAITRESP              SDMMC_CMD_WAITRESP_Msk                 /*!<WAITRESP[1:0] bits (Wait for response bits) */
14336 #define SDMMC_CMD_WAITRESP_0            (0x1U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000040 */
14337 #define SDMMC_CMD_WAITRESP_1            (0x2U << SDMMC_CMD_WAITRESP_Pos)       /*!< 0x00000080 */
14338 
14339 #define SDMMC_CMD_WAITINT_Pos           (8U)
14340 #define SDMMC_CMD_WAITINT_Msk           (0x1U << SDMMC_CMD_WAITINT_Pos)        /*!< 0x00000100 */
14341 #define SDMMC_CMD_WAITINT               SDMMC_CMD_WAITINT_Msk                  /*!<CPSM Waits for Interrupt Request                               */
14342 #define SDMMC_CMD_WAITPEND_Pos          (9U)
14343 #define SDMMC_CMD_WAITPEND_Msk          (0x1U << SDMMC_CMD_WAITPEND_Pos)       /*!< 0x00000200 */
14344 #define SDMMC_CMD_WAITPEND              SDMMC_CMD_WAITPEND_Msk                 /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
14345 #define SDMMC_CMD_CPSMEN_Pos            (10U)
14346 #define SDMMC_CMD_CPSMEN_Msk            (0x1U << SDMMC_CMD_CPSMEN_Pos)         /*!< 0x00000400 */
14347 #define SDMMC_CMD_CPSMEN                SDMMC_CMD_CPSMEN_Msk                   /*!<Command path state machine (CPSM) Enable bit                   */
14348 #define SDMMC_CMD_SDIOSUSPEND_Pos       (11U)
14349 #define SDMMC_CMD_SDIOSUSPEND_Msk       (0x1U << SDMMC_CMD_SDIOSUSPEND_Pos)    /*!< 0x00000800 */
14350 #define SDMMC_CMD_SDIOSUSPEND           SDMMC_CMD_SDIOSUSPEND_Msk              /*!<SD I/O suspend command                                         */
14351 
14352 /*****************  Bit definition for SDMMC_RESPCMD register  *****************/
14353 #define SDMMC_RESPCMD_RESPCMD_Pos       (0U)
14354 #define SDMMC_RESPCMD_RESPCMD_Msk       (0x3FU << SDMMC_RESPCMD_RESPCMD_Pos)   /*!< 0x0000003F */
14355 #define SDMMC_RESPCMD_RESPCMD           SDMMC_RESPCMD_RESPCMD_Msk              /*!<Response command index */
14356 
14357 /******************  Bit definition for SDMMC_RESP1 register  ******************/
14358 #define SDMMC_RESP1_CARDSTATUS1_Pos     (0U)
14359 #define SDMMC_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFU << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
14360 #define SDMMC_RESP1_CARDSTATUS1         SDMMC_RESP1_CARDSTATUS1_Msk            /*!<Card Status */
14361 
14362 /******************  Bit definition for SDMMC_RESP2 register  ******************/
14363 #define SDMMC_RESP2_CARDSTATUS2_Pos     (0U)
14364 #define SDMMC_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFU << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
14365 #define SDMMC_RESP2_CARDSTATUS2         SDMMC_RESP2_CARDSTATUS2_Msk            /*!<Card Status */
14366 
14367 /******************  Bit definition for SDMMC_RESP3 register  ******************/
14368 #define SDMMC_RESP3_CARDSTATUS3_Pos     (0U)
14369 #define SDMMC_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFU << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
14370 #define SDMMC_RESP3_CARDSTATUS3         SDMMC_RESP3_CARDSTATUS3_Msk            /*!<Card Status */
14371 
14372 /******************  Bit definition for SDMMC_RESP4 register  ******************/
14373 #define SDMMC_RESP4_CARDSTATUS4_Pos     (0U)
14374 #define SDMMC_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFU << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
14375 #define SDMMC_RESP4_CARDSTATUS4         SDMMC_RESP4_CARDSTATUS4_Msk            /*!<Card Status */
14376 
14377 /******************  Bit definition for SDMMC_DTIMER register  *****************/
14378 #define SDMMC_DTIMER_DATATIME_Pos       (0U)
14379 #define SDMMC_DTIMER_DATATIME_Msk       (0xFFFFFFFFU << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
14380 #define SDMMC_DTIMER_DATATIME           SDMMC_DTIMER_DATATIME_Msk              /*!<Data timeout period. */
14381 
14382 /******************  Bit definition for SDMMC_DLEN register  *******************/
14383 #define SDMMC_DLEN_DATALENGTH_Pos       (0U)
14384 #define SDMMC_DLEN_DATALENGTH_Msk       (0x1FFFFFFU << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
14385 #define SDMMC_DLEN_DATALENGTH           SDMMC_DLEN_DATALENGTH_Msk              /*!<Data length value    */
14386 
14387 /******************  Bit definition for SDMMC_DCTRL register  ******************/
14388 #define SDMMC_DCTRL_DTEN_Pos            (0U)
14389 #define SDMMC_DCTRL_DTEN_Msk            (0x1U << SDMMC_DCTRL_DTEN_Pos)         /*!< 0x00000001 */
14390 #define SDMMC_DCTRL_DTEN                SDMMC_DCTRL_DTEN_Msk                   /*!<Data transfer enabled bit         */
14391 #define SDMMC_DCTRL_DTDIR_Pos           (1U)
14392 #define SDMMC_DCTRL_DTDIR_Msk           (0x1U << SDMMC_DCTRL_DTDIR_Pos)        /*!< 0x00000002 */
14393 #define SDMMC_DCTRL_DTDIR               SDMMC_DCTRL_DTDIR_Msk                  /*!<Data transfer direction selection */
14394 #define SDMMC_DCTRL_DTMODE_Pos          (2U)
14395 #define SDMMC_DCTRL_DTMODE_Msk          (0x1U << SDMMC_DCTRL_DTMODE_Pos)       /*!< 0x00000004 */
14396 #define SDMMC_DCTRL_DTMODE              SDMMC_DCTRL_DTMODE_Msk                 /*!<Data transfer mode selection      */
14397 #define SDMMC_DCTRL_DMAEN_Pos           (3U)
14398 #define SDMMC_DCTRL_DMAEN_Msk           (0x1U << SDMMC_DCTRL_DMAEN_Pos)        /*!< 0x00000008 */
14399 #define SDMMC_DCTRL_DMAEN               SDMMC_DCTRL_DMAEN_Msk                  /*!<DMA enabled bit                   */
14400 
14401 #define SDMMC_DCTRL_DBLOCKSIZE_Pos      (4U)
14402 #define SDMMC_DCTRL_DBLOCKSIZE_Msk      (0xFU << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x000000F0 */
14403 #define SDMMC_DCTRL_DBLOCKSIZE          SDMMC_DCTRL_DBLOCKSIZE_Msk             /*!<DBLOCKSIZE[3:0] bits (Data block size) */
14404 #define SDMMC_DCTRL_DBLOCKSIZE_0        (0x1U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000010 */
14405 #define SDMMC_DCTRL_DBLOCKSIZE_1        (0x2U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000020 */
14406 #define SDMMC_DCTRL_DBLOCKSIZE_2        (0x4U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000040 */
14407 #define SDMMC_DCTRL_DBLOCKSIZE_3        (0x8U << SDMMC_DCTRL_DBLOCKSIZE_Pos)   /*!< 0x00000080 */
14408 
14409 #define SDMMC_DCTRL_RWSTART_Pos         (8U)
14410 #define SDMMC_DCTRL_RWSTART_Msk         (0x1U << SDMMC_DCTRL_RWSTART_Pos)      /*!< 0x00000100 */
14411 #define SDMMC_DCTRL_RWSTART             SDMMC_DCTRL_RWSTART_Msk                /*!<Read wait start         */
14412 #define SDMMC_DCTRL_RWSTOP_Pos          (9U)
14413 #define SDMMC_DCTRL_RWSTOP_Msk          (0x1U << SDMMC_DCTRL_RWSTOP_Pos)       /*!< 0x00000200 */
14414 #define SDMMC_DCTRL_RWSTOP              SDMMC_DCTRL_RWSTOP_Msk                 /*!<Read wait stop          */
14415 #define SDMMC_DCTRL_RWMOD_Pos           (10U)
14416 #define SDMMC_DCTRL_RWMOD_Msk           (0x1U << SDMMC_DCTRL_RWMOD_Pos)        /*!< 0x00000400 */
14417 #define SDMMC_DCTRL_RWMOD               SDMMC_DCTRL_RWMOD_Msk                  /*!<Read wait mode          */
14418 #define SDMMC_DCTRL_SDIOEN_Pos          (11U)
14419 #define SDMMC_DCTRL_SDIOEN_Msk          (0x1U << SDMMC_DCTRL_SDIOEN_Pos)       /*!< 0x00000800 */
14420 #define SDMMC_DCTRL_SDIOEN              SDMMC_DCTRL_SDIOEN_Msk                 /*!<SD I/O enable functions */
14421 
14422 /******************  Bit definition for SDMMC_DCOUNT register  *****************/
14423 #define SDMMC_DCOUNT_DATACOUNT_Pos      (0U)
14424 #define SDMMC_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFU << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
14425 #define SDMMC_DCOUNT_DATACOUNT          SDMMC_DCOUNT_DATACOUNT_Msk             /*!<Data count value */
14426 
14427 /******************  Bit definition for SDMMC_STA register  ********************/
14428 #define SDMMC_STA_CCRCFAIL_Pos          (0U)
14429 #define SDMMC_STA_CCRCFAIL_Msk          (0x1U << SDMMC_STA_CCRCFAIL_Pos)       /*!< 0x00000001 */
14430 #define SDMMC_STA_CCRCFAIL              SDMMC_STA_CCRCFAIL_Msk                 /*!<Command response received (CRC check failed)  */
14431 #define SDMMC_STA_DCRCFAIL_Pos          (1U)
14432 #define SDMMC_STA_DCRCFAIL_Msk          (0x1U << SDMMC_STA_DCRCFAIL_Pos)       /*!< 0x00000002 */
14433 #define SDMMC_STA_DCRCFAIL              SDMMC_STA_DCRCFAIL_Msk                 /*!<Data block sent/received (CRC check failed)   */
14434 #define SDMMC_STA_CTIMEOUT_Pos          (2U)
14435 #define SDMMC_STA_CTIMEOUT_Msk          (0x1U << SDMMC_STA_CTIMEOUT_Pos)       /*!< 0x00000004 */
14436 #define SDMMC_STA_CTIMEOUT              SDMMC_STA_CTIMEOUT_Msk                 /*!<Command response timeout                      */
14437 #define SDMMC_STA_DTIMEOUT_Pos          (3U)
14438 #define SDMMC_STA_DTIMEOUT_Msk          (0x1U << SDMMC_STA_DTIMEOUT_Pos)       /*!< 0x00000008 */
14439 #define SDMMC_STA_DTIMEOUT              SDMMC_STA_DTIMEOUT_Msk                 /*!<Data timeout                                  */
14440 #define SDMMC_STA_TXUNDERR_Pos          (4U)
14441 #define SDMMC_STA_TXUNDERR_Msk          (0x1U << SDMMC_STA_TXUNDERR_Pos)       /*!< 0x00000010 */
14442 #define SDMMC_STA_TXUNDERR              SDMMC_STA_TXUNDERR_Msk                 /*!<Transmit FIFO underrun error                  */
14443 #define SDMMC_STA_RXOVERR_Pos           (5U)
14444 #define SDMMC_STA_RXOVERR_Msk           (0x1U << SDMMC_STA_RXOVERR_Pos)        /*!< 0x00000020 */
14445 #define SDMMC_STA_RXOVERR               SDMMC_STA_RXOVERR_Msk                  /*!<Received FIFO overrun error                   */
14446 #define SDMMC_STA_CMDREND_Pos           (6U)
14447 #define SDMMC_STA_CMDREND_Msk           (0x1U << SDMMC_STA_CMDREND_Pos)        /*!< 0x00000040 */
14448 #define SDMMC_STA_CMDREND               SDMMC_STA_CMDREND_Msk                  /*!<Command response received (CRC check passed)  */
14449 #define SDMMC_STA_CMDSENT_Pos           (7U)
14450 #define SDMMC_STA_CMDSENT_Msk           (0x1U << SDMMC_STA_CMDSENT_Pos)        /*!< 0x00000080 */
14451 #define SDMMC_STA_CMDSENT               SDMMC_STA_CMDSENT_Msk                  /*!<Command sent (no response required)           */
14452 #define SDMMC_STA_DATAEND_Pos           (8U)
14453 #define SDMMC_STA_DATAEND_Msk           (0x1U << SDMMC_STA_DATAEND_Pos)        /*!< 0x00000100 */
14454 #define SDMMC_STA_DATAEND               SDMMC_STA_DATAEND_Msk                  /*!<Data end (data counter, SDIDCOUNT, is zero)   */
14455 #define SDMMC_STA_STBITERR_Pos          (9U)
14456 #define SDMMC_STA_STBITERR_Msk          (0x1U << SDMMC_STA_STBITERR_Pos)       /*!< 0x00000200 */
14457 #define SDMMC_STA_STBITERR              SDMMC_STA_STBITERR_Msk                 /*!<Start bit not detected on all data signals in wide bus mode */
14458 #define SDMMC_STA_DBCKEND_Pos           (10U)
14459 #define SDMMC_STA_DBCKEND_Msk           (0x1U << SDMMC_STA_DBCKEND_Pos)        /*!< 0x00000400 */
14460 #define SDMMC_STA_DBCKEND               SDMMC_STA_DBCKEND_Msk                  /*!<Data block sent/received (CRC check passed)   */
14461 #define SDMMC_STA_CMDACT_Pos            (11U)
14462 #define SDMMC_STA_CMDACT_Msk            (0x1U << SDMMC_STA_CMDACT_Pos)         /*!< 0x00000800 */
14463 #define SDMMC_STA_CMDACT                SDMMC_STA_CMDACT_Msk                   /*!<Command transfer in progress                  */
14464 #define SDMMC_STA_TXACT_Pos             (12U)
14465 #define SDMMC_STA_TXACT_Msk             (0x1U << SDMMC_STA_TXACT_Pos)          /*!< 0x00001000 */
14466 #define SDMMC_STA_TXACT                 SDMMC_STA_TXACT_Msk                    /*!<Data transmit in progress                     */
14467 #define SDMMC_STA_RXACT_Pos             (13U)
14468 #define SDMMC_STA_RXACT_Msk             (0x1U << SDMMC_STA_RXACT_Pos)          /*!< 0x00002000 */
14469 #define SDMMC_STA_RXACT                 SDMMC_STA_RXACT_Msk                    /*!<Data receive in progress                      */
14470 #define SDMMC_STA_TXFIFOHE_Pos          (14U)
14471 #define SDMMC_STA_TXFIFOHE_Msk          (0x1U << SDMMC_STA_TXFIFOHE_Pos)       /*!< 0x00004000 */
14472 #define SDMMC_STA_TXFIFOHE              SDMMC_STA_TXFIFOHE_Msk                 /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
14473 #define SDMMC_STA_RXFIFOHF_Pos          (15U)
14474 #define SDMMC_STA_RXFIFOHF_Msk          (0x1U << SDMMC_STA_RXFIFOHF_Pos)       /*!< 0x00008000 */
14475 #define SDMMC_STA_RXFIFOHF              SDMMC_STA_RXFIFOHF_Msk                 /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
14476 #define SDMMC_STA_TXFIFOF_Pos           (16U)
14477 #define SDMMC_STA_TXFIFOF_Msk           (0x1U << SDMMC_STA_TXFIFOF_Pos)        /*!< 0x00010000 */
14478 #define SDMMC_STA_TXFIFOF               SDMMC_STA_TXFIFOF_Msk                  /*!<Transmit FIFO full                            */
14479 #define SDMMC_STA_RXFIFOF_Pos           (17U)
14480 #define SDMMC_STA_RXFIFOF_Msk           (0x1U << SDMMC_STA_RXFIFOF_Pos)        /*!< 0x00020000 */
14481 #define SDMMC_STA_RXFIFOF               SDMMC_STA_RXFIFOF_Msk                  /*!<Receive FIFO full                             */
14482 #define SDMMC_STA_TXFIFOE_Pos           (18U)
14483 #define SDMMC_STA_TXFIFOE_Msk           (0x1U << SDMMC_STA_TXFIFOE_Pos)        /*!< 0x00040000 */
14484 #define SDMMC_STA_TXFIFOE               SDMMC_STA_TXFIFOE_Msk                  /*!<Transmit FIFO empty                           */
14485 #define SDMMC_STA_RXFIFOE_Pos           (19U)
14486 #define SDMMC_STA_RXFIFOE_Msk           (0x1U << SDMMC_STA_RXFIFOE_Pos)        /*!< 0x00080000 */
14487 #define SDMMC_STA_RXFIFOE               SDMMC_STA_RXFIFOE_Msk                  /*!<Receive FIFO empty                            */
14488 #define SDMMC_STA_TXDAVL_Pos            (20U)
14489 #define SDMMC_STA_TXDAVL_Msk            (0x1U << SDMMC_STA_TXDAVL_Pos)         /*!< 0x00100000 */
14490 #define SDMMC_STA_TXDAVL                SDMMC_STA_TXDAVL_Msk                   /*!<Data available in transmit FIFO               */
14491 #define SDMMC_STA_RXDAVL_Pos            (21U)
14492 #define SDMMC_STA_RXDAVL_Msk            (0x1U << SDMMC_STA_RXDAVL_Pos)         /*!< 0x00200000 */
14493 #define SDMMC_STA_RXDAVL                SDMMC_STA_RXDAVL_Msk                   /*!<Data available in receive FIFO                */
14494 #define SDMMC_STA_SDIOIT_Pos            (22U)
14495 #define SDMMC_STA_SDIOIT_Msk            (0x1U << SDMMC_STA_SDIOIT_Pos)         /*!< 0x00400000 */
14496 #define SDMMC_STA_SDIOIT                SDMMC_STA_SDIOIT_Msk                   /*!<SDIO interrupt received                       */
14497 
14498 /*******************  Bit definition for SDMMC_ICR register  *******************/
14499 #define SDMMC_ICR_CCRCFAILC_Pos         (0U)
14500 #define SDMMC_ICR_CCRCFAILC_Msk         (0x1U << SDMMC_ICR_CCRCFAILC_Pos)      /*!< 0x00000001 */
14501 #define SDMMC_ICR_CCRCFAILC             SDMMC_ICR_CCRCFAILC_Msk                /*!<CCRCFAIL flag clear bit */
14502 #define SDMMC_ICR_DCRCFAILC_Pos         (1U)
14503 #define SDMMC_ICR_DCRCFAILC_Msk         (0x1U << SDMMC_ICR_DCRCFAILC_Pos)      /*!< 0x00000002 */
14504 #define SDMMC_ICR_DCRCFAILC             SDMMC_ICR_DCRCFAILC_Msk                /*!<DCRCFAIL flag clear bit */
14505 #define SDMMC_ICR_CTIMEOUTC_Pos         (2U)
14506 #define SDMMC_ICR_CTIMEOUTC_Msk         (0x1U << SDMMC_ICR_CTIMEOUTC_Pos)      /*!< 0x00000004 */
14507 #define SDMMC_ICR_CTIMEOUTC             SDMMC_ICR_CTIMEOUTC_Msk                /*!<CTIMEOUT flag clear bit */
14508 #define SDMMC_ICR_DTIMEOUTC_Pos         (3U)
14509 #define SDMMC_ICR_DTIMEOUTC_Msk         (0x1U << SDMMC_ICR_DTIMEOUTC_Pos)      /*!< 0x00000008 */
14510 #define SDMMC_ICR_DTIMEOUTC             SDMMC_ICR_DTIMEOUTC_Msk                /*!<DTIMEOUT flag clear bit */
14511 #define SDMMC_ICR_TXUNDERRC_Pos         (4U)
14512 #define SDMMC_ICR_TXUNDERRC_Msk         (0x1U << SDMMC_ICR_TXUNDERRC_Pos)      /*!< 0x00000010 */
14513 #define SDMMC_ICR_TXUNDERRC             SDMMC_ICR_TXUNDERRC_Msk                /*!<TXUNDERR flag clear bit */
14514 #define SDMMC_ICR_RXOVERRC_Pos          (5U)
14515 #define SDMMC_ICR_RXOVERRC_Msk          (0x1U << SDMMC_ICR_RXOVERRC_Pos)       /*!< 0x00000020 */
14516 #define SDMMC_ICR_RXOVERRC              SDMMC_ICR_RXOVERRC_Msk                 /*!<RXOVERR flag clear bit  */
14517 #define SDMMC_ICR_CMDRENDC_Pos          (6U)
14518 #define SDMMC_ICR_CMDRENDC_Msk          (0x1U << SDMMC_ICR_CMDRENDC_Pos)       /*!< 0x00000040 */
14519 #define SDMMC_ICR_CMDRENDC              SDMMC_ICR_CMDRENDC_Msk                 /*!<CMDREND flag clear bit  */
14520 #define SDMMC_ICR_CMDSENTC_Pos          (7U)
14521 #define SDMMC_ICR_CMDSENTC_Msk          (0x1U << SDMMC_ICR_CMDSENTC_Pos)       /*!< 0x00000080 */
14522 #define SDMMC_ICR_CMDSENTC              SDMMC_ICR_CMDSENTC_Msk                 /*!<CMDSENT flag clear bit  */
14523 #define SDMMC_ICR_DATAENDC_Pos          (8U)
14524 #define SDMMC_ICR_DATAENDC_Msk          (0x1U << SDMMC_ICR_DATAENDC_Pos)       /*!< 0x00000100 */
14525 #define SDMMC_ICR_DATAENDC              SDMMC_ICR_DATAENDC_Msk                 /*!<DATAEND flag clear bit  */
14526 #define SDMMC_ICR_STBITERRC_Pos         (9U)
14527 #define SDMMC_ICR_STBITERRC_Msk         (0x1U << SDMMC_ICR_STBITERRC_Pos)      /*!< 0x00000200 */
14528 #define SDMMC_ICR_STBITERRC             SDMMC_ICR_STBITERRC_Msk                /*!<STBITERR flag clear bit */
14529 #define SDMMC_ICR_DBCKENDC_Pos          (10U)
14530 #define SDMMC_ICR_DBCKENDC_Msk          (0x1U << SDMMC_ICR_DBCKENDC_Pos)       /*!< 0x00000400 */
14531 #define SDMMC_ICR_DBCKENDC              SDMMC_ICR_DBCKENDC_Msk                 /*!<DBCKEND flag clear bit  */
14532 #define SDMMC_ICR_SDIOITC_Pos           (22U)
14533 #define SDMMC_ICR_SDIOITC_Msk           (0x1U << SDMMC_ICR_SDIOITC_Pos)        /*!< 0x00400000 */
14534 #define SDMMC_ICR_SDIOITC               SDMMC_ICR_SDIOITC_Msk                  /*!<SDIOIT flag clear bit   */
14535 
14536 /******************  Bit definition for SDMMC_MASK register  *******************/
14537 #define SDMMC_MASK_CCRCFAILIE_Pos       (0U)
14538 #define SDMMC_MASK_CCRCFAILIE_Msk       (0x1U << SDMMC_MASK_CCRCFAILIE_Pos)    /*!< 0x00000001 */
14539 #define SDMMC_MASK_CCRCFAILIE           SDMMC_MASK_CCRCFAILIE_Msk              /*!<Command CRC Fail Interrupt Enable          */
14540 #define SDMMC_MASK_DCRCFAILIE_Pos       (1U)
14541 #define SDMMC_MASK_DCRCFAILIE_Msk       (0x1U << SDMMC_MASK_DCRCFAILIE_Pos)    /*!< 0x00000002 */
14542 #define SDMMC_MASK_DCRCFAILIE           SDMMC_MASK_DCRCFAILIE_Msk              /*!<Data CRC Fail Interrupt Enable             */
14543 #define SDMMC_MASK_CTIMEOUTIE_Pos       (2U)
14544 #define SDMMC_MASK_CTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_CTIMEOUTIE_Pos)    /*!< 0x00000004 */
14545 #define SDMMC_MASK_CTIMEOUTIE           SDMMC_MASK_CTIMEOUTIE_Msk              /*!<Command TimeOut Interrupt Enable           */
14546 #define SDMMC_MASK_DTIMEOUTIE_Pos       (3U)
14547 #define SDMMC_MASK_DTIMEOUTIE_Msk       (0x1U << SDMMC_MASK_DTIMEOUTIE_Pos)    /*!< 0x00000008 */
14548 #define SDMMC_MASK_DTIMEOUTIE           SDMMC_MASK_DTIMEOUTIE_Msk              /*!<Data TimeOut Interrupt Enable              */
14549 #define SDMMC_MASK_TXUNDERRIE_Pos       (4U)
14550 #define SDMMC_MASK_TXUNDERRIE_Msk       (0x1U << SDMMC_MASK_TXUNDERRIE_Pos)    /*!< 0x00000010 */
14551 #define SDMMC_MASK_TXUNDERRIE           SDMMC_MASK_TXUNDERRIE_Msk              /*!<Tx FIFO UnderRun Error Interrupt Enable    */
14552 #define SDMMC_MASK_RXOVERRIE_Pos        (5U)
14553 #define SDMMC_MASK_RXOVERRIE_Msk        (0x1U << SDMMC_MASK_RXOVERRIE_Pos)     /*!< 0x00000020 */
14554 #define SDMMC_MASK_RXOVERRIE            SDMMC_MASK_RXOVERRIE_Msk               /*!<Rx FIFO OverRun Error Interrupt Enable     */
14555 #define SDMMC_MASK_CMDRENDIE_Pos        (6U)
14556 #define SDMMC_MASK_CMDRENDIE_Msk        (0x1U << SDMMC_MASK_CMDRENDIE_Pos)     /*!< 0x00000040 */
14557 #define SDMMC_MASK_CMDRENDIE            SDMMC_MASK_CMDRENDIE_Msk               /*!<Command Response Received Interrupt Enable */
14558 #define SDMMC_MASK_CMDSENTIE_Pos        (7U)
14559 #define SDMMC_MASK_CMDSENTIE_Msk        (0x1U << SDMMC_MASK_CMDSENTIE_Pos)     /*!< 0x00000080 */
14560 #define SDMMC_MASK_CMDSENTIE            SDMMC_MASK_CMDSENTIE_Msk               /*!<Command Sent Interrupt Enable              */
14561 #define SDMMC_MASK_DATAENDIE_Pos        (8U)
14562 #define SDMMC_MASK_DATAENDIE_Msk        (0x1U << SDMMC_MASK_DATAENDIE_Pos)     /*!< 0x00000100 */
14563 #define SDMMC_MASK_DATAENDIE            SDMMC_MASK_DATAENDIE_Msk               /*!<Data End Interrupt Enable                  */
14564 #define SDMMC_MASK_DBCKENDIE_Pos        (10U)
14565 #define SDMMC_MASK_DBCKENDIE_Msk        (0x1U << SDMMC_MASK_DBCKENDIE_Pos)     /*!< 0x00000400 */
14566 #define SDMMC_MASK_DBCKENDIE            SDMMC_MASK_DBCKENDIE_Msk               /*!<Data Block End Interrupt Enable            */
14567 #define SDMMC_MASK_CMDACTIE_Pos         (11U)
14568 #define SDMMC_MASK_CMDACTIE_Msk         (0x1U << SDMMC_MASK_CMDACTIE_Pos)      /*!< 0x00000800 */
14569 #define SDMMC_MASK_CMDACTIE             SDMMC_MASK_CMDACTIE_Msk                /*!<CCommand Acting Interrupt Enable           */
14570 #define SDMMC_MASK_TXACTIE_Pos          (12U)
14571 #define SDMMC_MASK_TXACTIE_Msk          (0x1U << SDMMC_MASK_TXACTIE_Pos)       /*!< 0x00001000 */
14572 #define SDMMC_MASK_TXACTIE              SDMMC_MASK_TXACTIE_Msk                 /*!<Data Transmit Acting Interrupt Enable      */
14573 #define SDMMC_MASK_RXACTIE_Pos          (13U)
14574 #define SDMMC_MASK_RXACTIE_Msk          (0x1U << SDMMC_MASK_RXACTIE_Pos)       /*!< 0x00002000 */
14575 #define SDMMC_MASK_RXACTIE              SDMMC_MASK_RXACTIE_Msk                 /*!<Data receive acting interrupt enabled      */
14576 #define SDMMC_MASK_TXFIFOHEIE_Pos       (14U)
14577 #define SDMMC_MASK_TXFIFOHEIE_Msk       (0x1U << SDMMC_MASK_TXFIFOHEIE_Pos)    /*!< 0x00004000 */
14578 #define SDMMC_MASK_TXFIFOHEIE           SDMMC_MASK_TXFIFOHEIE_Msk              /*!<Tx FIFO Half Empty interrupt Enable        */
14579 #define SDMMC_MASK_RXFIFOHFIE_Pos       (15U)
14580 #define SDMMC_MASK_RXFIFOHFIE_Msk       (0x1U << SDMMC_MASK_RXFIFOHFIE_Pos)    /*!< 0x00008000 */
14581 #define SDMMC_MASK_RXFIFOHFIE           SDMMC_MASK_RXFIFOHFIE_Msk              /*!<Rx FIFO Half Full interrupt Enable         */
14582 #define SDMMC_MASK_TXFIFOFIE_Pos        (16U)
14583 #define SDMMC_MASK_TXFIFOFIE_Msk        (0x1U << SDMMC_MASK_TXFIFOFIE_Pos)     /*!< 0x00010000 */
14584 #define SDMMC_MASK_TXFIFOFIE            SDMMC_MASK_TXFIFOFIE_Msk               /*!<Tx FIFO Full interrupt Enable              */
14585 #define SDMMC_MASK_RXFIFOFIE_Pos        (17U)
14586 #define SDMMC_MASK_RXFIFOFIE_Msk        (0x1U << SDMMC_MASK_RXFIFOFIE_Pos)     /*!< 0x00020000 */
14587 #define SDMMC_MASK_RXFIFOFIE            SDMMC_MASK_RXFIFOFIE_Msk               /*!<Rx FIFO Full interrupt Enable              */
14588 #define SDMMC_MASK_TXFIFOEIE_Pos        (18U)
14589 #define SDMMC_MASK_TXFIFOEIE_Msk        (0x1U << SDMMC_MASK_TXFIFOEIE_Pos)     /*!< 0x00040000 */
14590 #define SDMMC_MASK_TXFIFOEIE            SDMMC_MASK_TXFIFOEIE_Msk               /*!<Tx FIFO Empty interrupt Enable             */
14591 #define SDMMC_MASK_RXFIFOEIE_Pos        (19U)
14592 #define SDMMC_MASK_RXFIFOEIE_Msk        (0x1U << SDMMC_MASK_RXFIFOEIE_Pos)     /*!< 0x00080000 */
14593 #define SDMMC_MASK_RXFIFOEIE            SDMMC_MASK_RXFIFOEIE_Msk               /*!<Rx FIFO Empty interrupt Enable             */
14594 #define SDMMC_MASK_TXDAVLIE_Pos         (20U)
14595 #define SDMMC_MASK_TXDAVLIE_Msk         (0x1U << SDMMC_MASK_TXDAVLIE_Pos)      /*!< 0x00100000 */
14596 #define SDMMC_MASK_TXDAVLIE             SDMMC_MASK_TXDAVLIE_Msk                /*!<Data available in Tx FIFO interrupt Enable */
14597 #define SDMMC_MASK_RXDAVLIE_Pos         (21U)
14598 #define SDMMC_MASK_RXDAVLIE_Msk         (0x1U << SDMMC_MASK_RXDAVLIE_Pos)      /*!< 0x00200000 */
14599 #define SDMMC_MASK_RXDAVLIE             SDMMC_MASK_RXDAVLIE_Msk                /*!<Data available in Rx FIFO interrupt Enable */
14600 #define SDMMC_MASK_SDIOITIE_Pos         (22U)
14601 #define SDMMC_MASK_SDIOITIE_Msk         (0x1U << SDMMC_MASK_SDIOITIE_Pos)      /*!< 0x00400000 */
14602 #define SDMMC_MASK_SDIOITIE             SDMMC_MASK_SDIOITIE_Msk                /*!<SDIO Mode Interrupt Received interrupt Enable */
14603 
14604 /*****************  Bit definition for SDMMC_FIFOCNT register  *****************/
14605 #define SDMMC_FIFOCNT_FIFOCOUNT_Pos     (0U)
14606 #define SDMMC_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFU << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
14607 #define SDMMC_FIFOCNT_FIFOCOUNT         SDMMC_FIFOCNT_FIFOCOUNT_Msk            /*!<Remaining number of words to be written to or read from the FIFO */
14608 
14609 /******************  Bit definition for SDMMC_FIFO register  *******************/
14610 #define SDMMC_FIFO_FIFODATA_Pos         (0U)
14611 #define SDMMC_FIFO_FIFODATA_Msk         (0xFFFFFFFFU << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
14612 #define SDMMC_FIFO_FIFODATA             SDMMC_FIFO_FIFODATA_Msk                /*!<Receive and transmit FIFO data */
14613 
14614 /******************************************************************************/
14615 /*                                                                            */
14616 /*                        Serial Peripheral Interface (SPI)                   */
14617 /*                                                                            */
14618 /******************************************************************************/
14619 /*******************  Bit definition for SPI_CR1 register  ********************/
14620 #define SPI_CR1_CPHA_Pos         (0U)
14621 #define SPI_CR1_CPHA_Msk         (0x1U << SPI_CR1_CPHA_Pos)                    /*!< 0x00000001 */
14622 #define SPI_CR1_CPHA             SPI_CR1_CPHA_Msk                              /*!<Clock Phase      */
14623 #define SPI_CR1_CPOL_Pos         (1U)
14624 #define SPI_CR1_CPOL_Msk         (0x1U << SPI_CR1_CPOL_Pos)                    /*!< 0x00000002 */
14625 #define SPI_CR1_CPOL             SPI_CR1_CPOL_Msk                              /*!<Clock Polarity   */
14626 #define SPI_CR1_MSTR_Pos         (2U)
14627 #define SPI_CR1_MSTR_Msk         (0x1U << SPI_CR1_MSTR_Pos)                    /*!< 0x00000004 */
14628 #define SPI_CR1_MSTR             SPI_CR1_MSTR_Msk                              /*!<Master Selection */
14629 
14630 #define SPI_CR1_BR_Pos           (3U)
14631 #define SPI_CR1_BR_Msk           (0x7U << SPI_CR1_BR_Pos)                      /*!< 0x00000038 */
14632 #define SPI_CR1_BR               SPI_CR1_BR_Msk                                /*!<BR[2:0] bits (Baud Rate Control) */
14633 #define SPI_CR1_BR_0             (0x1U << SPI_CR1_BR_Pos)                      /*!< 0x00000008 */
14634 #define SPI_CR1_BR_1             (0x2U << SPI_CR1_BR_Pos)                      /*!< 0x00000010 */
14635 #define SPI_CR1_BR_2             (0x4U << SPI_CR1_BR_Pos)                      /*!< 0x00000020 */
14636 
14637 #define SPI_CR1_SPE_Pos          (6U)
14638 #define SPI_CR1_SPE_Msk          (0x1U << SPI_CR1_SPE_Pos)                     /*!< 0x00000040 */
14639 #define SPI_CR1_SPE              SPI_CR1_SPE_Msk                               /*!<SPI Enable                          */
14640 #define SPI_CR1_LSBFIRST_Pos     (7U)
14641 #define SPI_CR1_LSBFIRST_Msk     (0x1U << SPI_CR1_LSBFIRST_Pos)                /*!< 0x00000080 */
14642 #define SPI_CR1_LSBFIRST         SPI_CR1_LSBFIRST_Msk                          /*!<Frame Format                        */
14643 #define SPI_CR1_SSI_Pos          (8U)
14644 #define SPI_CR1_SSI_Msk          (0x1U << SPI_CR1_SSI_Pos)                     /*!< 0x00000100 */
14645 #define SPI_CR1_SSI              SPI_CR1_SSI_Msk                               /*!<Internal slave select               */
14646 #define SPI_CR1_SSM_Pos          (9U)
14647 #define SPI_CR1_SSM_Msk          (0x1U << SPI_CR1_SSM_Pos)                     /*!< 0x00000200 */
14648 #define SPI_CR1_SSM              SPI_CR1_SSM_Msk                               /*!<Software slave management           */
14649 #define SPI_CR1_RXONLY_Pos       (10U)
14650 #define SPI_CR1_RXONLY_Msk       (0x1U << SPI_CR1_RXONLY_Pos)                  /*!< 0x00000400 */
14651 #define SPI_CR1_RXONLY           SPI_CR1_RXONLY_Msk                            /*!<Receive only                        */
14652 #define SPI_CR1_CRCL_Pos         (11U)
14653 #define SPI_CR1_CRCL_Msk         (0x1U << SPI_CR1_CRCL_Pos)                    /*!< 0x00000800 */
14654 #define SPI_CR1_CRCL             SPI_CR1_CRCL_Msk                              /*!< CRC Length */
14655 #define SPI_CR1_CRCNEXT_Pos      (12U)
14656 #define SPI_CR1_CRCNEXT_Msk      (0x1U << SPI_CR1_CRCNEXT_Pos)                 /*!< 0x00001000 */
14657 #define SPI_CR1_CRCNEXT          SPI_CR1_CRCNEXT_Msk                           /*!<Transmit CRC next                   */
14658 #define SPI_CR1_CRCEN_Pos        (13U)
14659 #define SPI_CR1_CRCEN_Msk        (0x1U << SPI_CR1_CRCEN_Pos)                   /*!< 0x00002000 */
14660 #define SPI_CR1_CRCEN            SPI_CR1_CRCEN_Msk                             /*!<Hardware CRC calculation enable     */
14661 #define SPI_CR1_BIDIOE_Pos       (14U)
14662 #define SPI_CR1_BIDIOE_Msk       (0x1U << SPI_CR1_BIDIOE_Pos)                  /*!< 0x00004000 */
14663 #define SPI_CR1_BIDIOE           SPI_CR1_BIDIOE_Msk                            /*!<Output enable in bidirectional mode */
14664 #define SPI_CR1_BIDIMODE_Pos     (15U)
14665 #define SPI_CR1_BIDIMODE_Msk     (0x1U << SPI_CR1_BIDIMODE_Pos)                /*!< 0x00008000 */
14666 #define SPI_CR1_BIDIMODE         SPI_CR1_BIDIMODE_Msk                          /*!<Bidirectional data mode enable      */
14667 
14668 /*******************  Bit definition for SPI_CR2 register  ********************/
14669 #define SPI_CR2_RXDMAEN_Pos      (0U)
14670 #define SPI_CR2_RXDMAEN_Msk      (0x1U << SPI_CR2_RXDMAEN_Pos)                 /*!< 0x00000001 */
14671 #define SPI_CR2_RXDMAEN          SPI_CR2_RXDMAEN_Msk                           /*!< Rx Buffer DMA Enable */
14672 #define SPI_CR2_TXDMAEN_Pos      (1U)
14673 #define SPI_CR2_TXDMAEN_Msk      (0x1U << SPI_CR2_TXDMAEN_Pos)                 /*!< 0x00000002 */
14674 #define SPI_CR2_TXDMAEN          SPI_CR2_TXDMAEN_Msk                           /*!< Tx Buffer DMA Enable */
14675 #define SPI_CR2_SSOE_Pos         (2U)
14676 #define SPI_CR2_SSOE_Msk         (0x1U << SPI_CR2_SSOE_Pos)                    /*!< 0x00000004 */
14677 #define SPI_CR2_SSOE             SPI_CR2_SSOE_Msk                              /*!< SS Output Enable */
14678 #define SPI_CR2_NSSP_Pos         (3U)
14679 #define SPI_CR2_NSSP_Msk         (0x1U << SPI_CR2_NSSP_Pos)                    /*!< 0x00000008 */
14680 #define SPI_CR2_NSSP             SPI_CR2_NSSP_Msk                              /*!< NSS pulse management Enable */
14681 #define SPI_CR2_FRF_Pos          (4U)
14682 #define SPI_CR2_FRF_Msk          (0x1U << SPI_CR2_FRF_Pos)                     /*!< 0x00000010 */
14683 #define SPI_CR2_FRF              SPI_CR2_FRF_Msk                               /*!< Frame Format Enable */
14684 #define SPI_CR2_ERRIE_Pos        (5U)
14685 #define SPI_CR2_ERRIE_Msk        (0x1U << SPI_CR2_ERRIE_Pos)                   /*!< 0x00000020 */
14686 #define SPI_CR2_ERRIE            SPI_CR2_ERRIE_Msk                             /*!< Error Interrupt Enable */
14687 #define SPI_CR2_RXNEIE_Pos       (6U)
14688 #define SPI_CR2_RXNEIE_Msk       (0x1U << SPI_CR2_RXNEIE_Pos)                  /*!< 0x00000040 */
14689 #define SPI_CR2_RXNEIE           SPI_CR2_RXNEIE_Msk                            /*!< RX buffer Not Empty Interrupt Enable */
14690 #define SPI_CR2_TXEIE_Pos        (7U)
14691 #define SPI_CR2_TXEIE_Msk        (0x1U << SPI_CR2_TXEIE_Pos)                   /*!< 0x00000080 */
14692 #define SPI_CR2_TXEIE            SPI_CR2_TXEIE_Msk                             /*!< Tx buffer Empty Interrupt Enable */
14693 #define SPI_CR2_DS_Pos           (8U)
14694 #define SPI_CR2_DS_Msk           (0xFU << SPI_CR2_DS_Pos)                      /*!< 0x00000F00 */
14695 #define SPI_CR2_DS               SPI_CR2_DS_Msk                                /*!< DS[3:0] Data Size */
14696 #define SPI_CR2_DS_0             (0x1U << SPI_CR2_DS_Pos)                      /*!< 0x00000100 */
14697 #define SPI_CR2_DS_1             (0x2U << SPI_CR2_DS_Pos)                      /*!< 0x00000200 */
14698 #define SPI_CR2_DS_2             (0x4U << SPI_CR2_DS_Pos)                      /*!< 0x00000400 */
14699 #define SPI_CR2_DS_3             (0x8U << SPI_CR2_DS_Pos)                      /*!< 0x00000800 */
14700 #define SPI_CR2_FRXTH_Pos        (12U)
14701 #define SPI_CR2_FRXTH_Msk        (0x1U << SPI_CR2_FRXTH_Pos)                   /*!< 0x00001000 */
14702 #define SPI_CR2_FRXTH            SPI_CR2_FRXTH_Msk                             /*!< FIFO reception Threshold */
14703 #define SPI_CR2_LDMARX_Pos       (13U)
14704 #define SPI_CR2_LDMARX_Msk       (0x1U << SPI_CR2_LDMARX_Pos)                  /*!< 0x00002000 */
14705 #define SPI_CR2_LDMARX           SPI_CR2_LDMARX_Msk                            /*!< Last DMA transfer for reception */
14706 #define SPI_CR2_LDMATX_Pos       (14U)
14707 #define SPI_CR2_LDMATX_Msk       (0x1U << SPI_CR2_LDMATX_Pos)                  /*!< 0x00004000 */
14708 #define SPI_CR2_LDMATX           SPI_CR2_LDMATX_Msk                            /*!< Last DMA transfer for transmission */
14709 
14710 /********************  Bit definition for SPI_SR register  ********************/
14711 #define SPI_SR_RXNE_Pos          (0U)
14712 #define SPI_SR_RXNE_Msk          (0x1U << SPI_SR_RXNE_Pos)                     /*!< 0x00000001 */
14713 #define SPI_SR_RXNE              SPI_SR_RXNE_Msk                               /*!< Receive buffer Not Empty */
14714 #define SPI_SR_TXE_Pos           (1U)
14715 #define SPI_SR_TXE_Msk           (0x1U << SPI_SR_TXE_Pos)                      /*!< 0x00000002 */
14716 #define SPI_SR_TXE               SPI_SR_TXE_Msk                                /*!< Transmit buffer Empty */
14717 #define SPI_SR_CHSIDE_Pos        (2U)
14718 #define SPI_SR_CHSIDE_Msk        (0x1U << SPI_SR_CHSIDE_Pos)                   /*!< 0x00000004 */
14719 #define SPI_SR_CHSIDE            SPI_SR_CHSIDE_Msk                             /*!< Channel side */
14720 #define SPI_SR_UDR_Pos           (3U)
14721 #define SPI_SR_UDR_Msk           (0x1U << SPI_SR_UDR_Pos)                      /*!< 0x00000008 */
14722 #define SPI_SR_UDR               SPI_SR_UDR_Msk                                /*!< Underrun flag */
14723 #define SPI_SR_CRCERR_Pos        (4U)
14724 #define SPI_SR_CRCERR_Msk        (0x1U << SPI_SR_CRCERR_Pos)                   /*!< 0x00000010 */
14725 #define SPI_SR_CRCERR            SPI_SR_CRCERR_Msk                             /*!< CRC Error flag */
14726 #define SPI_SR_MODF_Pos          (5U)
14727 #define SPI_SR_MODF_Msk          (0x1U << SPI_SR_MODF_Pos)                     /*!< 0x00000020 */
14728 #define SPI_SR_MODF              SPI_SR_MODF_Msk                               /*!< Mode fault */
14729 #define SPI_SR_OVR_Pos           (6U)
14730 #define SPI_SR_OVR_Msk           (0x1U << SPI_SR_OVR_Pos)                      /*!< 0x00000040 */
14731 #define SPI_SR_OVR               SPI_SR_OVR_Msk                                /*!< Overrun flag */
14732 #define SPI_SR_BSY_Pos           (7U)
14733 #define SPI_SR_BSY_Msk           (0x1U << SPI_SR_BSY_Pos)                      /*!< 0x00000080 */
14734 #define SPI_SR_BSY               SPI_SR_BSY_Msk                                /*!< Busy flag */
14735 #define SPI_SR_FRE_Pos           (8U)
14736 #define SPI_SR_FRE_Msk           (0x1U << SPI_SR_FRE_Pos)                      /*!< 0x00000100 */
14737 #define SPI_SR_FRE               SPI_SR_FRE_Msk                                /*!< TI frame format error */
14738 #define SPI_SR_FRLVL_Pos         (9U)
14739 #define SPI_SR_FRLVL_Msk         (0x3U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000600 */
14740 #define SPI_SR_FRLVL             SPI_SR_FRLVL_Msk                              /*!< FIFO Reception Level */
14741 #define SPI_SR_FRLVL_0           (0x1U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000200 */
14742 #define SPI_SR_FRLVL_1           (0x2U << SPI_SR_FRLVL_Pos)                    /*!< 0x00000400 */
14743 #define SPI_SR_FTLVL_Pos         (11U)
14744 #define SPI_SR_FTLVL_Msk         (0x3U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001800 */
14745 #define SPI_SR_FTLVL             SPI_SR_FTLVL_Msk                              /*!< FIFO Transmission Level */
14746 #define SPI_SR_FTLVL_0           (0x1U << SPI_SR_FTLVL_Pos)                    /*!< 0x00000800 */
14747 #define SPI_SR_FTLVL_1           (0x2U << SPI_SR_FTLVL_Pos)                    /*!< 0x00001000 */
14748 
14749 /********************  Bit definition for SPI_DR register  ********************/
14750 #define SPI_DR_DR_Pos            (0U)
14751 #define SPI_DR_DR_Msk            (0xFFFFU << SPI_DR_DR_Pos)                    /*!< 0x0000FFFF */
14752 #define SPI_DR_DR                SPI_DR_DR_Msk                                 /*!<Data Register           */
14753 
14754 /*******************  Bit definition for SPI_CRCPR register  ******************/
14755 #define SPI_CRCPR_CRCPOLY_Pos    (0U)
14756 #define SPI_CRCPR_CRCPOLY_Msk    (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)            /*!< 0x0000FFFF */
14757 #define SPI_CRCPR_CRCPOLY        SPI_CRCPR_CRCPOLY_Msk                         /*!<CRC polynomial register */
14758 
14759 /******************  Bit definition for SPI_RXCRCR register  ******************/
14760 #define SPI_RXCRCR_RXCRC_Pos     (0U)
14761 #define SPI_RXCRCR_RXCRC_Msk     (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)             /*!< 0x0000FFFF */
14762 #define SPI_RXCRCR_RXCRC         SPI_RXCRCR_RXCRC_Msk                          /*!<Rx CRC Register         */
14763 
14764 /******************  Bit definition for SPI_TXCRCR register  ******************/
14765 #define SPI_TXCRCR_TXCRC_Pos     (0U)
14766 #define SPI_TXCRCR_TXCRC_Msk     (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)             /*!< 0x0000FFFF */
14767 #define SPI_TXCRCR_TXCRC         SPI_TXCRCR_TXCRC_Msk                          /*!<Tx CRC Register         */
14768 
14769 /******************************************************************************/
14770 /*                                                                            */
14771 /*                                    QUADSPI                                 */
14772 /*                                                                            */
14773 /******************************************************************************/
14774 /*****************  Bit definition for QUADSPI_CR register  *******************/
14775 #define QUADSPI_CR_EN_Pos              (0U)
14776 #define QUADSPI_CR_EN_Msk              (0x1U << QUADSPI_CR_EN_Pos)             /*!< 0x00000001 */
14777 #define QUADSPI_CR_EN                  QUADSPI_CR_EN_Msk                       /*!< Enable */
14778 #define QUADSPI_CR_ABORT_Pos           (1U)
14779 #define QUADSPI_CR_ABORT_Msk           (0x1U << QUADSPI_CR_ABORT_Pos)          /*!< 0x00000002 */
14780 #define QUADSPI_CR_ABORT               QUADSPI_CR_ABORT_Msk                    /*!< Abort request */
14781 #define QUADSPI_CR_DMAEN_Pos           (2U)
14782 #define QUADSPI_CR_DMAEN_Msk           (0x1U << QUADSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */
14783 #define QUADSPI_CR_DMAEN               QUADSPI_CR_DMAEN_Msk                    /*!< DMA Enable */
14784 #define QUADSPI_CR_TCEN_Pos            (3U)
14785 #define QUADSPI_CR_TCEN_Msk            (0x1U << QUADSPI_CR_TCEN_Pos)           /*!< 0x00000008 */
14786 #define QUADSPI_CR_TCEN                QUADSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */
14787 #define QUADSPI_CR_SSHIFT_Pos          (4U)
14788 #define QUADSPI_CR_SSHIFT_Msk          (0x1U << QUADSPI_CR_SSHIFT_Pos)         /*!< 0x00000010 */
14789 #define QUADSPI_CR_SSHIFT              QUADSPI_CR_SSHIFT_Msk                   /*!< Sample Shift */
14790 #define QUADSPI_CR_DFM_Pos             (6U)
14791 #define QUADSPI_CR_DFM_Msk             (0x1U << QUADSPI_CR_DFM_Pos)            /*!< 0x00000040 */
14792 #define QUADSPI_CR_DFM                 QUADSPI_CR_DFM_Msk                      /*!< Dual-flash mode */
14793 #define QUADSPI_CR_FSEL_Pos            (7U)
14794 #define QUADSPI_CR_FSEL_Msk            (0x1U << QUADSPI_CR_FSEL_Pos)           /*!< 0x00000080 */
14795 #define QUADSPI_CR_FSEL                QUADSPI_CR_FSEL_Msk                     /*!< Flash memory selection */
14796 #define QUADSPI_CR_FTHRES_Pos          (8U)
14797 #define QUADSPI_CR_FTHRES_Msk          (0xFU << QUADSPI_CR_FTHRES_Pos)         /*!< 0x00000F00 */
14798 #define QUADSPI_CR_FTHRES              QUADSPI_CR_FTHRES_Msk                   /*!< FTHRES[3:0] FIFO Level */
14799 #define QUADSPI_CR_TEIE_Pos            (16U)
14800 #define QUADSPI_CR_TEIE_Msk            (0x1U << QUADSPI_CR_TEIE_Pos)           /*!< 0x00010000 */
14801 #define QUADSPI_CR_TEIE                QUADSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */
14802 #define QUADSPI_CR_TCIE_Pos            (17U)
14803 #define QUADSPI_CR_TCIE_Msk            (0x1U << QUADSPI_CR_TCIE_Pos)           /*!< 0x00020000 */
14804 #define QUADSPI_CR_TCIE                QUADSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */
14805 #define QUADSPI_CR_FTIE_Pos            (18U)
14806 #define QUADSPI_CR_FTIE_Msk            (0x1U << QUADSPI_CR_FTIE_Pos)           /*!< 0x00040000 */
14807 #define QUADSPI_CR_FTIE                QUADSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */
14808 #define QUADSPI_CR_SMIE_Pos            (19U)
14809 #define QUADSPI_CR_SMIE_Msk            (0x1U << QUADSPI_CR_SMIE_Pos)           /*!< 0x00080000 */
14810 #define QUADSPI_CR_SMIE                QUADSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */
14811 #define QUADSPI_CR_TOIE_Pos            (20U)
14812 #define QUADSPI_CR_TOIE_Msk            (0x1U << QUADSPI_CR_TOIE_Pos)           /*!< 0x00100000 */
14813 #define QUADSPI_CR_TOIE                QUADSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */
14814 #define QUADSPI_CR_APMS_Pos            (22U)
14815 #define QUADSPI_CR_APMS_Msk            (0x1U << QUADSPI_CR_APMS_Pos)           /*!< 0x00400000 */
14816 #define QUADSPI_CR_APMS                QUADSPI_CR_APMS_Msk                     /*!< Automatic Polling Mode Stop */
14817 #define QUADSPI_CR_PMM_Pos             (23U)
14818 #define QUADSPI_CR_PMM_Msk             (0x1U << QUADSPI_CR_PMM_Pos)            /*!< 0x00800000 */
14819 #define QUADSPI_CR_PMM                 QUADSPI_CR_PMM_Msk                      /*!< Polling Match Mode */
14820 #define QUADSPI_CR_PRESCALER_Pos       (24U)
14821 #define QUADSPI_CR_PRESCALER_Msk       (0xFFU << QUADSPI_CR_PRESCALER_Pos)     /*!< 0xFF000000 */
14822 #define QUADSPI_CR_PRESCALER           QUADSPI_CR_PRESCALER_Msk                /*!< PRESCALER[7:0] Clock prescaler */
14823 
14824 /*****************  Bit definition for QUADSPI_DCR register  ******************/
14825 #define QUADSPI_DCR_CKMODE_Pos         (0U)
14826 #define QUADSPI_DCR_CKMODE_Msk         (0x1U << QUADSPI_DCR_CKMODE_Pos)        /*!< 0x00000001 */
14827 #define QUADSPI_DCR_CKMODE             QUADSPI_DCR_CKMODE_Msk                  /*!< Mode 0 / Mode 3 */
14828 #define QUADSPI_DCR_CSHT_Pos           (8U)
14829 #define QUADSPI_DCR_CSHT_Msk           (0x7U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000700 */
14830 #define QUADSPI_DCR_CSHT               QUADSPI_DCR_CSHT_Msk                    /*!< CSHT[2:0]: ChipSelect High Time */
14831 #define QUADSPI_DCR_CSHT_0             (0x1U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000100 */
14832 #define QUADSPI_DCR_CSHT_1             (0x2U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000200 */
14833 #define QUADSPI_DCR_CSHT_2             (0x4U << QUADSPI_DCR_CSHT_Pos)          /*!< 0x00000400 */
14834 #define QUADSPI_DCR_FSIZE_Pos          (16U)
14835 #define QUADSPI_DCR_FSIZE_Msk          (0x1FU << QUADSPI_DCR_FSIZE_Pos)        /*!< 0x001F0000 */
14836 #define QUADSPI_DCR_FSIZE              QUADSPI_DCR_FSIZE_Msk                   /*!< FSIZE[4:0]: Flash Size */
14837 
14838 /******************  Bit definition for QUADSPI_SR register  *******************/
14839 #define QUADSPI_SR_TEF_Pos             (0U)
14840 #define QUADSPI_SR_TEF_Msk             (0x1U << QUADSPI_SR_TEF_Pos)            /*!< 0x00000001 */
14841 #define QUADSPI_SR_TEF                 QUADSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */
14842 #define QUADSPI_SR_TCF_Pos             (1U)
14843 #define QUADSPI_SR_TCF_Msk             (0x1U << QUADSPI_SR_TCF_Pos)            /*!< 0x00000002 */
14844 #define QUADSPI_SR_TCF                 QUADSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */
14845 #define QUADSPI_SR_FTF_Pos             (2U)
14846 #define QUADSPI_SR_FTF_Msk             (0x1U << QUADSPI_SR_FTF_Pos)            /*!< 0x00000004 */
14847 #define QUADSPI_SR_FTF                 QUADSPI_SR_FTF_Msk                      /*!< FIFO Threshlod Flag */
14848 #define QUADSPI_SR_SMF_Pos             (3U)
14849 #define QUADSPI_SR_SMF_Msk             (0x1U << QUADSPI_SR_SMF_Pos)            /*!< 0x00000008 */
14850 #define QUADSPI_SR_SMF                 QUADSPI_SR_SMF_Msk                      /*!< Status Match Flag */
14851 #define QUADSPI_SR_TOF_Pos             (4U)
14852 #define QUADSPI_SR_TOF_Msk             (0x1U << QUADSPI_SR_TOF_Pos)            /*!< 0x00000010 */
14853 #define QUADSPI_SR_TOF                 QUADSPI_SR_TOF_Msk                      /*!< Timeout Flag */
14854 #define QUADSPI_SR_BUSY_Pos            (5U)
14855 #define QUADSPI_SR_BUSY_Msk            (0x1U << QUADSPI_SR_BUSY_Pos)           /*!< 0x00000020 */
14856 #define QUADSPI_SR_BUSY                QUADSPI_SR_BUSY_Msk                     /*!< Busy */
14857 #define QUADSPI_SR_FLEVEL_Pos          (8U)
14858 #define QUADSPI_SR_FLEVEL_Msk          (0x1FU << QUADSPI_SR_FLEVEL_Pos)        /*!< 0x00001F00 */
14859 #define QUADSPI_SR_FLEVEL              QUADSPI_SR_FLEVEL_Msk                   /*!< FIFO Threshlod Flag */
14860 
14861 /******************  Bit definition for QUADSPI_FCR register  ******************/
14862 #define QUADSPI_FCR_CTEF_Pos           (0U)
14863 #define QUADSPI_FCR_CTEF_Msk           (0x1U << QUADSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */
14864 #define QUADSPI_FCR_CTEF               QUADSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */
14865 #define QUADSPI_FCR_CTCF_Pos           (1U)
14866 #define QUADSPI_FCR_CTCF_Msk           (0x1U << QUADSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */
14867 #define QUADSPI_FCR_CTCF               QUADSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */
14868 #define QUADSPI_FCR_CSMF_Pos           (3U)
14869 #define QUADSPI_FCR_CSMF_Msk           (0x1U << QUADSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */
14870 #define QUADSPI_FCR_CSMF               QUADSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */
14871 #define QUADSPI_FCR_CTOF_Pos           (4U)
14872 #define QUADSPI_FCR_CTOF_Msk           (0x1U << QUADSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */
14873 #define QUADSPI_FCR_CTOF               QUADSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */
14874 
14875 /******************  Bit definition for QUADSPI_DLR register  ******************/
14876 #define QUADSPI_DLR_DL_Pos             (0U)
14877 #define QUADSPI_DLR_DL_Msk             (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */
14878 #define QUADSPI_DLR_DL                 QUADSPI_DLR_DL_Msk                      /*!< DL[31:0]: Data Length */
14879 
14880 /******************  Bit definition for QUADSPI_CCR register  ******************/
14881 #define QUADSPI_CCR_INSTRUCTION_Pos    (0U)
14882 #define QUADSPI_CCR_INSTRUCTION_Msk    (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos)  /*!< 0x000000FF */
14883 #define QUADSPI_CCR_INSTRUCTION        QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
14884 #define QUADSPI_CCR_IMODE_Pos          (8U)
14885 #define QUADSPI_CCR_IMODE_Msk          (0x3U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000300 */
14886 #define QUADSPI_CCR_IMODE              QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
14887 #define QUADSPI_CCR_IMODE_0            (0x1U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000100 */
14888 #define QUADSPI_CCR_IMODE_1            (0x2U << QUADSPI_CCR_IMODE_Pos)         /*!< 0x00000200 */
14889 #define QUADSPI_CCR_ADMODE_Pos         (10U)
14890 #define QUADSPI_CCR_ADMODE_Msk         (0x3U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000C00 */
14891 #define QUADSPI_CCR_ADMODE             QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
14892 #define QUADSPI_CCR_ADMODE_0           (0x1U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */
14893 #define QUADSPI_CCR_ADMODE_1           (0x2U << QUADSPI_CCR_ADMODE_Pos)        /*!< 0x00000800 */
14894 #define QUADSPI_CCR_ADSIZE_Pos         (12U)
14895 #define QUADSPI_CCR_ADSIZE_Msk         (0x3U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */
14896 #define QUADSPI_CCR_ADSIZE             QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
14897 #define QUADSPI_CCR_ADSIZE_0           (0x1U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */
14898 #define QUADSPI_CCR_ADSIZE_1           (0x2U << QUADSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */
14899 #define QUADSPI_CCR_ABMODE_Pos         (14U)
14900 #define QUADSPI_CCR_ABMODE_Msk         (0x3U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x0000C000 */
14901 #define QUADSPI_CCR_ABMODE             QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
14902 #define QUADSPI_CCR_ABMODE_0           (0x1U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00004000 */
14903 #define QUADSPI_CCR_ABMODE_1           (0x2U << QUADSPI_CCR_ABMODE_Pos)        /*!< 0x00008000 */
14904 #define QUADSPI_CCR_ABSIZE_Pos         (16U)
14905 #define QUADSPI_CCR_ABSIZE_Msk         (0x3U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00030000 */
14906 #define QUADSPI_CCR_ABSIZE             QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
14907 #define QUADSPI_CCR_ABSIZE_0           (0x1U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00010000 */
14908 #define QUADSPI_CCR_ABSIZE_1           (0x2U << QUADSPI_CCR_ABSIZE_Pos)        /*!< 0x00020000 */
14909 #define QUADSPI_CCR_DCYC_Pos           (18U)
14910 #define QUADSPI_CCR_DCYC_Msk           (0x1FU << QUADSPI_CCR_DCYC_Pos)         /*!< 0x007C0000 */
14911 #define QUADSPI_CCR_DCYC               QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
14912 #define QUADSPI_CCR_DMODE_Pos          (24U)
14913 #define QUADSPI_CCR_DMODE_Msk          (0x3U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x03000000 */
14914 #define QUADSPI_CCR_DMODE              QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
14915 #define QUADSPI_CCR_DMODE_0            (0x1U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */
14916 #define QUADSPI_CCR_DMODE_1            (0x2U << QUADSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */
14917 #define QUADSPI_CCR_FMODE_Pos          (26U)
14918 #define QUADSPI_CCR_FMODE_Msk          (0x3U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x0C000000 */
14919 #define QUADSPI_CCR_FMODE              QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
14920 #define QUADSPI_CCR_FMODE_0            (0x1U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x04000000 */
14921 #define QUADSPI_CCR_FMODE_1            (0x2U << QUADSPI_CCR_FMODE_Pos)         /*!< 0x08000000 */
14922 #define QUADSPI_CCR_SIOO_Pos           (28U)
14923 #define QUADSPI_CCR_SIOO_Msk           (0x1U << QUADSPI_CCR_SIOO_Pos)          /*!< 0x10000000 */
14924 #define QUADSPI_CCR_SIOO               QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
14925 #define QUADSPI_CCR_DHHC_Pos           (30U)
14926 #define QUADSPI_CCR_DHHC_Msk           (0x1U << QUADSPI_CCR_DHHC_Pos)          /*!< 0x40000000 */
14927 #define QUADSPI_CCR_DHHC               QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold */
14928 #define QUADSPI_CCR_DDRM_Pos           (31U)
14929 #define QUADSPI_CCR_DDRM_Msk           (0x1U << QUADSPI_CCR_DDRM_Pos)          /*!< 0x80000000 */
14930 #define QUADSPI_CCR_DDRM               QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
14931 
14932 /******************  Bit definition for QUADSPI_AR register  *******************/
14933 #define QUADSPI_AR_ADDRESS_Pos         (0U)
14934 #define QUADSPI_AR_ADDRESS_Msk         (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
14935 #define QUADSPI_AR_ADDRESS             QUADSPI_AR_ADDRESS_Msk                  /*!< ADDRESS[31:0]: Address */
14936 
14937 /******************  Bit definition for QUADSPI_ABR register  ******************/
14938 #define QUADSPI_ABR_ALTERNATE_Pos      (0U)
14939 #define QUADSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
14940 #define QUADSPI_ABR_ALTERNATE          QUADSPI_ABR_ALTERNATE_Msk               /*!< ALTERNATE[31:0]: Alternate Bytes */
14941 
14942 /******************  Bit definition for QUADSPI_DR register  *******************/
14943 #define QUADSPI_DR_DATA_Pos            (0U)
14944 #define QUADSPI_DR_DATA_Msk            (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */
14945 #define QUADSPI_DR_DATA                QUADSPI_DR_DATA_Msk                     /*!< DATA[31:0]: Data */
14946 
14947 /******************  Bit definition for QUADSPI_PSMKR register  ****************/
14948 #define QUADSPI_PSMKR_MASK_Pos         (0U)
14949 #define QUADSPI_PSMKR_MASK_Msk         (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
14950 #define QUADSPI_PSMKR_MASK             QUADSPI_PSMKR_MASK_Msk                  /*!< MASK[31:0]: Status Mask */
14951 
14952 /******************  Bit definition for QUADSPI_PSMAR register  ****************/
14953 #define QUADSPI_PSMAR_MATCH_Pos        (0U)
14954 #define QUADSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
14955 #define QUADSPI_PSMAR_MATCH            QUADSPI_PSMAR_MATCH_Msk                 /*!< MATCH[31:0]: Status Match */
14956 
14957 /******************  Bit definition for QUADSPI_PIR register  *****************/
14958 #define QUADSPI_PIR_INTERVAL_Pos       (0U)
14959 #define QUADSPI_PIR_INTERVAL_Msk       (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */
14960 #define QUADSPI_PIR_INTERVAL           QUADSPI_PIR_INTERVAL_Msk                /*!< INTERVAL[15:0]: Polling Interval */
14961 
14962 /******************  Bit definition for QUADSPI_LPTR register  *****************/
14963 #define QUADSPI_LPTR_TIMEOUT_Pos       (0U)
14964 #define QUADSPI_LPTR_TIMEOUT_Msk       (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */
14965 #define QUADSPI_LPTR_TIMEOUT           QUADSPI_LPTR_TIMEOUT_Msk                /*!< TIMEOUT[15:0]: Timeout period */
14966 
14967 /******************************************************************************/
14968 /*                                                                            */
14969 /*                                 SYSCFG                                     */
14970 /*                                                                            */
14971 /******************************************************************************/
14972 /******************  Bit definition for SYSCFG_MEMRMP register  ***************/
14973 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
14974 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000007 */
14975 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
14976 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
14977 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
14978 #define SYSCFG_MEMRMP_MEM_MODE_2        (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000004 */
14979 
14980 #define SYSCFG_MEMRMP_FB_MODE_Pos       (8U)
14981 #define SYSCFG_MEMRMP_FB_MODE_Msk       (0x1U << SYSCFG_MEMRMP_FB_MODE_Pos)    /*!< 0x00000100 */
14982 #define SYSCFG_MEMRMP_FB_MODE           SYSCFG_MEMRMP_FB_MODE_Msk              /*!< Flash Bank mode selection */
14983 
14984 /******************  Bit definition for SYSCFG_CFGR1 register  ******************/
14985 #define SYSCFG_CFGR1_FWDIS_Pos          (0U)
14986 #define SYSCFG_CFGR1_FWDIS_Msk          (0x1U << SYSCFG_CFGR1_FWDIS_Pos)       /*!< 0x00000001 */
14987 #define SYSCFG_CFGR1_FWDIS              SYSCFG_CFGR1_FWDIS_Msk                 /*!< FIREWALL access enable*/
14988 #define SYSCFG_CFGR1_BOOSTEN_Pos        (8U)
14989 #define SYSCFG_CFGR1_BOOSTEN_Msk        (0x1U << SYSCFG_CFGR1_BOOSTEN_Pos)     /*!< 0x00000100 */
14990 #define SYSCFG_CFGR1_BOOSTEN            SYSCFG_CFGR1_BOOSTEN_Msk               /*!< I/O analog switch voltage booster enable */
14991 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos    (16U)
14992 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
14993 #define SYSCFG_CFGR1_I2C_PB6_FMP        SYSCFG_CFGR1_I2C_PB6_FMP_Msk           /*!< I2C PB6 Fast mode plus */
14994 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos    (17U)
14995 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
14996 #define SYSCFG_CFGR1_I2C_PB7_FMP        SYSCFG_CFGR1_I2C_PB7_FMP_Msk           /*!< I2C PB7 Fast mode plus */
14997 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos    (18U)
14998 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
14999 #define SYSCFG_CFGR1_I2C_PB8_FMP        SYSCFG_CFGR1_I2C_PB8_FMP_Msk           /*!< I2C PB8 Fast mode plus */
15000 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos    (19U)
15001 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk    (0x1U << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
15002 #define SYSCFG_CFGR1_I2C_PB9_FMP        SYSCFG_CFGR1_I2C_PB9_FMP_Msk           /*!< I2C PB9 Fast mode plus */
15003 #define SYSCFG_CFGR1_I2C1_FMP_Pos       (20U)
15004 #define SYSCFG_CFGR1_I2C1_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C1_FMP_Pos)    /*!< 0x00100000 */
15005 #define SYSCFG_CFGR1_I2C1_FMP           SYSCFG_CFGR1_I2C1_FMP_Msk              /*!< I2C1 Fast mode plus */
15006 #define SYSCFG_CFGR1_I2C2_FMP_Pos       (21U)
15007 #define SYSCFG_CFGR1_I2C2_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C2_FMP_Pos)    /*!< 0x00200000 */
15008 #define SYSCFG_CFGR1_I2C2_FMP           SYSCFG_CFGR1_I2C2_FMP_Msk              /*!< I2C2 Fast mode plus */
15009 #define SYSCFG_CFGR1_I2C3_FMP_Pos       (22U)
15010 #define SYSCFG_CFGR1_I2C3_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C3_FMP_Pos)    /*!< 0x00400000 */
15011 #define SYSCFG_CFGR1_I2C3_FMP           SYSCFG_CFGR1_I2C3_FMP_Msk              /*!< I2C3 Fast mode plus */
15012 #define SYSCFG_CFGR1_I2C4_FMP_Pos       (23U)
15013 #define SYSCFG_CFGR1_I2C4_FMP_Msk       (0x1U << SYSCFG_CFGR1_I2C4_FMP_Pos)    /*!< 0x00800000 */
15014 #define SYSCFG_CFGR1_I2C4_FMP           SYSCFG_CFGR1_I2C4_FMP_Msk              /*!< I2C4 Fast mode plus */
15015 #define SYSCFG_CFGR1_FPU_IE_0           (0x04000000U)                          /*!<  Invalid operation Interrupt enable */
15016 #define SYSCFG_CFGR1_FPU_IE_1           (0x08000000U)                          /*!<  Divide-by-zero Interrupt enable */
15017 #define SYSCFG_CFGR1_FPU_IE_2           (0x10000000U)                          /*!<  Underflow Interrupt enable */
15018 #define SYSCFG_CFGR1_FPU_IE_3           (0x20000000U)                          /*!<  Overflow Interrupt enable */
15019 #define SYSCFG_CFGR1_FPU_IE_4           (0x40000000U)                          /*!<  Input denormal Interrupt enable */
15020 #define SYSCFG_CFGR1_FPU_IE_5           (0x80000000U)                          /*!<  Inexact Interrupt enable (interrupt disabled at reset) */
15021 
15022 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
15023 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
15024 #define SYSCFG_EXTICR1_EXTI0_Msk        (0xFU << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
15025 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
15026 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
15027 #define SYSCFG_EXTICR1_EXTI1_Msk        (0xFU << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
15028 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
15029 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
15030 #define SYSCFG_EXTICR1_EXTI2_Msk        (0xFU << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
15031 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
15032 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
15033 #define SYSCFG_EXTICR1_EXTI3_Msk        (0xFU << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
15034 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
15035 
15036 /**
15037   * @brief   EXTI0 configuration
15038   */
15039 #define SYSCFG_EXTICR1_EXTI0_PA             (0x00000000U)                      /*!<PA[0] pin */
15040 #define SYSCFG_EXTICR1_EXTI0_PB             (0x00000001U)                      /*!<PB[0] pin */
15041 #define SYSCFG_EXTICR1_EXTI0_PC             (0x00000002U)                      /*!<PC[0] pin */
15042 #define SYSCFG_EXTICR1_EXTI0_PD             (0x00000003U)                      /*!<PD[0] pin */
15043 #define SYSCFG_EXTICR1_EXTI0_PE             (0x00000004U)                      /*!<PE[0] pin */
15044 #define SYSCFG_EXTICR1_EXTI0_PF             (0x00000005U)                      /*!<PF[0] pin */
15045 #define SYSCFG_EXTICR1_EXTI0_PG             (0x00000006U)                      /*!<PG[0] pin */
15046 #define SYSCFG_EXTICR1_EXTI0_PH             (0x00000007U)                      /*!<PH[0] pin */
15047 #define SYSCFG_EXTICR1_EXTI0_PI             (0x00000008U)                      /*!<PI[0] pin */
15048 
15049 /**
15050   * @brief   EXTI1 configuration
15051   */
15052 #define SYSCFG_EXTICR1_EXTI1_PA             (0x00000000U)                      /*!<PA[1] pin */
15053 #define SYSCFG_EXTICR1_EXTI1_PB             (0x00000010U)                      /*!<PB[1] pin */
15054 #define SYSCFG_EXTICR1_EXTI1_PC             (0x00000020U)                      /*!<PC[1] pin */
15055 #define SYSCFG_EXTICR1_EXTI1_PD             (0x00000030U)                      /*!<PD[1] pin */
15056 #define SYSCFG_EXTICR1_EXTI1_PE             (0x00000040U)                      /*!<PE[1] pin */
15057 #define SYSCFG_EXTICR1_EXTI1_PF             (0x00000050U)                      /*!<PF[1] pin */
15058 #define SYSCFG_EXTICR1_EXTI1_PG             (0x00000060U)                      /*!<PG[1] pin */
15059 #define SYSCFG_EXTICR1_EXTI1_PH             (0x00000070U)                      /*!<PH[1] pin */
15060 #define SYSCFG_EXTICR1_EXTI1_PI             (0x00000080U)                      /*!<PI[1] pin */
15061 
15062 /**
15063   * @brief   EXTI2 configuration
15064   */
15065 #define SYSCFG_EXTICR1_EXTI2_PA             (0x00000000U)                      /*!<PA[2] pin */
15066 #define SYSCFG_EXTICR1_EXTI2_PB             (0x00000100U)                      /*!<PB[2] pin */
15067 #define SYSCFG_EXTICR1_EXTI2_PC             (0x00000200U)                      /*!<PC[2] pin */
15068 #define SYSCFG_EXTICR1_EXTI2_PD             (0x00000300U)                      /*!<PD[2] pin */
15069 #define SYSCFG_EXTICR1_EXTI2_PE             (0x00000400U)                      /*!<PE[2] pin */
15070 #define SYSCFG_EXTICR1_EXTI2_PF             (0x00000500U)                      /*!<PF[2] pin */
15071 #define SYSCFG_EXTICR1_EXTI2_PG             (0x00000600U)                      /*!<PG[2] pin */
15072 #define SYSCFG_EXTICR1_EXTI2_PH             (0x00000700U)                      /*!<PH[2] pin */
15073 #define SYSCFG_EXTICR1_EXTI2_PI             (0x00000800U)                      /*!<PI[2] pin */
15074 
15075 /**
15076   * @brief   EXTI3 configuration
15077   */
15078 #define SYSCFG_EXTICR1_EXTI3_PA             (0x00000000U)                      /*!<PA[3] pin */
15079 #define SYSCFG_EXTICR1_EXTI3_PB             (0x00001000U)                      /*!<PB[3] pin */
15080 #define SYSCFG_EXTICR1_EXTI3_PC             (0x00002000U)                      /*!<PC[3] pin */
15081 #define SYSCFG_EXTICR1_EXTI3_PD             (0x00003000U)                      /*!<PD[3] pin */
15082 #define SYSCFG_EXTICR1_EXTI3_PE             (0x00004000U)                      /*!<PE[3] pin */
15083 #define SYSCFG_EXTICR1_EXTI3_PF             (0x00005000U)                      /*!<PF[3] pin */
15084 #define SYSCFG_EXTICR1_EXTI3_PG             (0x00006000U)                      /*!<PG[3] pin */
15085 #define SYSCFG_EXTICR1_EXTI3_PH             (0x00007000U)                      /*!<PH[3] pin */
15086 #define SYSCFG_EXTICR1_EXTI3_PI             (0x00008000U)                      /*!<PI[3] pin */
15087 
15088 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
15089 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
15090 #define SYSCFG_EXTICR2_EXTI4_Msk        (0xFU << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
15091 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
15092 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
15093 #define SYSCFG_EXTICR2_EXTI5_Msk        (0xFU << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
15094 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
15095 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
15096 #define SYSCFG_EXTICR2_EXTI6_Msk        (0xFU << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
15097 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
15098 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
15099 #define SYSCFG_EXTICR2_EXTI7_Msk        (0xFU << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
15100 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
15101 /**
15102   * @brief   EXTI4 configuration
15103   */
15104 #define SYSCFG_EXTICR2_EXTI4_PA             (0x00000000U)                      /*!<PA[4] pin */
15105 #define SYSCFG_EXTICR2_EXTI4_PB             (0x00000001U)                      /*!<PB[4] pin */
15106 #define SYSCFG_EXTICR2_EXTI4_PC             (0x00000002U)                      /*!<PC[4] pin */
15107 #define SYSCFG_EXTICR2_EXTI4_PD             (0x00000003U)                      /*!<PD[4] pin */
15108 #define SYSCFG_EXTICR2_EXTI4_PE             (0x00000004U)                      /*!<PE[4] pin */
15109 #define SYSCFG_EXTICR2_EXTI4_PF             (0x00000005U)                      /*!<PF[4] pin */
15110 #define SYSCFG_EXTICR2_EXTI4_PG             (0x00000006U)                      /*!<PG[4] pin */
15111 #define SYSCFG_EXTICR2_EXTI4_PH             (0x00000007U)                      /*!<PH[4] pin */
15112 #define SYSCFG_EXTICR2_EXTI4_PI             (0x00000008U)                      /*!<PI[4] pin */
15113 
15114 /**
15115   * @brief   EXTI5 configuration
15116   */
15117 #define SYSCFG_EXTICR2_EXTI5_PA             (0x00000000U)                      /*!<PA[5] pin */
15118 #define SYSCFG_EXTICR2_EXTI5_PB             (0x00000010U)                      /*!<PB[5] pin */
15119 #define SYSCFG_EXTICR2_EXTI5_PC             (0x00000020U)                      /*!<PC[5] pin */
15120 #define SYSCFG_EXTICR2_EXTI5_PD             (0x00000030U)                      /*!<PD[5] pin */
15121 #define SYSCFG_EXTICR2_EXTI5_PE             (0x00000040U)                      /*!<PE[5] pin */
15122 #define SYSCFG_EXTICR2_EXTI5_PF             (0x00000050U)                      /*!<PF[5] pin */
15123 #define SYSCFG_EXTICR2_EXTI5_PG             (0x00000060U)                      /*!<PG[5] pin */
15124 #define SYSCFG_EXTICR2_EXTI5_PH             (0x00000070U)                      /*!<PH[5] pin */
15125 #define SYSCFG_EXTICR2_EXTI5_PI             (0x00000080U)                      /*!<PI[5] pin */
15126 
15127 /**
15128   * @brief   EXTI6 configuration
15129   */
15130 #define SYSCFG_EXTICR2_EXTI6_PA             (0x00000000U)                      /*!<PA[6] pin */
15131 #define SYSCFG_EXTICR2_EXTI6_PB             (0x00000100U)                      /*!<PB[6] pin */
15132 #define SYSCFG_EXTICR2_EXTI6_PC             (0x00000200U)                      /*!<PC[6] pin */
15133 #define SYSCFG_EXTICR2_EXTI6_PD             (0x00000300U)                      /*!<PD[6] pin */
15134 #define SYSCFG_EXTICR2_EXTI6_PE             (0x00000400U)                      /*!<PE[6] pin */
15135 #define SYSCFG_EXTICR2_EXTI6_PF             (0x00000500U)                      /*!<PF[6] pin */
15136 #define SYSCFG_EXTICR2_EXTI6_PG             (0x00000600U)                      /*!<PG[6] pin */
15137 #define SYSCFG_EXTICR2_EXTI6_PH             (0x00000700U)                      /*!<PH[6] pin */
15138 #define SYSCFG_EXTICR2_EXTI6_PI             (0x00000800U)                      /*!<PI[6] pin */
15139 
15140 /**
15141   * @brief   EXTI7 configuration
15142   */
15143 #define SYSCFG_EXTICR2_EXTI7_PA             (0x00000000U)                      /*!<PA[7] pin */
15144 #define SYSCFG_EXTICR2_EXTI7_PB             (0x00001000U)                      /*!<PB[7] pin */
15145 #define SYSCFG_EXTICR2_EXTI7_PC             (0x00002000U)                      /*!<PC[7] pin */
15146 #define SYSCFG_EXTICR2_EXTI7_PD             (0x00003000U)                      /*!<PD[7] pin */
15147 #define SYSCFG_EXTICR2_EXTI7_PE             (0x00004000U)                      /*!<PE[7] pin */
15148 #define SYSCFG_EXTICR2_EXTI7_PF             (0x00005000U)                      /*!<PF[7] pin */
15149 #define SYSCFG_EXTICR2_EXTI7_PG             (0x00006000U)                      /*!<PG[7] pin */
15150 #define SYSCFG_EXTICR2_EXTI7_PH             (0x00007000U)                      /*!<PH[7] pin */
15151 #define SYSCFG_EXTICR2_EXTI7_PI             (0x00008000U)                      /*!<PI[7] pin */
15152 
15153 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
15154 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
15155 #define SYSCFG_EXTICR3_EXTI8_Msk        (0xFU << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
15156 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
15157 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
15158 #define SYSCFG_EXTICR3_EXTI9_Msk        (0xFU << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
15159 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
15160 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
15161 #define SYSCFG_EXTICR3_EXTI10_Msk       (0xFU << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
15162 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
15163 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
15164 #define SYSCFG_EXTICR3_EXTI11_Msk       (0xFU << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
15165 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
15166 
15167 /**
15168   * @brief   EXTI8 configuration
15169   */
15170 #define SYSCFG_EXTICR3_EXTI8_PA             (0x00000000U)                      /*!<PA[8] pin */
15171 #define SYSCFG_EXTICR3_EXTI8_PB             (0x00000001U)                      /*!<PB[8] pin */
15172 #define SYSCFG_EXTICR3_EXTI8_PC             (0x00000002U)                      /*!<PC[8] pin */
15173 #define SYSCFG_EXTICR3_EXTI8_PD             (0x00000003U)                      /*!<PD[8] pin */
15174 #define SYSCFG_EXTICR3_EXTI8_PE             (0x00000004U)                      /*!<PE[8] pin */
15175 #define SYSCFG_EXTICR3_EXTI8_PF             (0x00000005U)                      /*!<PF[8] pin */
15176 #define SYSCFG_EXTICR3_EXTI8_PG             (0x00000006U)                      /*!<PG[8] pin */
15177 #define SYSCFG_EXTICR3_EXTI8_PH             (0x00000007U)                      /*!<PH[8] pin */
15178 #define SYSCFG_EXTICR3_EXTI8_PI             (0x00000008U)                      /*!<PI[8] pin */
15179 
15180 /**
15181   * @brief   EXTI9 configuration
15182   */
15183 #define SYSCFG_EXTICR3_EXTI9_PA             (0x00000000U)                      /*!<PA[9] pin */
15184 #define SYSCFG_EXTICR3_EXTI9_PB             (0x00000010U)                      /*!<PB[9] pin */
15185 #define SYSCFG_EXTICR3_EXTI9_PC             (0x00000020U)                      /*!<PC[9] pin */
15186 #define SYSCFG_EXTICR3_EXTI9_PD             (0x00000030U)                      /*!<PD[9] pin */
15187 #define SYSCFG_EXTICR3_EXTI9_PE             (0x00000040U)                      /*!<PE[9] pin */
15188 #define SYSCFG_EXTICR3_EXTI9_PF             (0x00000050U)                      /*!<PF[9] pin */
15189 #define SYSCFG_EXTICR3_EXTI9_PG             (0x00000060U)                      /*!<PG[9] pin */
15190 #define SYSCFG_EXTICR3_EXTI9_PH             (0x00000070U)                      /*!<PH[9] pin */
15191 #define SYSCFG_EXTICR3_EXTI9_PI             (0x00000080U)                      /*!<PI[9] pin */
15192 
15193 /**
15194   * @brief   EXTI10 configuration
15195   */
15196 #define SYSCFG_EXTICR3_EXTI10_PA            (0x00000000U)                      /*!<PA[10] pin */
15197 #define SYSCFG_EXTICR3_EXTI10_PB            (0x00000100U)                      /*!<PB[10] pin */
15198 #define SYSCFG_EXTICR3_EXTI10_PC            (0x00000200U)                      /*!<PC[10] pin */
15199 #define SYSCFG_EXTICR3_EXTI10_PD            (0x00000300U)                      /*!<PD[10] pin */
15200 #define SYSCFG_EXTICR3_EXTI10_PE            (0x00000400U)                      /*!<PE[10] pin */
15201 #define SYSCFG_EXTICR3_EXTI10_PF            (0x00000500U)                      /*!<PF[10] pin */
15202 #define SYSCFG_EXTICR3_EXTI10_PG            (0x00000600U)                      /*!<PG[10] pin */
15203 #define SYSCFG_EXTICR3_EXTI10_PH            (0x00000700U)                      /*!<PH[10] pin */
15204 #define SYSCFG_EXTICR3_EXTI10_PI            (0x00000800U)                      /*!<PI[10] pin */
15205 
15206 /**
15207   * @brief   EXTI11 configuration
15208   */
15209 #define SYSCFG_EXTICR3_EXTI11_PA            (0x00000000U)                      /*!<PA[11] pin */
15210 #define SYSCFG_EXTICR3_EXTI11_PB            (0x00001000U)                      /*!<PB[11] pin */
15211 #define SYSCFG_EXTICR3_EXTI11_PC            (0x00002000U)                      /*!<PC[11] pin */
15212 #define SYSCFG_EXTICR3_EXTI11_PD            (0x00003000U)                      /*!<PD[11] pin */
15213 #define SYSCFG_EXTICR3_EXTI11_PE            (0x00004000U)                      /*!<PE[11] pin */
15214 #define SYSCFG_EXTICR3_EXTI11_PF            (0x00005000U)                      /*!<PF[11] pin */
15215 #define SYSCFG_EXTICR3_EXTI11_PG            (0x00006000U)                      /*!<PG[11] pin */
15216 #define SYSCFG_EXTICR3_EXTI11_PH            (0x00007000U)                      /*!<PH[11] pin */
15217 #define SYSCFG_EXTICR3_EXTI11_PI            (0x00008000U)                      /*!<PI[11] pin */
15218 
15219 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
15220 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
15221 #define SYSCFG_EXTICR4_EXTI12_Msk       (0x7U << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x00000007 */
15222 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
15223 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
15224 #define SYSCFG_EXTICR4_EXTI13_Msk       (0x7U << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x00000070 */
15225 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
15226 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
15227 #define SYSCFG_EXTICR4_EXTI14_Msk       (0x7U << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000700 */
15228 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
15229 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
15230 #define SYSCFG_EXTICR4_EXTI15_Msk       (0x7U << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x00007000 */
15231 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
15232 
15233 /**
15234   * @brief   EXTI12 configuration
15235   */
15236 #define SYSCFG_EXTICR4_EXTI12_PA            (0x00000000U)                      /*!<PA[12] pin */
15237 #define SYSCFG_EXTICR4_EXTI12_PB            (0x00000001U)                      /*!<PB[12] pin */
15238 #define SYSCFG_EXTICR4_EXTI12_PC            (0x00000002U)                      /*!<PC[12] pin */
15239 #define SYSCFG_EXTICR4_EXTI12_PD            (0x00000003U)                      /*!<PD[12] pin */
15240 #define SYSCFG_EXTICR4_EXTI12_PE            (0x00000004U)                      /*!<PE[12] pin */
15241 #define SYSCFG_EXTICR4_EXTI12_PF            (0x00000005U)                      /*!<PF[12] pin */
15242 #define SYSCFG_EXTICR4_EXTI12_PG            (0x00000006U)                      /*!<PG[12] pin */
15243 #define SYSCFG_EXTICR4_EXTI12_PH            (0x00000007U)                      /*!<PH[12] pin */
15244 
15245 /**
15246   * @brief   EXTI13 configuration
15247   */
15248 #define SYSCFG_EXTICR4_EXTI13_PA            (0x00000000U)                      /*!<PA[13] pin */
15249 #define SYSCFG_EXTICR4_EXTI13_PB            (0x00000010U)                      /*!<PB[13] pin */
15250 #define SYSCFG_EXTICR4_EXTI13_PC            (0x00000020U)                      /*!<PC[13] pin */
15251 #define SYSCFG_EXTICR4_EXTI13_PD            (0x00000030U)                      /*!<PD[13] pin */
15252 #define SYSCFG_EXTICR4_EXTI13_PE            (0x00000040U)                      /*!<PE[13] pin */
15253 #define SYSCFG_EXTICR4_EXTI13_PF            (0x00000050U)                      /*!<PF[13] pin */
15254 #define SYSCFG_EXTICR4_EXTI13_PG            (0x00000060U)                      /*!<PG[13] pin */
15255 #define SYSCFG_EXTICR4_EXTI13_PH            (0x00000070U)                      /*!<PH[13] pin */
15256 
15257 /**
15258   * @brief   EXTI14 configuration
15259   */
15260 #define SYSCFG_EXTICR4_EXTI14_PA            (0x00000000U)                      /*!<PA[14] pin */
15261 #define SYSCFG_EXTICR4_EXTI14_PB            (0x00000100U)                      /*!<PB[14] pin */
15262 #define SYSCFG_EXTICR4_EXTI14_PC            (0x00000200U)                      /*!<PC[14] pin */
15263 #define SYSCFG_EXTICR4_EXTI14_PD            (0x00000300U)                      /*!<PD[14] pin */
15264 #define SYSCFG_EXTICR4_EXTI14_PE            (0x00000400U)                      /*!<PE[14] pin */
15265 #define SYSCFG_EXTICR4_EXTI14_PF            (0x00000500U)                      /*!<PF[14] pin */
15266 #define SYSCFG_EXTICR4_EXTI14_PG            (0x00000600U)                      /*!<PG[14] pin */
15267 #define SYSCFG_EXTICR4_EXTI14_PH            (0x00000700U)                      /*!<PH[14] pin */
15268 
15269 /**
15270   * @brief   EXTI15 configuration
15271   */
15272 #define SYSCFG_EXTICR4_EXTI15_PA            (0x00000000U)                      /*!<PA[15] pin */
15273 #define SYSCFG_EXTICR4_EXTI15_PB            (0x00001000U)                      /*!<PB[15] pin */
15274 #define SYSCFG_EXTICR4_EXTI15_PC            (0x00002000U)                      /*!<PC[15] pin */
15275 #define SYSCFG_EXTICR4_EXTI15_PD            (0x00003000U)                      /*!<PD[15] pin */
15276 #define SYSCFG_EXTICR4_EXTI15_PE            (0x00004000U)                      /*!<PE[15] pin */
15277 #define SYSCFG_EXTICR4_EXTI15_PF            (0x00005000U)                      /*!<PF[15] pin */
15278 #define SYSCFG_EXTICR4_EXTI15_PG            (0x00006000U)                      /*!<PG[15] pin */
15279 #define SYSCFG_EXTICR4_EXTI15_PH            (0x00007000U)                      /*!<PH[15] pin */
15280 
15281 /******************  Bit definition for SYSCFG_SCSR register  ****************/
15282 #define SYSCFG_SCSR_SRAM2ER_Pos         (0U)
15283 #define SYSCFG_SCSR_SRAM2ER_Msk         (0x1U << SYSCFG_SCSR_SRAM2ER_Pos)      /*!< 0x00000001 */
15284 #define SYSCFG_SCSR_SRAM2ER             SYSCFG_SCSR_SRAM2ER_Msk                /*!< SRAM2 Erase Request */
15285 #define SYSCFG_SCSR_SRAM2BSY_Pos        (1U)
15286 #define SYSCFG_SCSR_SRAM2BSY_Msk        (0x1U << SYSCFG_SCSR_SRAM2BSY_Pos)     /*!< 0x00000002 */
15287 #define SYSCFG_SCSR_SRAM2BSY            SYSCFG_SCSR_SRAM2BSY_Msk               /*!< SRAM2 Erase Ongoing */
15288 
15289 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
15290 #define SYSCFG_CFGR2_CLL_Pos            (0U)
15291 #define SYSCFG_CFGR2_CLL_Msk            (0x1U << SYSCFG_CFGR2_CLL_Pos)         /*!< 0x00000001 */
15292 #define SYSCFG_CFGR2_CLL                SYSCFG_CFGR2_CLL_Msk                   /*!< Core Lockup Lock */
15293 #define SYSCFG_CFGR2_SPL_Pos            (1U)
15294 #define SYSCFG_CFGR2_SPL_Msk            (0x1U << SYSCFG_CFGR2_SPL_Pos)         /*!< 0x00000002 */
15295 #define SYSCFG_CFGR2_SPL                SYSCFG_CFGR2_SPL_Msk                   /*!< SRAM Parity Lock*/
15296 #define SYSCFG_CFGR2_PVDL_Pos           (2U)
15297 #define SYSCFG_CFGR2_PVDL_Msk           (0x1U << SYSCFG_CFGR2_PVDL_Pos)        /*!< 0x00000004 */
15298 #define SYSCFG_CFGR2_PVDL               SYSCFG_CFGR2_PVDL_Msk                  /*!<  PVD Lock */
15299 #define SYSCFG_CFGR2_ECCL_Pos           (3U)
15300 #define SYSCFG_CFGR2_ECCL_Msk           (0x1U << SYSCFG_CFGR2_ECCL_Pos)        /*!< 0x00000008 */
15301 #define SYSCFG_CFGR2_ECCL               SYSCFG_CFGR2_ECCL_Msk                  /*!< ECC Lock*/
15302 #define SYSCFG_CFGR2_SPF_Pos            (8U)
15303 #define SYSCFG_CFGR2_SPF_Msk            (0x1U << SYSCFG_CFGR2_SPF_Pos)         /*!< 0x00000100 */
15304 #define SYSCFG_CFGR2_SPF                SYSCFG_CFGR2_SPF_Msk                   /*!< SRAM Parity Flag */
15305 
15306 /******************  Bit definition for SYSCFG_SWPR register  ****************/
15307 #define SYSCFG_SWPR_PAGE0_Pos           (0U)
15308 #define SYSCFG_SWPR_PAGE0_Msk           (0x1U << SYSCFG_SWPR_PAGE0_Pos)        /*!< 0x00000001 */
15309 #define SYSCFG_SWPR_PAGE0               SYSCFG_SWPR_PAGE0_Msk                  /*!< SRAM2 Write protection page 0 */
15310 #define SYSCFG_SWPR_PAGE1_Pos           (1U)
15311 #define SYSCFG_SWPR_PAGE1_Msk           (0x1U << SYSCFG_SWPR_PAGE1_Pos)        /*!< 0x00000002 */
15312 #define SYSCFG_SWPR_PAGE1               SYSCFG_SWPR_PAGE1_Msk                  /*!< SRAM2 Write protection page 1 */
15313 #define SYSCFG_SWPR_PAGE2_Pos           (2U)
15314 #define SYSCFG_SWPR_PAGE2_Msk           (0x1U << SYSCFG_SWPR_PAGE2_Pos)        /*!< 0x00000004 */
15315 #define SYSCFG_SWPR_PAGE2               SYSCFG_SWPR_PAGE2_Msk                  /*!< SRAM2 Write protection page 2 */
15316 #define SYSCFG_SWPR_PAGE3_Pos           (3U)
15317 #define SYSCFG_SWPR_PAGE3_Msk           (0x1U << SYSCFG_SWPR_PAGE3_Pos)        /*!< 0x00000008 */
15318 #define SYSCFG_SWPR_PAGE3               SYSCFG_SWPR_PAGE3_Msk                  /*!< SRAM2 Write protection page 3 */
15319 #define SYSCFG_SWPR_PAGE4_Pos           (4U)
15320 #define SYSCFG_SWPR_PAGE4_Msk           (0x1U << SYSCFG_SWPR_PAGE4_Pos)        /*!< 0x00000010 */
15321 #define SYSCFG_SWPR_PAGE4               SYSCFG_SWPR_PAGE4_Msk                  /*!< SRAM2 Write protection page 4 */
15322 #define SYSCFG_SWPR_PAGE5_Pos           (5U)
15323 #define SYSCFG_SWPR_PAGE5_Msk           (0x1U << SYSCFG_SWPR_PAGE5_Pos)        /*!< 0x00000020 */
15324 #define SYSCFG_SWPR_PAGE5               SYSCFG_SWPR_PAGE5_Msk                  /*!< SRAM2 Write protection page 5 */
15325 #define SYSCFG_SWPR_PAGE6_Pos           (6U)
15326 #define SYSCFG_SWPR_PAGE6_Msk           (0x1U << SYSCFG_SWPR_PAGE6_Pos)        /*!< 0x00000040 */
15327 #define SYSCFG_SWPR_PAGE6               SYSCFG_SWPR_PAGE6_Msk                  /*!< SRAM2 Write protection page 6 */
15328 #define SYSCFG_SWPR_PAGE7_Pos           (7U)
15329 #define SYSCFG_SWPR_PAGE7_Msk           (0x1U << SYSCFG_SWPR_PAGE7_Pos)        /*!< 0x00000080 */
15330 #define SYSCFG_SWPR_PAGE7               SYSCFG_SWPR_PAGE7_Msk                  /*!< SRAM2 Write protection page 7 */
15331 #define SYSCFG_SWPR_PAGE8_Pos           (8U)
15332 #define SYSCFG_SWPR_PAGE8_Msk           (0x1U << SYSCFG_SWPR_PAGE8_Pos)        /*!< 0x00000100 */
15333 #define SYSCFG_SWPR_PAGE8               SYSCFG_SWPR_PAGE8_Msk                  /*!< SRAM2 Write protection page 8 */
15334 #define SYSCFG_SWPR_PAGE9_Pos           (9U)
15335 #define SYSCFG_SWPR_PAGE9_Msk           (0x1U << SYSCFG_SWPR_PAGE9_Pos)        /*!< 0x00000200 */
15336 #define SYSCFG_SWPR_PAGE9               SYSCFG_SWPR_PAGE9_Msk                  /*!< SRAM2 Write protection page 9 */
15337 #define SYSCFG_SWPR_PAGE10_Pos          (10U)
15338 #define SYSCFG_SWPR_PAGE10_Msk          (0x1U << SYSCFG_SWPR_PAGE10_Pos)       /*!< 0x00000400 */
15339 #define SYSCFG_SWPR_PAGE10              SYSCFG_SWPR_PAGE10_Msk                 /*!< SRAM2 Write protection page 10*/
15340 #define SYSCFG_SWPR_PAGE11_Pos          (11U)
15341 #define SYSCFG_SWPR_PAGE11_Msk          (0x1U << SYSCFG_SWPR_PAGE11_Pos)       /*!< 0x00000800 */
15342 #define SYSCFG_SWPR_PAGE11              SYSCFG_SWPR_PAGE11_Msk                 /*!< SRAM2 Write protection page 11*/
15343 #define SYSCFG_SWPR_PAGE12_Pos          (12U)
15344 #define SYSCFG_SWPR_PAGE12_Msk          (0x1U << SYSCFG_SWPR_PAGE12_Pos)       /*!< 0x00001000 */
15345 #define SYSCFG_SWPR_PAGE12              SYSCFG_SWPR_PAGE12_Msk                 /*!< SRAM2 Write protection page 12*/
15346 #define SYSCFG_SWPR_PAGE13_Pos          (13U)
15347 #define SYSCFG_SWPR_PAGE13_Msk          (0x1U << SYSCFG_SWPR_PAGE13_Pos)       /*!< 0x00002000 */
15348 #define SYSCFG_SWPR_PAGE13              SYSCFG_SWPR_PAGE13_Msk                 /*!< SRAM2 Write protection page 13*/
15349 #define SYSCFG_SWPR_PAGE14_Pos          (14U)
15350 #define SYSCFG_SWPR_PAGE14_Msk          (0x1U << SYSCFG_SWPR_PAGE14_Pos)       /*!< 0x00004000 */
15351 #define SYSCFG_SWPR_PAGE14              SYSCFG_SWPR_PAGE14_Msk                 /*!< SRAM2 Write protection page 14*/
15352 #define SYSCFG_SWPR_PAGE15_Pos          (15U)
15353 #define SYSCFG_SWPR_PAGE15_Msk          (0x1U << SYSCFG_SWPR_PAGE15_Pos)       /*!< 0x00008000 */
15354 #define SYSCFG_SWPR_PAGE15              SYSCFG_SWPR_PAGE15_Msk                 /*!< SRAM2 Write protection page 15*/
15355 #define SYSCFG_SWPR_PAGE16_Pos          (16U)
15356 #define SYSCFG_SWPR_PAGE16_Msk          (0x1U << SYSCFG_SWPR_PAGE16_Pos)       /*!< 0x00010000 */
15357 #define SYSCFG_SWPR_PAGE16              SYSCFG_SWPR_PAGE16_Msk                 /*!< SRAM2 Write protection page 16*/
15358 #define SYSCFG_SWPR_PAGE17_Pos          (17U)
15359 #define SYSCFG_SWPR_PAGE17_Msk          (0x1U << SYSCFG_SWPR_PAGE17_Pos)       /*!< 0x00020000 */
15360 #define SYSCFG_SWPR_PAGE17              SYSCFG_SWPR_PAGE17_Msk                 /*!< SRAM2 Write protection page 17*/
15361 #define SYSCFG_SWPR_PAGE18_Pos          (18U)
15362 #define SYSCFG_SWPR_PAGE18_Msk          (0x1U << SYSCFG_SWPR_PAGE18_Pos)       /*!< 0x00040000 */
15363 #define SYSCFG_SWPR_PAGE18              SYSCFG_SWPR_PAGE18_Msk                 /*!< SRAM2 Write protection page 18*/
15364 #define SYSCFG_SWPR_PAGE19_Pos          (19U)
15365 #define SYSCFG_SWPR_PAGE19_Msk          (0x1U << SYSCFG_SWPR_PAGE19_Pos)       /*!< 0x00080000 */
15366 #define SYSCFG_SWPR_PAGE19              SYSCFG_SWPR_PAGE19_Msk                 /*!< SRAM2 Write protection page 19*/
15367 #define SYSCFG_SWPR_PAGE20_Pos          (20U)
15368 #define SYSCFG_SWPR_PAGE20_Msk          (0x1U << SYSCFG_SWPR_PAGE20_Pos)       /*!< 0x00100000 */
15369 #define SYSCFG_SWPR_PAGE20              SYSCFG_SWPR_PAGE20_Msk                 /*!< SRAM2 Write protection page 20*/
15370 #define SYSCFG_SWPR_PAGE21_Pos          (21U)
15371 #define SYSCFG_SWPR_PAGE21_Msk          (0x1U << SYSCFG_SWPR_PAGE21_Pos)       /*!< 0x00200000 */
15372 #define SYSCFG_SWPR_PAGE21              SYSCFG_SWPR_PAGE21_Msk                 /*!< SRAM2 Write protection page 21*/
15373 #define SYSCFG_SWPR_PAGE22_Pos          (22U)
15374 #define SYSCFG_SWPR_PAGE22_Msk          (0x1U << SYSCFG_SWPR_PAGE22_Pos)       /*!< 0x00400000 */
15375 #define SYSCFG_SWPR_PAGE22              SYSCFG_SWPR_PAGE22_Msk                 /*!< SRAM2 Write protection page 22*/
15376 #define SYSCFG_SWPR_PAGE23_Pos          (23U)
15377 #define SYSCFG_SWPR_PAGE23_Msk          (0x1U << SYSCFG_SWPR_PAGE23_Pos)       /*!< 0x00800000 */
15378 #define SYSCFG_SWPR_PAGE23              SYSCFG_SWPR_PAGE23_Msk                 /*!< SRAM2 Write protection page 23*/
15379 #define SYSCFG_SWPR_PAGE24_Pos          (24U)
15380 #define SYSCFG_SWPR_PAGE24_Msk          (0x1U << SYSCFG_SWPR_PAGE24_Pos)       /*!< 0x01000000 */
15381 #define SYSCFG_SWPR_PAGE24              SYSCFG_SWPR_PAGE24_Msk                 /*!< SRAM2 Write protection page 24*/
15382 #define SYSCFG_SWPR_PAGE25_Pos          (25U)
15383 #define SYSCFG_SWPR_PAGE25_Msk          (0x1U << SYSCFG_SWPR_PAGE25_Pos)       /*!< 0x02000000 */
15384 #define SYSCFG_SWPR_PAGE25              SYSCFG_SWPR_PAGE25_Msk                 /*!< SRAM2 Write protection page 25*/
15385 #define SYSCFG_SWPR_PAGE26_Pos          (26U)
15386 #define SYSCFG_SWPR_PAGE26_Msk          (0x1U << SYSCFG_SWPR_PAGE26_Pos)       /*!< 0x04000000 */
15387 #define SYSCFG_SWPR_PAGE26              SYSCFG_SWPR_PAGE26_Msk                 /*!< SRAM2 Write protection page 26*/
15388 #define SYSCFG_SWPR_PAGE27_Pos          (27U)
15389 #define SYSCFG_SWPR_PAGE27_Msk          (0x1U << SYSCFG_SWPR_PAGE27_Pos)       /*!< 0x08000000 */
15390 #define SYSCFG_SWPR_PAGE27              SYSCFG_SWPR_PAGE27_Msk                 /*!< SRAM2 Write protection page 27*/
15391 #define SYSCFG_SWPR_PAGE28_Pos          (28U)
15392 #define SYSCFG_SWPR_PAGE28_Msk          (0x1U << SYSCFG_SWPR_PAGE28_Pos)       /*!< 0x10000000 */
15393 #define SYSCFG_SWPR_PAGE28              SYSCFG_SWPR_PAGE28_Msk                 /*!< SRAM2 Write protection page 28*/
15394 #define SYSCFG_SWPR_PAGE29_Pos          (29U)
15395 #define SYSCFG_SWPR_PAGE29_Msk          (0x1U << SYSCFG_SWPR_PAGE29_Pos)       /*!< 0x20000000 */
15396 #define SYSCFG_SWPR_PAGE29              SYSCFG_SWPR_PAGE29_Msk                 /*!< SRAM2 Write protection page 29*/
15397 #define SYSCFG_SWPR_PAGE30_Pos          (30U)
15398 #define SYSCFG_SWPR_PAGE30_Msk          (0x1U << SYSCFG_SWPR_PAGE30_Pos)       /*!< 0x40000000 */
15399 #define SYSCFG_SWPR_PAGE30              SYSCFG_SWPR_PAGE30_Msk                 /*!< SRAM2 Write protection page 30*/
15400 #define SYSCFG_SWPR_PAGE31_Pos          (31U)
15401 #define SYSCFG_SWPR_PAGE31_Msk          (0x1U << SYSCFG_SWPR_PAGE31_Pos)       /*!< 0x80000000 */
15402 #define SYSCFG_SWPR_PAGE31              SYSCFG_SWPR_PAGE31_Msk                 /*!< SRAM2 Write protection page 31*/
15403 
15404 /******************  Bit definition for SYSCFG_SWPR2 register  ***************/
15405 #define SYSCFG_SWPR2_PAGE32_Pos         (0U)
15406 #define SYSCFG_SWPR2_PAGE32_Msk         (0x1U << SYSCFG_SWPR2_PAGE32_Pos)      /*!< 0x00000001 */
15407 #define SYSCFG_SWPR2_PAGE32             SYSCFG_SWPR2_PAGE32_Msk                /*!< SRAM2 Write protection page 32*/
15408 #define SYSCFG_SWPR2_PAGE33_Pos         (1U)
15409 #define SYSCFG_SWPR2_PAGE33_Msk         (0x1U << SYSCFG_SWPR2_PAGE33_Pos)      /*!< 0x00000002 */
15410 #define SYSCFG_SWPR2_PAGE33             SYSCFG_SWPR2_PAGE33_Msk                /*!< SRAM2 Write protection page 33*/
15411 #define SYSCFG_SWPR2_PAGE34_Pos         (2U)
15412 #define SYSCFG_SWPR2_PAGE34_Msk         (0x1U << SYSCFG_SWPR2_PAGE34_Pos)      /*!< 0x00000004 */
15413 #define SYSCFG_SWPR2_PAGE34             SYSCFG_SWPR2_PAGE34_Msk                /*!< SRAM2 Write protection page 34*/
15414 #define SYSCFG_SWPR2_PAGE35_Pos         (3U)
15415 #define SYSCFG_SWPR2_PAGE35_Msk         (0x1U << SYSCFG_SWPR2_PAGE35_Pos)      /*!< 0x00000008 */
15416 #define SYSCFG_SWPR2_PAGE35             SYSCFG_SWPR2_PAGE35_Msk                /*!< SRAM2 Write protection page 35*/
15417 #define SYSCFG_SWPR2_PAGE36_Pos         (4U)
15418 #define SYSCFG_SWPR2_PAGE36_Msk         (0x1U << SYSCFG_SWPR2_PAGE36_Pos)      /*!< 0x00000010 */
15419 #define SYSCFG_SWPR2_PAGE36             SYSCFG_SWPR2_PAGE36_Msk                /*!< SRAM2 Write protection page 36*/
15420 #define SYSCFG_SWPR2_PAGE37_Pos         (5U)
15421 #define SYSCFG_SWPR2_PAGE37_Msk         (0x1U << SYSCFG_SWPR2_PAGE37_Pos)      /*!< 0x00000020 */
15422 #define SYSCFG_SWPR2_PAGE37             SYSCFG_SWPR2_PAGE37_Msk                /*!< SRAM2 Write protection page 37*/
15423 #define SYSCFG_SWPR2_PAGE38_Pos         (6U)
15424 #define SYSCFG_SWPR2_PAGE38_Msk         (0x1U << SYSCFG_SWPR2_PAGE38_Pos)      /*!< 0x00000040 */
15425 #define SYSCFG_SWPR2_PAGE38             SYSCFG_SWPR2_PAGE38_Msk                /*!< SRAM2 Write protection page 38*/
15426 #define SYSCFG_SWPR2_PAGE39_Pos         (7U)
15427 #define SYSCFG_SWPR2_PAGE39_Msk         (0x1U << SYSCFG_SWPR2_PAGE39_Pos)      /*!< 0x00000080 */
15428 #define SYSCFG_SWPR2_PAGE39             SYSCFG_SWPR2_PAGE39_Msk                /*!< SRAM2 Write protection page 39*/
15429 #define SYSCFG_SWPR2_PAGE40_Pos         (8U)
15430 #define SYSCFG_SWPR2_PAGE40_Msk         (0x1U << SYSCFG_SWPR2_PAGE40_Pos)      /*!< 0x00000100 */
15431 #define SYSCFG_SWPR2_PAGE40             SYSCFG_SWPR2_PAGE40_Msk                /*!< SRAM2 Write protection page 40*/
15432 #define SYSCFG_SWPR2_PAGE41_Pos         (9U)
15433 #define SYSCFG_SWPR2_PAGE41_Msk         (0x1U << SYSCFG_SWPR2_PAGE41_Pos)      /*!< 0x00000200 */
15434 #define SYSCFG_SWPR2_PAGE41             SYSCFG_SWPR2_PAGE41_Msk                /*!< SRAM2 Write protection page 41*/
15435 #define SYSCFG_SWPR2_PAGE42_Pos         (10U)
15436 #define SYSCFG_SWPR2_PAGE42_Msk         (0x1U << SYSCFG_SWPR2_PAGE42_Pos)      /*!< 0x00000400 */
15437 #define SYSCFG_SWPR2_PAGE42             SYSCFG_SWPR2_PAGE42_Msk                /*!< SRAM2 Write protection page 42*/
15438 #define SYSCFG_SWPR2_PAGE43_Pos         (11U)
15439 #define SYSCFG_SWPR2_PAGE43_Msk         (0x1U << SYSCFG_SWPR2_PAGE43_Pos)      /*!< 0x00000800 */
15440 #define SYSCFG_SWPR2_PAGE43             SYSCFG_SWPR2_PAGE43_Msk                /*!< SRAM2 Write protection page 43*/
15441 #define SYSCFG_SWPR2_PAGE44_Pos         (12U)
15442 #define SYSCFG_SWPR2_PAGE44_Msk         (0x1U << SYSCFG_SWPR2_PAGE44_Pos)      /*!< 0x00001000 */
15443 #define SYSCFG_SWPR2_PAGE44             SYSCFG_SWPR2_PAGE44_Msk                /*!< SRAM2 Write protection page 44*/
15444 #define SYSCFG_SWPR2_PAGE45_Pos         (13U)
15445 #define SYSCFG_SWPR2_PAGE45_Msk         (0x1U << SYSCFG_SWPR2_PAGE45_Pos)      /*!< 0x00002000 */
15446 #define SYSCFG_SWPR2_PAGE45             SYSCFG_SWPR2_PAGE45_Msk                /*!< SRAM2 Write protection page 45*/
15447 #define SYSCFG_SWPR2_PAGE46_Pos         (14U)
15448 #define SYSCFG_SWPR2_PAGE46_Msk         (0x1U << SYSCFG_SWPR2_PAGE46_Pos)      /*!< 0x00004000 */
15449 #define SYSCFG_SWPR2_PAGE46             SYSCFG_SWPR2_PAGE46_Msk                /*!< SRAM2 Write protection page 46*/
15450 #define SYSCFG_SWPR2_PAGE47_Pos         (15U)
15451 #define SYSCFG_SWPR2_PAGE47_Msk         (0x1U << SYSCFG_SWPR2_PAGE47_Pos)      /*!< 0x00008000 */
15452 #define SYSCFG_SWPR2_PAGE47             SYSCFG_SWPR2_PAGE47_Msk                /*!< SRAM2 Write protection page 47*/
15453 #define SYSCFG_SWPR2_PAGE48_Pos         (16U)
15454 #define SYSCFG_SWPR2_PAGE48_Msk         (0x1U << SYSCFG_SWPR2_PAGE48_Pos)      /*!< 0x00010000 */
15455 #define SYSCFG_SWPR2_PAGE48             SYSCFG_SWPR2_PAGE48_Msk                /*!< SRAM2 Write protection page 48*/
15456 #define SYSCFG_SWPR2_PAGE49_Pos         (17U)
15457 #define SYSCFG_SWPR2_PAGE49_Msk         (0x1U << SYSCFG_SWPR2_PAGE49_Pos)      /*!< 0x00020000 */
15458 #define SYSCFG_SWPR2_PAGE49             SYSCFG_SWPR2_PAGE49_Msk                /*!< SRAM2 Write protection page 49*/
15459 #define SYSCFG_SWPR2_PAGE50_Pos         (18U)
15460 #define SYSCFG_SWPR2_PAGE50_Msk         (0x1U << SYSCFG_SWPR2_PAGE50_Pos)      /*!< 0x00040000 */
15461 #define SYSCFG_SWPR2_PAGE50             SYSCFG_SWPR2_PAGE50_Msk                /*!< SRAM2 Write protection page 50*/
15462 #define SYSCFG_SWPR2_PAGE51_Pos         (19U)
15463 #define SYSCFG_SWPR2_PAGE51_Msk         (0x1U << SYSCFG_SWPR2_PAGE51_Pos)      /*!< 0x00080000 */
15464 #define SYSCFG_SWPR2_PAGE51             SYSCFG_SWPR2_PAGE51_Msk                /*!< SRAM2 Write protection page 51*/
15465 #define SYSCFG_SWPR2_PAGE52_Pos         (20U)
15466 #define SYSCFG_SWPR2_PAGE52_Msk         (0x1U << SYSCFG_SWPR2_PAGE52_Pos)      /*!< 0x00100000 */
15467 #define SYSCFG_SWPR2_PAGE52             SYSCFG_SWPR2_PAGE52_Msk                /*!< SRAM2 Write protection page 52*/
15468 #define SYSCFG_SWPR2_PAGE53_Pos         (21U)
15469 #define SYSCFG_SWPR2_PAGE53_Msk         (0x1U << SYSCFG_SWPR2_PAGE53_Pos)      /*!< 0x00200000 */
15470 #define SYSCFG_SWPR2_PAGE53             SYSCFG_SWPR2_PAGE53_Msk                /*!< SRAM2 Write protection page 53*/
15471 #define SYSCFG_SWPR2_PAGE54_Pos         (22U)
15472 #define SYSCFG_SWPR2_PAGE54_Msk         (0x1U << SYSCFG_SWPR2_PAGE54_Pos)      /*!< 0x00400000 */
15473 #define SYSCFG_SWPR2_PAGE54             SYSCFG_SWPR2_PAGE54_Msk                /*!< SRAM2 Write protection page 54*/
15474 #define SYSCFG_SWPR2_PAGE55_Pos         (23U)
15475 #define SYSCFG_SWPR2_PAGE55_Msk         (0x1U << SYSCFG_SWPR2_PAGE55_Pos)      /*!< 0x00800000 */
15476 #define SYSCFG_SWPR2_PAGE55             SYSCFG_SWPR2_PAGE55_Msk                /*!< SRAM2 Write protection page 55*/
15477 #define SYSCFG_SWPR2_PAGE56_Pos         (24U)
15478 #define SYSCFG_SWPR2_PAGE56_Msk         (0x1U << SYSCFG_SWPR2_PAGE56_Pos)      /*!< 0x01000000 */
15479 #define SYSCFG_SWPR2_PAGE56             SYSCFG_SWPR2_PAGE56_Msk                /*!< SRAM2 Write protection page 56*/
15480 #define SYSCFG_SWPR2_PAGE57_Pos         (25U)
15481 #define SYSCFG_SWPR2_PAGE57_Msk         (0x1U << SYSCFG_SWPR2_PAGE57_Pos)      /*!< 0x02000000 */
15482 #define SYSCFG_SWPR2_PAGE57             SYSCFG_SWPR2_PAGE57_Msk                /*!< SRAM2 Write protection page 57*/
15483 #define SYSCFG_SWPR2_PAGE58_Pos         (26U)
15484 #define SYSCFG_SWPR2_PAGE58_Msk         (0x1U << SYSCFG_SWPR2_PAGE58_Pos)      /*!< 0x04000000 */
15485 #define SYSCFG_SWPR2_PAGE58             SYSCFG_SWPR2_PAGE58_Msk                /*!< SRAM2 Write protection page 58*/
15486 #define SYSCFG_SWPR2_PAGE59_Pos         (27U)
15487 #define SYSCFG_SWPR2_PAGE59_Msk         (0x1U << SYSCFG_SWPR2_PAGE59_Pos)      /*!< 0x08000000 */
15488 #define SYSCFG_SWPR2_PAGE59             SYSCFG_SWPR2_PAGE59_Msk                /*!< SRAM2 Write protection page 59*/
15489 #define SYSCFG_SWPR2_PAGE60_Pos         (28U)
15490 #define SYSCFG_SWPR2_PAGE60_Msk         (0x1U << SYSCFG_SWPR2_PAGE60_Pos)      /*!< 0x10000000 */
15491 #define SYSCFG_SWPR2_PAGE60             SYSCFG_SWPR2_PAGE60_Msk                /*!< SRAM2 Write protection page 60*/
15492 #define SYSCFG_SWPR2_PAGE61_Pos         (29U)
15493 #define SYSCFG_SWPR2_PAGE61_Msk         (0x1U << SYSCFG_SWPR2_PAGE61_Pos)      /*!< 0x20000000 */
15494 #define SYSCFG_SWPR2_PAGE61             SYSCFG_SWPR2_PAGE61_Msk                /*!< SRAM2 Write protection page 61*/
15495 #define SYSCFG_SWPR2_PAGE62_Pos         (30U)
15496 #define SYSCFG_SWPR2_PAGE62_Msk         (0x1U << SYSCFG_SWPR2_PAGE62_Pos)      /*!< 0x40000000 */
15497 #define SYSCFG_SWPR2_PAGE62             SYSCFG_SWPR2_PAGE62_Msk                /*!< SRAM2 Write protection page 62*/
15498 #define SYSCFG_SWPR2_PAGE63_Pos         (31U)
15499 #define SYSCFG_SWPR2_PAGE63_Msk         (0x1U << SYSCFG_SWPR2_PAGE63_Pos)      /*!< 0x80000000 */
15500 #define SYSCFG_SWPR2_PAGE63             SYSCFG_SWPR2_PAGE63_Msk                /*!< SRAM2 Write protection page 63*/
15501 
15502 /******************  Bit definition for SYSCFG_SKR register  ****************/
15503 #define SYSCFG_SKR_KEY_Pos              (0U)
15504 #define SYSCFG_SKR_KEY_Msk              (0xFFU << SYSCFG_SKR_KEY_Pos)          /*!< 0x000000FF */
15505 #define SYSCFG_SKR_KEY                  SYSCFG_SKR_KEY_Msk                     /*!<  SRAM2 write protection key for software erase  */
15506 
15507 
15508 
15509 
15510 /******************************************************************************/
15511 /*                                                                            */
15512 /*                                    TIM                                     */
15513 /*                                                                            */
15514 /******************************************************************************/
15515 /*******************  Bit definition for TIM_CR1 register  ********************/
15516 #define TIM_CR1_CEN_Pos           (0U)
15517 #define TIM_CR1_CEN_Msk           (0x1U << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
15518 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
15519 #define TIM_CR1_UDIS_Pos          (1U)
15520 #define TIM_CR1_UDIS_Msk          (0x1U << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
15521 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
15522 #define TIM_CR1_URS_Pos           (2U)
15523 #define TIM_CR1_URS_Msk           (0x1U << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
15524 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
15525 #define TIM_CR1_OPM_Pos           (3U)
15526 #define TIM_CR1_OPM_Msk           (0x1U << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
15527 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
15528 #define TIM_CR1_DIR_Pos           (4U)
15529 #define TIM_CR1_DIR_Msk           (0x1U << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
15530 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
15531 
15532 #define TIM_CR1_CMS_Pos           (5U)
15533 #define TIM_CR1_CMS_Msk           (0x3U << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
15534 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
15535 #define TIM_CR1_CMS_0             (0x1U << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
15536 #define TIM_CR1_CMS_1             (0x2U << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
15537 
15538 #define TIM_CR1_ARPE_Pos          (7U)
15539 #define TIM_CR1_ARPE_Msk          (0x1U << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
15540 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
15541 
15542 #define TIM_CR1_CKD_Pos           (8U)
15543 #define TIM_CR1_CKD_Msk           (0x3U << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
15544 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
15545 #define TIM_CR1_CKD_0             (0x1U << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
15546 #define TIM_CR1_CKD_1             (0x2U << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
15547 
15548 #define TIM_CR1_UIFREMAP_Pos      (11U)
15549 #define TIM_CR1_UIFREMAP_Msk      (0x1U << TIM_CR1_UIFREMAP_Pos)               /*!< 0x00000800 */
15550 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
15551 
15552 /*******************  Bit definition for TIM_CR2 register  ********************/
15553 #define TIM_CR2_CCPC_Pos          (0U)
15554 #define TIM_CR2_CCPC_Msk          (0x1U << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
15555 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
15556 #define TIM_CR2_CCUS_Pos          (2U)
15557 #define TIM_CR2_CCUS_Msk          (0x1U << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
15558 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
15559 #define TIM_CR2_CCDS_Pos          (3U)
15560 #define TIM_CR2_CCDS_Msk          (0x1U << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
15561 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
15562 
15563 #define TIM_CR2_MMS_Pos           (4U)
15564 #define TIM_CR2_MMS_Msk           (0x7U << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
15565 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
15566 #define TIM_CR2_MMS_0             (0x1U << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
15567 #define TIM_CR2_MMS_1             (0x2U << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
15568 #define TIM_CR2_MMS_2             (0x4U << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
15569 
15570 #define TIM_CR2_TI1S_Pos          (7U)
15571 #define TIM_CR2_TI1S_Msk          (0x1U << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
15572 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
15573 #define TIM_CR2_OIS1_Pos          (8U)
15574 #define TIM_CR2_OIS1_Msk          (0x1U << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
15575 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
15576 #define TIM_CR2_OIS1N_Pos         (9U)
15577 #define TIM_CR2_OIS1N_Msk         (0x1U << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
15578 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
15579 #define TIM_CR2_OIS2_Pos          (10U)
15580 #define TIM_CR2_OIS2_Msk          (0x1U << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
15581 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
15582 #define TIM_CR2_OIS2N_Pos         (11U)
15583 #define TIM_CR2_OIS2N_Msk         (0x1U << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
15584 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
15585 #define TIM_CR2_OIS3_Pos          (12U)
15586 #define TIM_CR2_OIS3_Msk          (0x1U << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
15587 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
15588 #define TIM_CR2_OIS3N_Pos         (13U)
15589 #define TIM_CR2_OIS3N_Msk         (0x1U << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
15590 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
15591 #define TIM_CR2_OIS4_Pos          (14U)
15592 #define TIM_CR2_OIS4_Msk          (0x1U << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
15593 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
15594 #define TIM_CR2_OIS5_Pos          (16U)
15595 #define TIM_CR2_OIS5_Msk          (0x1U << TIM_CR2_OIS5_Pos)                   /*!< 0x00010000 */
15596 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
15597 #define TIM_CR2_OIS6_Pos          (18U)
15598 #define TIM_CR2_OIS6_Msk          (0x1U << TIM_CR2_OIS6_Pos)                   /*!< 0x00040000 */
15599 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
15600 
15601 #define TIM_CR2_MMS2_Pos          (20U)
15602 #define TIM_CR2_MMS2_Msk          (0xFU << TIM_CR2_MMS2_Pos)                   /*!< 0x00F00000 */
15603 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
15604 #define TIM_CR2_MMS2_0            (0x1U << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
15605 #define TIM_CR2_MMS2_1            (0x2U << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
15606 #define TIM_CR2_MMS2_2            (0x4U << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
15607 #define TIM_CR2_MMS2_3            (0x8U << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
15608 
15609 /*******************  Bit definition for TIM_SMCR register  *******************/
15610 #define TIM_SMCR_SMS_Pos          (0U)
15611 #define TIM_SMCR_SMS_Msk          (0x10007U << TIM_SMCR_SMS_Pos)               /*!< 0x00010007 */
15612 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
15613 #define TIM_SMCR_SMS_0            (0x00001U << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
15614 #define TIM_SMCR_SMS_1            (0x00002U << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
15615 #define TIM_SMCR_SMS_2            (0x00004U << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
15616 #define TIM_SMCR_SMS_3            (0x10000U << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
15617 
15618 #define TIM_SMCR_OCCS_Pos         (3U)
15619 #define TIM_SMCR_OCCS_Msk         (0x1U << TIM_SMCR_OCCS_Pos)                  /*!< 0x00000008 */
15620 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
15621 
15622 #define TIM_SMCR_TS_Pos           (4U)
15623 #define TIM_SMCR_TS_Msk           (0x7U << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
15624 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
15625 #define TIM_SMCR_TS_0             (0x1U << TIM_SMCR_TS_Pos)                    /*!< 0x00000010 */
15626 #define TIM_SMCR_TS_1             (0x2U << TIM_SMCR_TS_Pos)                    /*!< 0x00000020 */
15627 #define TIM_SMCR_TS_2             (0x4U << TIM_SMCR_TS_Pos)                    /*!< 0x00000040 */
15628 
15629 #define TIM_SMCR_MSM_Pos          (7U)
15630 #define TIM_SMCR_MSM_Msk          (0x1U << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
15631 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
15632 
15633 #define TIM_SMCR_ETF_Pos          (8U)
15634 #define TIM_SMCR_ETF_Msk          (0xFU << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
15635 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
15636 #define TIM_SMCR_ETF_0            (0x1U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
15637 #define TIM_SMCR_ETF_1            (0x2U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
15638 #define TIM_SMCR_ETF_2            (0x4U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
15639 #define TIM_SMCR_ETF_3            (0x8U << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
15640 
15641 #define TIM_SMCR_ETPS_Pos         (12U)
15642 #define TIM_SMCR_ETPS_Msk         (0x3U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
15643 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
15644 #define TIM_SMCR_ETPS_0           (0x1U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
15645 #define TIM_SMCR_ETPS_1           (0x2U << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
15646 
15647 #define TIM_SMCR_ECE_Pos          (14U)
15648 #define TIM_SMCR_ECE_Msk          (0x1U << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
15649 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
15650 #define TIM_SMCR_ETP_Pos          (15U)
15651 #define TIM_SMCR_ETP_Msk          (0x1U << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
15652 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
15653 
15654 /*******************  Bit definition for TIM_DIER register  *******************/
15655 #define TIM_DIER_UIE_Pos          (0U)
15656 #define TIM_DIER_UIE_Msk          (0x1U << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
15657 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
15658 #define TIM_DIER_CC1IE_Pos        (1U)
15659 #define TIM_DIER_CC1IE_Msk        (0x1U << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
15660 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
15661 #define TIM_DIER_CC2IE_Pos        (2U)
15662 #define TIM_DIER_CC2IE_Msk        (0x1U << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
15663 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
15664 #define TIM_DIER_CC3IE_Pos        (3U)
15665 #define TIM_DIER_CC3IE_Msk        (0x1U << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
15666 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
15667 #define TIM_DIER_CC4IE_Pos        (4U)
15668 #define TIM_DIER_CC4IE_Msk        (0x1U << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
15669 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
15670 #define TIM_DIER_COMIE_Pos        (5U)
15671 #define TIM_DIER_COMIE_Msk        (0x1U << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
15672 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
15673 #define TIM_DIER_TIE_Pos          (6U)
15674 #define TIM_DIER_TIE_Msk          (0x1U << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
15675 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
15676 #define TIM_DIER_BIE_Pos          (7U)
15677 #define TIM_DIER_BIE_Msk          (0x1U << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
15678 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
15679 #define TIM_DIER_UDE_Pos          (8U)
15680 #define TIM_DIER_UDE_Msk          (0x1U << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
15681 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
15682 #define TIM_DIER_CC1DE_Pos        (9U)
15683 #define TIM_DIER_CC1DE_Msk        (0x1U << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
15684 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
15685 #define TIM_DIER_CC2DE_Pos        (10U)
15686 #define TIM_DIER_CC2DE_Msk        (0x1U << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
15687 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
15688 #define TIM_DIER_CC3DE_Pos        (11U)
15689 #define TIM_DIER_CC3DE_Msk        (0x1U << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
15690 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
15691 #define TIM_DIER_CC4DE_Pos        (12U)
15692 #define TIM_DIER_CC4DE_Msk        (0x1U << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
15693 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
15694 #define TIM_DIER_COMDE_Pos        (13U)
15695 #define TIM_DIER_COMDE_Msk        (0x1U << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
15696 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
15697 #define TIM_DIER_TDE_Pos          (14U)
15698 #define TIM_DIER_TDE_Msk          (0x1U << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
15699 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
15700 
15701 /********************  Bit definition for TIM_SR register  ********************/
15702 #define TIM_SR_UIF_Pos            (0U)
15703 #define TIM_SR_UIF_Msk            (0x1U << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
15704 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
15705 #define TIM_SR_CC1IF_Pos          (1U)
15706 #define TIM_SR_CC1IF_Msk          (0x1U << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
15707 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
15708 #define TIM_SR_CC2IF_Pos          (2U)
15709 #define TIM_SR_CC2IF_Msk          (0x1U << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
15710 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
15711 #define TIM_SR_CC3IF_Pos          (3U)
15712 #define TIM_SR_CC3IF_Msk          (0x1U << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
15713 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
15714 #define TIM_SR_CC4IF_Pos          (4U)
15715 #define TIM_SR_CC4IF_Msk          (0x1U << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
15716 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
15717 #define TIM_SR_COMIF_Pos          (5U)
15718 #define TIM_SR_COMIF_Msk          (0x1U << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
15719 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
15720 #define TIM_SR_TIF_Pos            (6U)
15721 #define TIM_SR_TIF_Msk            (0x1U << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
15722 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
15723 #define TIM_SR_BIF_Pos            (7U)
15724 #define TIM_SR_BIF_Msk            (0x1U << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
15725 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
15726 #define TIM_SR_B2IF_Pos           (8U)
15727 #define TIM_SR_B2IF_Msk           (0x1U << TIM_SR_B2IF_Pos)                    /*!< 0x00000100 */
15728 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
15729 #define TIM_SR_CC1OF_Pos          (9U)
15730 #define TIM_SR_CC1OF_Msk          (0x1U << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
15731 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
15732 #define TIM_SR_CC2OF_Pos          (10U)
15733 #define TIM_SR_CC2OF_Msk          (0x1U << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
15734 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
15735 #define TIM_SR_CC3OF_Pos          (11U)
15736 #define TIM_SR_CC3OF_Msk          (0x1U << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
15737 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
15738 #define TIM_SR_CC4OF_Pos          (12U)
15739 #define TIM_SR_CC4OF_Msk          (0x1U << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
15740 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
15741 #define TIM_SR_SBIF_Pos           (13U)
15742 #define TIM_SR_SBIF_Msk           (0x1U << TIM_SR_SBIF_Pos)                    /*!< 0x00002000 */
15743 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
15744 #define TIM_SR_CC5IF_Pos          (16U)
15745 #define TIM_SR_CC5IF_Msk          (0x1U << TIM_SR_CC5IF_Pos)                   /*!< 0x00010000 */
15746 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
15747 #define TIM_SR_CC6IF_Pos          (17U)
15748 #define TIM_SR_CC6IF_Msk          (0x1U << TIM_SR_CC6IF_Pos)                   /*!< 0x00020000 */
15749 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
15750 
15751 
15752 /*******************  Bit definition for TIM_EGR register  ********************/
15753 #define TIM_EGR_UG_Pos            (0U)
15754 #define TIM_EGR_UG_Msk            (0x1U << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
15755 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
15756 #define TIM_EGR_CC1G_Pos          (1U)
15757 #define TIM_EGR_CC1G_Msk          (0x1U << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
15758 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
15759 #define TIM_EGR_CC2G_Pos          (2U)
15760 #define TIM_EGR_CC2G_Msk          (0x1U << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
15761 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
15762 #define TIM_EGR_CC3G_Pos          (3U)
15763 #define TIM_EGR_CC3G_Msk          (0x1U << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
15764 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
15765 #define TIM_EGR_CC4G_Pos          (4U)
15766 #define TIM_EGR_CC4G_Msk          (0x1U << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
15767 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
15768 #define TIM_EGR_COMG_Pos          (5U)
15769 #define TIM_EGR_COMG_Msk          (0x1U << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
15770 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
15771 #define TIM_EGR_TG_Pos            (6U)
15772 #define TIM_EGR_TG_Msk            (0x1U << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
15773 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
15774 #define TIM_EGR_BG_Pos            (7U)
15775 #define TIM_EGR_BG_Msk            (0x1U << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
15776 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
15777 #define TIM_EGR_B2G_Pos           (8U)
15778 #define TIM_EGR_B2G_Msk           (0x1U << TIM_EGR_B2G_Pos)                    /*!< 0x00000100 */
15779 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
15780 
15781 
15782 /******************  Bit definition for TIM_CCMR1 register  *******************/
15783 #define TIM_CCMR1_CC1S_Pos        (0U)
15784 #define TIM_CCMR1_CC1S_Msk        (0x3U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
15785 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
15786 #define TIM_CCMR1_CC1S_0          (0x1U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
15787 #define TIM_CCMR1_CC1S_1          (0x2U << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
15788 
15789 #define TIM_CCMR1_OC1FE_Pos       (2U)
15790 #define TIM_CCMR1_OC1FE_Msk       (0x1U << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
15791 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
15792 #define TIM_CCMR1_OC1PE_Pos       (3U)
15793 #define TIM_CCMR1_OC1PE_Msk       (0x1U << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
15794 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
15795 
15796 #define TIM_CCMR1_OC1M_Pos        (4U)
15797 #define TIM_CCMR1_OC1M_Msk        (0x1007U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010070 */
15798 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
15799 #define TIM_CCMR1_OC1M_0          (0x0001U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
15800 #define TIM_CCMR1_OC1M_1          (0x0002U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
15801 #define TIM_CCMR1_OC1M_2          (0x0004U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
15802 #define TIM_CCMR1_OC1M_3          (0x1000U << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
15803 
15804 #define TIM_CCMR1_OC1CE_Pos       (7U)
15805 #define TIM_CCMR1_OC1CE_Msk       (0x1U << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
15806 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
15807 
15808 #define TIM_CCMR1_CC2S_Pos        (8U)
15809 #define TIM_CCMR1_CC2S_Msk        (0x3U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
15810 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
15811 #define TIM_CCMR1_CC2S_0          (0x1U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
15812 #define TIM_CCMR1_CC2S_1          (0x2U << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
15813 
15814 #define TIM_CCMR1_OC2FE_Pos       (10U)
15815 #define TIM_CCMR1_OC2FE_Msk       (0x1U << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
15816 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
15817 #define TIM_CCMR1_OC2PE_Pos       (11U)
15818 #define TIM_CCMR1_OC2PE_Msk       (0x1U << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
15819 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
15820 
15821 #define TIM_CCMR1_OC2M_Pos        (12U)
15822 #define TIM_CCMR1_OC2M_Msk        (0x1007U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01007000 */
15823 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
15824 #define TIM_CCMR1_OC2M_0          (0x0001U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
15825 #define TIM_CCMR1_OC2M_1          (0x0002U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
15826 #define TIM_CCMR1_OC2M_2          (0x0004U << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
15827 #define TIM_CCMR1_OC2M_3          (0x1000U << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
15828 
15829 #define TIM_CCMR1_OC2CE_Pos       (15U)
15830 #define TIM_CCMR1_OC2CE_Msk       (0x1U << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
15831 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
15832 
15833 /*----------------------------------------------------------------------------*/
15834 #define TIM_CCMR1_IC1PSC_Pos      (2U)
15835 #define TIM_CCMR1_IC1PSC_Msk      (0x3U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
15836 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
15837 #define TIM_CCMR1_IC1PSC_0        (0x1U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
15838 #define TIM_CCMR1_IC1PSC_1        (0x2U << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
15839 
15840 #define TIM_CCMR1_IC1F_Pos        (4U)
15841 #define TIM_CCMR1_IC1F_Msk        (0xFU << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
15842 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
15843 #define TIM_CCMR1_IC1F_0          (0x1U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
15844 #define TIM_CCMR1_IC1F_1          (0x2U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
15845 #define TIM_CCMR1_IC1F_2          (0x4U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
15846 #define TIM_CCMR1_IC1F_3          (0x8U << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
15847 
15848 #define TIM_CCMR1_IC2PSC_Pos      (10U)
15849 #define TIM_CCMR1_IC2PSC_Msk      (0x3U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
15850 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
15851 #define TIM_CCMR1_IC2PSC_0        (0x1U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
15852 #define TIM_CCMR1_IC2PSC_1        (0x2U << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
15853 
15854 #define TIM_CCMR1_IC2F_Pos        (12U)
15855 #define TIM_CCMR1_IC2F_Msk        (0xFU << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
15856 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
15857 #define TIM_CCMR1_IC2F_0          (0x1U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
15858 #define TIM_CCMR1_IC2F_1          (0x2U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
15859 #define TIM_CCMR1_IC2F_2          (0x4U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
15860 #define TIM_CCMR1_IC2F_3          (0x8U << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
15861 
15862 /******************  Bit definition for TIM_CCMR2 register  *******************/
15863 #define TIM_CCMR2_CC3S_Pos        (0U)
15864 #define TIM_CCMR2_CC3S_Msk        (0x3U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
15865 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
15866 #define TIM_CCMR2_CC3S_0          (0x1U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
15867 #define TIM_CCMR2_CC3S_1          (0x2U << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
15868 
15869 #define TIM_CCMR2_OC3FE_Pos       (2U)
15870 #define TIM_CCMR2_OC3FE_Msk       (0x1U << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
15871 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
15872 #define TIM_CCMR2_OC3PE_Pos       (3U)
15873 #define TIM_CCMR2_OC3PE_Msk       (0x1U << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
15874 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
15875 
15876 #define TIM_CCMR2_OC3M_Pos        (4U)
15877 #define TIM_CCMR2_OC3M_Msk        (0x1007U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010070 */
15878 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
15879 #define TIM_CCMR2_OC3M_0          (0x0001U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000010 */
15880 #define TIM_CCMR2_OC3M_1          (0x0002U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000020 */
15881 #define TIM_CCMR2_OC3M_2          (0x0004U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00000040 */
15882 #define TIM_CCMR2_OC3M_3          (0x1000U << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
15883 
15884 #define TIM_CCMR2_OC3CE_Pos       (7U)
15885 #define TIM_CCMR2_OC3CE_Msk       (0x1U << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
15886 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
15887 
15888 #define TIM_CCMR2_CC4S_Pos        (8U)
15889 #define TIM_CCMR2_CC4S_Msk        (0x3U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
15890 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
15891 #define TIM_CCMR2_CC4S_0          (0x1U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
15892 #define TIM_CCMR2_CC4S_1          (0x2U << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
15893 
15894 #define TIM_CCMR2_OC4FE_Pos       (10U)
15895 #define TIM_CCMR2_OC4FE_Msk       (0x1U << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
15896 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
15897 #define TIM_CCMR2_OC4PE_Pos       (11U)
15898 #define TIM_CCMR2_OC4PE_Msk       (0x1U << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
15899 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
15900 
15901 #define TIM_CCMR2_OC4M_Pos        (12U)
15902 #define TIM_CCMR2_OC4M_Msk        (0x1007U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01007000 */
15903 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
15904 #define TIM_CCMR2_OC4M_0          (0x0001U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00001000 */
15905 #define TIM_CCMR2_OC4M_1          (0x0002U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00002000 */
15906 #define TIM_CCMR2_OC4M_2          (0x0004U << TIM_CCMR2_OC4M_Pos)              /*!< 0x00004000 */
15907 #define TIM_CCMR2_OC4M_3          (0x1000U << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
15908 
15909 #define TIM_CCMR2_OC4CE_Pos       (15U)
15910 #define TIM_CCMR2_OC4CE_Msk       (0x1U << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
15911 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
15912 
15913 /*----------------------------------------------------------------------------*/
15914 #define TIM_CCMR2_IC3PSC_Pos      (2U)
15915 #define TIM_CCMR2_IC3PSC_Msk      (0x3U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
15916 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
15917 #define TIM_CCMR2_IC3PSC_0        (0x1U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
15918 #define TIM_CCMR2_IC3PSC_1        (0x2U << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
15919 
15920 #define TIM_CCMR2_IC3F_Pos        (4U)
15921 #define TIM_CCMR2_IC3F_Msk        (0xFU << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
15922 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
15923 #define TIM_CCMR2_IC3F_0          (0x1U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
15924 #define TIM_CCMR2_IC3F_1          (0x2U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
15925 #define TIM_CCMR2_IC3F_2          (0x4U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
15926 #define TIM_CCMR2_IC3F_3          (0x8U << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
15927 
15928 #define TIM_CCMR2_IC4PSC_Pos      (10U)
15929 #define TIM_CCMR2_IC4PSC_Msk      (0x3U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
15930 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
15931 #define TIM_CCMR2_IC4PSC_0        (0x1U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
15932 #define TIM_CCMR2_IC4PSC_1        (0x2U << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
15933 
15934 #define TIM_CCMR2_IC4F_Pos        (12U)
15935 #define TIM_CCMR2_IC4F_Msk        (0xFU << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
15936 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
15937 #define TIM_CCMR2_IC4F_0          (0x1U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
15938 #define TIM_CCMR2_IC4F_1          (0x2U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
15939 #define TIM_CCMR2_IC4F_2          (0x4U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
15940 #define TIM_CCMR2_IC4F_3          (0x8U << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
15941 
15942 /******************  Bit definition for TIM_CCMR3 register  *******************/
15943 #define TIM_CCMR3_OC5FE_Pos       (2U)
15944 #define TIM_CCMR3_OC5FE_Msk       (0x1U << TIM_CCMR3_OC5FE_Pos)                /*!< 0x00000004 */
15945 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
15946 #define TIM_CCMR3_OC5PE_Pos       (3U)
15947 #define TIM_CCMR3_OC5PE_Msk       (0x1U << TIM_CCMR3_OC5PE_Pos)                /*!< 0x00000008 */
15948 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
15949 
15950 #define TIM_CCMR3_OC5M_Pos        (4U)
15951 #define TIM_CCMR3_OC5M_Msk        (0x1007U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010070 */
15952 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
15953 #define TIM_CCMR3_OC5M_0          (0x0001U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000010 */
15954 #define TIM_CCMR3_OC5M_1          (0x0002U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000020 */
15955 #define TIM_CCMR3_OC5M_2          (0x0004U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00000040 */
15956 #define TIM_CCMR3_OC5M_3          (0x1000U << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
15957 
15958 #define TIM_CCMR3_OC5CE_Pos       (7U)
15959 #define TIM_CCMR3_OC5CE_Msk       (0x1U << TIM_CCMR3_OC5CE_Pos)                /*!< 0x00000080 */
15960 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
15961 
15962 #define TIM_CCMR3_OC6FE_Pos       (10U)
15963 #define TIM_CCMR3_OC6FE_Msk       (0x1U << TIM_CCMR3_OC6FE_Pos)                /*!< 0x00000400 */
15964 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
15965 #define TIM_CCMR3_OC6PE_Pos       (11U)
15966 #define TIM_CCMR3_OC6PE_Msk       (0x1U << TIM_CCMR3_OC6PE_Pos)                /*!< 0x00000800 */
15967 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
15968 
15969 #define TIM_CCMR3_OC6M_Pos        (12U)
15970 #define TIM_CCMR3_OC6M_Msk        (0x1007U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01007000 */
15971 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
15972 #define TIM_CCMR3_OC6M_0          (0x0001U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00001000 */
15973 #define TIM_CCMR3_OC6M_1          (0x0002U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00002000 */
15974 #define TIM_CCMR3_OC6M_2          (0x0004U << TIM_CCMR3_OC6M_Pos)              /*!< 0x00004000 */
15975 #define TIM_CCMR3_OC6M_3          (0x1000U << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
15976 
15977 #define TIM_CCMR3_OC6CE_Pos       (15U)
15978 #define TIM_CCMR3_OC6CE_Msk       (0x1U << TIM_CCMR3_OC6CE_Pos)                /*!< 0x00008000 */
15979 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
15980 
15981 /*******************  Bit definition for TIM_CCER register  *******************/
15982 #define TIM_CCER_CC1E_Pos         (0U)
15983 #define TIM_CCER_CC1E_Msk         (0x1U << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
15984 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
15985 #define TIM_CCER_CC1P_Pos         (1U)
15986 #define TIM_CCER_CC1P_Msk         (0x1U << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
15987 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
15988 #define TIM_CCER_CC1NE_Pos        (2U)
15989 #define TIM_CCER_CC1NE_Msk        (0x1U << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
15990 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
15991 #define TIM_CCER_CC1NP_Pos        (3U)
15992 #define TIM_CCER_CC1NP_Msk        (0x1U << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
15993 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
15994 #define TIM_CCER_CC2E_Pos         (4U)
15995 #define TIM_CCER_CC2E_Msk         (0x1U << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
15996 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
15997 #define TIM_CCER_CC2P_Pos         (5U)
15998 #define TIM_CCER_CC2P_Msk         (0x1U << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
15999 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
16000 #define TIM_CCER_CC2NE_Pos        (6U)
16001 #define TIM_CCER_CC2NE_Msk        (0x1U << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
16002 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
16003 #define TIM_CCER_CC2NP_Pos        (7U)
16004 #define TIM_CCER_CC2NP_Msk        (0x1U << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
16005 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
16006 #define TIM_CCER_CC3E_Pos         (8U)
16007 #define TIM_CCER_CC3E_Msk         (0x1U << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
16008 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
16009 #define TIM_CCER_CC3P_Pos         (9U)
16010 #define TIM_CCER_CC3P_Msk         (0x1U << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
16011 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
16012 #define TIM_CCER_CC3NE_Pos        (10U)
16013 #define TIM_CCER_CC3NE_Msk        (0x1U << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
16014 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
16015 #define TIM_CCER_CC3NP_Pos        (11U)
16016 #define TIM_CCER_CC3NP_Msk        (0x1U << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
16017 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
16018 #define TIM_CCER_CC4E_Pos         (12U)
16019 #define TIM_CCER_CC4E_Msk         (0x1U << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
16020 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
16021 #define TIM_CCER_CC4P_Pos         (13U)
16022 #define TIM_CCER_CC4P_Msk         (0x1U << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
16023 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
16024 #define TIM_CCER_CC4NP_Pos        (15U)
16025 #define TIM_CCER_CC4NP_Msk        (0x1U << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
16026 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
16027 #define TIM_CCER_CC5E_Pos         (16U)
16028 #define TIM_CCER_CC5E_Msk         (0x1U << TIM_CCER_CC5E_Pos)                  /*!< 0x00010000 */
16029 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
16030 #define TIM_CCER_CC5P_Pos         (17U)
16031 #define TIM_CCER_CC5P_Msk         (0x1U << TIM_CCER_CC5P_Pos)                  /*!< 0x00020000 */
16032 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
16033 #define TIM_CCER_CC6E_Pos         (20U)
16034 #define TIM_CCER_CC6E_Msk         (0x1U << TIM_CCER_CC6E_Pos)                  /*!< 0x00100000 */
16035 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
16036 #define TIM_CCER_CC6P_Pos         (21U)
16037 #define TIM_CCER_CC6P_Msk         (0x1U << TIM_CCER_CC6P_Pos)                  /*!< 0x00200000 */
16038 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
16039 
16040 /*******************  Bit definition for TIM_CNT register  ********************/
16041 #define TIM_CNT_CNT_Pos           (0U)
16042 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFU << TIM_CNT_CNT_Pos)             /*!< 0xFFFFFFFF */
16043 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
16044 #define TIM_CNT_UIFCPY_Pos        (31U)
16045 #define TIM_CNT_UIFCPY_Msk        (0x1U << TIM_CNT_UIFCPY_Pos)                 /*!< 0x80000000 */
16046 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
16047 
16048 /*******************  Bit definition for TIM_PSC register  ********************/
16049 #define TIM_PSC_PSC_Pos           (0U)
16050 #define TIM_PSC_PSC_Msk           (0xFFFFU << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
16051 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
16052 
16053 /*******************  Bit definition for TIM_ARR register  ********************/
16054 #define TIM_ARR_ARR_Pos           (0U)
16055 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFU << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
16056 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
16057 
16058 /*******************  Bit definition for TIM_RCR register  ********************/
16059 #define TIM_RCR_REP_Pos           (0U)
16060 #define TIM_RCR_REP_Msk           (0xFFFFU << TIM_RCR_REP_Pos)                 /*!< 0x0000FFFF */
16061 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
16062 
16063 /*******************  Bit definition for TIM_CCR1 register  *******************/
16064 #define TIM_CCR1_CCR1_Pos         (0U)
16065 #define TIM_CCR1_CCR1_Msk         (0xFFFFU << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
16066 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
16067 
16068 /*******************  Bit definition for TIM_CCR2 register  *******************/
16069 #define TIM_CCR2_CCR2_Pos         (0U)
16070 #define TIM_CCR2_CCR2_Msk         (0xFFFFU << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
16071 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
16072 
16073 /*******************  Bit definition for TIM_CCR3 register  *******************/
16074 #define TIM_CCR3_CCR3_Pos         (0U)
16075 #define TIM_CCR3_CCR3_Msk         (0xFFFFU << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
16076 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
16077 
16078 /*******************  Bit definition for TIM_CCR4 register  *******************/
16079 #define TIM_CCR4_CCR4_Pos         (0U)
16080 #define TIM_CCR4_CCR4_Msk         (0xFFFFU << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
16081 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
16082 
16083 /*******************  Bit definition for TIM_CCR5 register  *******************/
16084 #define TIM_CCR5_CCR5_Pos         (0U)
16085 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFU << TIM_CCR5_CCR5_Pos)           /*!< 0xFFFFFFFF */
16086 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
16087 #define TIM_CCR5_GC5C1_Pos        (29U)
16088 #define TIM_CCR5_GC5C1_Msk        (0x1U << TIM_CCR5_GC5C1_Pos)                 /*!< 0x20000000 */
16089 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
16090 #define TIM_CCR5_GC5C2_Pos        (30U)
16091 #define TIM_CCR5_GC5C2_Msk        (0x1U << TIM_CCR5_GC5C2_Pos)                 /*!< 0x40000000 */
16092 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
16093 #define TIM_CCR5_GC5C3_Pos        (31U)
16094 #define TIM_CCR5_GC5C3_Msk        (0x1U << TIM_CCR5_GC5C3_Pos)                 /*!< 0x80000000 */
16095 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
16096 
16097 /*******************  Bit definition for TIM_CCR6 register  *******************/
16098 #define TIM_CCR6_CCR6_Pos         (0U)
16099 #define TIM_CCR6_CCR6_Msk         (0xFFFFU << TIM_CCR6_CCR6_Pos)               /*!< 0x0000FFFF */
16100 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
16101 
16102 /*******************  Bit definition for TIM_BDTR register  *******************/
16103 #define TIM_BDTR_DTG_Pos          (0U)
16104 #define TIM_BDTR_DTG_Msk          (0xFFU << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
16105 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
16106 #define TIM_BDTR_DTG_0            (0x01U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
16107 #define TIM_BDTR_DTG_1            (0x02U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
16108 #define TIM_BDTR_DTG_2            (0x04U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
16109 #define TIM_BDTR_DTG_3            (0x08U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
16110 #define TIM_BDTR_DTG_4            (0x10U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
16111 #define TIM_BDTR_DTG_5            (0x20U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
16112 #define TIM_BDTR_DTG_6            (0x40U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
16113 #define TIM_BDTR_DTG_7            (0x80U << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
16114 
16115 #define TIM_BDTR_LOCK_Pos         (8U)
16116 #define TIM_BDTR_LOCK_Msk         (0x3U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
16117 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
16118 #define TIM_BDTR_LOCK_0           (0x1U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
16119 #define TIM_BDTR_LOCK_1           (0x2U << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
16120 
16121 #define TIM_BDTR_OSSI_Pos         (10U)
16122 #define TIM_BDTR_OSSI_Msk         (0x1U << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
16123 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
16124 #define TIM_BDTR_OSSR_Pos         (11U)
16125 #define TIM_BDTR_OSSR_Msk         (0x1U << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
16126 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
16127 #define TIM_BDTR_BKE_Pos          (12U)
16128 #define TIM_BDTR_BKE_Msk          (0x1U << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
16129 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
16130 #define TIM_BDTR_BKP_Pos          (13U)
16131 #define TIM_BDTR_BKP_Msk          (0x1U << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
16132 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
16133 #define TIM_BDTR_AOE_Pos          (14U)
16134 #define TIM_BDTR_AOE_Msk          (0x1U << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
16135 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
16136 #define TIM_BDTR_MOE_Pos          (15U)
16137 #define TIM_BDTR_MOE_Msk          (0x1U << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
16138 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
16139 
16140 #define TIM_BDTR_BKF_Pos          (16U)
16141 #define TIM_BDTR_BKF_Msk          (0xFU << TIM_BDTR_BKF_Pos)                   /*!< 0x000F0000 */
16142 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
16143 #define TIM_BDTR_BK2F_Pos         (20U)
16144 #define TIM_BDTR_BK2F_Msk         (0xFU << TIM_BDTR_BK2F_Pos)                  /*!< 0x00F00000 */
16145 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
16146 
16147 #define TIM_BDTR_BK2E_Pos         (24U)
16148 #define TIM_BDTR_BK2E_Msk         (0x1U << TIM_BDTR_BK2E_Pos)                  /*!< 0x01000000 */
16149 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
16150 #define TIM_BDTR_BK2P_Pos         (25U)
16151 #define TIM_BDTR_BK2P_Msk         (0x1U << TIM_BDTR_BK2P_Pos)                  /*!< 0x02000000 */
16152 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
16153 
16154 /*******************  Bit definition for TIM_DCR register  ********************/
16155 #define TIM_DCR_DBA_Pos           (0U)
16156 #define TIM_DCR_DBA_Msk           (0x1FU << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
16157 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
16158 #define TIM_DCR_DBA_0             (0x01U << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
16159 #define TIM_DCR_DBA_1             (0x02U << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
16160 #define TIM_DCR_DBA_2             (0x04U << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
16161 #define TIM_DCR_DBA_3             (0x08U << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
16162 #define TIM_DCR_DBA_4             (0x10U << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
16163 
16164 #define TIM_DCR_DBL_Pos           (8U)
16165 #define TIM_DCR_DBL_Msk           (0x1FU << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
16166 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
16167 #define TIM_DCR_DBL_0             (0x01U << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
16168 #define TIM_DCR_DBL_1             (0x02U << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
16169 #define TIM_DCR_DBL_2             (0x04U << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
16170 #define TIM_DCR_DBL_3             (0x08U << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
16171 #define TIM_DCR_DBL_4             (0x10U << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
16172 
16173 /*******************  Bit definition for TIM_DMAR register  *******************/
16174 #define TIM_DMAR_DMAB_Pos         (0U)
16175 #define TIM_DMAR_DMAB_Msk         (0xFFFFU << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
16176 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
16177 
16178 /*******************  Bit definition for TIM1_OR1 register  *******************/
16179 #define TIM1_OR1_ETR_ADC1_RMP_Pos      (0U)
16180 #define TIM1_OR1_ETR_ADC1_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000003 */
16181 #define TIM1_OR1_ETR_ADC1_RMP          TIM1_OR1_ETR_ADC1_RMP_Msk               /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */
16182 #define TIM1_OR1_ETR_ADC1_RMP_0        (0x1U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000001 */
16183 #define TIM1_OR1_ETR_ADC1_RMP_1        (0x2U << TIM1_OR1_ETR_ADC1_RMP_Pos)     /*!< 0x00000002 */
16184 
16185 #define TIM1_OR1_ETR_ADC3_RMP_Pos      (2U)
16186 #define TIM1_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
16187 #define TIM1_OR1_ETR_ADC3_RMP          TIM1_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */
16188 #define TIM1_OR1_ETR_ADC3_RMP_0        (0x1U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
16189 #define TIM1_OR1_ETR_ADC3_RMP_1        (0x2U << TIM1_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
16190 
16191 #define TIM1_OR1_TI1_RMP_Pos           (4U)
16192 #define TIM1_OR1_TI1_RMP_Msk           (0x1U << TIM1_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
16193 #define TIM1_OR1_TI1_RMP               TIM1_OR1_TI1_RMP_Msk                    /*!<TIM1 Input Capture 1 remap */
16194 
16195 /*******************  Bit definition for TIM1_OR2 register  *******************/
16196 #define TIM1_OR2_BKINE_Pos             (0U)
16197 #define TIM1_OR2_BKINE_Msk             (0x1U << TIM1_OR2_BKINE_Pos)            /*!< 0x00000001 */
16198 #define TIM1_OR2_BKINE                 TIM1_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
16199 #define TIM1_OR2_BKCMP1E_Pos           (1U)
16200 #define TIM1_OR2_BKCMP1E_Msk           (0x1U << TIM1_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
16201 #define TIM1_OR2_BKCMP1E               TIM1_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
16202 #define TIM1_OR2_BKCMP2E_Pos           (2U)
16203 #define TIM1_OR2_BKCMP2E_Msk           (0x1U << TIM1_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
16204 #define TIM1_OR2_BKCMP2E               TIM1_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
16205 #define TIM1_OR2_BKDF1BK0E_Pos         (8U)
16206 #define TIM1_OR2_BKDF1BK0E_Msk         (0x1U << TIM1_OR2_BKDF1BK0E_Pos)        /*!< 0x00000100 */
16207 #define TIM1_OR2_BKDF1BK0E             TIM1_OR2_BKDF1BK0E_Msk                  /*!<BRK DFSDM1_BREAK[0] enable */
16208 #define TIM1_OR2_BKINP_Pos             (9U)
16209 #define TIM1_OR2_BKINP_Msk             (0x1U << TIM1_OR2_BKINP_Pos)            /*!< 0x00000200 */
16210 #define TIM1_OR2_BKINP                 TIM1_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
16211 #define TIM1_OR2_BKCMP1P_Pos           (10U)
16212 #define TIM1_OR2_BKCMP1P_Msk           (0x1U << TIM1_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
16213 #define TIM1_OR2_BKCMP1P               TIM1_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
16214 #define TIM1_OR2_BKCMP2P_Pos           (11U)
16215 #define TIM1_OR2_BKCMP2P_Msk           (0x1U << TIM1_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
16216 #define TIM1_OR2_BKCMP2P               TIM1_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
16217 
16218 #define TIM1_OR2_ETRSEL_Pos            (14U)
16219 #define TIM1_OR2_ETRSEL_Msk            (0x7U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
16220 #define TIM1_OR2_ETRSEL                TIM1_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */
16221 #define TIM1_OR2_ETRSEL_0              (0x1U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
16222 #define TIM1_OR2_ETRSEL_1              (0x2U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
16223 #define TIM1_OR2_ETRSEL_2              (0x4U << TIM1_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
16224 
16225 /*******************  Bit definition for TIM1_OR3 register  *******************/
16226 #define TIM1_OR3_BK2INE_Pos            (0U)
16227 #define TIM1_OR3_BK2INE_Msk            (0x1U << TIM1_OR3_BK2INE_Pos)           /*!< 0x00000001 */
16228 #define TIM1_OR3_BK2INE                TIM1_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
16229 #define TIM1_OR3_BK2CMP1E_Pos          (1U)
16230 #define TIM1_OR3_BK2CMP1E_Msk          (0x1U << TIM1_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
16231 #define TIM1_OR3_BK2CMP1E              TIM1_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
16232 #define TIM1_OR3_BK2CMP2E_Pos          (2U)
16233 #define TIM1_OR3_BK2CMP2E_Msk          (0x1U << TIM1_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
16234 #define TIM1_OR3_BK2CMP2E              TIM1_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
16235 #define TIM1_OR3_BK2DF1BK1E_Pos        (8U)
16236 #define TIM1_OR3_BK2DF1BK1E_Msk        (0x1U << TIM1_OR3_BK2DF1BK1E_Pos)       /*!< 0x00000100 */
16237 #define TIM1_OR3_BK2DF1BK1E            TIM1_OR3_BK2DF1BK1E_Msk                 /*!<BRK2 DFSDM1_BREAK[1] enable */
16238 #define TIM1_OR3_BK2INP_Pos            (9U)
16239 #define TIM1_OR3_BK2INP_Msk            (0x1U << TIM1_OR3_BK2INP_Pos)           /*!< 0x00000200 */
16240 #define TIM1_OR3_BK2INP                TIM1_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
16241 #define TIM1_OR3_BK2CMP1P_Pos          (10U)
16242 #define TIM1_OR3_BK2CMP1P_Msk          (0x1U << TIM1_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
16243 #define TIM1_OR3_BK2CMP1P              TIM1_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
16244 #define TIM1_OR3_BK2CMP2P_Pos          (11U)
16245 #define TIM1_OR3_BK2CMP2P_Msk          (0x1U << TIM1_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
16246 #define TIM1_OR3_BK2CMP2P              TIM1_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
16247 
16248 /*******************  Bit definition for TIM8_OR1 register  *******************/
16249 #define TIM8_OR1_ETR_ADC2_RMP_Pos      (0U)
16250 #define TIM8_OR1_ETR_ADC2_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000003 */
16251 #define TIM8_OR1_ETR_ADC2_RMP          TIM8_OR1_ETR_ADC2_RMP_Msk               /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */
16252 #define TIM8_OR1_ETR_ADC2_RMP_0        (0x1U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000001 */
16253 #define TIM8_OR1_ETR_ADC2_RMP_1        (0x2U << TIM8_OR1_ETR_ADC2_RMP_Pos)     /*!< 0x00000002 */
16254 
16255 #define TIM8_OR1_ETR_ADC3_RMP_Pos      (2U)
16256 #define TIM8_OR1_ETR_ADC3_RMP_Msk      (0x3U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x0000000C */
16257 #define TIM8_OR1_ETR_ADC3_RMP          TIM8_OR1_ETR_ADC3_RMP_Msk               /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */
16258 #define TIM8_OR1_ETR_ADC3_RMP_0        (0x1U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000004 */
16259 #define TIM8_OR1_ETR_ADC3_RMP_1        (0x2U << TIM8_OR1_ETR_ADC3_RMP_Pos)     /*!< 0x00000008 */
16260 
16261 #define TIM8_OR1_TI1_RMP_Pos           (4U)
16262 #define TIM8_OR1_TI1_RMP_Msk           (0x1U << TIM8_OR1_TI1_RMP_Pos)          /*!< 0x00000010 */
16263 #define TIM8_OR1_TI1_RMP               TIM8_OR1_TI1_RMP_Msk                    /*!<TIM8 Input Capture 1 remap */
16264 
16265 /*******************  Bit definition for TIM8_OR2 register  *******************/
16266 #define TIM8_OR2_BKINE_Pos             (0U)
16267 #define TIM8_OR2_BKINE_Msk             (0x1U << TIM8_OR2_BKINE_Pos)            /*!< 0x00000001 */
16268 #define TIM8_OR2_BKINE                 TIM8_OR2_BKINE_Msk                      /*!<BRK BKIN input enable */
16269 #define TIM8_OR2_BKCMP1E_Pos           (1U)
16270 #define TIM8_OR2_BKCMP1E_Msk           (0x1U << TIM8_OR2_BKCMP1E_Pos)          /*!< 0x00000002 */
16271 #define TIM8_OR2_BKCMP1E               TIM8_OR2_BKCMP1E_Msk                    /*!<BRK COMP1 enable */
16272 #define TIM8_OR2_BKCMP2E_Pos           (2U)
16273 #define TIM8_OR2_BKCMP2E_Msk           (0x1U << TIM8_OR2_BKCMP2E_Pos)          /*!< 0x00000004 */
16274 #define TIM8_OR2_BKCMP2E               TIM8_OR2_BKCMP2E_Msk                    /*!<BRK COMP2 enable */
16275 #define TIM8_OR2_BKDF1BK2E_Pos         (8U)
16276 #define TIM8_OR2_BKDF1BK2E_Msk         (0x1U << TIM8_OR2_BKDF1BK2E_Pos)        /*!< 0x00000100 */
16277 #define TIM8_OR2_BKDF1BK2E             TIM8_OR2_BKDF1BK2E_Msk                  /*!<BRK DFSDM1_BREAK[2] enable */
16278 #define TIM8_OR2_BKINP_Pos             (9U)
16279 #define TIM8_OR2_BKINP_Msk             (0x1U << TIM8_OR2_BKINP_Pos)            /*!< 0x00000200 */
16280 #define TIM8_OR2_BKINP                 TIM8_OR2_BKINP_Msk                      /*!<BRK BKIN input polarity */
16281 #define TIM8_OR2_BKCMP1P_Pos           (10U)
16282 #define TIM8_OR2_BKCMP1P_Msk           (0x1U << TIM8_OR2_BKCMP1P_Pos)          /*!< 0x00000400 */
16283 #define TIM8_OR2_BKCMP1P               TIM8_OR2_BKCMP1P_Msk                    /*!<BRK COMP1 input polarity */
16284 #define TIM8_OR2_BKCMP2P_Pos           (11U)
16285 #define TIM8_OR2_BKCMP2P_Msk           (0x1U << TIM8_OR2_BKCMP2P_Pos)          /*!< 0x00000800 */
16286 #define TIM8_OR2_BKCMP2P               TIM8_OR2_BKCMP2P_Msk                    /*!<BRK COMP2 input polarity */
16287 
16288 #define TIM8_OR2_ETRSEL_Pos            (14U)
16289 #define TIM8_OR2_ETRSEL_Msk            (0x7U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x0001C000 */
16290 #define TIM8_OR2_ETRSEL                TIM8_OR2_ETRSEL_Msk                     /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */
16291 #define TIM8_OR2_ETRSEL_0              (0x1U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00004000 */
16292 #define TIM8_OR2_ETRSEL_1              (0x2U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00008000 */
16293 #define TIM8_OR2_ETRSEL_2              (0x4U << TIM8_OR2_ETRSEL_Pos)           /*!< 0x00010000 */
16294 
16295 /*******************  Bit definition for TIM8_OR3 register  *******************/
16296 #define TIM8_OR3_BK2INE_Pos            (0U)
16297 #define TIM8_OR3_BK2INE_Msk            (0x1U << TIM8_OR3_BK2INE_Pos)           /*!< 0x00000001 */
16298 #define TIM8_OR3_BK2INE                TIM8_OR3_BK2INE_Msk                     /*!<BRK2 BKIN2 input enable */
16299 #define TIM8_OR3_BK2CMP1E_Pos          (1U)
16300 #define TIM8_OR3_BK2CMP1E_Msk          (0x1U << TIM8_OR3_BK2CMP1E_Pos)         /*!< 0x00000002 */
16301 #define TIM8_OR3_BK2CMP1E              TIM8_OR3_BK2CMP1E_Msk                   /*!<BRK2 COMP1 enable */
16302 #define TIM8_OR3_BK2CMP2E_Pos          (2U)
16303 #define TIM8_OR3_BK2CMP2E_Msk          (0x1U << TIM8_OR3_BK2CMP2E_Pos)         /*!< 0x00000004 */
16304 #define TIM8_OR3_BK2CMP2E              TIM8_OR3_BK2CMP2E_Msk                   /*!<BRK2 COMP2 enable */
16305 #define TIM8_OR3_BK2DF1BK3E_Pos        (8U)
16306 #define TIM8_OR3_BK2DF1BK3E_Msk        (0x1U << TIM8_OR3_BK2DF1BK3E_Pos)       /*!< 0x00000100 */
16307 #define TIM8_OR3_BK2DF1BK3E            TIM8_OR3_BK2DF1BK3E_Msk                 /*!<BRK2 DFSDM1_BREAK[3] enable */
16308 #define TIM8_OR3_BK2INP_Pos            (9U)
16309 #define TIM8_OR3_BK2INP_Msk            (0x1U << TIM8_OR3_BK2INP_Pos)           /*!< 0x00000200 */
16310 #define TIM8_OR3_BK2INP                TIM8_OR3_BK2INP_Msk                     /*!<BRK2 BKIN2 input polarity */
16311 #define TIM8_OR3_BK2CMP1P_Pos          (10U)
16312 #define TIM8_OR3_BK2CMP1P_Msk          (0x1U << TIM8_OR3_BK2CMP1P_Pos)         /*!< 0x00000400 */
16313 #define TIM8_OR3_BK2CMP1P              TIM8_OR3_BK2CMP1P_Msk                   /*!<BRK2 COMP1 input polarity */
16314 #define TIM8_OR3_BK2CMP2P_Pos          (11U)
16315 #define TIM8_OR3_BK2CMP2P_Msk          (0x1U << TIM8_OR3_BK2CMP2P_Pos)         /*!< 0x00000800 */
16316 #define TIM8_OR3_BK2CMP2P              TIM8_OR3_BK2CMP2P_Msk                   /*!<BRK2 COMP2 input polarity */
16317 
16318 /*******************  Bit definition for TIM2_OR1 register  *******************/
16319 #define TIM2_OR1_ITR1_RMP_Pos     (0U)
16320 #define TIM2_OR1_ITR1_RMP_Msk     (0x1U << TIM2_OR1_ITR1_RMP_Pos)              /*!< 0x00000001 */
16321 #define TIM2_OR1_ITR1_RMP         TIM2_OR1_ITR1_RMP_Msk                        /*!<TIM2 Internal trigger 1 remap */
16322 #define TIM2_OR1_ETR1_RMP_Pos     (1U)
16323 #define TIM2_OR1_ETR1_RMP_Msk     (0x1U << TIM2_OR1_ETR1_RMP_Pos)              /*!< 0x00000002 */
16324 #define TIM2_OR1_ETR1_RMP         TIM2_OR1_ETR1_RMP_Msk                        /*!<TIM2 External trigger 1 remap */
16325 
16326 #define TIM2_OR1_TI4_RMP_Pos      (2U)
16327 #define TIM2_OR1_TI4_RMP_Msk      (0x3U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x0000000C */
16328 #define TIM2_OR1_TI4_RMP          TIM2_OR1_TI4_RMP_Msk                         /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */
16329 #define TIM2_OR1_TI4_RMP_0        (0x1U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000004 */
16330 #define TIM2_OR1_TI4_RMP_1        (0x2U << TIM2_OR1_TI4_RMP_Pos)               /*!< 0x00000008 */
16331 
16332 /*******************  Bit definition for TIM2_OR2 register  *******************/
16333 #define TIM2_OR2_ETRSEL_Pos       (14U)
16334 #define TIM2_OR2_ETRSEL_Msk       (0x7U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
16335 #define TIM2_OR2_ETRSEL           TIM2_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */
16336 #define TIM2_OR2_ETRSEL_0         (0x1U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
16337 #define TIM2_OR2_ETRSEL_1         (0x2U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
16338 #define TIM2_OR2_ETRSEL_2         (0x4U << TIM2_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
16339 
16340 /*******************  Bit definition for TIM3_OR1 register  *******************/
16341 #define TIM3_OR1_TI1_RMP_Pos      (0U)
16342 #define TIM3_OR1_TI1_RMP_Msk      (0x3U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000003 */
16343 #define TIM3_OR1_TI1_RMP          TIM3_OR1_TI1_RMP_Msk                         /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */
16344 #define TIM3_OR1_TI1_RMP_0        (0x1U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000001 */
16345 #define TIM3_OR1_TI1_RMP_1        (0x2U << TIM3_OR1_TI1_RMP_Pos)               /*!< 0x00000002 */
16346 
16347 /*******************  Bit definition for TIM3_OR2 register  *******************/
16348 #define TIM3_OR2_ETRSEL_Pos       (14U)
16349 #define TIM3_OR2_ETRSEL_Msk       (0x7U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x0001C000 */
16350 #define TIM3_OR2_ETRSEL           TIM3_OR2_ETRSEL_Msk                          /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */
16351 #define TIM3_OR2_ETRSEL_0         (0x1U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00004000 */
16352 #define TIM3_OR2_ETRSEL_1         (0x2U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00008000 */
16353 #define TIM3_OR2_ETRSEL_2         (0x4U << TIM3_OR2_ETRSEL_Pos)                /*!< 0x00010000 */
16354 
16355 /*******************  Bit definition for TIM15_OR1 register  ******************/
16356 #define TIM15_OR1_TI1_RMP_Pos           (0U)
16357 #define TIM15_OR1_TI1_RMP_Msk           (0x1U << TIM15_OR1_TI1_RMP_Pos)        /*!< 0x00000001 */
16358 #define TIM15_OR1_TI1_RMP               TIM15_OR1_TI1_RMP_Msk                  /*!<TIM15 Input Capture 1 remap */
16359 
16360 #define TIM15_OR1_ENCODER_MODE_Pos      (1U)
16361 #define TIM15_OR1_ENCODER_MODE_Msk      (0x3U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000006 */
16362 #define TIM15_OR1_ENCODER_MODE          TIM15_OR1_ENCODER_MODE_Msk             /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */
16363 #define TIM15_OR1_ENCODER_MODE_0        (0x1U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000002 */
16364 #define TIM15_OR1_ENCODER_MODE_1        (0x2U << TIM15_OR1_ENCODER_MODE_Pos)   /*!< 0x00000004 */
16365 
16366 /*******************  Bit definition for TIM15_OR2 register  ******************/
16367 #define TIM15_OR2_BKINE_Pos             (0U)
16368 #define TIM15_OR2_BKINE_Msk             (0x1U << TIM15_OR2_BKINE_Pos)          /*!< 0x00000001 */
16369 #define TIM15_OR2_BKINE                 TIM15_OR2_BKINE_Msk                    /*!<BRK BKIN input enable */
16370 #define TIM15_OR2_BKCMP1E_Pos           (1U)
16371 #define TIM15_OR2_BKCMP1E_Msk           (0x1U << TIM15_OR2_BKCMP1E_Pos)        /*!< 0x00000002 */
16372 #define TIM15_OR2_BKCMP1E               TIM15_OR2_BKCMP1E_Msk                  /*!<BRK COMP1 enable */
16373 #define TIM15_OR2_BKCMP2E_Pos           (2U)
16374 #define TIM15_OR2_BKCMP2E_Msk           (0x1U << TIM15_OR2_BKCMP2E_Pos)        /*!< 0x00000004 */
16375 #define TIM15_OR2_BKCMP2E               TIM15_OR2_BKCMP2E_Msk                  /*!<BRK COMP2 enable */
16376 #define TIM15_OR2_BKDF1BK0E_Pos         (8U)
16377 #define TIM15_OR2_BKDF1BK0E_Msk         (0x1U << TIM15_OR2_BKDF1BK0E_Pos)      /*!< 0x00000100 */
16378 #define TIM15_OR2_BKDF1BK0E             TIM15_OR2_BKDF1BK0E_Msk                /*!<BRK DFSDM1_BREAK[0] enable */
16379 #define TIM15_OR2_BKINP_Pos             (9U)
16380 #define TIM15_OR2_BKINP_Msk             (0x1U << TIM15_OR2_BKINP_Pos)          /*!< 0x00000200 */
16381 #define TIM15_OR2_BKINP                 TIM15_OR2_BKINP_Msk                    /*!<BRK BKIN input polarity */
16382 #define TIM15_OR2_BKCMP1P_Pos           (10U)
16383 #define TIM15_OR2_BKCMP1P_Msk           (0x1U << TIM15_OR2_BKCMP1P_Pos)        /*!< 0x00000400 */
16384 #define TIM15_OR2_BKCMP1P               TIM15_OR2_BKCMP1P_Msk                  /*!<BRK COMP1 input polarity */
16385 #define TIM15_OR2_BKCMP2P_Pos           (11U)
16386 #define TIM15_OR2_BKCMP2P_Msk           (0x1U << TIM15_OR2_BKCMP2P_Pos)        /*!< 0x00000800 */
16387 #define TIM15_OR2_BKCMP2P               TIM15_OR2_BKCMP2P_Msk                  /*!<BRK COMP2 input polarity */
16388 
16389 /*******************  Bit definition for TIM16_OR1 register  ******************/
16390 #define TIM16_OR1_TI1_RMP_Pos      (0U)
16391 #define TIM16_OR1_TI1_RMP_Msk      (0x7U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000007 */
16392 #define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[2:0] bits (TIM16 Input Capture 1 remap) */
16393 #define TIM16_OR1_TI1_RMP_0        (0x1U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
16394 #define TIM16_OR1_TI1_RMP_1        (0x2U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
16395 #define TIM16_OR1_TI1_RMP_2        (0x4U << TIM16_OR1_TI1_RMP_Pos)             /*!< 0x00000004 */
16396 
16397 /*******************  Bit definition for TIM16_OR2 register  ******************/
16398 #define TIM16_OR2_BKINE_Pos        (0U)
16399 #define TIM16_OR2_BKINE_Msk        (0x1U << TIM16_OR2_BKINE_Pos)               /*!< 0x00000001 */
16400 #define TIM16_OR2_BKINE            TIM16_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
16401 #define TIM16_OR2_BKCMP1E_Pos      (1U)
16402 #define TIM16_OR2_BKCMP1E_Msk      (0x1U << TIM16_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
16403 #define TIM16_OR2_BKCMP1E          TIM16_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
16404 #define TIM16_OR2_BKCMP2E_Pos      (2U)
16405 #define TIM16_OR2_BKCMP2E_Msk      (0x1U << TIM16_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
16406 #define TIM16_OR2_BKCMP2E          TIM16_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
16407 #define TIM16_OR2_BKDF1BK1E_Pos    (8U)
16408 #define TIM16_OR2_BKDF1BK1E_Msk    (0x1U << TIM16_OR2_BKDF1BK1E_Pos)           /*!< 0x00000100 */
16409 #define TIM16_OR2_BKDF1BK1E        TIM16_OR2_BKDF1BK1E_Msk                     /*!<BRK DFSDM1_BREAK[1] enable */
16410 #define TIM16_OR2_BKINP_Pos        (9U)
16411 #define TIM16_OR2_BKINP_Msk        (0x1U << TIM16_OR2_BKINP_Pos)               /*!< 0x00000200 */
16412 #define TIM16_OR2_BKINP            TIM16_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
16413 #define TIM16_OR2_BKCMP1P_Pos      (10U)
16414 #define TIM16_OR2_BKCMP1P_Msk      (0x1U << TIM16_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
16415 #define TIM16_OR2_BKCMP1P          TIM16_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
16416 #define TIM16_OR2_BKCMP2P_Pos      (11U)
16417 #define TIM16_OR2_BKCMP2P_Msk      (0x1U << TIM16_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
16418 #define TIM16_OR2_BKCMP2P          TIM16_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
16419 
16420 /*******************  Bit definition for TIM17_OR1 register  ******************/
16421 #define TIM17_OR1_TI1_RMP_Pos      (0U)
16422 #define TIM17_OR1_TI1_RMP_Msk      (0x3U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000003 */
16423 #define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */
16424 #define TIM17_OR1_TI1_RMP_0        (0x1U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000001 */
16425 #define TIM17_OR1_TI1_RMP_1        (0x2U << TIM17_OR1_TI1_RMP_Pos)             /*!< 0x00000002 */
16426 
16427 /*******************  Bit definition for TIM17_OR2 register  ******************/
16428 #define TIM17_OR2_BKINE_Pos        (0U)
16429 #define TIM17_OR2_BKINE_Msk        (0x1U << TIM17_OR2_BKINE_Pos)               /*!< 0x00000001 */
16430 #define TIM17_OR2_BKINE            TIM17_OR2_BKINE_Msk                         /*!<BRK BKIN input enable */
16431 #define TIM17_OR2_BKCMP1E_Pos      (1U)
16432 #define TIM17_OR2_BKCMP1E_Msk      (0x1U << TIM17_OR2_BKCMP1E_Pos)             /*!< 0x00000002 */
16433 #define TIM17_OR2_BKCMP1E          TIM17_OR2_BKCMP1E_Msk                       /*!<BRK COMP1 enable */
16434 #define TIM17_OR2_BKCMP2E_Pos      (2U)
16435 #define TIM17_OR2_BKCMP2E_Msk      (0x1U << TIM17_OR2_BKCMP2E_Pos)             /*!< 0x00000004 */
16436 #define TIM17_OR2_BKCMP2E          TIM17_OR2_BKCMP2E_Msk                       /*!<BRK COMP2 enable */
16437 #define TIM17_OR2_BKDF1BK2E_Pos    (8U)
16438 #define TIM17_OR2_BKDF1BK2E_Msk    (0x1U << TIM17_OR2_BKDF1BK2E_Pos)           /*!< 0x00000100 */
16439 #define TIM17_OR2_BKDF1BK2E        TIM17_OR2_BKDF1BK2E_Msk                     /*!<BRK DFSDM1_BREAK[2] enable */
16440 #define TIM17_OR2_BKINP_Pos        (9U)
16441 #define TIM17_OR2_BKINP_Msk        (0x1U << TIM17_OR2_BKINP_Pos)               /*!< 0x00000200 */
16442 #define TIM17_OR2_BKINP            TIM17_OR2_BKINP_Msk                         /*!<BRK BKIN input polarity */
16443 #define TIM17_OR2_BKCMP1P_Pos      (10U)
16444 #define TIM17_OR2_BKCMP1P_Msk      (0x1U << TIM17_OR2_BKCMP1P_Pos)             /*!< 0x00000400 */
16445 #define TIM17_OR2_BKCMP1P          TIM17_OR2_BKCMP1P_Msk                       /*!<BRK COMP1 input polarity */
16446 #define TIM17_OR2_BKCMP2P_Pos      (11U)
16447 #define TIM17_OR2_BKCMP2P_Msk      (0x1U << TIM17_OR2_BKCMP2P_Pos)             /*!< 0x00000800 */
16448 #define TIM17_OR2_BKCMP2P          TIM17_OR2_BKCMP2P_Msk                       /*!<BRK COMP2 input polarity */
16449 
16450 /******************************************************************************/
16451 /*                                                                            */
16452 /*                         Low Power Timer (LPTTIM)                           */
16453 /*                                                                            */
16454 /******************************************************************************/
16455 /******************  Bit definition for LPTIM_ISR register  *******************/
16456 #define LPTIM_ISR_CMPM_Pos          (0U)
16457 #define LPTIM_ISR_CMPM_Msk          (0x1U << LPTIM_ISR_CMPM_Pos)               /*!< 0x00000001 */
16458 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
16459 #define LPTIM_ISR_ARRM_Pos          (1U)
16460 #define LPTIM_ISR_ARRM_Msk          (0x1U << LPTIM_ISR_ARRM_Pos)               /*!< 0x00000002 */
16461 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
16462 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
16463 #define LPTIM_ISR_EXTTRIG_Msk       (0x1U << LPTIM_ISR_EXTTRIG_Pos)            /*!< 0x00000004 */
16464 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
16465 #define LPTIM_ISR_CMPOK_Pos         (3U)
16466 #define LPTIM_ISR_CMPOK_Msk         (0x1U << LPTIM_ISR_CMPOK_Pos)              /*!< 0x00000008 */
16467 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
16468 #define LPTIM_ISR_ARROK_Pos         (4U)
16469 #define LPTIM_ISR_ARROK_Msk         (0x1U << LPTIM_ISR_ARROK_Pos)              /*!< 0x00000010 */
16470 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
16471 #define LPTIM_ISR_UP_Pos            (5U)
16472 #define LPTIM_ISR_UP_Msk            (0x1U << LPTIM_ISR_UP_Pos)                 /*!< 0x00000020 */
16473 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
16474 #define LPTIM_ISR_DOWN_Pos          (6U)
16475 #define LPTIM_ISR_DOWN_Msk          (0x1U << LPTIM_ISR_DOWN_Pos)               /*!< 0x00000040 */
16476 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
16477 
16478 /******************  Bit definition for LPTIM_ICR register  *******************/
16479 #define LPTIM_ICR_CMPMCF_Pos        (0U)
16480 #define LPTIM_ICR_CMPMCF_Msk        (0x1U << LPTIM_ICR_CMPMCF_Pos)             /*!< 0x00000001 */
16481 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
16482 #define LPTIM_ICR_ARRMCF_Pos        (1U)
16483 #define LPTIM_ICR_ARRMCF_Msk        (0x1U << LPTIM_ICR_ARRMCF_Pos)             /*!< 0x00000002 */
16484 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
16485 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
16486 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1U << LPTIM_ICR_EXTTRIGCF_Pos)          /*!< 0x00000004 */
16487 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
16488 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
16489 #define LPTIM_ICR_CMPOKCF_Msk       (0x1U << LPTIM_ICR_CMPOKCF_Pos)            /*!< 0x00000008 */
16490 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
16491 #define LPTIM_ICR_ARROKCF_Pos       (4U)
16492 #define LPTIM_ICR_ARROKCF_Msk       (0x1U << LPTIM_ICR_ARROKCF_Pos)            /*!< 0x00000010 */
16493 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
16494 #define LPTIM_ICR_UPCF_Pos          (5U)
16495 #define LPTIM_ICR_UPCF_Msk          (0x1U << LPTIM_ICR_UPCF_Pos)               /*!< 0x00000020 */
16496 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
16497 #define LPTIM_ICR_DOWNCF_Pos        (6U)
16498 #define LPTIM_ICR_DOWNCF_Msk        (0x1U << LPTIM_ICR_DOWNCF_Pos)             /*!< 0x00000040 */
16499 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
16500 
16501 /******************  Bit definition for LPTIM_IER register ********************/
16502 #define LPTIM_IER_CMPMIE_Pos        (0U)
16503 #define LPTIM_IER_CMPMIE_Msk        (0x1U << LPTIM_IER_CMPMIE_Pos)             /*!< 0x00000001 */
16504 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
16505 #define LPTIM_IER_ARRMIE_Pos        (1U)
16506 #define LPTIM_IER_ARRMIE_Msk        (0x1U << LPTIM_IER_ARRMIE_Pos)             /*!< 0x00000002 */
16507 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
16508 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
16509 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1U << LPTIM_IER_EXTTRIGIE_Pos)          /*!< 0x00000004 */
16510 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
16511 #define LPTIM_IER_CMPOKIE_Pos       (3U)
16512 #define LPTIM_IER_CMPOKIE_Msk       (0x1U << LPTIM_IER_CMPOKIE_Pos)            /*!< 0x00000008 */
16513 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
16514 #define LPTIM_IER_ARROKIE_Pos       (4U)
16515 #define LPTIM_IER_ARROKIE_Msk       (0x1U << LPTIM_IER_ARROKIE_Pos)            /*!< 0x00000010 */
16516 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
16517 #define LPTIM_IER_UPIE_Pos          (5U)
16518 #define LPTIM_IER_UPIE_Msk          (0x1U << LPTIM_IER_UPIE_Pos)               /*!< 0x00000020 */
16519 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
16520 #define LPTIM_IER_DOWNIE_Pos        (6U)
16521 #define LPTIM_IER_DOWNIE_Msk        (0x1U << LPTIM_IER_DOWNIE_Pos)             /*!< 0x00000040 */
16522 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
16523 
16524 /******************  Bit definition for LPTIM_CFGR register *******************/
16525 #define LPTIM_CFGR_CKSEL_Pos        (0U)
16526 #define LPTIM_CFGR_CKSEL_Msk        (0x1U << LPTIM_CFGR_CKSEL_Pos)             /*!< 0x00000001 */
16527 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
16528 
16529 #define LPTIM_CFGR_CKPOL_Pos        (1U)
16530 #define LPTIM_CFGR_CKPOL_Msk        (0x3U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000006 */
16531 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
16532 #define LPTIM_CFGR_CKPOL_0          (0x1U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
16533 #define LPTIM_CFGR_CKPOL_1          (0x2U << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
16534 
16535 #define LPTIM_CFGR_CKFLT_Pos        (3U)
16536 #define LPTIM_CFGR_CKFLT_Msk        (0x3U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000018 */
16537 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
16538 #define LPTIM_CFGR_CKFLT_0          (0x1U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
16539 #define LPTIM_CFGR_CKFLT_1          (0x2U << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
16540 
16541 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
16542 #define LPTIM_CFGR_TRGFLT_Msk       (0x3U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x000000C0 */
16543 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
16544 #define LPTIM_CFGR_TRGFLT_0         (0x1U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
16545 #define LPTIM_CFGR_TRGFLT_1         (0x2U << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
16546 
16547 #define LPTIM_CFGR_PRESC_Pos        (9U)
16548 #define LPTIM_CFGR_PRESC_Msk        (0x7U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000E00 */
16549 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
16550 #define LPTIM_CFGR_PRESC_0          (0x1U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
16551 #define LPTIM_CFGR_PRESC_1          (0x2U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
16552 #define LPTIM_CFGR_PRESC_2          (0x4U << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
16553 
16554 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
16555 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x0000E000 */
16556 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
16557 #define LPTIM_CFGR_TRIGSEL_0        (0x1U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
16558 #define LPTIM_CFGR_TRIGSEL_1        (0x2U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
16559 #define LPTIM_CFGR_TRIGSEL_2        (0x4U << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
16560 
16561 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
16562 #define LPTIM_CFGR_TRIGEN_Msk       (0x3U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00060000 */
16563 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
16564 #define LPTIM_CFGR_TRIGEN_0         (0x1U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
16565 #define LPTIM_CFGR_TRIGEN_1         (0x2U << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
16566 
16567 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
16568 #define LPTIM_CFGR_TIMOUT_Msk       (0x1U << LPTIM_CFGR_TIMOUT_Pos)            /*!< 0x00080000 */
16569 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
16570 #define LPTIM_CFGR_WAVE_Pos         (20U)
16571 #define LPTIM_CFGR_WAVE_Msk         (0x1U << LPTIM_CFGR_WAVE_Pos)              /*!< 0x00100000 */
16572 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
16573 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
16574 #define LPTIM_CFGR_WAVPOL_Msk       (0x1U << LPTIM_CFGR_WAVPOL_Pos)            /*!< 0x00200000 */
16575 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
16576 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
16577 #define LPTIM_CFGR_PRELOAD_Msk      (0x1U << LPTIM_CFGR_PRELOAD_Pos)           /*!< 0x00400000 */
16578 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
16579 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
16580 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1U << LPTIM_CFGR_COUNTMODE_Pos)         /*!< 0x00800000 */
16581 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
16582 #define LPTIM_CFGR_ENC_Pos          (24U)
16583 #define LPTIM_CFGR_ENC_Msk          (0x1U << LPTIM_CFGR_ENC_Pos)               /*!< 0x01000000 */
16584 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
16585 
16586 /******************  Bit definition for LPTIM_CR register  ********************/
16587 #define LPTIM_CR_ENABLE_Pos         (0U)
16588 #define LPTIM_CR_ENABLE_Msk         (0x1U << LPTIM_CR_ENABLE_Pos)              /*!< 0x00000001 */
16589 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
16590 #define LPTIM_CR_SNGSTRT_Pos        (1U)
16591 #define LPTIM_CR_SNGSTRT_Msk        (0x1U << LPTIM_CR_SNGSTRT_Pos)             /*!< 0x00000002 */
16592 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
16593 #define LPTIM_CR_CNTSTRT_Pos        (2U)
16594 #define LPTIM_CR_CNTSTRT_Msk        (0x1U << LPTIM_CR_CNTSTRT_Pos)             /*!< 0x00000004 */
16595 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
16596 
16597 /******************  Bit definition for LPTIM_CMP register  *******************/
16598 #define LPTIM_CMP_CMP_Pos           (0U)
16599 #define LPTIM_CMP_CMP_Msk           (0xFFFFU << LPTIM_CMP_CMP_Pos)             /*!< 0x0000FFFF */
16600 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
16601 
16602 /******************  Bit definition for LPTIM_ARR register  *******************/
16603 #define LPTIM_ARR_ARR_Pos           (0U)
16604 #define LPTIM_ARR_ARR_Msk           (0xFFFFU << LPTIM_ARR_ARR_Pos)             /*!< 0x0000FFFF */
16605 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
16606 
16607 /******************  Bit definition for LPTIM_CNT register  *******************/
16608 #define LPTIM_CNT_CNT_Pos           (0U)
16609 #define LPTIM_CNT_CNT_Msk           (0xFFFFU << LPTIM_CNT_CNT_Pos)             /*!< 0x0000FFFF */
16610 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
16611 
16612 /******************  Bit definition for LPTIM_OR register  ********************/
16613 #define LPTIM_OR_OR_Pos             (0U)
16614 #define LPTIM_OR_OR_Msk             (0x3U << LPTIM_OR_OR_Pos)                  /*!< 0x00000003 */
16615 #define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
16616 #define LPTIM_OR_OR_0               (0x1U << LPTIM_OR_OR_Pos)                  /*!< 0x00000001 */
16617 #define LPTIM_OR_OR_1               (0x2U << LPTIM_OR_OR_Pos)                  /*!< 0x00000002 */
16618 
16619 /******************************************************************************/
16620 /*                                                                            */
16621 /*                      Analog Comparators (COMP)                             */
16622 /*                                                                            */
16623 /******************************************************************************/
16624 /**********************  Bit definition for COMP_CSR register  ****************/
16625 #define COMP_CSR_EN_Pos            (0U)
16626 #define COMP_CSR_EN_Msk            (0x1U << COMP_CSR_EN_Pos)                   /*!< 0x00000001 */
16627 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
16628 
16629 #define COMP_CSR_PWRMODE_Pos       (2U)
16630 #define COMP_CSR_PWRMODE_Msk       (0x3U << COMP_CSR_PWRMODE_Pos)              /*!< 0x0000000C */
16631 #define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
16632 #define COMP_CSR_PWRMODE_0         (0x1U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000004 */
16633 #define COMP_CSR_PWRMODE_1         (0x2U << COMP_CSR_PWRMODE_Pos)              /*!< 0x00000008 */
16634 
16635 #define COMP_CSR_INMSEL_Pos        (4U)
16636 #define COMP_CSR_INMSEL_Msk        (0x7U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000070 */
16637 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
16638 #define COMP_CSR_INMSEL_0          (0x1U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000010 */
16639 #define COMP_CSR_INMSEL_1          (0x2U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000020 */
16640 #define COMP_CSR_INMSEL_2          (0x4U << COMP_CSR_INMSEL_Pos)               /*!< 0x00000040 */
16641 
16642 #define COMP_CSR_INPSEL_Pos        (7U)
16643 #define COMP_CSR_INPSEL_Msk        (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
16644 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
16645 #define COMP_CSR_INPSEL_0          (0x1U << COMP_CSR_INPSEL_Pos)               /*!< 0x00000080 */
16646 
16647 #define COMP_CSR_WINMODE_Pos       (9U)
16648 #define COMP_CSR_WINMODE_Msk       (0x1U << COMP_CSR_WINMODE_Pos)              /*!< 0x00000200 */
16649 #define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
16650 
16651 #define COMP_CSR_POLARITY_Pos      (15U)
16652 #define COMP_CSR_POLARITY_Msk      (0x1U << COMP_CSR_POLARITY_Pos)             /*!< 0x00008000 */
16653 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
16654 
16655 #define COMP_CSR_HYST_Pos          (16U)
16656 #define COMP_CSR_HYST_Msk          (0x3U << COMP_CSR_HYST_Pos)                 /*!< 0x00030000 */
16657 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
16658 #define COMP_CSR_HYST_0            (0x1U << COMP_CSR_HYST_Pos)                 /*!< 0x00010000 */
16659 #define COMP_CSR_HYST_1            (0x2U << COMP_CSR_HYST_Pos)                 /*!< 0x00020000 */
16660 
16661 #define COMP_CSR_BLANKING_Pos      (18U)
16662 #define COMP_CSR_BLANKING_Msk      (0x7U << COMP_CSR_BLANKING_Pos)             /*!< 0x001C0000 */
16663 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
16664 #define COMP_CSR_BLANKING_0        (0x1U << COMP_CSR_BLANKING_Pos)             /*!< 0x00040000 */
16665 #define COMP_CSR_BLANKING_1        (0x2U << COMP_CSR_BLANKING_Pos)             /*!< 0x00080000 */
16666 #define COMP_CSR_BLANKING_2        (0x4U << COMP_CSR_BLANKING_Pos)             /*!< 0x00100000 */
16667 
16668 #define COMP_CSR_BRGEN_Pos         (22U)
16669 #define COMP_CSR_BRGEN_Msk         (0x1U << COMP_CSR_BRGEN_Pos)                /*!< 0x00400000 */
16670 #define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
16671 #define COMP_CSR_SCALEN_Pos        (23U)
16672 #define COMP_CSR_SCALEN_Msk        (0x1U << COMP_CSR_SCALEN_Pos)               /*!< 0x00800000 */
16673 #define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
16674 
16675 #define COMP_CSR_VALUE_Pos         (30U)
16676 #define COMP_CSR_VALUE_Msk         (0x1U << COMP_CSR_VALUE_Pos)                /*!< 0x40000000 */
16677 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
16678 
16679 #define COMP_CSR_LOCK_Pos          (31U)
16680 #define COMP_CSR_LOCK_Msk          (0x1U << COMP_CSR_LOCK_Pos)                 /*!< 0x80000000 */
16681 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
16682 
16683 /******************************************************************************/
16684 /*                                                                            */
16685 /*                         Operational Amplifier (OPAMP)                      */
16686 /*                                                                            */
16687 /******************************************************************************/
16688 /*********************  Bit definition for OPAMPx_CSR register  ***************/
16689 #define OPAMP_CSR_OPAMPxEN_Pos           (0U)
16690 #define OPAMP_CSR_OPAMPxEN_Msk           (0x1U << OPAMP_CSR_OPAMPxEN_Pos)      /*!< 0x00000001 */
16691 #define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
16692 #define OPAMP_CSR_OPALPM_Pos             (1U)
16693 #define OPAMP_CSR_OPALPM_Msk             (0x1U << OPAMP_CSR_OPALPM_Pos)        /*!< 0x00000002 */
16694 #define OPAMP_CSR_OPALPM                 OPAMP_CSR_OPALPM_Msk                  /*!< Operational amplifier Low Power Mode */
16695 
16696 #define OPAMP_CSR_OPAMODE_Pos            (2U)
16697 #define OPAMP_CSR_OPAMODE_Msk            (0x3U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x0000000C */
16698 #define OPAMP_CSR_OPAMODE                OPAMP_CSR_OPAMODE_Msk                 /*!< Operational amplifier PGA mode */
16699 #define OPAMP_CSR_OPAMODE_0              (0x1U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000004 */
16700 #define OPAMP_CSR_OPAMODE_1              (0x2U << OPAMP_CSR_OPAMODE_Pos)       /*!< 0x00000008 */
16701 
16702 #define OPAMP_CSR_PGGAIN_Pos             (4U)
16703 #define OPAMP_CSR_PGGAIN_Msk             (0x3U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000030 */
16704 #define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
16705 #define OPAMP_CSR_PGGAIN_0               (0x1U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000010 */
16706 #define OPAMP_CSR_PGGAIN_1               (0x2U << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00000020 */
16707 
16708 #define OPAMP_CSR_VMSEL_Pos              (8U)
16709 #define OPAMP_CSR_VMSEL_Msk              (0x3U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000300 */
16710 #define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
16711 #define OPAMP_CSR_VMSEL_0                (0x1U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000100 */
16712 #define OPAMP_CSR_VMSEL_1                (0x2U << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000200 */
16713 
16714 #define OPAMP_CSR_VPSEL_Pos              (10U)
16715 #define OPAMP_CSR_VPSEL_Msk              (0x1U << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000400 */
16716 #define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
16717 #define OPAMP_CSR_CALON_Pos              (12U)
16718 #define OPAMP_CSR_CALON_Msk              (0x1U << OPAMP_CSR_CALON_Pos)         /*!< 0x00001000 */
16719 #define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
16720 #define OPAMP_CSR_CALSEL_Pos             (13U)
16721 #define OPAMP_CSR_CALSEL_Msk             (0x1U << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
16722 #define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
16723 #define OPAMP_CSR_USERTRIM_Pos           (14U)
16724 #define OPAMP_CSR_USERTRIM_Msk           (0x1U << OPAMP_CSR_USERTRIM_Pos)      /*!< 0x00004000 */
16725 #define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
16726 #define OPAMP_CSR_CALOUT_Pos             (15U)
16727 #define OPAMP_CSR_CALOUT_Msk             (0x1U << OPAMP_CSR_CALOUT_Pos)        /*!< 0x00008000 */
16728 #define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier1 calibration output */
16729 
16730 /*********************  Bit definition for OPAMP1_CSR register  ***************/
16731 #define OPAMP1_CSR_OPAEN_Pos              (0U)
16732 #define OPAMP1_CSR_OPAEN_Msk              (0x1U << OPAMP1_CSR_OPAEN_Pos)       /*!< 0x00000001 */
16733 #define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
16734 #define OPAMP1_CSR_OPALPM_Pos             (1U)
16735 #define OPAMP1_CSR_OPALPM_Msk             (0x1U << OPAMP1_CSR_OPALPM_Pos)      /*!< 0x00000002 */
16736 #define OPAMP1_CSR_OPALPM                 OPAMP1_CSR_OPALPM_Msk                /*!< Operational amplifier1 Low Power Mode */
16737 
16738 #define OPAMP1_CSR_OPAMODE_Pos            (2U)
16739 #define OPAMP1_CSR_OPAMODE_Msk            (0x3U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
16740 #define OPAMP1_CSR_OPAMODE                OPAMP1_CSR_OPAMODE_Msk               /*!< Operational amplifier1 PGA mode */
16741 #define OPAMP1_CSR_OPAMODE_0              (0x1U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
16742 #define OPAMP1_CSR_OPAMODE_1              (0x2U << OPAMP1_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
16743 
16744 #define OPAMP1_CSR_PGAGAIN_Pos            (4U)
16745 #define OPAMP1_CSR_PGAGAIN_Msk            (0x3U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
16746 #define OPAMP1_CSR_PGAGAIN                OPAMP1_CSR_PGAGAIN_Msk               /*!< Operational amplifier1 Programmable amplifier gain value */
16747 #define OPAMP1_CSR_PGAGAIN_0              (0x1U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
16748 #define OPAMP1_CSR_PGAGAIN_1              (0x2U << OPAMP1_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
16749 
16750 #define OPAMP1_CSR_VMSEL_Pos              (8U)
16751 #define OPAMP1_CSR_VMSEL_Msk              (0x3U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000300 */
16752 #define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
16753 #define OPAMP1_CSR_VMSEL_0                (0x1U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000100 */
16754 #define OPAMP1_CSR_VMSEL_1                (0x2U << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000200 */
16755 
16756 #define OPAMP1_CSR_VPSEL_Pos              (10U)
16757 #define OPAMP1_CSR_VPSEL_Msk              (0x1U << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000400 */
16758 #define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
16759 #define OPAMP1_CSR_CALON_Pos              (12U)
16760 #define OPAMP1_CSR_CALON_Msk              (0x1U << OPAMP1_CSR_CALON_Pos)       /*!< 0x00001000 */
16761 #define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
16762 #define OPAMP1_CSR_CALSEL_Pos             (13U)
16763 #define OPAMP1_CSR_CALSEL_Msk             (0x1U << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
16764 #define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
16765 #define OPAMP1_CSR_USERTRIM_Pos           (14U)
16766 #define OPAMP1_CSR_USERTRIM_Msk           (0x1U << OPAMP1_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
16767 #define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
16768 #define OPAMP1_CSR_CALOUT_Pos             (15U)
16769 #define OPAMP1_CSR_CALOUT_Msk             (0x1U << OPAMP1_CSR_CALOUT_Pos)      /*!< 0x00008000 */
16770 #define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
16771 
16772 #define OPAMP1_CSR_OPARANGE_Pos           (31U)
16773 #define OPAMP1_CSR_OPARANGE_Msk           (0x1U << OPAMP1_CSR_OPARANGE_Pos)    /*!< 0x80000000 */
16774 #define OPAMP1_CSR_OPARANGE               OPAMP1_CSR_OPARANGE_Msk              /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
16775 
16776 /*********************  Bit definition for OPAMP2_CSR register  ***************/
16777 #define OPAMP2_CSR_OPAEN_Pos              (0U)
16778 #define OPAMP2_CSR_OPAEN_Msk              (0x1U << OPAMP2_CSR_OPAEN_Pos)       /*!< 0x00000001 */
16779 #define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
16780 #define OPAMP2_CSR_OPALPM_Pos             (1U)
16781 #define OPAMP2_CSR_OPALPM_Msk             (0x1U << OPAMP2_CSR_OPALPM_Pos)      /*!< 0x00000002 */
16782 #define OPAMP2_CSR_OPALPM                 OPAMP2_CSR_OPALPM_Msk                /*!< Operational amplifier2 Low Power Mode */
16783 
16784 #define OPAMP2_CSR_OPAMODE_Pos            (2U)
16785 #define OPAMP2_CSR_OPAMODE_Msk            (0x3U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x0000000C */
16786 #define OPAMP2_CSR_OPAMODE                OPAMP2_CSR_OPAMODE_Msk               /*!< Operational amplifier2 PGA mode */
16787 #define OPAMP2_CSR_OPAMODE_0              (0x1U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000004 */
16788 #define OPAMP2_CSR_OPAMODE_1              (0x2U << OPAMP2_CSR_OPAMODE_Pos)     /*!< 0x00000008 */
16789 
16790 #define OPAMP2_CSR_PGAGAIN_Pos            (4U)
16791 #define OPAMP2_CSR_PGAGAIN_Msk            (0x3U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000030 */
16792 #define OPAMP2_CSR_PGAGAIN                OPAMP2_CSR_PGAGAIN_Msk               /*!< Operational amplifier2 Programmable amplifier gain value */
16793 #define OPAMP2_CSR_PGAGAIN_0              (0x1U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000010 */
16794 #define OPAMP2_CSR_PGAGAIN_1              (0x2U << OPAMP2_CSR_PGAGAIN_Pos)     /*!< 0x00000020 */
16795 
16796 #define OPAMP2_CSR_VMSEL_Pos              (8U)
16797 #define OPAMP2_CSR_VMSEL_Msk              (0x3U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000300 */
16798 #define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
16799 #define OPAMP2_CSR_VMSEL_0                (0x1U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000100 */
16800 #define OPAMP2_CSR_VMSEL_1                (0x2U << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000200 */
16801 
16802 #define OPAMP2_CSR_VPSEL_Pos              (10U)
16803 #define OPAMP2_CSR_VPSEL_Msk              (0x1U << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000400 */
16804 #define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
16805 #define OPAMP2_CSR_CALON_Pos              (12U)
16806 #define OPAMP2_CSR_CALON_Msk              (0x1U << OPAMP2_CSR_CALON_Pos)       /*!< 0x00001000 */
16807 #define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
16808 #define OPAMP2_CSR_CALSEL_Pos             (13U)
16809 #define OPAMP2_CSR_CALSEL_Msk             (0x1U << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
16810 #define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
16811 #define OPAMP2_CSR_USERTRIM_Pos           (14U)
16812 #define OPAMP2_CSR_USERTRIM_Msk           (0x1U << OPAMP2_CSR_USERTRIM_Pos)    /*!< 0x00004000 */
16813 #define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
16814 #define OPAMP2_CSR_CALOUT_Pos             (15U)
16815 #define OPAMP2_CSR_CALOUT_Msk             (0x1U << OPAMP2_CSR_CALOUT_Pos)      /*!< 0x00008000 */
16816 #define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
16817 
16818 /*******************  Bit definition for OPAMP_OTR register  ******************/
16819 #define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
16820 #define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETN_Pos)  /*!< 0x0000001F */
16821 #define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
16822 #define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
16823 #define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP_OTR_TRIMOFFSETP_Pos)  /*!< 0x00001F00 */
16824 #define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
16825 
16826 /*******************  Bit definition for OPAMP1_OTR register  ******************/
16827 #define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
16828 #define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
16829 #define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
16830 #define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
16831 #define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
16832 #define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
16833 
16834 /*******************  Bit definition for OPAMP2_OTR register  ******************/
16835 #define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)
16836 #define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
16837 #define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
16838 #define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)
16839 #define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FU << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
16840 #define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
16841 
16842 /*******************  Bit definition for OPAMP_LPOTR register  ****************/
16843 #define OPAMP_LPOTR_TRIMLPOFFSETN_Pos    (0U)
16844 #define OPAMP_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
16845 #define OPAMP_LPOTR_TRIMLPOFFSETN        OPAMP_LPOTR_TRIMLPOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
16846 #define OPAMP_LPOTR_TRIMLPOFFSETP_Pos    (8U)
16847 #define OPAMP_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
16848 #define OPAMP_LPOTR_TRIMLPOFFSETP        OPAMP_LPOTR_TRIMLPOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
16849 
16850 /*******************  Bit definition for OPAMP1_LPOTR register  ****************/
16851 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Pos    (0U)
16852 #define OPAMP1_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
16853 #define OPAMP1_LPOTR_TRIMLPOFFSETN        OPAMP1_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
16854 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Pos    (8U)
16855 #define OPAMP1_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP1_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
16856 #define OPAMP1_LPOTR_TRIMLPOFFSETP        OPAMP1_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
16857 
16858 /*******************  Bit definition for OPAMP2_LPOTR register  ****************/
16859 #define OPAMP2_LPOTR_TRIMLPOFFSETN_Pos    (0U)
16860 #define OPAMP2_LPOTR_TRIMLPOFFSETN_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */
16861 #define OPAMP2_LPOTR_TRIMLPOFFSETN        OPAMP2_LPOTR_TRIMLPOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
16862 #define OPAMP2_LPOTR_TRIMLPOFFSETP_Pos    (8U)
16863 #define OPAMP2_LPOTR_TRIMLPOFFSETP_Msk    (0x1FU << OPAMP2_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */
16864 #define OPAMP2_LPOTR_TRIMLPOFFSETP        OPAMP2_LPOTR_TRIMLPOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
16865 
16866 /******************************************************************************/
16867 /*                                                                            */
16868 /*                          Touch Sensing Controller (TSC)                    */
16869 /*                                                                            */
16870 /******************************************************************************/
16871 /*******************  Bit definition for TSC_CR register  *********************/
16872 #define TSC_CR_TSCE_Pos          (0U)
16873 #define TSC_CR_TSCE_Msk          (0x1U << TSC_CR_TSCE_Pos)                     /*!< 0x00000001 */
16874 #define TSC_CR_TSCE              TSC_CR_TSCE_Msk                               /*!<Touch sensing controller enable */
16875 #define TSC_CR_START_Pos         (1U)
16876 #define TSC_CR_START_Msk         (0x1U << TSC_CR_START_Pos)                    /*!< 0x00000002 */
16877 #define TSC_CR_START             TSC_CR_START_Msk                              /*!<Start acquisition */
16878 #define TSC_CR_AM_Pos            (2U)
16879 #define TSC_CR_AM_Msk            (0x1U << TSC_CR_AM_Pos)                       /*!< 0x00000004 */
16880 #define TSC_CR_AM                TSC_CR_AM_Msk                                 /*!<Acquisition mode */
16881 #define TSC_CR_SYNCPOL_Pos       (3U)
16882 #define TSC_CR_SYNCPOL_Msk       (0x1U << TSC_CR_SYNCPOL_Pos)                  /*!< 0x00000008 */
16883 #define TSC_CR_SYNCPOL           TSC_CR_SYNCPOL_Msk                            /*!<Synchronization pin polarity */
16884 #define TSC_CR_IODEF_Pos         (4U)
16885 #define TSC_CR_IODEF_Msk         (0x1U << TSC_CR_IODEF_Pos)                    /*!< 0x00000010 */
16886 #define TSC_CR_IODEF             TSC_CR_IODEF_Msk                              /*!<IO default mode */
16887 
16888 #define TSC_CR_MCV_Pos           (5U)
16889 #define TSC_CR_MCV_Msk           (0x7U << TSC_CR_MCV_Pos)                      /*!< 0x000000E0 */
16890 #define TSC_CR_MCV               TSC_CR_MCV_Msk                                /*!<MCV[2:0] bits (Max Count Value) */
16891 #define TSC_CR_MCV_0             (0x1U << TSC_CR_MCV_Pos)                      /*!< 0x00000020 */
16892 #define TSC_CR_MCV_1             (0x2U << TSC_CR_MCV_Pos)                      /*!< 0x00000040 */
16893 #define TSC_CR_MCV_2             (0x4U << TSC_CR_MCV_Pos)                      /*!< 0x00000080 */
16894 
16895 #define TSC_CR_PGPSC_Pos         (12U)
16896 #define TSC_CR_PGPSC_Msk         (0x7U << TSC_CR_PGPSC_Pos)                    /*!< 0x00007000 */
16897 #define TSC_CR_PGPSC             TSC_CR_PGPSC_Msk                              /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
16898 #define TSC_CR_PGPSC_0           (0x1U << TSC_CR_PGPSC_Pos)                    /*!< 0x00001000 */
16899 #define TSC_CR_PGPSC_1           (0x2U << TSC_CR_PGPSC_Pos)                    /*!< 0x00002000 */
16900 #define TSC_CR_PGPSC_2           (0x4U << TSC_CR_PGPSC_Pos)                    /*!< 0x00004000 */
16901 
16902 #define TSC_CR_SSPSC_Pos         (15U)
16903 #define TSC_CR_SSPSC_Msk         (0x1U << TSC_CR_SSPSC_Pos)                    /*!< 0x00008000 */
16904 #define TSC_CR_SSPSC             TSC_CR_SSPSC_Msk                              /*!<Spread Spectrum Prescaler */
16905 #define TSC_CR_SSE_Pos           (16U)
16906 #define TSC_CR_SSE_Msk           (0x1U << TSC_CR_SSE_Pos)                      /*!< 0x00010000 */
16907 #define TSC_CR_SSE               TSC_CR_SSE_Msk                                /*!<Spread Spectrum Enable */
16908 
16909 #define TSC_CR_SSD_Pos           (17U)
16910 #define TSC_CR_SSD_Msk           (0x7FU << TSC_CR_SSD_Pos)                     /*!< 0x00FE0000 */
16911 #define TSC_CR_SSD               TSC_CR_SSD_Msk                                /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
16912 #define TSC_CR_SSD_0             (0x01U << TSC_CR_SSD_Pos)                     /*!< 0x00020000 */
16913 #define TSC_CR_SSD_1             (0x02U << TSC_CR_SSD_Pos)                     /*!< 0x00040000 */
16914 #define TSC_CR_SSD_2             (0x04U << TSC_CR_SSD_Pos)                     /*!< 0x00080000 */
16915 #define TSC_CR_SSD_3             (0x08U << TSC_CR_SSD_Pos)                     /*!< 0x00100000 */
16916 #define TSC_CR_SSD_4             (0x10U << TSC_CR_SSD_Pos)                     /*!< 0x00200000 */
16917 #define TSC_CR_SSD_5             (0x20U << TSC_CR_SSD_Pos)                     /*!< 0x00400000 */
16918 #define TSC_CR_SSD_6             (0x40U << TSC_CR_SSD_Pos)                     /*!< 0x00800000 */
16919 
16920 #define TSC_CR_CTPL_Pos          (24U)
16921 #define TSC_CR_CTPL_Msk          (0xFU << TSC_CR_CTPL_Pos)                     /*!< 0x0F000000 */
16922 #define TSC_CR_CTPL              TSC_CR_CTPL_Msk                               /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
16923 #define TSC_CR_CTPL_0            (0x1U << TSC_CR_CTPL_Pos)                     /*!< 0x01000000 */
16924 #define TSC_CR_CTPL_1            (0x2U << TSC_CR_CTPL_Pos)                     /*!< 0x02000000 */
16925 #define TSC_CR_CTPL_2            (0x4U << TSC_CR_CTPL_Pos)                     /*!< 0x04000000 */
16926 #define TSC_CR_CTPL_3            (0x8U << TSC_CR_CTPL_Pos)                     /*!< 0x08000000 */
16927 
16928 #define TSC_CR_CTPH_Pos          (28U)
16929 #define TSC_CR_CTPH_Msk          (0xFU << TSC_CR_CTPH_Pos)                     /*!< 0xF0000000 */
16930 #define TSC_CR_CTPH              TSC_CR_CTPH_Msk                               /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
16931 #define TSC_CR_CTPH_0            (0x1U << TSC_CR_CTPH_Pos)                     /*!< 0x10000000 */
16932 #define TSC_CR_CTPH_1            (0x2U << TSC_CR_CTPH_Pos)                     /*!< 0x20000000 */
16933 #define TSC_CR_CTPH_2            (0x4U << TSC_CR_CTPH_Pos)                     /*!< 0x40000000 */
16934 #define TSC_CR_CTPH_3            (0x8U << TSC_CR_CTPH_Pos)                     /*!< 0x80000000 */
16935 
16936 /*******************  Bit definition for TSC_IER register  ********************/
16937 #define TSC_IER_EOAIE_Pos        (0U)
16938 #define TSC_IER_EOAIE_Msk        (0x1U << TSC_IER_EOAIE_Pos)                   /*!< 0x00000001 */
16939 #define TSC_IER_EOAIE            TSC_IER_EOAIE_Msk                             /*!<End of acquisition interrupt enable */
16940 #define TSC_IER_MCEIE_Pos        (1U)
16941 #define TSC_IER_MCEIE_Msk        (0x1U << TSC_IER_MCEIE_Pos)                   /*!< 0x00000002 */
16942 #define TSC_IER_MCEIE            TSC_IER_MCEIE_Msk                             /*!<Max count error interrupt enable */
16943 
16944 /*******************  Bit definition for TSC_ICR register  ********************/
16945 #define TSC_ICR_EOAIC_Pos        (0U)
16946 #define TSC_ICR_EOAIC_Msk        (0x1U << TSC_ICR_EOAIC_Pos)                   /*!< 0x00000001 */
16947 #define TSC_ICR_EOAIC            TSC_ICR_EOAIC_Msk                             /*!<End of acquisition interrupt clear */
16948 #define TSC_ICR_MCEIC_Pos        (1U)
16949 #define TSC_ICR_MCEIC_Msk        (0x1U << TSC_ICR_MCEIC_Pos)                   /*!< 0x00000002 */
16950 #define TSC_ICR_MCEIC            TSC_ICR_MCEIC_Msk                             /*!<Max count error interrupt clear */
16951 
16952 /*******************  Bit definition for TSC_ISR register  ********************/
16953 #define TSC_ISR_EOAF_Pos         (0U)
16954 #define TSC_ISR_EOAF_Msk         (0x1U << TSC_ISR_EOAF_Pos)                    /*!< 0x00000001 */
16955 #define TSC_ISR_EOAF             TSC_ISR_EOAF_Msk                              /*!<End of acquisition flag */
16956 #define TSC_ISR_MCEF_Pos         (1U)
16957 #define TSC_ISR_MCEF_Msk         (0x1U << TSC_ISR_MCEF_Pos)                    /*!< 0x00000002 */
16958 #define TSC_ISR_MCEF             TSC_ISR_MCEF_Msk                              /*!<Max count error flag */
16959 
16960 /*******************  Bit definition for TSC_IOHCR register  ******************/
16961 #define TSC_IOHCR_G1_IO1_Pos     (0U)
16962 #define TSC_IOHCR_G1_IO1_Msk     (0x1U << TSC_IOHCR_G1_IO1_Pos)                /*!< 0x00000001 */
16963 #define TSC_IOHCR_G1_IO1         TSC_IOHCR_G1_IO1_Msk                          /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
16964 #define TSC_IOHCR_G1_IO2_Pos     (1U)
16965 #define TSC_IOHCR_G1_IO2_Msk     (0x1U << TSC_IOHCR_G1_IO2_Pos)                /*!< 0x00000002 */
16966 #define TSC_IOHCR_G1_IO2         TSC_IOHCR_G1_IO2_Msk                          /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
16967 #define TSC_IOHCR_G1_IO3_Pos     (2U)
16968 #define TSC_IOHCR_G1_IO3_Msk     (0x1U << TSC_IOHCR_G1_IO3_Pos)                /*!< 0x00000004 */
16969 #define TSC_IOHCR_G1_IO3         TSC_IOHCR_G1_IO3_Msk                          /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
16970 #define TSC_IOHCR_G1_IO4_Pos     (3U)
16971 #define TSC_IOHCR_G1_IO4_Msk     (0x1U << TSC_IOHCR_G1_IO4_Pos)                /*!< 0x00000008 */
16972 #define TSC_IOHCR_G1_IO4         TSC_IOHCR_G1_IO4_Msk                          /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
16973 #define TSC_IOHCR_G2_IO1_Pos     (4U)
16974 #define TSC_IOHCR_G2_IO1_Msk     (0x1U << TSC_IOHCR_G2_IO1_Pos)                /*!< 0x00000010 */
16975 #define TSC_IOHCR_G2_IO1         TSC_IOHCR_G2_IO1_Msk                          /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
16976 #define TSC_IOHCR_G2_IO2_Pos     (5U)
16977 #define TSC_IOHCR_G2_IO2_Msk     (0x1U << TSC_IOHCR_G2_IO2_Pos)                /*!< 0x00000020 */
16978 #define TSC_IOHCR_G2_IO2         TSC_IOHCR_G2_IO2_Msk                          /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
16979 #define TSC_IOHCR_G2_IO3_Pos     (6U)
16980 #define TSC_IOHCR_G2_IO3_Msk     (0x1U << TSC_IOHCR_G2_IO3_Pos)                /*!< 0x00000040 */
16981 #define TSC_IOHCR_G2_IO3         TSC_IOHCR_G2_IO3_Msk                          /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
16982 #define TSC_IOHCR_G2_IO4_Pos     (7U)
16983 #define TSC_IOHCR_G2_IO4_Msk     (0x1U << TSC_IOHCR_G2_IO4_Pos)                /*!< 0x00000080 */
16984 #define TSC_IOHCR_G2_IO4         TSC_IOHCR_G2_IO4_Msk                          /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
16985 #define TSC_IOHCR_G3_IO1_Pos     (8U)
16986 #define TSC_IOHCR_G3_IO1_Msk     (0x1U << TSC_IOHCR_G3_IO1_Pos)                /*!< 0x00000100 */
16987 #define TSC_IOHCR_G3_IO1         TSC_IOHCR_G3_IO1_Msk                          /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
16988 #define TSC_IOHCR_G3_IO2_Pos     (9U)
16989 #define TSC_IOHCR_G3_IO2_Msk     (0x1U << TSC_IOHCR_G3_IO2_Pos)                /*!< 0x00000200 */
16990 #define TSC_IOHCR_G3_IO2         TSC_IOHCR_G3_IO2_Msk                          /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
16991 #define TSC_IOHCR_G3_IO3_Pos     (10U)
16992 #define TSC_IOHCR_G3_IO3_Msk     (0x1U << TSC_IOHCR_G3_IO3_Pos)                /*!< 0x00000400 */
16993 #define TSC_IOHCR_G3_IO3         TSC_IOHCR_G3_IO3_Msk                          /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
16994 #define TSC_IOHCR_G3_IO4_Pos     (11U)
16995 #define TSC_IOHCR_G3_IO4_Msk     (0x1U << TSC_IOHCR_G3_IO4_Pos)                /*!< 0x00000800 */
16996 #define TSC_IOHCR_G3_IO4         TSC_IOHCR_G3_IO4_Msk                          /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
16997 #define TSC_IOHCR_G4_IO1_Pos     (12U)
16998 #define TSC_IOHCR_G4_IO1_Msk     (0x1U << TSC_IOHCR_G4_IO1_Pos)                /*!< 0x00001000 */
16999 #define TSC_IOHCR_G4_IO1         TSC_IOHCR_G4_IO1_Msk                          /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
17000 #define TSC_IOHCR_G4_IO2_Pos     (13U)
17001 #define TSC_IOHCR_G4_IO2_Msk     (0x1U << TSC_IOHCR_G4_IO2_Pos)                /*!< 0x00002000 */
17002 #define TSC_IOHCR_G4_IO2         TSC_IOHCR_G4_IO2_Msk                          /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
17003 #define TSC_IOHCR_G4_IO3_Pos     (14U)
17004 #define TSC_IOHCR_G4_IO3_Msk     (0x1U << TSC_IOHCR_G4_IO3_Pos)                /*!< 0x00004000 */
17005 #define TSC_IOHCR_G4_IO3         TSC_IOHCR_G4_IO3_Msk                          /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
17006 #define TSC_IOHCR_G4_IO4_Pos     (15U)
17007 #define TSC_IOHCR_G4_IO4_Msk     (0x1U << TSC_IOHCR_G4_IO4_Pos)                /*!< 0x00008000 */
17008 #define TSC_IOHCR_G4_IO4         TSC_IOHCR_G4_IO4_Msk                          /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
17009 #define TSC_IOHCR_G5_IO1_Pos     (16U)
17010 #define TSC_IOHCR_G5_IO1_Msk     (0x1U << TSC_IOHCR_G5_IO1_Pos)                /*!< 0x00010000 */
17011 #define TSC_IOHCR_G5_IO1         TSC_IOHCR_G5_IO1_Msk                          /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
17012 #define TSC_IOHCR_G5_IO2_Pos     (17U)
17013 #define TSC_IOHCR_G5_IO2_Msk     (0x1U << TSC_IOHCR_G5_IO2_Pos)                /*!< 0x00020000 */
17014 #define TSC_IOHCR_G5_IO2         TSC_IOHCR_G5_IO2_Msk                          /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
17015 #define TSC_IOHCR_G5_IO3_Pos     (18U)
17016 #define TSC_IOHCR_G5_IO3_Msk     (0x1U << TSC_IOHCR_G5_IO3_Pos)                /*!< 0x00040000 */
17017 #define TSC_IOHCR_G5_IO3         TSC_IOHCR_G5_IO3_Msk                          /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
17018 #define TSC_IOHCR_G5_IO4_Pos     (19U)
17019 #define TSC_IOHCR_G5_IO4_Msk     (0x1U << TSC_IOHCR_G5_IO4_Pos)                /*!< 0x00080000 */
17020 #define TSC_IOHCR_G5_IO4         TSC_IOHCR_G5_IO4_Msk                          /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
17021 #define TSC_IOHCR_G6_IO1_Pos     (20U)
17022 #define TSC_IOHCR_G6_IO1_Msk     (0x1U << TSC_IOHCR_G6_IO1_Pos)                /*!< 0x00100000 */
17023 #define TSC_IOHCR_G6_IO1         TSC_IOHCR_G6_IO1_Msk                          /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
17024 #define TSC_IOHCR_G6_IO2_Pos     (21U)
17025 #define TSC_IOHCR_G6_IO2_Msk     (0x1U << TSC_IOHCR_G6_IO2_Pos)                /*!< 0x00200000 */
17026 #define TSC_IOHCR_G6_IO2         TSC_IOHCR_G6_IO2_Msk                          /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
17027 #define TSC_IOHCR_G6_IO3_Pos     (22U)
17028 #define TSC_IOHCR_G6_IO3_Msk     (0x1U << TSC_IOHCR_G6_IO3_Pos)                /*!< 0x00400000 */
17029 #define TSC_IOHCR_G6_IO3         TSC_IOHCR_G6_IO3_Msk                          /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
17030 #define TSC_IOHCR_G6_IO4_Pos     (23U)
17031 #define TSC_IOHCR_G6_IO4_Msk     (0x1U << TSC_IOHCR_G6_IO4_Pos)                /*!< 0x00800000 */
17032 #define TSC_IOHCR_G6_IO4         TSC_IOHCR_G6_IO4_Msk                          /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
17033 #define TSC_IOHCR_G7_IO1_Pos     (24U)
17034 #define TSC_IOHCR_G7_IO1_Msk     (0x1U << TSC_IOHCR_G7_IO1_Pos)                /*!< 0x01000000 */
17035 #define TSC_IOHCR_G7_IO1         TSC_IOHCR_G7_IO1_Msk                          /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
17036 #define TSC_IOHCR_G7_IO2_Pos     (25U)
17037 #define TSC_IOHCR_G7_IO2_Msk     (0x1U << TSC_IOHCR_G7_IO2_Pos)                /*!< 0x02000000 */
17038 #define TSC_IOHCR_G7_IO2         TSC_IOHCR_G7_IO2_Msk                          /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
17039 #define TSC_IOHCR_G7_IO3_Pos     (26U)
17040 #define TSC_IOHCR_G7_IO3_Msk     (0x1U << TSC_IOHCR_G7_IO3_Pos)                /*!< 0x04000000 */
17041 #define TSC_IOHCR_G7_IO3         TSC_IOHCR_G7_IO3_Msk                          /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
17042 #define TSC_IOHCR_G7_IO4_Pos     (27U)
17043 #define TSC_IOHCR_G7_IO4_Msk     (0x1U << TSC_IOHCR_G7_IO4_Pos)                /*!< 0x08000000 */
17044 #define TSC_IOHCR_G7_IO4         TSC_IOHCR_G7_IO4_Msk                          /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
17045 #define TSC_IOHCR_G8_IO1_Pos     (28U)
17046 #define TSC_IOHCR_G8_IO1_Msk     (0x1U << TSC_IOHCR_G8_IO1_Pos)                /*!< 0x10000000 */
17047 #define TSC_IOHCR_G8_IO1         TSC_IOHCR_G8_IO1_Msk                          /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
17048 #define TSC_IOHCR_G8_IO2_Pos     (29U)
17049 #define TSC_IOHCR_G8_IO2_Msk     (0x1U << TSC_IOHCR_G8_IO2_Pos)                /*!< 0x20000000 */
17050 #define TSC_IOHCR_G8_IO2         TSC_IOHCR_G8_IO2_Msk                          /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
17051 #define TSC_IOHCR_G8_IO3_Pos     (30U)
17052 #define TSC_IOHCR_G8_IO3_Msk     (0x1U << TSC_IOHCR_G8_IO3_Pos)                /*!< 0x40000000 */
17053 #define TSC_IOHCR_G8_IO3         TSC_IOHCR_G8_IO3_Msk                          /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
17054 #define TSC_IOHCR_G8_IO4_Pos     (31U)
17055 #define TSC_IOHCR_G8_IO4_Msk     (0x1U << TSC_IOHCR_G8_IO4_Pos)                /*!< 0x80000000 */
17056 #define TSC_IOHCR_G8_IO4         TSC_IOHCR_G8_IO4_Msk                          /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
17057 
17058 /*******************  Bit definition for TSC_IOASCR register  *****************/
17059 #define TSC_IOASCR_G1_IO1_Pos    (0U)
17060 #define TSC_IOASCR_G1_IO1_Msk    (0x1U << TSC_IOASCR_G1_IO1_Pos)               /*!< 0x00000001 */
17061 #define TSC_IOASCR_G1_IO1        TSC_IOASCR_G1_IO1_Msk                         /*!<GROUP1_IO1 analog switch enable */
17062 #define TSC_IOASCR_G1_IO2_Pos    (1U)
17063 #define TSC_IOASCR_G1_IO2_Msk    (0x1U << TSC_IOASCR_G1_IO2_Pos)               /*!< 0x00000002 */
17064 #define TSC_IOASCR_G1_IO2        TSC_IOASCR_G1_IO2_Msk                         /*!<GROUP1_IO2 analog switch enable */
17065 #define TSC_IOASCR_G1_IO3_Pos    (2U)
17066 #define TSC_IOASCR_G1_IO3_Msk    (0x1U << TSC_IOASCR_G1_IO3_Pos)               /*!< 0x00000004 */
17067 #define TSC_IOASCR_G1_IO3        TSC_IOASCR_G1_IO3_Msk                         /*!<GROUP1_IO3 analog switch enable */
17068 #define TSC_IOASCR_G1_IO4_Pos    (3U)
17069 #define TSC_IOASCR_G1_IO4_Msk    (0x1U << TSC_IOASCR_G1_IO4_Pos)               /*!< 0x00000008 */
17070 #define TSC_IOASCR_G1_IO4        TSC_IOASCR_G1_IO4_Msk                         /*!<GROUP1_IO4 analog switch enable */
17071 #define TSC_IOASCR_G2_IO1_Pos    (4U)
17072 #define TSC_IOASCR_G2_IO1_Msk    (0x1U << TSC_IOASCR_G2_IO1_Pos)               /*!< 0x00000010 */
17073 #define TSC_IOASCR_G2_IO1        TSC_IOASCR_G2_IO1_Msk                         /*!<GROUP2_IO1 analog switch enable */
17074 #define TSC_IOASCR_G2_IO2_Pos    (5U)
17075 #define TSC_IOASCR_G2_IO2_Msk    (0x1U << TSC_IOASCR_G2_IO2_Pos)               /*!< 0x00000020 */
17076 #define TSC_IOASCR_G2_IO2        TSC_IOASCR_G2_IO2_Msk                         /*!<GROUP2_IO2 analog switch enable */
17077 #define TSC_IOASCR_G2_IO3_Pos    (6U)
17078 #define TSC_IOASCR_G2_IO3_Msk    (0x1U << TSC_IOASCR_G2_IO3_Pos)               /*!< 0x00000040 */
17079 #define TSC_IOASCR_G2_IO3        TSC_IOASCR_G2_IO3_Msk                         /*!<GROUP2_IO3 analog switch enable */
17080 #define TSC_IOASCR_G2_IO4_Pos    (7U)
17081 #define TSC_IOASCR_G2_IO4_Msk    (0x1U << TSC_IOASCR_G2_IO4_Pos)               /*!< 0x00000080 */
17082 #define TSC_IOASCR_G2_IO4        TSC_IOASCR_G2_IO4_Msk                         /*!<GROUP2_IO4 analog switch enable */
17083 #define TSC_IOASCR_G3_IO1_Pos    (8U)
17084 #define TSC_IOASCR_G3_IO1_Msk    (0x1U << TSC_IOASCR_G3_IO1_Pos)               /*!< 0x00000100 */
17085 #define TSC_IOASCR_G3_IO1        TSC_IOASCR_G3_IO1_Msk                         /*!<GROUP3_IO1 analog switch enable */
17086 #define TSC_IOASCR_G3_IO2_Pos    (9U)
17087 #define TSC_IOASCR_G3_IO2_Msk    (0x1U << TSC_IOASCR_G3_IO2_Pos)               /*!< 0x00000200 */
17088 #define TSC_IOASCR_G3_IO2        TSC_IOASCR_G3_IO2_Msk                         /*!<GROUP3_IO2 analog switch enable */
17089 #define TSC_IOASCR_G3_IO3_Pos    (10U)
17090 #define TSC_IOASCR_G3_IO3_Msk    (0x1U << TSC_IOASCR_G3_IO3_Pos)               /*!< 0x00000400 */
17091 #define TSC_IOASCR_G3_IO3        TSC_IOASCR_G3_IO3_Msk                         /*!<GROUP3_IO3 analog switch enable */
17092 #define TSC_IOASCR_G3_IO4_Pos    (11U)
17093 #define TSC_IOASCR_G3_IO4_Msk    (0x1U << TSC_IOASCR_G3_IO4_Pos)               /*!< 0x00000800 */
17094 #define TSC_IOASCR_G3_IO4        TSC_IOASCR_G3_IO4_Msk                         /*!<GROUP3_IO4 analog switch enable */
17095 #define TSC_IOASCR_G4_IO1_Pos    (12U)
17096 #define TSC_IOASCR_G4_IO1_Msk    (0x1U << TSC_IOASCR_G4_IO1_Pos)               /*!< 0x00001000 */
17097 #define TSC_IOASCR_G4_IO1        TSC_IOASCR_G4_IO1_Msk                         /*!<GROUP4_IO1 analog switch enable */
17098 #define TSC_IOASCR_G4_IO2_Pos    (13U)
17099 #define TSC_IOASCR_G4_IO2_Msk    (0x1U << TSC_IOASCR_G4_IO2_Pos)               /*!< 0x00002000 */
17100 #define TSC_IOASCR_G4_IO2        TSC_IOASCR_G4_IO2_Msk                         /*!<GROUP4_IO2 analog switch enable */
17101 #define TSC_IOASCR_G4_IO3_Pos    (14U)
17102 #define TSC_IOASCR_G4_IO3_Msk    (0x1U << TSC_IOASCR_G4_IO3_Pos)               /*!< 0x00004000 */
17103 #define TSC_IOASCR_G4_IO3        TSC_IOASCR_G4_IO3_Msk                         /*!<GROUP4_IO3 analog switch enable */
17104 #define TSC_IOASCR_G4_IO4_Pos    (15U)
17105 #define TSC_IOASCR_G4_IO4_Msk    (0x1U << TSC_IOASCR_G4_IO4_Pos)               /*!< 0x00008000 */
17106 #define TSC_IOASCR_G4_IO4        TSC_IOASCR_G4_IO4_Msk                         /*!<GROUP4_IO4 analog switch enable */
17107 #define TSC_IOASCR_G5_IO1_Pos    (16U)
17108 #define TSC_IOASCR_G5_IO1_Msk    (0x1U << TSC_IOASCR_G5_IO1_Pos)               /*!< 0x00010000 */
17109 #define TSC_IOASCR_G5_IO1        TSC_IOASCR_G5_IO1_Msk                         /*!<GROUP5_IO1 analog switch enable */
17110 #define TSC_IOASCR_G5_IO2_Pos    (17U)
17111 #define TSC_IOASCR_G5_IO2_Msk    (0x1U << TSC_IOASCR_G5_IO2_Pos)               /*!< 0x00020000 */
17112 #define TSC_IOASCR_G5_IO2        TSC_IOASCR_G5_IO2_Msk                         /*!<GROUP5_IO2 analog switch enable */
17113 #define TSC_IOASCR_G5_IO3_Pos    (18U)
17114 #define TSC_IOASCR_G5_IO3_Msk    (0x1U << TSC_IOASCR_G5_IO3_Pos)               /*!< 0x00040000 */
17115 #define TSC_IOASCR_G5_IO3        TSC_IOASCR_G5_IO3_Msk                         /*!<GROUP5_IO3 analog switch enable */
17116 #define TSC_IOASCR_G5_IO4_Pos    (19U)
17117 #define TSC_IOASCR_G5_IO4_Msk    (0x1U << TSC_IOASCR_G5_IO4_Pos)               /*!< 0x00080000 */
17118 #define TSC_IOASCR_G5_IO4        TSC_IOASCR_G5_IO4_Msk                         /*!<GROUP5_IO4 analog switch enable */
17119 #define TSC_IOASCR_G6_IO1_Pos    (20U)
17120 #define TSC_IOASCR_G6_IO1_Msk    (0x1U << TSC_IOASCR_G6_IO1_Pos)               /*!< 0x00100000 */
17121 #define TSC_IOASCR_G6_IO1        TSC_IOASCR_G6_IO1_Msk                         /*!<GROUP6_IO1 analog switch enable */
17122 #define TSC_IOASCR_G6_IO2_Pos    (21U)
17123 #define TSC_IOASCR_G6_IO2_Msk    (0x1U << TSC_IOASCR_G6_IO2_Pos)               /*!< 0x00200000 */
17124 #define TSC_IOASCR_G6_IO2        TSC_IOASCR_G6_IO2_Msk                         /*!<GROUP6_IO2 analog switch enable */
17125 #define TSC_IOASCR_G6_IO3_Pos    (22U)
17126 #define TSC_IOASCR_G6_IO3_Msk    (0x1U << TSC_IOASCR_G6_IO3_Pos)               /*!< 0x00400000 */
17127 #define TSC_IOASCR_G6_IO3        TSC_IOASCR_G6_IO3_Msk                         /*!<GROUP6_IO3 analog switch enable */
17128 #define TSC_IOASCR_G6_IO4_Pos    (23U)
17129 #define TSC_IOASCR_G6_IO4_Msk    (0x1U << TSC_IOASCR_G6_IO4_Pos)               /*!< 0x00800000 */
17130 #define TSC_IOASCR_G6_IO4        TSC_IOASCR_G6_IO4_Msk                         /*!<GROUP6_IO4 analog switch enable */
17131 #define TSC_IOASCR_G7_IO1_Pos    (24U)
17132 #define TSC_IOASCR_G7_IO1_Msk    (0x1U << TSC_IOASCR_G7_IO1_Pos)               /*!< 0x01000000 */
17133 #define TSC_IOASCR_G7_IO1        TSC_IOASCR_G7_IO1_Msk                         /*!<GROUP7_IO1 analog switch enable */
17134 #define TSC_IOASCR_G7_IO2_Pos    (25U)
17135 #define TSC_IOASCR_G7_IO2_Msk    (0x1U << TSC_IOASCR_G7_IO2_Pos)               /*!< 0x02000000 */
17136 #define TSC_IOASCR_G7_IO2        TSC_IOASCR_G7_IO2_Msk                         /*!<GROUP7_IO2 analog switch enable */
17137 #define TSC_IOASCR_G7_IO3_Pos    (26U)
17138 #define TSC_IOASCR_G7_IO3_Msk    (0x1U << TSC_IOASCR_G7_IO3_Pos)               /*!< 0x04000000 */
17139 #define TSC_IOASCR_G7_IO3        TSC_IOASCR_G7_IO3_Msk                         /*!<GROUP7_IO3 analog switch enable */
17140 #define TSC_IOASCR_G7_IO4_Pos    (27U)
17141 #define TSC_IOASCR_G7_IO4_Msk    (0x1U << TSC_IOASCR_G7_IO4_Pos)               /*!< 0x08000000 */
17142 #define TSC_IOASCR_G7_IO4        TSC_IOASCR_G7_IO4_Msk                         /*!<GROUP7_IO4 analog switch enable */
17143 #define TSC_IOASCR_G8_IO1_Pos    (28U)
17144 #define TSC_IOASCR_G8_IO1_Msk    (0x1U << TSC_IOASCR_G8_IO1_Pos)               /*!< 0x10000000 */
17145 #define TSC_IOASCR_G8_IO1        TSC_IOASCR_G8_IO1_Msk                         /*!<GROUP8_IO1 analog switch enable */
17146 #define TSC_IOASCR_G8_IO2_Pos    (29U)
17147 #define TSC_IOASCR_G8_IO2_Msk    (0x1U << TSC_IOASCR_G8_IO2_Pos)               /*!< 0x20000000 */
17148 #define TSC_IOASCR_G8_IO2        TSC_IOASCR_G8_IO2_Msk                         /*!<GROUP8_IO2 analog switch enable */
17149 #define TSC_IOASCR_G8_IO3_Pos    (30U)
17150 #define TSC_IOASCR_G8_IO3_Msk    (0x1U << TSC_IOASCR_G8_IO3_Pos)               /*!< 0x40000000 */
17151 #define TSC_IOASCR_G8_IO3        TSC_IOASCR_G8_IO3_Msk                         /*!<GROUP8_IO3 analog switch enable */
17152 #define TSC_IOASCR_G8_IO4_Pos    (31U)
17153 #define TSC_IOASCR_G8_IO4_Msk    (0x1U << TSC_IOASCR_G8_IO4_Pos)               /*!< 0x80000000 */
17154 #define TSC_IOASCR_G8_IO4        TSC_IOASCR_G8_IO4_Msk                         /*!<GROUP8_IO4 analog switch enable */
17155 
17156 /*******************  Bit definition for TSC_IOSCR register  ******************/
17157 #define TSC_IOSCR_G1_IO1_Pos     (0U)
17158 #define TSC_IOSCR_G1_IO1_Msk     (0x1U << TSC_IOSCR_G1_IO1_Pos)                /*!< 0x00000001 */
17159 #define TSC_IOSCR_G1_IO1         TSC_IOSCR_G1_IO1_Msk                          /*!<GROUP1_IO1 sampling mode */
17160 #define TSC_IOSCR_G1_IO2_Pos     (1U)
17161 #define TSC_IOSCR_G1_IO2_Msk     (0x1U << TSC_IOSCR_G1_IO2_Pos)                /*!< 0x00000002 */
17162 #define TSC_IOSCR_G1_IO2         TSC_IOSCR_G1_IO2_Msk                          /*!<GROUP1_IO2 sampling mode */
17163 #define TSC_IOSCR_G1_IO3_Pos     (2U)
17164 #define TSC_IOSCR_G1_IO3_Msk     (0x1U << TSC_IOSCR_G1_IO3_Pos)                /*!< 0x00000004 */
17165 #define TSC_IOSCR_G1_IO3         TSC_IOSCR_G1_IO3_Msk                          /*!<GROUP1_IO3 sampling mode */
17166 #define TSC_IOSCR_G1_IO4_Pos     (3U)
17167 #define TSC_IOSCR_G1_IO4_Msk     (0x1U << TSC_IOSCR_G1_IO4_Pos)                /*!< 0x00000008 */
17168 #define TSC_IOSCR_G1_IO4         TSC_IOSCR_G1_IO4_Msk                          /*!<GROUP1_IO4 sampling mode */
17169 #define TSC_IOSCR_G2_IO1_Pos     (4U)
17170 #define TSC_IOSCR_G2_IO1_Msk     (0x1U << TSC_IOSCR_G2_IO1_Pos)                /*!< 0x00000010 */
17171 #define TSC_IOSCR_G2_IO1         TSC_IOSCR_G2_IO1_Msk                          /*!<GROUP2_IO1 sampling mode */
17172 #define TSC_IOSCR_G2_IO2_Pos     (5U)
17173 #define TSC_IOSCR_G2_IO2_Msk     (0x1U << TSC_IOSCR_G2_IO2_Pos)                /*!< 0x00000020 */
17174 #define TSC_IOSCR_G2_IO2         TSC_IOSCR_G2_IO2_Msk                          /*!<GROUP2_IO2 sampling mode */
17175 #define TSC_IOSCR_G2_IO3_Pos     (6U)
17176 #define TSC_IOSCR_G2_IO3_Msk     (0x1U << TSC_IOSCR_G2_IO3_Pos)                /*!< 0x00000040 */
17177 #define TSC_IOSCR_G2_IO3         TSC_IOSCR_G2_IO3_Msk                          /*!<GROUP2_IO3 sampling mode */
17178 #define TSC_IOSCR_G2_IO4_Pos     (7U)
17179 #define TSC_IOSCR_G2_IO4_Msk     (0x1U << TSC_IOSCR_G2_IO4_Pos)                /*!< 0x00000080 */
17180 #define TSC_IOSCR_G2_IO4         TSC_IOSCR_G2_IO4_Msk                          /*!<GROUP2_IO4 sampling mode */
17181 #define TSC_IOSCR_G3_IO1_Pos     (8U)
17182 #define TSC_IOSCR_G3_IO1_Msk     (0x1U << TSC_IOSCR_G3_IO1_Pos)                /*!< 0x00000100 */
17183 #define TSC_IOSCR_G3_IO1         TSC_IOSCR_G3_IO1_Msk                          /*!<GROUP3_IO1 sampling mode */
17184 #define TSC_IOSCR_G3_IO2_Pos     (9U)
17185 #define TSC_IOSCR_G3_IO2_Msk     (0x1U << TSC_IOSCR_G3_IO2_Pos)                /*!< 0x00000200 */
17186 #define TSC_IOSCR_G3_IO2         TSC_IOSCR_G3_IO2_Msk                          /*!<GROUP3_IO2 sampling mode */
17187 #define TSC_IOSCR_G3_IO3_Pos     (10U)
17188 #define TSC_IOSCR_G3_IO3_Msk     (0x1U << TSC_IOSCR_G3_IO3_Pos)                /*!< 0x00000400 */
17189 #define TSC_IOSCR_G3_IO3         TSC_IOSCR_G3_IO3_Msk                          /*!<GROUP3_IO3 sampling mode */
17190 #define TSC_IOSCR_G3_IO4_Pos     (11U)
17191 #define TSC_IOSCR_G3_IO4_Msk     (0x1U << TSC_IOSCR_G3_IO4_Pos)                /*!< 0x00000800 */
17192 #define TSC_IOSCR_G3_IO4         TSC_IOSCR_G3_IO4_Msk                          /*!<GROUP3_IO4 sampling mode */
17193 #define TSC_IOSCR_G4_IO1_Pos     (12U)
17194 #define TSC_IOSCR_G4_IO1_Msk     (0x1U << TSC_IOSCR_G4_IO1_Pos)                /*!< 0x00001000 */
17195 #define TSC_IOSCR_G4_IO1         TSC_IOSCR_G4_IO1_Msk                          /*!<GROUP4_IO1 sampling mode */
17196 #define TSC_IOSCR_G4_IO2_Pos     (13U)
17197 #define TSC_IOSCR_G4_IO2_Msk     (0x1U << TSC_IOSCR_G4_IO2_Pos)                /*!< 0x00002000 */
17198 #define TSC_IOSCR_G4_IO2         TSC_IOSCR_G4_IO2_Msk                          /*!<GROUP4_IO2 sampling mode */
17199 #define TSC_IOSCR_G4_IO3_Pos     (14U)
17200 #define TSC_IOSCR_G4_IO3_Msk     (0x1U << TSC_IOSCR_G4_IO3_Pos)                /*!< 0x00004000 */
17201 #define TSC_IOSCR_G4_IO3         TSC_IOSCR_G4_IO3_Msk                          /*!<GROUP4_IO3 sampling mode */
17202 #define TSC_IOSCR_G4_IO4_Pos     (15U)
17203 #define TSC_IOSCR_G4_IO4_Msk     (0x1U << TSC_IOSCR_G4_IO4_Pos)                /*!< 0x00008000 */
17204 #define TSC_IOSCR_G4_IO4         TSC_IOSCR_G4_IO4_Msk                          /*!<GROUP4_IO4 sampling mode */
17205 #define TSC_IOSCR_G5_IO1_Pos     (16U)
17206 #define TSC_IOSCR_G5_IO1_Msk     (0x1U << TSC_IOSCR_G5_IO1_Pos)                /*!< 0x00010000 */
17207 #define TSC_IOSCR_G5_IO1         TSC_IOSCR_G5_IO1_Msk                          /*!<GROUP5_IO1 sampling mode */
17208 #define TSC_IOSCR_G5_IO2_Pos     (17U)
17209 #define TSC_IOSCR_G5_IO2_Msk     (0x1U << TSC_IOSCR_G5_IO2_Pos)                /*!< 0x00020000 */
17210 #define TSC_IOSCR_G5_IO2         TSC_IOSCR_G5_IO2_Msk                          /*!<GROUP5_IO2 sampling mode */
17211 #define TSC_IOSCR_G5_IO3_Pos     (18U)
17212 #define TSC_IOSCR_G5_IO3_Msk     (0x1U << TSC_IOSCR_G5_IO3_Pos)                /*!< 0x00040000 */
17213 #define TSC_IOSCR_G5_IO3         TSC_IOSCR_G5_IO3_Msk                          /*!<GROUP5_IO3 sampling mode */
17214 #define TSC_IOSCR_G5_IO4_Pos     (19U)
17215 #define TSC_IOSCR_G5_IO4_Msk     (0x1U << TSC_IOSCR_G5_IO4_Pos)                /*!< 0x00080000 */
17216 #define TSC_IOSCR_G5_IO4         TSC_IOSCR_G5_IO4_Msk                          /*!<GROUP5_IO4 sampling mode */
17217 #define TSC_IOSCR_G6_IO1_Pos     (20U)
17218 #define TSC_IOSCR_G6_IO1_Msk     (0x1U << TSC_IOSCR_G6_IO1_Pos)                /*!< 0x00100000 */
17219 #define TSC_IOSCR_G6_IO1         TSC_IOSCR_G6_IO1_Msk                          /*!<GROUP6_IO1 sampling mode */
17220 #define TSC_IOSCR_G6_IO2_Pos     (21U)
17221 #define TSC_IOSCR_G6_IO2_Msk     (0x1U << TSC_IOSCR_G6_IO2_Pos)                /*!< 0x00200000 */
17222 #define TSC_IOSCR_G6_IO2         TSC_IOSCR_G6_IO2_Msk                          /*!<GROUP6_IO2 sampling mode */
17223 #define TSC_IOSCR_G6_IO3_Pos     (22U)
17224 #define TSC_IOSCR_G6_IO3_Msk     (0x1U << TSC_IOSCR_G6_IO3_Pos)                /*!< 0x00400000 */
17225 #define TSC_IOSCR_G6_IO3         TSC_IOSCR_G6_IO3_Msk                          /*!<GROUP6_IO3 sampling mode */
17226 #define TSC_IOSCR_G6_IO4_Pos     (23U)
17227 #define TSC_IOSCR_G6_IO4_Msk     (0x1U << TSC_IOSCR_G6_IO4_Pos)                /*!< 0x00800000 */
17228 #define TSC_IOSCR_G6_IO4         TSC_IOSCR_G6_IO4_Msk                          /*!<GROUP6_IO4 sampling mode */
17229 #define TSC_IOSCR_G7_IO1_Pos     (24U)
17230 #define TSC_IOSCR_G7_IO1_Msk     (0x1U << TSC_IOSCR_G7_IO1_Pos)                /*!< 0x01000000 */
17231 #define TSC_IOSCR_G7_IO1         TSC_IOSCR_G7_IO1_Msk                          /*!<GROUP7_IO1 sampling mode */
17232 #define TSC_IOSCR_G7_IO2_Pos     (25U)
17233 #define TSC_IOSCR_G7_IO2_Msk     (0x1U << TSC_IOSCR_G7_IO2_Pos)                /*!< 0x02000000 */
17234 #define TSC_IOSCR_G7_IO2         TSC_IOSCR_G7_IO2_Msk                          /*!<GROUP7_IO2 sampling mode */
17235 #define TSC_IOSCR_G7_IO3_Pos     (26U)
17236 #define TSC_IOSCR_G7_IO3_Msk     (0x1U << TSC_IOSCR_G7_IO3_Pos)                /*!< 0x04000000 */
17237 #define TSC_IOSCR_G7_IO3         TSC_IOSCR_G7_IO3_Msk                          /*!<GROUP7_IO3 sampling mode */
17238 #define TSC_IOSCR_G7_IO4_Pos     (27U)
17239 #define TSC_IOSCR_G7_IO4_Msk     (0x1U << TSC_IOSCR_G7_IO4_Pos)                /*!< 0x08000000 */
17240 #define TSC_IOSCR_G7_IO4         TSC_IOSCR_G7_IO4_Msk                          /*!<GROUP7_IO4 sampling mode */
17241 #define TSC_IOSCR_G8_IO1_Pos     (28U)
17242 #define TSC_IOSCR_G8_IO1_Msk     (0x1U << TSC_IOSCR_G8_IO1_Pos)                /*!< 0x10000000 */
17243 #define TSC_IOSCR_G8_IO1         TSC_IOSCR_G8_IO1_Msk                          /*!<GROUP8_IO1 sampling mode */
17244 #define TSC_IOSCR_G8_IO2_Pos     (29U)
17245 #define TSC_IOSCR_G8_IO2_Msk     (0x1U << TSC_IOSCR_G8_IO2_Pos)                /*!< 0x20000000 */
17246 #define TSC_IOSCR_G8_IO2         TSC_IOSCR_G8_IO2_Msk                          /*!<GROUP8_IO2 sampling mode */
17247 #define TSC_IOSCR_G8_IO3_Pos     (30U)
17248 #define TSC_IOSCR_G8_IO3_Msk     (0x1U << TSC_IOSCR_G8_IO3_Pos)                /*!< 0x40000000 */
17249 #define TSC_IOSCR_G8_IO3         TSC_IOSCR_G8_IO3_Msk                          /*!<GROUP8_IO3 sampling mode */
17250 #define TSC_IOSCR_G8_IO4_Pos     (31U)
17251 #define TSC_IOSCR_G8_IO4_Msk     (0x1U << TSC_IOSCR_G8_IO4_Pos)                /*!< 0x80000000 */
17252 #define TSC_IOSCR_G8_IO4         TSC_IOSCR_G8_IO4_Msk                          /*!<GROUP8_IO4 sampling mode */
17253 
17254 /*******************  Bit definition for TSC_IOCCR register  ******************/
17255 #define TSC_IOCCR_G1_IO1_Pos     (0U)
17256 #define TSC_IOCCR_G1_IO1_Msk     (0x1U << TSC_IOCCR_G1_IO1_Pos)                /*!< 0x00000001 */
17257 #define TSC_IOCCR_G1_IO1         TSC_IOCCR_G1_IO1_Msk                          /*!<GROUP1_IO1 channel mode */
17258 #define TSC_IOCCR_G1_IO2_Pos     (1U)
17259 #define TSC_IOCCR_G1_IO2_Msk     (0x1U << TSC_IOCCR_G1_IO2_Pos)                /*!< 0x00000002 */
17260 #define TSC_IOCCR_G1_IO2         TSC_IOCCR_G1_IO2_Msk                          /*!<GROUP1_IO2 channel mode */
17261 #define TSC_IOCCR_G1_IO3_Pos     (2U)
17262 #define TSC_IOCCR_G1_IO3_Msk     (0x1U << TSC_IOCCR_G1_IO3_Pos)                /*!< 0x00000004 */
17263 #define TSC_IOCCR_G1_IO3         TSC_IOCCR_G1_IO3_Msk                          /*!<GROUP1_IO3 channel mode */
17264 #define TSC_IOCCR_G1_IO4_Pos     (3U)
17265 #define TSC_IOCCR_G1_IO4_Msk     (0x1U << TSC_IOCCR_G1_IO4_Pos)                /*!< 0x00000008 */
17266 #define TSC_IOCCR_G1_IO4         TSC_IOCCR_G1_IO4_Msk                          /*!<GROUP1_IO4 channel mode */
17267 #define TSC_IOCCR_G2_IO1_Pos     (4U)
17268 #define TSC_IOCCR_G2_IO1_Msk     (0x1U << TSC_IOCCR_G2_IO1_Pos)                /*!< 0x00000010 */
17269 #define TSC_IOCCR_G2_IO1         TSC_IOCCR_G2_IO1_Msk                          /*!<GROUP2_IO1 channel mode */
17270 #define TSC_IOCCR_G2_IO2_Pos     (5U)
17271 #define TSC_IOCCR_G2_IO2_Msk     (0x1U << TSC_IOCCR_G2_IO2_Pos)                /*!< 0x00000020 */
17272 #define TSC_IOCCR_G2_IO2         TSC_IOCCR_G2_IO2_Msk                          /*!<GROUP2_IO2 channel mode */
17273 #define TSC_IOCCR_G2_IO3_Pos     (6U)
17274 #define TSC_IOCCR_G2_IO3_Msk     (0x1U << TSC_IOCCR_G2_IO3_Pos)                /*!< 0x00000040 */
17275 #define TSC_IOCCR_G2_IO3         TSC_IOCCR_G2_IO3_Msk                          /*!<GROUP2_IO3 channel mode */
17276 #define TSC_IOCCR_G2_IO4_Pos     (7U)
17277 #define TSC_IOCCR_G2_IO4_Msk     (0x1U << TSC_IOCCR_G2_IO4_Pos)                /*!< 0x00000080 */
17278 #define TSC_IOCCR_G2_IO4         TSC_IOCCR_G2_IO4_Msk                          /*!<GROUP2_IO4 channel mode */
17279 #define TSC_IOCCR_G3_IO1_Pos     (8U)
17280 #define TSC_IOCCR_G3_IO1_Msk     (0x1U << TSC_IOCCR_G3_IO1_Pos)                /*!< 0x00000100 */
17281 #define TSC_IOCCR_G3_IO1         TSC_IOCCR_G3_IO1_Msk                          /*!<GROUP3_IO1 channel mode */
17282 #define TSC_IOCCR_G3_IO2_Pos     (9U)
17283 #define TSC_IOCCR_G3_IO2_Msk     (0x1U << TSC_IOCCR_G3_IO2_Pos)                /*!< 0x00000200 */
17284 #define TSC_IOCCR_G3_IO2         TSC_IOCCR_G3_IO2_Msk                          /*!<GROUP3_IO2 channel mode */
17285 #define TSC_IOCCR_G3_IO3_Pos     (10U)
17286 #define TSC_IOCCR_G3_IO3_Msk     (0x1U << TSC_IOCCR_G3_IO3_Pos)                /*!< 0x00000400 */
17287 #define TSC_IOCCR_G3_IO3         TSC_IOCCR_G3_IO3_Msk                          /*!<GROUP3_IO3 channel mode */
17288 #define TSC_IOCCR_G3_IO4_Pos     (11U)
17289 #define TSC_IOCCR_G3_IO4_Msk     (0x1U << TSC_IOCCR_G3_IO4_Pos)                /*!< 0x00000800 */
17290 #define TSC_IOCCR_G3_IO4         TSC_IOCCR_G3_IO4_Msk                          /*!<GROUP3_IO4 channel mode */
17291 #define TSC_IOCCR_G4_IO1_Pos     (12U)
17292 #define TSC_IOCCR_G4_IO1_Msk     (0x1U << TSC_IOCCR_G4_IO1_Pos)                /*!< 0x00001000 */
17293 #define TSC_IOCCR_G4_IO1         TSC_IOCCR_G4_IO1_Msk                          /*!<GROUP4_IO1 channel mode */
17294 #define TSC_IOCCR_G4_IO2_Pos     (13U)
17295 #define TSC_IOCCR_G4_IO2_Msk     (0x1U << TSC_IOCCR_G4_IO2_Pos)                /*!< 0x00002000 */
17296 #define TSC_IOCCR_G4_IO2         TSC_IOCCR_G4_IO2_Msk                          /*!<GROUP4_IO2 channel mode */
17297 #define TSC_IOCCR_G4_IO3_Pos     (14U)
17298 #define TSC_IOCCR_G4_IO3_Msk     (0x1U << TSC_IOCCR_G4_IO3_Pos)                /*!< 0x00004000 */
17299 #define TSC_IOCCR_G4_IO3         TSC_IOCCR_G4_IO3_Msk                          /*!<GROUP4_IO3 channel mode */
17300 #define TSC_IOCCR_G4_IO4_Pos     (15U)
17301 #define TSC_IOCCR_G4_IO4_Msk     (0x1U << TSC_IOCCR_G4_IO4_Pos)                /*!< 0x00008000 */
17302 #define TSC_IOCCR_G4_IO4         TSC_IOCCR_G4_IO4_Msk                          /*!<GROUP4_IO4 channel mode */
17303 #define TSC_IOCCR_G5_IO1_Pos     (16U)
17304 #define TSC_IOCCR_G5_IO1_Msk     (0x1U << TSC_IOCCR_G5_IO1_Pos)                /*!< 0x00010000 */
17305 #define TSC_IOCCR_G5_IO1         TSC_IOCCR_G5_IO1_Msk                          /*!<GROUP5_IO1 channel mode */
17306 #define TSC_IOCCR_G5_IO2_Pos     (17U)
17307 #define TSC_IOCCR_G5_IO2_Msk     (0x1U << TSC_IOCCR_G5_IO2_Pos)                /*!< 0x00020000 */
17308 #define TSC_IOCCR_G5_IO2         TSC_IOCCR_G5_IO2_Msk                          /*!<GROUP5_IO2 channel mode */
17309 #define TSC_IOCCR_G5_IO3_Pos     (18U)
17310 #define TSC_IOCCR_G5_IO3_Msk     (0x1U << TSC_IOCCR_G5_IO3_Pos)                /*!< 0x00040000 */
17311 #define TSC_IOCCR_G5_IO3         TSC_IOCCR_G5_IO3_Msk                          /*!<GROUP5_IO3 channel mode */
17312 #define TSC_IOCCR_G5_IO4_Pos     (19U)
17313 #define TSC_IOCCR_G5_IO4_Msk     (0x1U << TSC_IOCCR_G5_IO4_Pos)                /*!< 0x00080000 */
17314 #define TSC_IOCCR_G5_IO4         TSC_IOCCR_G5_IO4_Msk                          /*!<GROUP5_IO4 channel mode */
17315 #define TSC_IOCCR_G6_IO1_Pos     (20U)
17316 #define TSC_IOCCR_G6_IO1_Msk     (0x1U << TSC_IOCCR_G6_IO1_Pos)                /*!< 0x00100000 */
17317 #define TSC_IOCCR_G6_IO1         TSC_IOCCR_G6_IO1_Msk                          /*!<GROUP6_IO1 channel mode */
17318 #define TSC_IOCCR_G6_IO2_Pos     (21U)
17319 #define TSC_IOCCR_G6_IO2_Msk     (0x1U << TSC_IOCCR_G6_IO2_Pos)                /*!< 0x00200000 */
17320 #define TSC_IOCCR_G6_IO2         TSC_IOCCR_G6_IO2_Msk                          /*!<GROUP6_IO2 channel mode */
17321 #define TSC_IOCCR_G6_IO3_Pos     (22U)
17322 #define TSC_IOCCR_G6_IO3_Msk     (0x1U << TSC_IOCCR_G6_IO3_Pos)                /*!< 0x00400000 */
17323 #define TSC_IOCCR_G6_IO3         TSC_IOCCR_G6_IO3_Msk                          /*!<GROUP6_IO3 channel mode */
17324 #define TSC_IOCCR_G6_IO4_Pos     (23U)
17325 #define TSC_IOCCR_G6_IO4_Msk     (0x1U << TSC_IOCCR_G6_IO4_Pos)                /*!< 0x00800000 */
17326 #define TSC_IOCCR_G6_IO4         TSC_IOCCR_G6_IO4_Msk                          /*!<GROUP6_IO4 channel mode */
17327 #define TSC_IOCCR_G7_IO1_Pos     (24U)
17328 #define TSC_IOCCR_G7_IO1_Msk     (0x1U << TSC_IOCCR_G7_IO1_Pos)                /*!< 0x01000000 */
17329 #define TSC_IOCCR_G7_IO1         TSC_IOCCR_G7_IO1_Msk                          /*!<GROUP7_IO1 channel mode */
17330 #define TSC_IOCCR_G7_IO2_Pos     (25U)
17331 #define TSC_IOCCR_G7_IO2_Msk     (0x1U << TSC_IOCCR_G7_IO2_Pos)                /*!< 0x02000000 */
17332 #define TSC_IOCCR_G7_IO2         TSC_IOCCR_G7_IO2_Msk                          /*!<GROUP7_IO2 channel mode */
17333 #define TSC_IOCCR_G7_IO3_Pos     (26U)
17334 #define TSC_IOCCR_G7_IO3_Msk     (0x1U << TSC_IOCCR_G7_IO3_Pos)                /*!< 0x04000000 */
17335 #define TSC_IOCCR_G7_IO3         TSC_IOCCR_G7_IO3_Msk                          /*!<GROUP7_IO3 channel mode */
17336 #define TSC_IOCCR_G7_IO4_Pos     (27U)
17337 #define TSC_IOCCR_G7_IO4_Msk     (0x1U << TSC_IOCCR_G7_IO4_Pos)                /*!< 0x08000000 */
17338 #define TSC_IOCCR_G7_IO4         TSC_IOCCR_G7_IO4_Msk                          /*!<GROUP7_IO4 channel mode */
17339 #define TSC_IOCCR_G8_IO1_Pos     (28U)
17340 #define TSC_IOCCR_G8_IO1_Msk     (0x1U << TSC_IOCCR_G8_IO1_Pos)                /*!< 0x10000000 */
17341 #define TSC_IOCCR_G8_IO1         TSC_IOCCR_G8_IO1_Msk                          /*!<GROUP8_IO1 channel mode */
17342 #define TSC_IOCCR_G8_IO2_Pos     (29U)
17343 #define TSC_IOCCR_G8_IO2_Msk     (0x1U << TSC_IOCCR_G8_IO2_Pos)                /*!< 0x20000000 */
17344 #define TSC_IOCCR_G8_IO2         TSC_IOCCR_G8_IO2_Msk                          /*!<GROUP8_IO2 channel mode */
17345 #define TSC_IOCCR_G8_IO3_Pos     (30U)
17346 #define TSC_IOCCR_G8_IO3_Msk     (0x1U << TSC_IOCCR_G8_IO3_Pos)                /*!< 0x40000000 */
17347 #define TSC_IOCCR_G8_IO3         TSC_IOCCR_G8_IO3_Msk                          /*!<GROUP8_IO3 channel mode */
17348 #define TSC_IOCCR_G8_IO4_Pos     (31U)
17349 #define TSC_IOCCR_G8_IO4_Msk     (0x1U << TSC_IOCCR_G8_IO4_Pos)                /*!< 0x80000000 */
17350 #define TSC_IOCCR_G8_IO4         TSC_IOCCR_G8_IO4_Msk                          /*!<GROUP8_IO4 channel mode */
17351 
17352 /*******************  Bit definition for TSC_IOGCSR register  *****************/
17353 #define TSC_IOGCSR_G1E_Pos       (0U)
17354 #define TSC_IOGCSR_G1E_Msk       (0x1U << TSC_IOGCSR_G1E_Pos)                  /*!< 0x00000001 */
17355 #define TSC_IOGCSR_G1E           TSC_IOGCSR_G1E_Msk                            /*!<Analog IO GROUP1 enable */
17356 #define TSC_IOGCSR_G2E_Pos       (1U)
17357 #define TSC_IOGCSR_G2E_Msk       (0x1U << TSC_IOGCSR_G2E_Pos)                  /*!< 0x00000002 */
17358 #define TSC_IOGCSR_G2E           TSC_IOGCSR_G2E_Msk                            /*!<Analog IO GROUP2 enable */
17359 #define TSC_IOGCSR_G3E_Pos       (2U)
17360 #define TSC_IOGCSR_G3E_Msk       (0x1U << TSC_IOGCSR_G3E_Pos)                  /*!< 0x00000004 */
17361 #define TSC_IOGCSR_G3E           TSC_IOGCSR_G3E_Msk                            /*!<Analog IO GROUP3 enable */
17362 #define TSC_IOGCSR_G4E_Pos       (3U)
17363 #define TSC_IOGCSR_G4E_Msk       (0x1U << TSC_IOGCSR_G4E_Pos)                  /*!< 0x00000008 */
17364 #define TSC_IOGCSR_G4E           TSC_IOGCSR_G4E_Msk                            /*!<Analog IO GROUP4 enable */
17365 #define TSC_IOGCSR_G5E_Pos       (4U)
17366 #define TSC_IOGCSR_G5E_Msk       (0x1U << TSC_IOGCSR_G5E_Pos)                  /*!< 0x00000010 */
17367 #define TSC_IOGCSR_G5E           TSC_IOGCSR_G5E_Msk                            /*!<Analog IO GROUP5 enable */
17368 #define TSC_IOGCSR_G6E_Pos       (5U)
17369 #define TSC_IOGCSR_G6E_Msk       (0x1U << TSC_IOGCSR_G6E_Pos)                  /*!< 0x00000020 */
17370 #define TSC_IOGCSR_G6E           TSC_IOGCSR_G6E_Msk                            /*!<Analog IO GROUP6 enable */
17371 #define TSC_IOGCSR_G7E_Pos       (6U)
17372 #define TSC_IOGCSR_G7E_Msk       (0x1U << TSC_IOGCSR_G7E_Pos)                  /*!< 0x00000040 */
17373 #define TSC_IOGCSR_G7E           TSC_IOGCSR_G7E_Msk                            /*!<Analog IO GROUP7 enable */
17374 #define TSC_IOGCSR_G8E_Pos       (7U)
17375 #define TSC_IOGCSR_G8E_Msk       (0x1U << TSC_IOGCSR_G8E_Pos)                  /*!< 0x00000080 */
17376 #define TSC_IOGCSR_G8E           TSC_IOGCSR_G8E_Msk                            /*!<Analog IO GROUP8 enable */
17377 #define TSC_IOGCSR_G1S_Pos       (16U)
17378 #define TSC_IOGCSR_G1S_Msk       (0x1U << TSC_IOGCSR_G1S_Pos)                  /*!< 0x00010000 */
17379 #define TSC_IOGCSR_G1S           TSC_IOGCSR_G1S_Msk                            /*!<Analog IO GROUP1 status */
17380 #define TSC_IOGCSR_G2S_Pos       (17U)
17381 #define TSC_IOGCSR_G2S_Msk       (0x1U << TSC_IOGCSR_G2S_Pos)                  /*!< 0x00020000 */
17382 #define TSC_IOGCSR_G2S           TSC_IOGCSR_G2S_Msk                            /*!<Analog IO GROUP2 status */
17383 #define TSC_IOGCSR_G3S_Pos       (18U)
17384 #define TSC_IOGCSR_G3S_Msk       (0x1U << TSC_IOGCSR_G3S_Pos)                  /*!< 0x00040000 */
17385 #define TSC_IOGCSR_G3S           TSC_IOGCSR_G3S_Msk                            /*!<Analog IO GROUP3 status */
17386 #define TSC_IOGCSR_G4S_Pos       (19U)
17387 #define TSC_IOGCSR_G4S_Msk       (0x1U << TSC_IOGCSR_G4S_Pos)                  /*!< 0x00080000 */
17388 #define TSC_IOGCSR_G4S           TSC_IOGCSR_G4S_Msk                            /*!<Analog IO GROUP4 status */
17389 #define TSC_IOGCSR_G5S_Pos       (20U)
17390 #define TSC_IOGCSR_G5S_Msk       (0x1U << TSC_IOGCSR_G5S_Pos)                  /*!< 0x00100000 */
17391 #define TSC_IOGCSR_G5S           TSC_IOGCSR_G5S_Msk                            /*!<Analog IO GROUP5 status */
17392 #define TSC_IOGCSR_G6S_Pos       (21U)
17393 #define TSC_IOGCSR_G6S_Msk       (0x1U << TSC_IOGCSR_G6S_Pos)                  /*!< 0x00200000 */
17394 #define TSC_IOGCSR_G6S           TSC_IOGCSR_G6S_Msk                            /*!<Analog IO GROUP6 status */
17395 #define TSC_IOGCSR_G7S_Pos       (22U)
17396 #define TSC_IOGCSR_G7S_Msk       (0x1U << TSC_IOGCSR_G7S_Pos)                  /*!< 0x00400000 */
17397 #define TSC_IOGCSR_G7S           TSC_IOGCSR_G7S_Msk                            /*!<Analog IO GROUP7 status */
17398 #define TSC_IOGCSR_G8S_Pos       (23U)
17399 #define TSC_IOGCSR_G8S_Msk       (0x1U << TSC_IOGCSR_G8S_Pos)                  /*!< 0x00800000 */
17400 #define TSC_IOGCSR_G8S           TSC_IOGCSR_G8S_Msk                            /*!<Analog IO GROUP8 status */
17401 
17402 /*******************  Bit definition for TSC_IOGXCR register  *****************/
17403 #define TSC_IOGXCR_CNT_Pos       (0U)
17404 #define TSC_IOGXCR_CNT_Msk       (0x3FFFU << TSC_IOGXCR_CNT_Pos)               /*!< 0x00003FFF */
17405 #define TSC_IOGXCR_CNT           TSC_IOGXCR_CNT_Msk                            /*!<CNT[13:0] bits (Counter value) */
17406 
17407 /******************************************************************************/
17408 /*                                                                            */
17409 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
17410 /*                                                                            */
17411 /******************************************************************************/
17412 
17413 /*
17414 * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
17415 */
17416 #define USART_TCBGT_SUPPORT
17417 
17418 /******************  Bit definition for USART_CR1 register  *******************/
17419 #define USART_CR1_UE_Pos              (0U)
17420 #define USART_CR1_UE_Msk              (0x1U << USART_CR1_UE_Pos)               /*!< 0x00000001 */
17421 #define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!< USART Enable */
17422 #define USART_CR1_UESM_Pos            (1U)
17423 #define USART_CR1_UESM_Msk            (0x1U << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
17424 #define USART_CR1_UESM                USART_CR1_UESM_Msk                       /*!< USART Enable in STOP Mode */
17425 #define USART_CR1_RE_Pos              (2U)
17426 #define USART_CR1_RE_Msk              (0x1U << USART_CR1_RE_Pos)               /*!< 0x00000004 */
17427 #define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!< Receiver Enable */
17428 #define USART_CR1_TE_Pos              (3U)
17429 #define USART_CR1_TE_Msk              (0x1U << USART_CR1_TE_Pos)               /*!< 0x00000008 */
17430 #define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!< Transmitter Enable */
17431 #define USART_CR1_IDLEIE_Pos          (4U)
17432 #define USART_CR1_IDLEIE_Msk          (0x1U << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
17433 #define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!< IDLE Interrupt Enable */
17434 #define USART_CR1_RXNEIE_Pos          (5U)
17435 #define USART_CR1_RXNEIE_Msk          (0x1U << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
17436 #define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!< RXNE Interrupt Enable */
17437 #define USART_CR1_TCIE_Pos            (6U)
17438 #define USART_CR1_TCIE_Msk            (0x1U << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
17439 #define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!< Transmission Complete Interrupt Enable */
17440 #define USART_CR1_TXEIE_Pos           (7U)
17441 #define USART_CR1_TXEIE_Msk           (0x1U << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
17442 #define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!< TXE Interrupt Enable */
17443 #define USART_CR1_PEIE_Pos            (8U)
17444 #define USART_CR1_PEIE_Msk            (0x1U << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
17445 #define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!< PE Interrupt Enable */
17446 #define USART_CR1_PS_Pos              (9U)
17447 #define USART_CR1_PS_Msk              (0x1U << USART_CR1_PS_Pos)               /*!< 0x00000200 */
17448 #define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!< Parity Selection */
17449 #define USART_CR1_PCE_Pos             (10U)
17450 #define USART_CR1_PCE_Msk             (0x1U << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
17451 #define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!< Parity Control Enable */
17452 #define USART_CR1_WAKE_Pos            (11U)
17453 #define USART_CR1_WAKE_Msk            (0x1U << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
17454 #define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!< Receiver Wakeup method */
17455 #define USART_CR1_M_Pos               (12U)
17456 #define USART_CR1_M_Msk               (0x10001U << USART_CR1_M_Pos)            /*!< 0x10001000 */
17457 #define USART_CR1_M                   USART_CR1_M_Msk                          /*!< Word length */
17458 #define USART_CR1_M0_Pos              (12U)
17459 #define USART_CR1_M0_Msk              (0x1U << USART_CR1_M0_Pos)               /*!< 0x00001000 */
17460 #define USART_CR1_M0                  USART_CR1_M0_Msk                         /*!< Word length - Bit 0 */
17461 #define USART_CR1_MME_Pos             (13U)
17462 #define USART_CR1_MME_Msk             (0x1U << USART_CR1_MME_Pos)              /*!< 0x00002000 */
17463 #define USART_CR1_MME                 USART_CR1_MME_Msk                        /*!< Mute Mode Enable */
17464 #define USART_CR1_CMIE_Pos            (14U)
17465 #define USART_CR1_CMIE_Msk            (0x1U << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
17466 #define USART_CR1_CMIE                USART_CR1_CMIE_Msk                       /*!< Character match interrupt enable */
17467 #define USART_CR1_OVER8_Pos           (15U)
17468 #define USART_CR1_OVER8_Msk           (0x1U << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
17469 #define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!< Oversampling by 8-bit or 16-bit mode */
17470 #define USART_CR1_DEDT_Pos            (16U)
17471 #define USART_CR1_DEDT_Msk            (0x1FU << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
17472 #define USART_CR1_DEDT                USART_CR1_DEDT_Msk                       /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
17473 #define USART_CR1_DEDT_0              (0x01U << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
17474 #define USART_CR1_DEDT_1              (0x02U << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
17475 #define USART_CR1_DEDT_2              (0x04U << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
17476 #define USART_CR1_DEDT_3              (0x08U << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
17477 #define USART_CR1_DEDT_4              (0x10U << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
17478 #define USART_CR1_DEAT_Pos            (21U)
17479 #define USART_CR1_DEAT_Msk            (0x1FU << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
17480 #define USART_CR1_DEAT                USART_CR1_DEAT_Msk                       /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
17481 #define USART_CR1_DEAT_0              (0x01U << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
17482 #define USART_CR1_DEAT_1              (0x02U << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
17483 #define USART_CR1_DEAT_2              (0x04U << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
17484 #define USART_CR1_DEAT_3              (0x08U << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
17485 #define USART_CR1_DEAT_4              (0x10U << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
17486 #define USART_CR1_RTOIE_Pos           (26U)
17487 #define USART_CR1_RTOIE_Msk           (0x1U << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
17488 #define USART_CR1_RTOIE               USART_CR1_RTOIE_Msk                      /*!< Receive Time Out interrupt enable */
17489 #define USART_CR1_EOBIE_Pos           (27U)
17490 #define USART_CR1_EOBIE_Msk           (0x1U << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
17491 #define USART_CR1_EOBIE               USART_CR1_EOBIE_Msk                      /*!< End of Block interrupt enable */
17492 #define USART_CR1_M1_Pos              (28U)
17493 #define USART_CR1_M1_Msk              (0x1U << USART_CR1_M1_Pos)               /*!< 0x10000000 */
17494 #define USART_CR1_M1                  USART_CR1_M1_Msk                         /*!< Word length - Bit 1 */
17495 
17496 /******************  Bit definition for USART_CR2 register  *******************/
17497 #define USART_CR2_ADDM7_Pos           (4U)
17498 #define USART_CR2_ADDM7_Msk           (0x1U << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
17499 #define USART_CR2_ADDM7               USART_CR2_ADDM7_Msk                      /*!< 7-bit or 4-bit Address Detection */
17500 #define USART_CR2_LBDL_Pos            (5U)
17501 #define USART_CR2_LBDL_Msk            (0x1U << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
17502 #define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!< LIN Break Detection Length */
17503 #define USART_CR2_LBDIE_Pos           (6U)
17504 #define USART_CR2_LBDIE_Msk           (0x1U << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
17505 #define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!< LIN Break Detection Interrupt Enable */
17506 #define USART_CR2_LBCL_Pos            (8U)
17507 #define USART_CR2_LBCL_Msk            (0x1U << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
17508 #define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!< Last Bit Clock pulse */
17509 #define USART_CR2_CPHA_Pos            (9U)
17510 #define USART_CR2_CPHA_Msk            (0x1U << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
17511 #define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!< Clock Phase */
17512 #define USART_CR2_CPOL_Pos            (10U)
17513 #define USART_CR2_CPOL_Msk            (0x1U << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
17514 #define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!< Clock Polarity */
17515 #define USART_CR2_CLKEN_Pos           (11U)
17516 #define USART_CR2_CLKEN_Msk           (0x1U << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
17517 #define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!< Clock Enable */
17518 #define USART_CR2_STOP_Pos            (12U)
17519 #define USART_CR2_STOP_Msk            (0x3U << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
17520 #define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!< STOP[1:0] bits (STOP bits) */
17521 #define USART_CR2_STOP_0              (0x1U << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
17522 #define USART_CR2_STOP_1              (0x2U << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
17523 #define USART_CR2_LINEN_Pos           (14U)
17524 #define USART_CR2_LINEN_Msk           (0x1U << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
17525 #define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!< LIN mode enable */
17526 #define USART_CR2_SWAP_Pos            (15U)
17527 #define USART_CR2_SWAP_Msk            (0x1U << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
17528 #define USART_CR2_SWAP                USART_CR2_SWAP_Msk                       /*!< SWAP TX/RX pins */
17529 #define USART_CR2_RXINV_Pos           (16U)
17530 #define USART_CR2_RXINV_Msk           (0x1U << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
17531 #define USART_CR2_RXINV               USART_CR2_RXINV_Msk                      /*!< RX pin active level inversion */
17532 #define USART_CR2_TXINV_Pos           (17U)
17533 #define USART_CR2_TXINV_Msk           (0x1U << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
17534 #define USART_CR2_TXINV               USART_CR2_TXINV_Msk                      /*!< TX pin active level inversion */
17535 #define USART_CR2_DATAINV_Pos         (18U)
17536 #define USART_CR2_DATAINV_Msk         (0x1U << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
17537 #define USART_CR2_DATAINV             USART_CR2_DATAINV_Msk                    /*!< Binary data inversion */
17538 #define USART_CR2_MSBFIRST_Pos        (19U)
17539 #define USART_CR2_MSBFIRST_Msk        (0x1U << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
17540 #define USART_CR2_MSBFIRST            USART_CR2_MSBFIRST_Msk                   /*!< Most Significant Bit First */
17541 #define USART_CR2_ABREN_Pos           (20U)
17542 #define USART_CR2_ABREN_Msk           (0x1U << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
17543 #define USART_CR2_ABREN               USART_CR2_ABREN_Msk                      /*!< Auto Baud-Rate Enable*/
17544 #define USART_CR2_ABRMODE_Pos         (21U)
17545 #define USART_CR2_ABRMODE_Msk         (0x3U << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
17546 #define USART_CR2_ABRMODE             USART_CR2_ABRMODE_Msk                    /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
17547 #define USART_CR2_ABRMODE_0           (0x1U << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
17548 #define USART_CR2_ABRMODE_1           (0x2U << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
17549 #define USART_CR2_RTOEN_Pos           (23U)
17550 #define USART_CR2_RTOEN_Msk           (0x1U << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
17551 #define USART_CR2_RTOEN               USART_CR2_RTOEN_Msk                      /*!< Receiver Time-Out enable */
17552 #define USART_CR2_ADD_Pos             (24U)
17553 #define USART_CR2_ADD_Msk             (0xFFU << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
17554 #define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!< Address of the USART node */
17555 
17556 /******************  Bit definition for USART_CR3 register  *******************/
17557 #define USART_CR3_EIE_Pos             (0U)
17558 #define USART_CR3_EIE_Msk             (0x1U << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
17559 #define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!< Error Interrupt Enable */
17560 #define USART_CR3_IREN_Pos            (1U)
17561 #define USART_CR3_IREN_Msk            (0x1U << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
17562 #define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!< IrDA mode Enable */
17563 #define USART_CR3_IRLP_Pos            (2U)
17564 #define USART_CR3_IRLP_Msk            (0x1U << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
17565 #define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!< IrDA Low-Power */
17566 #define USART_CR3_HDSEL_Pos           (3U)
17567 #define USART_CR3_HDSEL_Msk           (0x1U << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
17568 #define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!< Half-Duplex Selection */
17569 #define USART_CR3_NACK_Pos            (4U)
17570 #define USART_CR3_NACK_Msk            (0x1U << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
17571 #define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!< SmartCard NACK enable */
17572 #define USART_CR3_SCEN_Pos            (5U)
17573 #define USART_CR3_SCEN_Msk            (0x1U << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
17574 #define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!< SmartCard mode enable */
17575 #define USART_CR3_DMAR_Pos            (6U)
17576 #define USART_CR3_DMAR_Msk            (0x1U << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
17577 #define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!< DMA Enable Receiver */
17578 #define USART_CR3_DMAT_Pos            (7U)
17579 #define USART_CR3_DMAT_Msk            (0x1U << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
17580 #define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!< DMA Enable Transmitter */
17581 #define USART_CR3_RTSE_Pos            (8U)
17582 #define USART_CR3_RTSE_Msk            (0x1U << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
17583 #define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!< RTS Enable */
17584 #define USART_CR3_CTSE_Pos            (9U)
17585 #define USART_CR3_CTSE_Msk            (0x1U << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
17586 #define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!< CTS Enable */
17587 #define USART_CR3_CTSIE_Pos           (10U)
17588 #define USART_CR3_CTSIE_Msk           (0x1U << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
17589 #define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!< CTS Interrupt Enable */
17590 #define USART_CR3_ONEBIT_Pos          (11U)
17591 #define USART_CR3_ONEBIT_Msk          (0x1U << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
17592 #define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!< One sample bit method enable */
17593 #define USART_CR3_OVRDIS_Pos          (12U)
17594 #define USART_CR3_OVRDIS_Msk          (0x1U << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
17595 #define USART_CR3_OVRDIS              USART_CR3_OVRDIS_Msk                     /*!< Overrun Disable */
17596 #define USART_CR3_DDRE_Pos            (13U)
17597 #define USART_CR3_DDRE_Msk            (0x1U << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
17598 #define USART_CR3_DDRE                USART_CR3_DDRE_Msk                       /*!< DMA Disable on Reception Error */
17599 #define USART_CR3_DEM_Pos             (14U)
17600 #define USART_CR3_DEM_Msk             (0x1U << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
17601 #define USART_CR3_DEM                 USART_CR3_DEM_Msk                        /*!< Driver Enable Mode */
17602 #define USART_CR3_DEP_Pos             (15U)
17603 #define USART_CR3_DEP_Msk             (0x1U << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
17604 #define USART_CR3_DEP                 USART_CR3_DEP_Msk                        /*!< Driver Enable Polarity Selection */
17605 #define USART_CR3_SCARCNT_Pos         (17U)
17606 #define USART_CR3_SCARCNT_Msk         (0x7U << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
17607 #define USART_CR3_SCARCNT             USART_CR3_SCARCNT_Msk                    /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
17608 #define USART_CR3_SCARCNT_0           (0x1U << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
17609 #define USART_CR3_SCARCNT_1           (0x2U << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
17610 #define USART_CR3_SCARCNT_2           (0x4U << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
17611 #define USART_CR3_WUS_Pos             (20U)
17612 #define USART_CR3_WUS_Msk             (0x3U << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
17613 #define USART_CR3_WUS                 USART_CR3_WUS_Msk                        /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
17614 #define USART_CR3_WUS_0               (0x1U << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
17615 #define USART_CR3_WUS_1               (0x2U << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
17616 #define USART_CR3_WUFIE_Pos           (22U)
17617 #define USART_CR3_WUFIE_Msk           (0x1U << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
17618 #define USART_CR3_WUFIE               USART_CR3_WUFIE_Msk                      /*!< Wake Up Interrupt Enable */
17619 #define USART_CR3_TCBGTIE_Pos         (24U)
17620 #define USART_CR3_TCBGTIE_Msk         (0x1U << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
17621 #define USART_CR3_TCBGTIE             USART_CR3_TCBGTIE_Msk                    /*!< Transmission Complete Before Guard Time Interrupt Enable */
17622 
17623 /******************  Bit definition for USART_BRR register  *******************/
17624 #define USART_BRR_DIV_FRACTION_Pos    (0U)
17625 #define USART_BRR_DIV_FRACTION_Msk    (0xFU << USART_BRR_DIV_FRACTION_Pos)     /*!< 0x0000000F */
17626 #define USART_BRR_DIV_FRACTION        USART_BRR_DIV_FRACTION_Msk               /*!< Fraction of USARTDIV */
17627 #define USART_BRR_DIV_MANTISSA_Pos    (4U)
17628 #define USART_BRR_DIV_MANTISSA_Msk    (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)   /*!< 0x0000FFF0 */
17629 #define USART_BRR_DIV_MANTISSA        USART_BRR_DIV_MANTISSA_Msk               /*!< Mantissa of USARTDIV */
17630 
17631 /******************  Bit definition for USART_GTPR register  ******************/
17632 #define USART_GTPR_PSC_Pos            (0U)
17633 #define USART_GTPR_PSC_Msk            (0xFFU << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
17634 #define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!< PSC[7:0] bits (Prescaler value) */
17635 #define USART_GTPR_GT_Pos             (8U)
17636 #define USART_GTPR_GT_Msk             (0xFFU << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
17637 #define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!< GT[7:0] bits (Guard time value) */
17638 
17639 /*******************  Bit definition for USART_RTOR register  *****************/
17640 #define USART_RTOR_RTO_Pos            (0U)
17641 #define USART_RTOR_RTO_Msk            (0xFFFFFFU << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
17642 #define USART_RTOR_RTO                USART_RTOR_RTO_Msk                       /*!< Receiver Time Out Value */
17643 #define USART_RTOR_BLEN_Pos           (24U)
17644 #define USART_RTOR_BLEN_Msk           (0xFFU << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
17645 #define USART_RTOR_BLEN               USART_RTOR_BLEN_Msk                      /*!< Block Length */
17646 
17647 /*******************  Bit definition for USART_RQR register  ******************/
17648 #define USART_RQR_ABRRQ_Pos           (0U)
17649 #define USART_RQR_ABRRQ_Msk           (0x1U << USART_RQR_ABRRQ_Pos)            /*!< 0x00000001 */
17650 #define USART_RQR_ABRRQ               USART_RQR_ABRRQ_Msk                      /*!< Auto-Baud Rate Request */
17651 #define USART_RQR_SBKRQ_Pos           (1U)
17652 #define USART_RQR_SBKRQ_Msk           (0x1U << USART_RQR_SBKRQ_Pos)            /*!< 0x00000002 */
17653 #define USART_RQR_SBKRQ               USART_RQR_SBKRQ_Msk                      /*!< Send Break Request */
17654 #define USART_RQR_MMRQ_Pos            (2U)
17655 #define USART_RQR_MMRQ_Msk            (0x1U << USART_RQR_MMRQ_Pos)             /*!< 0x00000004 */
17656 #define USART_RQR_MMRQ                USART_RQR_MMRQ_Msk                       /*!< Mute Mode Request */
17657 #define USART_RQR_RXFRQ_Pos           (3U)
17658 #define USART_RQR_RXFRQ_Msk           (0x1U << USART_RQR_RXFRQ_Pos)            /*!< 0x00000008 */
17659 #define USART_RQR_RXFRQ               USART_RQR_RXFRQ_Msk                      /*!< Receive Data flush Request */
17660 #define USART_RQR_TXFRQ_Pos           (4U)
17661 #define USART_RQR_TXFRQ_Msk           (0x1U << USART_RQR_TXFRQ_Pos)            /*!< 0x00000010 */
17662 #define USART_RQR_TXFRQ               USART_RQR_TXFRQ_Msk                      /*!< Transmit data flush Request */
17663 
17664 /*******************  Bit definition for USART_ISR register  ******************/
17665 #define USART_ISR_PE_Pos              (0U)
17666 #define USART_ISR_PE_Msk              (0x1U << USART_ISR_PE_Pos)               /*!< 0x00000001 */
17667 #define USART_ISR_PE                  USART_ISR_PE_Msk                         /*!< Parity Error */
17668 #define USART_ISR_FE_Pos              (1U)
17669 #define USART_ISR_FE_Msk              (0x1U << USART_ISR_FE_Pos)               /*!< 0x00000002 */
17670 #define USART_ISR_FE                  USART_ISR_FE_Msk                         /*!< Framing Error */
17671 #define USART_ISR_NE_Pos              (2U)
17672 #define USART_ISR_NE_Msk              (0x1U << USART_ISR_NE_Pos)               /*!< 0x00000004 */
17673 #define USART_ISR_NE                  USART_ISR_NE_Msk                         /*!< Noise Error detected Flag */
17674 #define USART_ISR_ORE_Pos             (3U)
17675 #define USART_ISR_ORE_Msk             (0x1U << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
17676 #define USART_ISR_ORE                 USART_ISR_ORE_Msk                        /*!< OverRun Error */
17677 #define USART_ISR_IDLE_Pos            (4U)
17678 #define USART_ISR_IDLE_Msk            (0x1U << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
17679 #define USART_ISR_IDLE                USART_ISR_IDLE_Msk                       /*!< IDLE line detected */
17680 #define USART_ISR_RXNE_Pos            (5U)
17681 #define USART_ISR_RXNE_Msk            (0x1U << USART_ISR_RXNE_Pos)             /*!< 0x00000020 */
17682 #define USART_ISR_RXNE                USART_ISR_RXNE_Msk                       /*!< Read Data Register Not Empty */
17683 #define USART_ISR_TC_Pos              (6U)
17684 #define USART_ISR_TC_Msk              (0x1U << USART_ISR_TC_Pos)               /*!< 0x00000040 */
17685 #define USART_ISR_TC                  USART_ISR_TC_Msk                         /*!< Transmission Complete */
17686 #define USART_ISR_TXE_Pos             (7U)
17687 #define USART_ISR_TXE_Msk             (0x1U << USART_ISR_TXE_Pos)              /*!< 0x00000080 */
17688 #define USART_ISR_TXE                 USART_ISR_TXE_Msk                        /*!< Transmit Data Register Empty */
17689 #define USART_ISR_LBDF_Pos            (8U)
17690 #define USART_ISR_LBDF_Msk            (0x1U << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
17691 #define USART_ISR_LBDF                USART_ISR_LBDF_Msk                       /*!< LIN Break Detection Flag */
17692 #define USART_ISR_CTSIF_Pos           (9U)
17693 #define USART_ISR_CTSIF_Msk           (0x1U << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
17694 #define USART_ISR_CTSIF               USART_ISR_CTSIF_Msk                      /*!< CTS interrupt flag */
17695 #define USART_ISR_CTS_Pos             (10U)
17696 #define USART_ISR_CTS_Msk             (0x1U << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
17697 #define USART_ISR_CTS                 USART_ISR_CTS_Msk                        /*!< CTS flag */
17698 #define USART_ISR_RTOF_Pos            (11U)
17699 #define USART_ISR_RTOF_Msk            (0x1U << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
17700 #define USART_ISR_RTOF                USART_ISR_RTOF_Msk                       /*!< Receiver Time Out */
17701 #define USART_ISR_EOBF_Pos            (12U)
17702 #define USART_ISR_EOBF_Msk            (0x1U << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
17703 #define USART_ISR_EOBF                USART_ISR_EOBF_Msk                       /*!< End Of Block Flag */
17704 #define USART_ISR_ABRE_Pos            (14U)
17705 #define USART_ISR_ABRE_Msk            (0x1U << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
17706 #define USART_ISR_ABRE                USART_ISR_ABRE_Msk                       /*!< Auto-Baud Rate Error */
17707 #define USART_ISR_ABRF_Pos            (15U)
17708 #define USART_ISR_ABRF_Msk            (0x1U << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
17709 #define USART_ISR_ABRF                USART_ISR_ABRF_Msk                       /*!< Auto-Baud Rate Flag */
17710 #define USART_ISR_BUSY_Pos            (16U)
17711 #define USART_ISR_BUSY_Msk            (0x1U << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
17712 #define USART_ISR_BUSY                USART_ISR_BUSY_Msk                       /*!< Busy Flag */
17713 #define USART_ISR_CMF_Pos             (17U)
17714 #define USART_ISR_CMF_Msk             (0x1U << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
17715 #define USART_ISR_CMF                 USART_ISR_CMF_Msk                        /*!< Character Match Flag */
17716 #define USART_ISR_SBKF_Pos            (18U)
17717 #define USART_ISR_SBKF_Msk            (0x1U << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
17718 #define USART_ISR_SBKF                USART_ISR_SBKF_Msk                       /*!< Send Break Flag */
17719 #define USART_ISR_RWU_Pos             (19U)
17720 #define USART_ISR_RWU_Msk             (0x1U << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
17721 #define USART_ISR_RWU                 USART_ISR_RWU_Msk                        /*!< Receive Wake Up from mute mode Flag */
17722 #define USART_ISR_WUF_Pos             (20U)
17723 #define USART_ISR_WUF_Msk             (0x1U << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
17724 #define USART_ISR_WUF                 USART_ISR_WUF_Msk                        /*!< Wake Up from stop mode Flag */
17725 #define USART_ISR_TEACK_Pos           (21U)
17726 #define USART_ISR_TEACK_Msk           (0x1U << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
17727 #define USART_ISR_TEACK               USART_ISR_TEACK_Msk                      /*!< Transmit Enable Acknowledge Flag */
17728 #define USART_ISR_REACK_Pos           (22U)
17729 #define USART_ISR_REACK_Msk           (0x1U << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
17730 #define USART_ISR_REACK               USART_ISR_REACK_Msk                      /*!< Receive Enable Acknowledge Flag */
17731 #define USART_ISR_TCBGT_Pos           (25U)
17732 #define USART_ISR_TCBGT_Msk           (0x1U << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
17733 #define USART_ISR_TCBGT               USART_ISR_TCBGT_Msk                      /*!< Transmission Complete Before Guard Time Completion Flag */
17734 
17735 /*******************  Bit definition for USART_ICR register  ******************/
17736 #define USART_ICR_PECF_Pos            (0U)
17737 #define USART_ICR_PECF_Msk            (0x1U << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
17738 #define USART_ICR_PECF                USART_ICR_PECF_Msk                       /*!< Parity Error Clear Flag */
17739 #define USART_ICR_FECF_Pos            (1U)
17740 #define USART_ICR_FECF_Msk            (0x1U << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
17741 #define USART_ICR_FECF                USART_ICR_FECF_Msk                       /*!< Framing Error Clear Flag */
17742 #define USART_ICR_NECF_Pos            (2U)
17743 #define USART_ICR_NECF_Msk            (0x1U << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
17744 #define USART_ICR_NECF                USART_ICR_NECF_Msk                       /*!< Noise Error detected Clear Flag */
17745 #define USART_ICR_ORECF_Pos           (3U)
17746 #define USART_ICR_ORECF_Msk           (0x1U << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
17747 #define USART_ICR_ORECF               USART_ICR_ORECF_Msk                      /*!< OverRun Error Clear Flag */
17748 #define USART_ICR_IDLECF_Pos          (4U)
17749 #define USART_ICR_IDLECF_Msk          (0x1U << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
17750 #define USART_ICR_IDLECF              USART_ICR_IDLECF_Msk                     /*!< IDLE line detected Clear Flag */
17751 #define USART_ICR_TCCF_Pos            (6U)
17752 #define USART_ICR_TCCF_Msk            (0x1U << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
17753 #define USART_ICR_TCCF                USART_ICR_TCCF_Msk                       /*!< Transmission Complete Clear Flag */
17754 #define USART_ICR_TCBGTCF_Pos         (7U)
17755 #define USART_ICR_TCBGTCF_Msk         (0x1U << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
17756 #define USART_ICR_TCBGTCF             USART_ICR_TCBGTCF_Msk                    /*!< Transmission Complete Before Guard Time Clear Flag */
17757 #define USART_ICR_LBDCF_Pos           (8U)
17758 #define USART_ICR_LBDCF_Msk           (0x1U << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
17759 #define USART_ICR_LBDCF               USART_ICR_LBDCF_Msk                      /*!< LIN Break Detection Clear Flag */
17760 #define USART_ICR_CTSCF_Pos           (9U)
17761 #define USART_ICR_CTSCF_Msk           (0x1U << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
17762 #define USART_ICR_CTSCF               USART_ICR_CTSCF_Msk                      /*!< CTS Interrupt Clear Flag */
17763 #define USART_ICR_RTOCF_Pos           (11U)
17764 #define USART_ICR_RTOCF_Msk           (0x1U << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
17765 #define USART_ICR_RTOCF               USART_ICR_RTOCF_Msk                      /*!< Receiver Time Out Clear Flag */
17766 #define USART_ICR_EOBCF_Pos           (12U)
17767 #define USART_ICR_EOBCF_Msk           (0x1U << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
17768 #define USART_ICR_EOBCF               USART_ICR_EOBCF_Msk                      /*!< End Of Block Clear Flag */
17769 #define USART_ICR_CMCF_Pos            (17U)
17770 #define USART_ICR_CMCF_Msk            (0x1U << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
17771 #define USART_ICR_CMCF                USART_ICR_CMCF_Msk                       /*!< Character Match Clear Flag */
17772 #define USART_ICR_WUCF_Pos            (20U)
17773 #define USART_ICR_WUCF_Msk            (0x1U << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
17774 #define USART_ICR_WUCF                USART_ICR_WUCF_Msk                       /*!< Wake Up from stop mode Clear Flag */
17775 
17776 /* Legacy defines */
17777 #define USART_ICR_NCF_Pos             USART_ICR_NECF_Pos
17778 #define USART_ICR_NCF_Msk             USART_ICR_NECF_Msk
17779 #define USART_ICR_NCF                 USART_ICR_NECF
17780 
17781 /*******************  Bit definition for USART_RDR register  ******************/
17782 #define USART_RDR_RDR_Pos             (0U)
17783 #define USART_RDR_RDR_Msk             (0x1FFU << USART_RDR_RDR_Pos)            /*!< 0x000001FF */
17784 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
17785 
17786 /*******************  Bit definition for USART_TDR register  ******************/
17787 #define USART_TDR_TDR_Pos             (0U)
17788 #define USART_TDR_TDR_Msk             (0x1FFU << USART_TDR_TDR_Pos)            /*!< 0x000001FF */
17789 #define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
17790 
17791 /******************************************************************************/
17792 /*                                                                            */
17793 /*           Single Wire Protocol Master Interface (SWPMI)                    */
17794 /*                                                                            */
17795 /******************************************************************************/
17796 
17797 /*******************  Bit definition for SWPMI_CR register   ********************/
17798 #define SWPMI_CR_RXDMA_Pos       (0U)
17799 #define SWPMI_CR_RXDMA_Msk       (0x1U << SWPMI_CR_RXDMA_Pos)                  /*!< 0x00000001 */
17800 #define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
17801 #define SWPMI_CR_TXDMA_Pos       (1U)
17802 #define SWPMI_CR_TXDMA_Msk       (0x1U << SWPMI_CR_TXDMA_Pos)                  /*!< 0x00000002 */
17803 #define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
17804 #define SWPMI_CR_RXMODE_Pos      (2U)
17805 #define SWPMI_CR_RXMODE_Msk      (0x1U << SWPMI_CR_RXMODE_Pos)                 /*!< 0x00000004 */
17806 #define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
17807 #define SWPMI_CR_TXMODE_Pos      (3U)
17808 #define SWPMI_CR_TXMODE_Msk      (0x1U << SWPMI_CR_TXMODE_Pos)                 /*!< 0x00000008 */
17809 #define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
17810 #define SWPMI_CR_LPBK_Pos        (4U)
17811 #define SWPMI_CR_LPBK_Msk        (0x1U << SWPMI_CR_LPBK_Pos)                   /*!< 0x00000010 */
17812 #define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
17813 #define SWPMI_CR_SWPACT_Pos      (5U)
17814 #define SWPMI_CR_SWPACT_Msk      (0x1U << SWPMI_CR_SWPACT_Pos)                 /*!< 0x00000020 */
17815 #define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
17816 #define SWPMI_CR_DEACT_Pos       (10U)
17817 #define SWPMI_CR_DEACT_Msk       (0x1U << SWPMI_CR_DEACT_Pos)                  /*!< 0x00000400 */
17818 #define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
17819 
17820 /*******************  Bit definition for SWPMI_BRR register  ********************/
17821 #define SWPMI_BRR_BR_Pos         (0U)
17822 #define SWPMI_BRR_BR_Msk         (0x3FU << SWPMI_BRR_BR_Pos)                   /*!< 0x0000003F */
17823 #define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[5:0] bits (Bitrate prescaler) */
17824 
17825 /*******************  Bit definition for SWPMI_ISR register  ********************/
17826 #define SWPMI_ISR_RXBFF_Pos      (0U)
17827 #define SWPMI_ISR_RXBFF_Msk      (0x1U << SWPMI_ISR_RXBFF_Pos)                 /*!< 0x00000001 */
17828 #define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
17829 #define SWPMI_ISR_TXBEF_Pos      (1U)
17830 #define SWPMI_ISR_TXBEF_Msk      (0x1U << SWPMI_ISR_TXBEF_Pos)                 /*!< 0x00000002 */
17831 #define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
17832 #define SWPMI_ISR_RXBERF_Pos     (2U)
17833 #define SWPMI_ISR_RXBERF_Msk     (0x1U << SWPMI_ISR_RXBERF_Pos)                /*!< 0x00000004 */
17834 #define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
17835 #define SWPMI_ISR_RXOVRF_Pos     (3U)
17836 #define SWPMI_ISR_RXOVRF_Msk     (0x1U << SWPMI_ISR_RXOVRF_Pos)                /*!< 0x00000008 */
17837 #define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
17838 #define SWPMI_ISR_TXUNRF_Pos     (4U)
17839 #define SWPMI_ISR_TXUNRF_Msk     (0x1U << SWPMI_ISR_TXUNRF_Pos)                /*!< 0x00000010 */
17840 #define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
17841 #define SWPMI_ISR_RXNE_Pos       (5U)
17842 #define SWPMI_ISR_RXNE_Msk       (0x1U << SWPMI_ISR_RXNE_Pos)                  /*!< 0x00000020 */
17843 #define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
17844 #define SWPMI_ISR_TXE_Pos        (6U)
17845 #define SWPMI_ISR_TXE_Msk        (0x1U << SWPMI_ISR_TXE_Pos)                   /*!< 0x00000040 */
17846 #define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
17847 #define SWPMI_ISR_TCF_Pos        (7U)
17848 #define SWPMI_ISR_TCF_Msk        (0x1U << SWPMI_ISR_TCF_Pos)                   /*!< 0x00000080 */
17849 #define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
17850 #define SWPMI_ISR_SRF_Pos        (8U)
17851 #define SWPMI_ISR_SRF_Msk        (0x1U << SWPMI_ISR_SRF_Pos)                   /*!< 0x00000100 */
17852 #define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
17853 #define SWPMI_ISR_SUSP_Pos       (9U)
17854 #define SWPMI_ISR_SUSP_Msk       (0x1U << SWPMI_ISR_SUSP_Pos)                  /*!< 0x00000200 */
17855 #define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
17856 #define SWPMI_ISR_DEACTF_Pos     (10U)
17857 #define SWPMI_ISR_DEACTF_Msk     (0x1U << SWPMI_ISR_DEACTF_Pos)                /*!< 0x00000400 */
17858 #define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
17859 
17860 /*******************  Bit definition for SWPMI_ICR register  ********************/
17861 #define SWPMI_ICR_CRXBFF_Pos     (0U)
17862 #define SWPMI_ICR_CRXBFF_Msk     (0x1U << SWPMI_ICR_CRXBFF_Pos)                /*!< 0x00000001 */
17863 #define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
17864 #define SWPMI_ICR_CTXBEF_Pos     (1U)
17865 #define SWPMI_ICR_CTXBEF_Msk     (0x1U << SWPMI_ICR_CTXBEF_Pos)                /*!< 0x00000002 */
17866 #define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
17867 #define SWPMI_ICR_CRXBERF_Pos    (2U)
17868 #define SWPMI_ICR_CRXBERF_Msk    (0x1U << SWPMI_ICR_CRXBERF_Pos)               /*!< 0x00000004 */
17869 #define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
17870 #define SWPMI_ICR_CRXOVRF_Pos    (3U)
17871 #define SWPMI_ICR_CRXOVRF_Msk    (0x1U << SWPMI_ICR_CRXOVRF_Pos)               /*!< 0x00000008 */
17872 #define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
17873 #define SWPMI_ICR_CTXUNRF_Pos    (4U)
17874 #define SWPMI_ICR_CTXUNRF_Msk    (0x1U << SWPMI_ICR_CTXUNRF_Pos)               /*!< 0x00000010 */
17875 #define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
17876 #define SWPMI_ICR_CTCF_Pos       (7U)
17877 #define SWPMI_ICR_CTCF_Msk       (0x1U << SWPMI_ICR_CTCF_Pos)                  /*!< 0x00000080 */
17878 #define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
17879 #define SWPMI_ICR_CSRF_Pos       (8U)
17880 #define SWPMI_ICR_CSRF_Msk       (0x1U << SWPMI_ICR_CSRF_Pos)                  /*!< 0x00000100 */
17881 #define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
17882 
17883 /*******************  Bit definition for SWPMI_IER register  ********************/
17884 #define SWPMI_IER_SRIE_Pos       (8U)
17885 #define SWPMI_IER_SRIE_Msk       (0x1U << SWPMI_IER_SRIE_Pos)                  /*!< 0x00000100 */
17886 #define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
17887 #define SWPMI_IER_TCIE_Pos       (7U)
17888 #define SWPMI_IER_TCIE_Msk       (0x1U << SWPMI_IER_TCIE_Pos)                  /*!< 0x00000080 */
17889 #define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
17890 #define SWPMI_IER_TIE_Pos        (6U)
17891 #define SWPMI_IER_TIE_Msk        (0x1U << SWPMI_IER_TIE_Pos)                   /*!< 0x00000040 */
17892 #define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
17893 #define SWPMI_IER_RIE_Pos        (5U)
17894 #define SWPMI_IER_RIE_Msk        (0x1U << SWPMI_IER_RIE_Pos)                   /*!< 0x00000020 */
17895 #define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
17896 #define SWPMI_IER_TXUNRIE_Pos    (4U)
17897 #define SWPMI_IER_TXUNRIE_Msk    (0x1U << SWPMI_IER_TXUNRIE_Pos)               /*!< 0x00000010 */
17898 #define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
17899 #define SWPMI_IER_RXOVRIE_Pos    (3U)
17900 #define SWPMI_IER_RXOVRIE_Msk    (0x1U << SWPMI_IER_RXOVRIE_Pos)               /*!< 0x00000008 */
17901 #define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
17902 #define SWPMI_IER_RXBERIE_Pos    (2U)
17903 #define SWPMI_IER_RXBERIE_Msk    (0x1U << SWPMI_IER_RXBERIE_Pos)               /*!< 0x00000004 */
17904 #define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
17905 #define SWPMI_IER_TXBEIE_Pos     (1U)
17906 #define SWPMI_IER_TXBEIE_Msk     (0x1U << SWPMI_IER_TXBEIE_Pos)                /*!< 0x00000002 */
17907 #define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
17908 #define SWPMI_IER_RXBFIE_Pos     (0U)
17909 #define SWPMI_IER_RXBFIE_Msk     (0x1U << SWPMI_IER_RXBFIE_Pos)                /*!< 0x00000001 */
17910 #define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
17911 
17912 /*******************  Bit definition for SWPMI_RFL register  ********************/
17913 #define SWPMI_RFL_RFL_Pos        (0U)
17914 #define SWPMI_RFL_RFL_Msk        (0x1FU << SWPMI_RFL_RFL_Pos)                  /*!< 0x0000001F */
17915 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
17916 #define SWPMI_RFL_RFL_0_1_Pos    (0U)
17917 #define SWPMI_RFL_RFL_0_1_Msk    (0x3U << SWPMI_RFL_RFL_0_1_Pos)               /*!< 0x00000003 */
17918 #define SWPMI_RFL_RFL_0_1        SWPMI_RFL_RFL_0_1_Msk                         /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
17919 
17920 /*******************  Bit definition for SWPMI_TDR register  ********************/
17921 #define SWPMI_TDR_TD_Pos         (0U)
17922 #define SWPMI_TDR_TD_Msk         (0xFFFFFFFFU << SWPMI_TDR_TD_Pos)             /*!< 0xFFFFFFFF */
17923 #define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
17924 
17925 /*******************  Bit definition for SWPMI_RDR register  ********************/
17926 #define SWPMI_RDR_RD_Pos         (0U)
17927 #define SWPMI_RDR_RD_Msk         (0xFFFFFFFFU << SWPMI_RDR_RD_Pos)             /*!< 0xFFFFFFFF */
17928 #define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register          */
17929 
17930 /*******************  Bit definition for SWPMI_OR register  ********************/
17931 #define SWPMI_OR_TBYP_Pos        (0U)
17932 #define SWPMI_OR_TBYP_Msk        (0x1U << SWPMI_OR_TBYP_Pos)                   /*!< 0x00000001 */
17933 #define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
17934 #define SWPMI_OR_CLASS_Pos       (1U)
17935 #define SWPMI_OR_CLASS_Msk       (0x1U << SWPMI_OR_CLASS_Pos)                  /*!< 0x00000002 */
17936 #define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP Voltage Class selection */
17937 
17938 /******************************************************************************/
17939 /*                                                                            */
17940 /*                                 VREFBUF                                    */
17941 /*                                                                            */
17942 /******************************************************************************/
17943 /*******************  Bit definition for VREFBUF_CSR register  ****************/
17944 #define VREFBUF_CSR_ENVR_Pos    (0U)
17945 #define VREFBUF_CSR_ENVR_Msk    (0x1U << VREFBUF_CSR_ENVR_Pos)                 /*!< 0x00000001 */
17946 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
17947 #define VREFBUF_CSR_HIZ_Pos     (1U)
17948 #define VREFBUF_CSR_HIZ_Msk     (0x1U << VREFBUF_CSR_HIZ_Pos)                  /*!< 0x00000002 */
17949 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
17950 #define VREFBUF_CSR_VRS_Pos     (2U)
17951 #define VREFBUF_CSR_VRS_Msk     (0x1U << VREFBUF_CSR_VRS_Pos)                  /*!< 0x00000004 */
17952 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */
17953 #define VREFBUF_CSR_VRR_Pos     (3U)
17954 #define VREFBUF_CSR_VRR_Msk     (0x1U << VREFBUF_CSR_VRR_Pos)                  /*!< 0x00000008 */
17955 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
17956 
17957 /*******************  Bit definition for VREFBUF_CCR register  ******************/
17958 #define VREFBUF_CCR_TRIM_Pos    (0U)
17959 #define VREFBUF_CCR_TRIM_Msk    (0x3FU << VREFBUF_CCR_TRIM_Pos)                /*!< 0x0000003F */
17960 #define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
17961 
17962 /******************************************************************************/
17963 /*                                                                            */
17964 /*                            Window WATCHDOG                                 */
17965 /*                                                                            */
17966 /******************************************************************************/
17967 /*******************  Bit definition for WWDG_CR register  ********************/
17968 #define WWDG_CR_T_Pos           (0U)
17969 #define WWDG_CR_T_Msk           (0x7FU << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
17970 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
17971 #define WWDG_CR_T_0             (0x01U << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
17972 #define WWDG_CR_T_1             (0x02U << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
17973 #define WWDG_CR_T_2             (0x04U << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
17974 #define WWDG_CR_T_3             (0x08U << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
17975 #define WWDG_CR_T_4             (0x10U << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
17976 #define WWDG_CR_T_5             (0x20U << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
17977 #define WWDG_CR_T_6             (0x40U << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
17978 
17979 #define WWDG_CR_WDGA_Pos        (7U)
17980 #define WWDG_CR_WDGA_Msk        (0x1U << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
17981 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
17982 
17983 /*******************  Bit definition for WWDG_CFR register  *******************/
17984 #define WWDG_CFR_W_Pos          (0U)
17985 #define WWDG_CFR_W_Msk          (0x7FU << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
17986 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
17987 #define WWDG_CFR_W_0            (0x01U << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
17988 #define WWDG_CFR_W_1            (0x02U << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
17989 #define WWDG_CFR_W_2            (0x04U << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
17990 #define WWDG_CFR_W_3            (0x08U << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
17991 #define WWDG_CFR_W_4            (0x10U << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
17992 #define WWDG_CFR_W_5            (0x20U << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
17993 #define WWDG_CFR_W_6            (0x40U << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
17994 
17995 #define WWDG_CFR_WDGTB_Pos      (7U)
17996 #define WWDG_CFR_WDGTB_Msk      (0x3U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
17997 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
17998 #define WWDG_CFR_WDGTB_0        (0x1U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000080 */
17999 #define WWDG_CFR_WDGTB_1        (0x2U << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000100 */
18000 
18001 #define WWDG_CFR_EWI_Pos        (9U)
18002 #define WWDG_CFR_EWI_Msk        (0x1U << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
18003 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
18004 
18005 /*******************  Bit definition for WWDG_SR register  ********************/
18006 #define WWDG_SR_EWIF_Pos        (0U)
18007 #define WWDG_SR_EWIF_Msk        (0x1U << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
18008 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
18009 
18010 
18011 /******************************************************************************/
18012 /*                                                                            */
18013 /*                                 Debug MCU                                  */
18014 /*                                                                            */
18015 /******************************************************************************/
18016 /********************  Bit definition for DBGMCU_IDCODE register  *************/
18017 #define DBGMCU_IDCODE_DEV_ID_Pos               (0U)
18018 #define DBGMCU_IDCODE_DEV_ID_Msk               (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
18019 #define DBGMCU_IDCODE_DEV_ID                   DBGMCU_IDCODE_DEV_ID_Msk
18020 #define DBGMCU_IDCODE_REV_ID_Pos               (16U)
18021 #define DBGMCU_IDCODE_REV_ID_Msk               (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
18022 #define DBGMCU_IDCODE_REV_ID                   DBGMCU_IDCODE_REV_ID_Msk
18023 
18024 /********************  Bit definition for DBGMCU_CR register  *****************/
18025 #define DBGMCU_CR_DBG_SLEEP_Pos                (0U)
18026 #define DBGMCU_CR_DBG_SLEEP_Msk                (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
18027 #define DBGMCU_CR_DBG_SLEEP                    DBGMCU_CR_DBG_SLEEP_Msk
18028 #define DBGMCU_CR_DBG_STOP_Pos                 (1U)
18029 #define DBGMCU_CR_DBG_STOP_Msk                 (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
18030 #define DBGMCU_CR_DBG_STOP                     DBGMCU_CR_DBG_STOP_Msk
18031 #define DBGMCU_CR_DBG_STANDBY_Pos              (2U)
18032 #define DBGMCU_CR_DBG_STANDBY_Msk              (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
18033 #define DBGMCU_CR_DBG_STANDBY                  DBGMCU_CR_DBG_STANDBY_Msk
18034 #define DBGMCU_CR_TRACE_IOEN_Pos               (5U)
18035 #define DBGMCU_CR_TRACE_IOEN_Msk               (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
18036 #define DBGMCU_CR_TRACE_IOEN                   DBGMCU_CR_TRACE_IOEN_Msk
18037 
18038 #define DBGMCU_CR_TRACE_MODE_Pos               (6U)
18039 #define DBGMCU_CR_TRACE_MODE_Msk               (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
18040 #define DBGMCU_CR_TRACE_MODE                   DBGMCU_CR_TRACE_MODE_Msk
18041 #define DBGMCU_CR_TRACE_MODE_0                 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
18042 #define DBGMCU_CR_TRACE_MODE_1                 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
18043 
18044 /********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
18045 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos      (0U)
18046 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
18047 #define DBGMCU_APB1FZR1_DBG_TIM2_STOP          DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
18048 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos      (1U)
18049 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
18050 #define DBGMCU_APB1FZR1_DBG_TIM3_STOP          DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
18051 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos      (2U)
18052 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
18053 #define DBGMCU_APB1FZR1_DBG_TIM4_STOP          DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
18054 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos      (3U)
18055 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
18056 #define DBGMCU_APB1FZR1_DBG_TIM5_STOP          DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
18057 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos      (4U)
18058 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
18059 #define DBGMCU_APB1FZR1_DBG_TIM6_STOP          DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
18060 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos      (5U)
18061 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
18062 #define DBGMCU_APB1FZR1_DBG_TIM7_STOP          DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
18063 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos       (10U)
18064 #define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
18065 #define DBGMCU_APB1FZR1_DBG_RTC_STOP           DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
18066 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos      (11U)
18067 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
18068 #define DBGMCU_APB1FZR1_DBG_WWDG_STOP          DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
18069 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos      (12U)
18070 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
18071 #define DBGMCU_APB1FZR1_DBG_IWDG_STOP          DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
18072 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos      (21U)
18073 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
18074 #define DBGMCU_APB1FZR1_DBG_I2C1_STOP          DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
18075 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos      (22U)
18076 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
18077 #define DBGMCU_APB1FZR1_DBG_I2C2_STOP          DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
18078 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos      (23U)
18079 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
18080 #define DBGMCU_APB1FZR1_DBG_I2C3_STOP          DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
18081 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos       (25U)
18082 #define DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk       (0x1U << DBGMCU_APB1FZR1_DBG_CAN_STOP_Pos) /*!< 0x02000000 */
18083 #define DBGMCU_APB1FZR1_DBG_CAN_STOP           DBGMCU_APB1FZR1_DBG_CAN_STOP_Msk
18084 #define DBGMCU_APB1FZR1_DBG_CAN2_STOP_Pos      (26U)
18085 #define DBGMCU_APB1FZR1_DBG_CAN2_STOP_Msk      (0x1U << DBGMCU_APB1FZR1_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
18086 #define DBGMCU_APB1FZR1_DBG_CAN2_STOP          DBGMCU_APB1FZR1_DBG_CAN2_STOP_Msk
18087 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos    (31U)
18088 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk    (0x1U << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
18089 #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP        DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
18090 
18091 /********************  Bit definition for DBGMCU_APB1FZR2 register  **********/
18092 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos      (1U)
18093 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk      (0x1U << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos) /*!< 0x00000002 */
18094 #define DBGMCU_APB1FZR2_DBG_I2C4_STOP          DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
18095 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos    (5U)
18096 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk    (0x1U << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) /*!< 0x00000020 */
18097 #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP        DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
18098 
18099 /********************  Bit definition for DBGMCU_APB2FZ register  ************/
18100 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos        (11U)
18101 #define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
18102 #define DBGMCU_APB2FZ_DBG_TIM1_STOP            DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
18103 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos        (13U)
18104 #define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk        (0x1U << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos) /*!< 0x00002000 */
18105 #define DBGMCU_APB2FZ_DBG_TIM8_STOP            DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
18106 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos       (16U)
18107 #define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
18108 #define DBGMCU_APB2FZ_DBG_TIM15_STOP           DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
18109 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos       (17U)
18110 #define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
18111 #define DBGMCU_APB2FZ_DBG_TIM16_STOP           DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
18112 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos       (18U)
18113 #define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk       (0x1U << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
18114 #define DBGMCU_APB2FZ_DBG_TIM17_STOP           DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
18115 
18116 /******************************************************************************/
18117 /*                                                                            */
18118 /*                                       USB_OTG                              */
18119 /*                                                                            */
18120 /******************************************************************************/
18121 /********************  Bit definition for USB_OTG_GOTGCTL register  ********************/
18122 #define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
18123 #define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
18124 #define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
18125 #define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
18126 #define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
18127 #define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
18128 #define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
18129 #define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
18130 #define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
18131 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
18132 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
18133 #define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
18134 #define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
18135 #define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
18136 #define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
18137 #define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
18138 #define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
18139 #define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
18140 #define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
18141 #define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
18142 #define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
18143 #define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
18144 #define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
18145 #define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
18146 #define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
18147 #define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
18148 #define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!<  B-session valid*/
18149 
18150 /********************  Bit definition for USB_OTG_HCFG register  ********************/
18151 
18152 #define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
18153 #define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
18154 #define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select */
18155 #define USB_OTG_HCFG_FSLSPCS_0                   (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
18156 #define USB_OTG_HCFG_FSLSPCS_1                   (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
18157 #define USB_OTG_HCFG_FSLSS_Pos                   (2U)
18158 #define USB_OTG_HCFG_FSLSS_Msk                   (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
18159 #define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
18160 
18161 /********************  Bit definition for USB_OTG_DCFG register  ********************/
18162 
18163 #define USB_OTG_DCFG_DSPD_Pos                    (0U)
18164 #define USB_OTG_DCFG_DSPD_Msk                    (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
18165 #define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
18166 #define USB_OTG_DCFG_DSPD_0                      (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
18167 #define USB_OTG_DCFG_DSPD_1                      (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
18168 #define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
18169 #define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
18170 #define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
18171 #define USB_OTG_DCFG_DAD_Pos                     (4U)
18172 #define USB_OTG_DCFG_DAD_Msk                     (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
18173 #define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
18174 #define USB_OTG_DCFG_DAD_0                       (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
18175 #define USB_OTG_DCFG_DAD_1                       (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
18176 #define USB_OTG_DCFG_DAD_2                       (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
18177 #define USB_OTG_DCFG_DAD_3                       (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
18178 #define USB_OTG_DCFG_DAD_4                       (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
18179 #define USB_OTG_DCFG_DAD_5                       (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
18180 #define USB_OTG_DCFG_DAD_6                       (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
18181 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
18182 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
18183 #define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
18184 #define USB_OTG_DCFG_PFIVL_0                     (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
18185 #define USB_OTG_DCFG_PFIVL_1                     (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
18186 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
18187 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
18188 #define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
18189 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
18190 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
18191 
18192 /********************  Bit definition for USB_OTG_PCGCR register  ********************/
18193 #define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
18194 #define USB_OTG_PCGCR_STPPCLK_Msk                (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
18195 #define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
18196 #define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
18197 #define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
18198 #define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
18199 #define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
18200 #define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
18201 #define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
18202 
18203 /********************  Bit definition for USB_OTG_GOTGINT register  ********************/
18204 #define USB_OTG_GOTGINT_SEDET_Pos                (2U)
18205 #define USB_OTG_GOTGINT_SEDET_Msk                (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
18206 #define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected */
18207 #define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
18208 #define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
18209 #define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change */
18210 #define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
18211 #define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
18212 #define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
18213 #define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
18214 #define USB_OTG_GOTGINT_HNGDET_Msk               (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
18215 #define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected */
18216 #define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
18217 #define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
18218 #define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change */
18219 #define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
18220 #define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
18221 #define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done */
18222 
18223 /********************  Bit definition for USB_OTG_DCTL register  ********************/
18224 #define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
18225 #define USB_OTG_DCTL_RWUSIG_Msk                  (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
18226 #define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
18227 #define USB_OTG_DCTL_SDIS_Pos                    (1U)
18228 #define USB_OTG_DCTL_SDIS_Msk                    (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
18229 #define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect */
18230 #define USB_OTG_DCTL_GINSTS_Pos                  (2U)
18231 #define USB_OTG_DCTL_GINSTS_Msk                  (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
18232 #define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status */
18233 #define USB_OTG_DCTL_GONSTS_Pos                  (3U)
18234 #define USB_OTG_DCTL_GONSTS_Msk                  (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
18235 #define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status */
18236 
18237 #define USB_OTG_DCTL_TCTL_Pos                    (4U)
18238 #define USB_OTG_DCTL_TCTL_Msk                    (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
18239 #define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
18240 #define USB_OTG_DCTL_TCTL_0                      (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
18241 #define USB_OTG_DCTL_TCTL_1                      (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
18242 #define USB_OTG_DCTL_TCTL_2                      (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
18243 #define USB_OTG_DCTL_SGINAK_Pos                  (7U)
18244 #define USB_OTG_DCTL_SGINAK_Msk                  (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
18245 #define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK */
18246 #define USB_OTG_DCTL_CGINAK_Pos                  (8U)
18247 #define USB_OTG_DCTL_CGINAK_Msk                  (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
18248 #define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK */
18249 #define USB_OTG_DCTL_SGONAK_Pos                  (9U)
18250 #define USB_OTG_DCTL_SGONAK_Msk                  (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
18251 #define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK */
18252 #define USB_OTG_DCTL_CGONAK_Pos                  (10U)
18253 #define USB_OTG_DCTL_CGONAK_Msk                  (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
18254 #define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK */
18255 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
18256 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
18257 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
18258 
18259 /********************  Bit definition for USB_OTG_HFIR register  ********************/
18260 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
18261 #define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
18262 #define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
18263 
18264 /********************  Bit definition for USB_OTG_HFNUM register  ********************/
18265 #define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
18266 #define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
18267 #define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number */
18268 #define USB_OTG_HFNUM_FTREM_Pos                  (16U)
18269 #define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
18270 #define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
18271 
18272 /********************  Bit definition for USB_OTG_DSTS register  ********************/
18273 #define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
18274 #define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
18275 #define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status */
18276 
18277 #define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
18278 #define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
18279 #define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
18280 #define USB_OTG_DSTS_ENUMSPD_0                   (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
18281 #define USB_OTG_DSTS_ENUMSPD_1                   (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
18282 #define USB_OTG_DSTS_EERR_Pos                    (3U)
18283 #define USB_OTG_DSTS_EERR_Msk                    (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
18284 #define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error */
18285 #define USB_OTG_DSTS_FNSOF_Pos                   (8U)
18286 #define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
18287 #define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
18288 
18289 /********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
18290 #define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
18291 #define USB_OTG_GAHBCFG_GINT_Msk                 (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
18292 #define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
18293 #define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
18294 #define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
18295 #define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
18296 #define USB_OTG_GAHBCFG_HBSTLEN_0                (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000002 */
18297 #define USB_OTG_GAHBCFG_HBSTLEN_1                (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000004 */
18298 #define USB_OTG_GAHBCFG_HBSTLEN_2                (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000008 */
18299 #define USB_OTG_GAHBCFG_HBSTLEN_3                (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x00000010 */
18300 #define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
18301 #define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
18302 #define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
18303 #define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
18304 #define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
18305 #define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
18306 #define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
18307 #define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
18308 #define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
18309 
18310 /********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
18311 
18312 #define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
18313 #define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
18314 #define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
18315 #define USB_OTG_GUSBCFG_TOCAL_0                  (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
18316 #define USB_OTG_GUSBCFG_TOCAL_1                  (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
18317 #define USB_OTG_GUSBCFG_TOCAL_2                  (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
18318 #define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
18319 #define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
18320 #define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
18321 #define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
18322 #define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
18323 #define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
18324 #define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
18325 #define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
18326 #define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
18327 #define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
18328 #define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
18329 #define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
18330 #define USB_OTG_GUSBCFG_TRDT_0                   (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
18331 #define USB_OTG_GUSBCFG_TRDT_1                   (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
18332 #define USB_OTG_GUSBCFG_TRDT_2                   (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
18333 #define USB_OTG_GUSBCFG_TRDT_3                   (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
18334 #define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
18335 #define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
18336 #define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
18337 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
18338 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
18339 #define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select */
18340 #define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
18341 #define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
18342 #define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume */
18343 #define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
18344 #define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
18345 #define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM */
18346 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
18347 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
18348 #define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
18349 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
18350 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
18351 #define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
18352 #define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
18353 #define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
18354 #define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
18355 #define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
18356 #define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
18357 #define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement */
18358 #define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
18359 #define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
18360 #define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through */
18361 #define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
18362 #define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
18363 #define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable */
18364 #define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
18365 #define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
18366 #define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode */
18367 #define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
18368 #define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
18369 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode */
18370 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
18371 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
18372 #define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet */
18373 
18374 /********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
18375 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
18376 #define USB_OTG_GRSTCTL_CSRST_Msk                (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
18377 #define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset */
18378 #define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
18379 #define USB_OTG_GRSTCTL_HSRST_Msk                (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
18380 #define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset */
18381 #define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
18382 #define USB_OTG_GRSTCTL_FCRST_Msk                (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
18383 #define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
18384 #define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
18385 #define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
18386 #define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush */
18387 #define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
18388 #define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
18389 #define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush */
18390 #define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
18391 #define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
18392 #define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
18393 #define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
18394 #define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
18395 #define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
18396 #define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
18397 #define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
18398 #define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
18399 #define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
18400 #define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
18401 #define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
18402 #define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
18403 #define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
18404 
18405 /********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
18406 #define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
18407 #define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
18408 #define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
18409 #define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
18410 #define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
18411 #define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
18412 #define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
18413 #define USB_OTG_DIEPMSK_TOM_Msk                  (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
18414 #define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
18415 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
18416 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
18417 #define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
18418 #define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
18419 #define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
18420 #define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask */
18421 #define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
18422 #define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
18423 #define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask */
18424 #define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
18425 #define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
18426 #define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask */
18427 #define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
18428 #define USB_OTG_DIEPMSK_BIM_Msk                  (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
18429 #define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask */
18430 
18431 /********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
18432 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
18433 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
18434 #define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available */
18435 #define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
18436 #define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
18437 #define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
18438 #define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
18439 #define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
18440 #define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
18441 #define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
18442 #define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
18443 #define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
18444 #define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
18445 #define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
18446 
18447 #define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
18448 #define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
18449 #define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
18450 #define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
18451 #define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
18452 #define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
18453 #define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
18454 #define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
18455 #define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
18456 #define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
18457 #define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
18458 
18459 /********************  Bit definition for USB_OTG_HAINT register  ********************/
18460 #define USB_OTG_HAINT_HAINT_Pos                  (0U)
18461 #define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
18462 #define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
18463 
18464 /********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
18465 #define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
18466 #define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
18467 #define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
18468 #define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
18469 #define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
18470 #define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask */
18471 #define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
18472 #define USB_OTG_DOEPMSK_STUPM_Msk                (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
18473 #define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask */
18474 #define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
18475 #define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
18476 #define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
18477 #define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
18478 #define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
18479 #define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask */
18480 #define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
18481 #define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
18482 #define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask */
18483 #define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
18484 #define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
18485 #define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask */
18486 
18487 /********************  Bit definition for USB_OTG_GINTSTS register  ********************/
18488 #define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
18489 #define USB_OTG_GINTSTS_CMOD_Msk                 (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
18490 #define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation */
18491 #define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
18492 #define USB_OTG_GINTSTS_MMIS_Msk                 (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
18493 #define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt */
18494 #define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
18495 #define USB_OTG_GINTSTS_OTGINT_Msk               (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
18496 #define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt */
18497 #define USB_OTG_GINTSTS_SOF_Pos                  (3U)
18498 #define USB_OTG_GINTSTS_SOF_Msk                  (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
18499 #define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame */
18500 #define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
18501 #define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
18502 #define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty */
18503 #define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
18504 #define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
18505 #define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty */
18506 #define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
18507 #define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
18508 #define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective */
18509 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
18510 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
18511 #define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
18512 #define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
18513 #define USB_OTG_GINTSTS_ESUSP_Msk                (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
18514 #define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend */
18515 #define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
18516 #define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
18517 #define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend */
18518 #define USB_OTG_GINTSTS_USBRST_Pos               (12U)
18519 #define USB_OTG_GINTSTS_USBRST_Msk               (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
18520 #define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset */
18521 #define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
18522 #define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
18523 #define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done */
18524 #define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
18525 #define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
18526 #define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt */
18527 #define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
18528 #define USB_OTG_GINTSTS_EOPF_Msk                 (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
18529 #define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt */
18530 #define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
18531 #define USB_OTG_GINTSTS_IEPINT_Msk               (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
18532 #define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt */
18533 #define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
18534 #define USB_OTG_GINTSTS_OEPINT_Msk               (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
18535 #define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt */
18536 #define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
18537 #define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
18538 #define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer */
18539 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
18540 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
18541 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
18542 #define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
18543 #define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
18544 #define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
18545 #define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
18546 #define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
18547 #define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt */
18548 #define USB_OTG_GINTSTS_HCINT_Pos                (25U)
18549 #define USB_OTG_GINTSTS_HCINT_Msk                (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
18550 #define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt */
18551 #define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
18552 #define USB_OTG_GINTSTS_PTXFE_Msk                (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
18553 #define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty */
18554 #define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
18555 #define USB_OTG_GINTSTS_LPMINT_Msk               (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
18556 #define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt */
18557 #define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
18558 #define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
18559 #define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change */
18560 #define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
18561 #define USB_OTG_GINTSTS_DISCINT_Msk              (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
18562 #define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt */
18563 #define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
18564 #define USB_OTG_GINTSTS_SRQINT_Msk               (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
18565 #define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
18566 #define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
18567 #define USB_OTG_GINTSTS_WKUINT_Msk               (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
18568 #define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt */
18569 
18570 /********************  Bit definition for USB_OTG_GINTMSK register  ********************/
18571 
18572 #define USB_OTG_GINTMSK_MMISM_Pos                (1U)
18573 #define USB_OTG_GINTMSK_MMISM_Msk                (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
18574 #define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask */
18575 #define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
18576 #define USB_OTG_GINTMSK_OTGINT_Msk               (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
18577 #define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask */
18578 #define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
18579 #define USB_OTG_GINTMSK_SOFM_Msk                 (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
18580 #define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask */
18581 #define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
18582 #define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
18583 #define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask */
18584 #define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
18585 #define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
18586 #define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask */
18587 #define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
18588 #define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
18589 #define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
18590 #define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
18591 #define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
18592 #define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
18593 #define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
18594 #define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
18595 #define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask */
18596 #define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
18597 #define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
18598 #define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask */
18599 #define USB_OTG_GINTMSK_USBRST_Pos               (12U)
18600 #define USB_OTG_GINTMSK_USBRST_Msk               (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
18601 #define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask */
18602 #define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
18603 #define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
18604 #define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask */
18605 #define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
18606 #define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
18607 #define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask */
18608 #define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
18609 #define USB_OTG_GINTMSK_EOPFM_Msk                (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
18610 #define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask */
18611 #define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
18612 #define USB_OTG_GINTMSK_EPMISM_Msk               (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
18613 #define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask */
18614 #define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
18615 #define USB_OTG_GINTMSK_IEPINT_Msk               (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
18616 #define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask */
18617 #define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
18618 #define USB_OTG_GINTMSK_OEPINT_Msk               (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
18619 #define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask */
18620 #define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
18621 #define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
18622 #define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
18623 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
18624 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
18625 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
18626 #define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
18627 #define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
18628 #define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask */
18629 #define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
18630 #define USB_OTG_GINTMSK_PRTIM_Msk                (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
18631 #define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask */
18632 #define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
18633 #define USB_OTG_GINTMSK_HCIM_Msk                 (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
18634 #define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask */
18635 #define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
18636 #define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
18637 #define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask */
18638 #define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
18639 #define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
18640 #define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask */
18641 #define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
18642 #define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
18643 #define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask */
18644 #define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
18645 #define USB_OTG_GINTMSK_DISCINT_Msk              (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
18646 #define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask */
18647 #define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
18648 #define USB_OTG_GINTMSK_SRQIM_Msk                (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
18649 #define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
18650 #define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
18651 #define USB_OTG_GINTMSK_WUIM_Msk                 (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
18652 #define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask */
18653 
18654 /********************  Bit definition for USB_OTG_DAINT register  ********************/
18655 #define USB_OTG_DAINT_IEPINT_Pos                 (0U)
18656 #define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
18657 #define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits */
18658 #define USB_OTG_DAINT_OEPINT_Pos                 (16U)
18659 #define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
18660 #define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
18661 
18662 /********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
18663 #define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
18664 #define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
18665 #define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
18666 
18667 /********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
18668 #define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
18669 #define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
18670 #define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits */
18671 #define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
18672 #define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
18673 #define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
18674 #define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
18675 #define USB_OTG_GRXSTSP_DPID_Msk                 (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
18676 #define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
18677 #define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
18678 #define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
18679 #define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
18680 
18681 /********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
18682 #define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
18683 #define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
18684 #define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
18685 #define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
18686 #define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
18687 #define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
18688 
18689 /********************  Bit definition for OTG register  ********************/
18690 
18691 #define USB_OTG_CHNUM_Pos                        (0U)
18692 #define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
18693 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
18694 #define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
18695 #define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
18696 #define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
18697 #define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
18698 #define USB_OTG_BCNT_Pos                         (4U)
18699 #define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
18700 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
18701 #define USB_OTG_DPID_Pos                         (15U)
18702 #define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
18703 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
18704 #define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
18705 #define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
18706 #define USB_OTG_PKTSTS_Pos                       (17U)
18707 #define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
18708 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
18709 #define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
18710 #define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
18711 #define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
18712 #define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
18713 #define USB_OTG_EPNUM_Pos                        (0U)
18714 #define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
18715 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
18716 #define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
18717 #define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
18718 #define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
18719 #define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
18720 #define USB_OTG_FRMNUM_Pos                       (21U)
18721 #define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
18722 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
18723 #define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
18724 #define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
18725 #define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
18726 #define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
18727 
18728 /********************  Bit definition for OTG register  ********************/
18729 
18730 #define USB_OTG_CHNUM_Pos                        (0U)
18731 #define USB_OTG_CHNUM_Msk                        (0xFU << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
18732 #define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
18733 #define USB_OTG_CHNUM_0                          (0x1U << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
18734 #define USB_OTG_CHNUM_1                          (0x2U << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
18735 #define USB_OTG_CHNUM_2                          (0x4U << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
18736 #define USB_OTG_CHNUM_3                          (0x8U << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
18737 #define USB_OTG_BCNT_Pos                         (4U)
18738 #define USB_OTG_BCNT_Msk                         (0x7FFU << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
18739 #define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
18740 #define USB_OTG_DPID_Pos                         (15U)
18741 #define USB_OTG_DPID_Msk                         (0x3U << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
18742 #define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
18743 #define USB_OTG_DPID_0                           (0x1U << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
18744 #define USB_OTG_DPID_1                           (0x2U << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
18745 #define USB_OTG_PKTSTS_Pos                       (17U)
18746 #define USB_OTG_PKTSTS_Msk                       (0xFU << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
18747 #define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
18748 #define USB_OTG_PKTSTS_0                         (0x1U << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
18749 #define USB_OTG_PKTSTS_1                         (0x2U << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
18750 #define USB_OTG_PKTSTS_2                         (0x4U << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
18751 #define USB_OTG_PKTSTS_3                         (0x8U << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
18752 #define USB_OTG_EPNUM_Pos                        (0U)
18753 #define USB_OTG_EPNUM_Msk                        (0xFU << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
18754 #define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
18755 #define USB_OTG_EPNUM_0                          (0x1U << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
18756 #define USB_OTG_EPNUM_1                          (0x2U << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
18757 #define USB_OTG_EPNUM_2                          (0x4U << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
18758 #define USB_OTG_EPNUM_3                          (0x8U << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
18759 #define USB_OTG_FRMNUM_Pos                       (21U)
18760 #define USB_OTG_FRMNUM_Msk                       (0xFU << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
18761 #define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
18762 #define USB_OTG_FRMNUM_0                         (0x1U << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
18763 #define USB_OTG_FRMNUM_1                         (0x2U << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
18764 #define USB_OTG_FRMNUM_2                         (0x4U << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
18765 #define USB_OTG_FRMNUM_3                         (0x8U << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
18766 
18767 /********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
18768 #define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
18769 #define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
18770 #define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
18771 
18772 /********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
18773 #define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
18774 #define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
18775 #define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
18776 
18777 /********************  Bit definition for OTG register  ********************/
18778 #define USB_OTG_NPTXFSA_Pos                      (0U)
18779 #define USB_OTG_NPTXFSA_Msk                      (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
18780 #define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
18781 #define USB_OTG_NPTXFD_Pos                       (16U)
18782 #define USB_OTG_NPTXFD_Msk                       (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
18783 #define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth */
18784 #define USB_OTG_TX0FSA_Pos                       (0U)
18785 #define USB_OTG_TX0FSA_Msk                       (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
18786 #define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address */
18787 #define USB_OTG_TX0FD_Pos                        (16U)
18788 #define USB_OTG_TX0FD_Msk                        (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
18789 #define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth */
18790 
18791 /********************  Bit definition for USB_OTG_DVBUSPULSE register  ********************/
18792 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
18793 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
18794 #define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
18795 
18796 /********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
18797 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
18798 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
18799 #define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
18800 
18801 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
18802 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
18803 #define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
18804 #define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
18805 #define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
18806 #define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
18807 #define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
18808 #define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
18809 #define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
18810 #define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
18811 #define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
18812 
18813 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
18814 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
18815 #define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
18816 #define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
18817 #define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
18818 #define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
18819 #define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
18820 #define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
18821 #define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
18822 #define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
18823 
18824 /********************  Bit definition for USB_OTG_DTHRCTL register  ***************/
18825 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
18826 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
18827 #define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
18828 #define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
18829 #define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
18830 #define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
18831 
18832 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
18833 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
18834 #define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
18835 #define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
18836 #define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
18837 #define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
18838 #define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
18839 #define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
18840 #define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
18841 #define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
18842 #define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
18843 #define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
18844 #define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
18845 #define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
18846 #define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
18847 
18848 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
18849 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
18850 #define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
18851 #define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
18852 #define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
18853 #define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
18854 #define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
18855 #define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
18856 #define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
18857 #define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
18858 #define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
18859 #define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
18860 #define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
18861 #define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
18862 #define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
18863 
18864 /********************  Bit definition for USB_OTG_DIEPEMPMSK register  ***************/
18865 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
18866 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
18867 #define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
18868 
18869 /********************  Bit definition for USB_OTG_DEACHINT register  ********************/
18870 #define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
18871 #define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
18872 #define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit */
18873 #define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
18874 #define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
18875 #define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
18876 
18877 /********************  Bit definition for USB_OTG_GCCFG register  ********************/
18878 #define USB_OTG_GCCFG_DCDET_Pos                  (0U)
18879 #define USB_OTG_GCCFG_DCDET_Msk                  (0x1U << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
18880 #define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
18881 #define USB_OTG_GCCFG_PDET_Pos                   (1U)
18882 #define USB_OTG_GCCFG_PDET_Msk                   (0x1U << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
18883 #define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
18884 #define USB_OTG_GCCFG_SDET_Pos                   (2U)
18885 #define USB_OTG_GCCFG_SDET_Msk                   (0x1U << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
18886 #define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
18887 #define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
18888 #define USB_OTG_GCCFG_PS2DET_Msk                 (0x1U << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
18889 #define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
18890 #define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
18891 #define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
18892 #define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
18893 #define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
18894 #define USB_OTG_GCCFG_BCDEN_Msk                  (0x1U << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
18895 #define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
18896 #define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
18897 #define USB_OTG_GCCFG_DCDEN_Msk                  (0x1U << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
18898 #define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
18899 #define USB_OTG_GCCFG_PDEN_Pos                   (19U)
18900 #define USB_OTG_GCCFG_PDEN_Msk                   (0x1U << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
18901 #define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
18902 #define USB_OTG_GCCFG_SDEN_Pos                   (20U)
18903 #define USB_OTG_GCCFG_SDEN_Msk                   (0x1U << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
18904 #define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
18905 #define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
18906 #define USB_OTG_GCCFG_VBDEN_Msk                  (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
18907 #define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
18908 
18909 /********************  Bit definition for USB_OTG_GPWRDN) register  ********************/
18910 #define USB_OTG_GPWRDN_DISABLEVBUS_Pos           (6U)
18911 #define USB_OTG_GPWRDN_DISABLEVBUS_Msk           (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) /*!< 0x00000040 */
18912 #define USB_OTG_GPWRDN_DISABLEVBUS               USB_OTG_GPWRDN_DISABLEVBUS_Msk /*!< Power down */
18913 
18914 /********************  Bit definition for USB_OTG_DEACHINTMSK register  ********************/
18915 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
18916 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
18917 #define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
18918 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
18919 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
18920 #define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
18921 
18922 /********************  Bit definition for USB_OTG_CID register  ********************/
18923 #define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
18924 #define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
18925 #define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
18926 
18927 
18928 /********************  Bit definition for USB_OTG_GHWCFG3 register  ********************/
18929 #define USB_OTG_GHWCFG3_LPMMode_Pos              (14U)
18930 #define USB_OTG_GHWCFG3_LPMMode_Msk              (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) /*!< 0x00004000 */
18931 #define USB_OTG_GHWCFG3_LPMMode                  USB_OTG_GHWCFG3_LPMMode_Msk   /* LPM mode specified for Mode of Operation */
18932 
18933 /********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
18934 #define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
18935 #define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
18936 #define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /* Enable best effort service latency */
18937 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
18938 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
18939 #define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */
18940 #define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
18941 #define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
18942 #define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /* Send LPM transaction */
18943 #define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
18944 #define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
18945 #define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /* LPM retry count */
18946 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
18947 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
18948 #define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /* LPMCHIDX: */
18949 #define USB_OTG_GLPMCFG_L1ResumeOK_Pos           (16U)
18950 #define USB_OTG_GLPMCFG_L1ResumeOK_Msk           (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) /*!< 0x00010000 */
18951 #define USB_OTG_GLPMCFG_L1ResumeOK               USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */
18952 #define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
18953 #define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
18954 #define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /* Port sleep status */
18955 #define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
18956 #define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
18957 #define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /* LPM response */
18958 #define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
18959 #define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
18960 #define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /* L1 deep sleep enable */
18961 #define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
18962 #define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
18963 #define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /* BESL threshold */
18964 #define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
18965 #define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
18966 #define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /* L1 shallow sleep enable */
18967 #define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
18968 #define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
18969 #define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /* bRemoteWake value received with last ACKed LPM Token */
18970 #define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
18971 #define USB_OTG_GLPMCFG_BESL_Msk                 (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
18972 #define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /* BESL value received with last ACKed LPM Token  */
18973 #define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
18974 #define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
18975 #define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /* LPM Token acknowledge enable*/
18976 #define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
18977 #define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
18978 #define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /* LPM support enable  */
18979 
18980 
18981 /********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
18982 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
18983 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
18984 #define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
18985 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
18986 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
18987 #define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
18988 #define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
18989 #define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
18990 #define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
18991 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
18992 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
18993 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
18994 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
18995 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
18996 #define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
18997 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
18998 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
18999 #define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
19000 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
19001 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19002 #define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
19003 #define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
19004 #define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19005 #define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
19006 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
19007 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19008 #define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
19009 
19010 /********************  Bit definition for USB_OTG_HPRT register  ********************/
19011 #define USB_OTG_HPRT_PCSTS_Pos                   (0U)
19012 #define USB_OTG_HPRT_PCSTS_Msk                   (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
19013 #define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status */
19014 #define USB_OTG_HPRT_PCDET_Pos                   (1U)
19015 #define USB_OTG_HPRT_PCDET_Msk                   (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
19016 #define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected */
19017 #define USB_OTG_HPRT_PENA_Pos                    (2U)
19018 #define USB_OTG_HPRT_PENA_Msk                    (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
19019 #define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable */
19020 #define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
19021 #define USB_OTG_HPRT_PENCHNG_Msk                 (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
19022 #define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
19023 #define USB_OTG_HPRT_POCA_Pos                    (4U)
19024 #define USB_OTG_HPRT_POCA_Msk                    (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
19025 #define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active */
19026 #define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
19027 #define USB_OTG_HPRT_POCCHNG_Msk                 (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
19028 #define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change */
19029 #define USB_OTG_HPRT_PRES_Pos                    (6U)
19030 #define USB_OTG_HPRT_PRES_Msk                    (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
19031 #define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume */
19032 #define USB_OTG_HPRT_PSUSP_Pos                   (7U)
19033 #define USB_OTG_HPRT_PSUSP_Msk                   (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
19034 #define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend */
19035 #define USB_OTG_HPRT_PRST_Pos                    (8U)
19036 #define USB_OTG_HPRT_PRST_Msk                    (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
19037 #define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset */
19038 
19039 #define USB_OTG_HPRT_PLSTS_Pos                   (10U)
19040 #define USB_OTG_HPRT_PLSTS_Msk                   (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
19041 #define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
19042 #define USB_OTG_HPRT_PLSTS_0                     (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
19043 #define USB_OTG_HPRT_PLSTS_1                     (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
19044 #define USB_OTG_HPRT_PPWR_Pos                    (12U)
19045 #define USB_OTG_HPRT_PPWR_Msk                    (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
19046 #define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
19047 
19048 #define USB_OTG_HPRT_PTCTL_Pos                   (13U)
19049 #define USB_OTG_HPRT_PTCTL_Msk                   (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
19050 #define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
19051 #define USB_OTG_HPRT_PTCTL_0                     (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
19052 #define USB_OTG_HPRT_PTCTL_1                     (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
19053 #define USB_OTG_HPRT_PTCTL_2                     (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
19054 #define USB_OTG_HPRT_PTCTL_3                     (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
19055 
19056 #define USB_OTG_HPRT_PSPD_Pos                    (17U)
19057 #define USB_OTG_HPRT_PSPD_Msk                    (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
19058 #define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
19059 #define USB_OTG_HPRT_PSPD_0                      (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
19060 #define USB_OTG_HPRT_PSPD_1                      (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
19061 
19062 /********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
19063 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
19064 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19065 #define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
19066 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
19067 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19068 #define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19069 #define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
19070 #define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19071 #define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
19072 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
19073 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19074 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
19075 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
19076 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19077 #define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
19078 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
19079 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19080 #define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
19081 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
19082 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19083 #define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
19084 #define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
19085 #define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19086 #define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
19087 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
19088 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
19089 #define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
19090 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
19091 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19092 #define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
19093 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
19094 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
19095 #define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
19096 
19097 /********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
19098 #define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
19099 #define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
19100 #define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
19101 #define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
19102 #define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
19103 #define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
19104 
19105 /********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
19106 #define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
19107 #define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19108 #define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
19109 #define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
19110 #define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19111 #define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
19112 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
19113 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
19114 #define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
19115 #define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
19116 #define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19117 #define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
19118 
19119 #define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
19120 #define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19121 #define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
19122 #define USB_OTG_DIEPCTL_EPTYP_0                  (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19123 #define USB_OTG_DIEPCTL_EPTYP_1                  (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19124 #define USB_OTG_DIEPCTL_STALL_Pos                (21U)
19125 #define USB_OTG_DIEPCTL_STALL_Msk                (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
19126 #define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
19127 
19128 #define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
19129 #define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
19130 #define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
19131 #define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
19132 #define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
19133 #define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
19134 #define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
19135 #define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
19136 #define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
19137 #define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
19138 #define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
19139 #define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
19140 #define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
19141 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
19142 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19143 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19144 #define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
19145 #define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19146 #define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
19147 #define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
19148 #define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19149 #define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
19150 #define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
19151 #define USB_OTG_DIEPCTL_EPENA_Msk                (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
19152 #define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
19153 
19154 /********************  Bit definition for USB_OTG_HCCHAR register  ********************/
19155 #define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
19156 #define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
19157 #define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
19158 
19159 #define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
19160 #define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
19161 #define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
19162 #define USB_OTG_HCCHAR_EPNUM_0                   (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
19163 #define USB_OTG_HCCHAR_EPNUM_1                   (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
19164 #define USB_OTG_HCCHAR_EPNUM_2                   (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
19165 #define USB_OTG_HCCHAR_EPNUM_3                   (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
19166 #define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
19167 #define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
19168 #define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
19169 #define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
19170 #define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
19171 #define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
19172 
19173 #define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
19174 #define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
19175 #define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
19176 #define USB_OTG_HCCHAR_EPTYP_0                   (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
19177 #define USB_OTG_HCCHAR_EPTYP_1                   (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
19178 
19179 #define USB_OTG_HCCHAR_MC_Pos                    (20U)
19180 #define USB_OTG_HCCHAR_MC_Msk                    (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
19181 #define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
19182 #define USB_OTG_HCCHAR_MC_0                      (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
19183 #define USB_OTG_HCCHAR_MC_1                      (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
19184 
19185 #define USB_OTG_HCCHAR_DAD_Pos                   (22U)
19186 #define USB_OTG_HCCHAR_DAD_Msk                   (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
19187 #define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
19188 #define USB_OTG_HCCHAR_DAD_0                     (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
19189 #define USB_OTG_HCCHAR_DAD_1                     (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
19190 #define USB_OTG_HCCHAR_DAD_2                     (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
19191 #define USB_OTG_HCCHAR_DAD_3                     (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
19192 #define USB_OTG_HCCHAR_DAD_4                     (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
19193 #define USB_OTG_HCCHAR_DAD_5                     (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
19194 #define USB_OTG_HCCHAR_DAD_6                     (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
19195 #define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
19196 #define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
19197 #define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
19198 #define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
19199 #define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
19200 #define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
19201 #define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
19202 #define USB_OTG_HCCHAR_CHENA_Msk                 (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
19203 #define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
19204 
19205 /********************  Bit definition for USB_OTG_HCSPLT register  ********************/
19206 
19207 #define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
19208 #define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
19209 #define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
19210 #define USB_OTG_HCSPLT_PRTADDR_0                 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
19211 #define USB_OTG_HCSPLT_PRTADDR_1                 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
19212 #define USB_OTG_HCSPLT_PRTADDR_2                 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
19213 #define USB_OTG_HCSPLT_PRTADDR_3                 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
19214 #define USB_OTG_HCSPLT_PRTADDR_4                 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
19215 #define USB_OTG_HCSPLT_PRTADDR_5                 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
19216 #define USB_OTG_HCSPLT_PRTADDR_6                 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
19217 
19218 #define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
19219 #define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
19220 #define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
19221 #define USB_OTG_HCSPLT_HUBADDR_0                 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
19222 #define USB_OTG_HCSPLT_HUBADDR_1                 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
19223 #define USB_OTG_HCSPLT_HUBADDR_2                 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
19224 #define USB_OTG_HCSPLT_HUBADDR_3                 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
19225 #define USB_OTG_HCSPLT_HUBADDR_4                 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
19226 #define USB_OTG_HCSPLT_HUBADDR_5                 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
19227 #define USB_OTG_HCSPLT_HUBADDR_6                 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
19228 
19229 #define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
19230 #define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
19231 #define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
19232 #define USB_OTG_HCSPLT_XACTPOS_0                 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
19233 #define USB_OTG_HCSPLT_XACTPOS_1                 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
19234 #define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
19235 #define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
19236 #define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
19237 #define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
19238 #define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
19239 #define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
19240 
19241 /********************  Bit definition for USB_OTG_HCINT register  ********************/
19242 #define USB_OTG_HCINT_XFRC_Pos                   (0U)
19243 #define USB_OTG_HCINT_XFRC_Msk                   (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
19244 #define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
19245 #define USB_OTG_HCINT_CHH_Pos                    (1U)
19246 #define USB_OTG_HCINT_CHH_Msk                    (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
19247 #define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
19248 #define USB_OTG_HCINT_AHBERR_Pos                 (2U)
19249 #define USB_OTG_HCINT_AHBERR_Msk                 (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
19250 #define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
19251 #define USB_OTG_HCINT_STALL_Pos                  (3U)
19252 #define USB_OTG_HCINT_STALL_Msk                  (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
19253 #define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
19254 #define USB_OTG_HCINT_NAK_Pos                    (4U)
19255 #define USB_OTG_HCINT_NAK_Msk                    (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
19256 #define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
19257 #define USB_OTG_HCINT_ACK_Pos                    (5U)
19258 #define USB_OTG_HCINT_ACK_Msk                    (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
19259 #define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
19260 #define USB_OTG_HCINT_NYET_Pos                   (6U)
19261 #define USB_OTG_HCINT_NYET_Msk                   (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
19262 #define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
19263 #define USB_OTG_HCINT_TXERR_Pos                  (7U)
19264 #define USB_OTG_HCINT_TXERR_Msk                  (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
19265 #define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
19266 #define USB_OTG_HCINT_BBERR_Pos                  (8U)
19267 #define USB_OTG_HCINT_BBERR_Msk                  (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
19268 #define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
19269 #define USB_OTG_HCINT_FRMOR_Pos                  (9U)
19270 #define USB_OTG_HCINT_FRMOR_Msk                  (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
19271 #define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
19272 #define USB_OTG_HCINT_DTERR_Pos                  (10U)
19273 #define USB_OTG_HCINT_DTERR_Msk                  (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
19274 #define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
19275 
19276 /********************  Bit definition for USB_OTG_DIEPINT register  ********************/
19277 #define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
19278 #define USB_OTG_DIEPINT_XFRC_Msk                 (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
19279 #define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
19280 #define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
19281 #define USB_OTG_DIEPINT_EPDISD_Msk               (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
19282 #define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
19283 #define USB_OTG_DIEPINT_TOC_Pos                  (3U)
19284 #define USB_OTG_DIEPINT_TOC_Msk                  (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
19285 #define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
19286 #define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
19287 #define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
19288 #define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
19289 #define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
19290 #define USB_OTG_DIEPINT_INEPNE_Msk               (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
19291 #define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
19292 #define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
19293 #define USB_OTG_DIEPINT_TXFE_Msk                 (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
19294 #define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
19295 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
19296 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
19297 #define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
19298 #define USB_OTG_DIEPINT_BNA_Pos                  (9U)
19299 #define USB_OTG_DIEPINT_BNA_Msk                  (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
19300 #define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
19301 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
19302 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
19303 #define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
19304 #define USB_OTG_DIEPINT_BERR_Pos                 (12U)
19305 #define USB_OTG_DIEPINT_BERR_Msk                 (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
19306 #define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
19307 #define USB_OTG_DIEPINT_NAK_Pos                  (13U)
19308 #define USB_OTG_DIEPINT_NAK_Msk                  (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
19309 #define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
19310 
19311 /********************  Bit definition for USB_OTG_HCINTMSK register  ********************/
19312 #define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
19313 #define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
19314 #define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
19315 #define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
19316 #define USB_OTG_HCINTMSK_CHHM_Msk                (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
19317 #define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
19318 #define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
19319 #define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
19320 #define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
19321 #define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
19322 #define USB_OTG_HCINTMSK_STALLM_Msk              (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
19323 #define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
19324 #define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
19325 #define USB_OTG_HCINTMSK_NAKM_Msk                (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
19326 #define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
19327 #define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
19328 #define USB_OTG_HCINTMSK_ACKM_Msk                (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
19329 #define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
19330 #define USB_OTG_HCINTMSK_NYET_Pos                (6U)
19331 #define USB_OTG_HCINTMSK_NYET_Msk                (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
19332 #define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
19333 #define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
19334 #define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
19335 #define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
19336 #define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
19337 #define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
19338 #define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
19339 #define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
19340 #define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
19341 #define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
19342 #define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
19343 #define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
19344 #define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
19345 
19346 /********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
19347 
19348 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
19349 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19350 #define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
19351 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
19352 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19353 #define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
19354 #define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
19355 #define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
19356 #define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
19357 /********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
19358 #define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
19359 #define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19360 #define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
19361 #define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
19362 #define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19363 #define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
19364 #define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
19365 #define USB_OTG_HCTSIZ_DOPING_Msk                (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
19366 #define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
19367 #define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
19368 #define USB_OTG_HCTSIZ_DPID_Msk                  (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
19369 #define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
19370 #define USB_OTG_HCTSIZ_DPID_0                    (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
19371 #define USB_OTG_HCTSIZ_DPID_1                    (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
19372 
19373 /********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
19374 #define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
19375 #define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19376 #define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
19377 
19378 /********************  Bit definition for USB_OTG_HCDMA register  ********************/
19379 #define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
19380 #define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19381 #define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
19382 
19383 /********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
19384 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
19385 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
19386 #define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space avail */
19387 
19388 /********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
19389 #define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
19390 #define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
19391 #define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
19392 #define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
19393 #define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
19394 #define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
19395 
19396 /********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
19397 
19398 #define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
19399 #define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19400 #define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
19401 #define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
19402 #define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19403 #define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
19404 #define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
19405 #define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19406 #define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
19407 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
19408 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19409 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19410 #define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
19411 #define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19412 #define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
19413 #define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
19414 #define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19415 #define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
19416 #define USB_OTG_DOEPCTL_EPTYP_0                  (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19417 #define USB_OTG_DOEPCTL_EPTYP_1                  (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19418 #define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
19419 #define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
19420 #define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
19421 #define USB_OTG_DOEPCTL_STALL_Pos                (21U)
19422 #define USB_OTG_DOEPCTL_STALL_Msk                (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
19423 #define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
19424 #define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
19425 #define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
19426 #define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
19427 #define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
19428 #define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
19429 #define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
19430 #define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
19431 #define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19432 #define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
19433 #define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
19434 #define USB_OTG_DOEPCTL_EPENA_Msk                (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
19435 #define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
19436 
19437 /********************  Bit definition for USB_OTG_DOEPINT register  ********************/
19438 #define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
19439 #define USB_OTG_DOEPINT_XFRC_Msk                 (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
19440 #define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
19441 #define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
19442 #define USB_OTG_DOEPINT_EPDISD_Msk               (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
19443 #define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
19444 #define USB_OTG_DOEPINT_STUP_Pos                 (3U)
19445 #define USB_OTG_DOEPINT_STUP_Msk                 (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
19446 #define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
19447 #define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
19448 #define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
19449 #define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
19450 #define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
19451 #define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
19452 #define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
19453 #define USB_OTG_DOEPINT_NYET_Pos                 (14U)
19454 #define USB_OTG_DOEPINT_NYET_Msk                 (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
19455 #define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
19456 
19457 /********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
19458 
19459 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
19460 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19461 #define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
19462 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
19463 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19464 #define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
19465 
19466 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
19467 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
19468 #define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
19469 #define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
19470 #define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
19471 
19472 /********************  Bit definition for PCGCCTL register  ********************/
19473 #define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
19474 #define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
19475 #define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
19476 #define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
19477 #define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
19478 #define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
19479 #define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
19480 #define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
19481 #define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
19482 
19483 
19484 /**
19485   * @}
19486   */
19487 
19488 /**
19489   * @}
19490   */
19491 
19492 /** @addtogroup Exported_macros
19493   * @{
19494   */
19495 
19496 /******************************* ADC Instances ********************************/
19497 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
19498                                        ((INSTANCE) == ADC2) || \
19499                                        ((INSTANCE) == ADC3))
19500 
19501 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
19502 
19503 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
19504 
19505 /******************************* AES Instances ********************************/
19506 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
19507 
19508 /******************************** CAN Instances ******************************/
19509 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
19510                                        ((INSTANCE) == CAN2))
19511 
19512 /******************************** COMP Instances ******************************/
19513 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
19514                                         ((INSTANCE) == COMP2))
19515 
19516 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
19517 
19518 /******************** COMP Instances with window mode capability **************/
19519 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
19520 
19521 /******************************* CRC Instances ********************************/
19522 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
19523 
19524 /******************************* DAC Instances ********************************/
19525 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
19526 
19527 /****************************** DFSDM Instances *******************************/
19528 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
19529                                                 ((INSTANCE) == DFSDM1_Filter1) || \
19530                                                 ((INSTANCE) == DFSDM1_Filter2) || \
19531                                                 ((INSTANCE) == DFSDM1_Filter3))
19532 
19533 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
19534                                                  ((INSTANCE) == DFSDM1_Channel1) || \
19535                                                  ((INSTANCE) == DFSDM1_Channel2) || \
19536                                                  ((INSTANCE) == DFSDM1_Channel3) || \
19537                                                  ((INSTANCE) == DFSDM1_Channel4) || \
19538                                                  ((INSTANCE) == DFSDM1_Channel5) || \
19539                                                  ((INSTANCE) == DFSDM1_Channel6) || \
19540                                                  ((INSTANCE) == DFSDM1_Channel7))
19541 
19542 /******************************* DCMI Instances *******************************/
19543 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
19544 
19545 /******************************* DMA2D Instances *******************************/
19546 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
19547 
19548 /******************************** DMA Instances *******************************/
19549 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
19550                                        ((INSTANCE) == DMA1_Channel2) || \
19551                                        ((INSTANCE) == DMA1_Channel3) || \
19552                                        ((INSTANCE) == DMA1_Channel4) || \
19553                                        ((INSTANCE) == DMA1_Channel5) || \
19554                                        ((INSTANCE) == DMA1_Channel6) || \
19555                                        ((INSTANCE) == DMA1_Channel7) || \
19556                                        ((INSTANCE) == DMA2_Channel1) || \
19557                                        ((INSTANCE) == DMA2_Channel2) || \
19558                                        ((INSTANCE) == DMA2_Channel3) || \
19559                                        ((INSTANCE) == DMA2_Channel4) || \
19560                                        ((INSTANCE) == DMA2_Channel5) || \
19561                                        ((INSTANCE) == DMA2_Channel6) || \
19562                                        ((INSTANCE) == DMA2_Channel7))
19563 
19564 /******************************* GPIO Instances *******************************/
19565 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
19566                                         ((INSTANCE) == GPIOB) || \
19567                                         ((INSTANCE) == GPIOC) || \
19568                                         ((INSTANCE) == GPIOD) || \
19569                                         ((INSTANCE) == GPIOE) || \
19570                                         ((INSTANCE) == GPIOF) || \
19571                                         ((INSTANCE) == GPIOG) || \
19572                                         ((INSTANCE) == GPIOH) || \
19573                                         ((INSTANCE) == GPIOI))
19574 
19575 /******************************* GPIO AF Instances ****************************/
19576 /* On L4, all GPIO Bank support AF */
19577 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
19578 
19579 /**************************** GPIO Lock Instances *****************************/
19580 /* On L4, all GPIO Bank support the Lock mechanism */
19581 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
19582 
19583 /******************************** I2C Instances *******************************/
19584 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
19585                                        ((INSTANCE) == I2C2) || \
19586                                        ((INSTANCE) == I2C3) || \
19587                                        ((INSTANCE) == I2C4))
19588 
19589 /****************** I2C Instances : wakeup capability from stop modes *********/
19590 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
19591 
19592 /******************************* LCD Instances ********************************/
19593 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
19594 
19595 /******************************* HCD Instances *******************************/
19596 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
19597 
19598 /****************************** OPAMP Instances *******************************/
19599 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
19600                                          ((INSTANCE) == OPAMP2))
19601 
19602 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
19603 
19604 /******************************* PCD Instances *******************************/
19605 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
19606 
19607 /******************************* QSPI Instances *******************************/
19608 #define IS_QSPI_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == QUADSPI)
19609 
19610 /******************************* RNG Instances ********************************/
19611 #define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
19612 
19613 /****************************** RTC Instances *********************************/
19614 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
19615 
19616 /******************************** SAI Instances *******************************/
19617 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
19618                                        ((INSTANCE) == SAI1_Block_B) || \
19619                                        ((INSTANCE) == SAI2_Block_A) || \
19620                                        ((INSTANCE) == SAI2_Block_B))
19621 
19622 /****************************** SDMMC Instances *******************************/
19623 #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
19624 
19625 /****************************** SMBUS Instances *******************************/
19626 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
19627                                          ((INSTANCE) == I2C2) || \
19628                                          ((INSTANCE) == I2C3) || \
19629                                          ((INSTANCE) == I2C4))
19630 
19631 /******************************** SPI Instances *******************************/
19632 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
19633                                        ((INSTANCE) == SPI2) || \
19634                                        ((INSTANCE) == SPI3))
19635 
19636 /******************************** SWPMI Instances *****************************/
19637 #define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
19638 
19639 /****************** LPTIM Instances : All supported instances *****************/
19640 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
19641                                          ((INSTANCE) == LPTIM2))
19642 
19643 /****************** TIM Instances : All supported instances *******************/
19644 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
19645                                          ((INSTANCE) == TIM2)   || \
19646                                          ((INSTANCE) == TIM3)   || \
19647                                          ((INSTANCE) == TIM4)   || \
19648                                          ((INSTANCE) == TIM5)   || \
19649                                          ((INSTANCE) == TIM6)   || \
19650                                          ((INSTANCE) == TIM7)   || \
19651                                          ((INSTANCE) == TIM8)   || \
19652                                          ((INSTANCE) == TIM15)  || \
19653                                          ((INSTANCE) == TIM16)  || \
19654                                          ((INSTANCE) == TIM17))
19655 
19656 /****************** TIM Instances : supporting 32 bits counter ****************/
19657 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
19658                                                ((INSTANCE) == TIM5))
19659 
19660 /****************** TIM Instances : supporting the break function *************/
19661 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
19662                                             ((INSTANCE) == TIM8)    || \
19663                                             ((INSTANCE) == TIM15)   || \
19664                                             ((INSTANCE) == TIM16)   || \
19665                                             ((INSTANCE) == TIM17))
19666 
19667 /************** TIM Instances : supporting Break source selection *************/
19668 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
19669                                                ((INSTANCE) == TIM8)   || \
19670                                                ((INSTANCE) == TIM15)  || \
19671                                                ((INSTANCE) == TIM16)  || \
19672                                                ((INSTANCE) == TIM17))
19673 
19674 /****************** TIM Instances : supporting 2 break inputs *****************/
19675 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
19676                                             ((INSTANCE) == TIM8))
19677 
19678 /************* TIM Instances : at least 1 capture/compare channel *************/
19679 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
19680                                          ((INSTANCE) == TIM2)   || \
19681                                          ((INSTANCE) == TIM3)   || \
19682                                          ((INSTANCE) == TIM4)   || \
19683                                          ((INSTANCE) == TIM5)   || \
19684                                          ((INSTANCE) == TIM8)   || \
19685                                          ((INSTANCE) == TIM15)  || \
19686                                          ((INSTANCE) == TIM16)  || \
19687                                          ((INSTANCE) == TIM17))
19688 
19689 /************ TIM Instances : at least 2 capture/compare channels *************/
19690 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
19691                                          ((INSTANCE) == TIM2)   || \
19692                                          ((INSTANCE) == TIM3)   || \
19693                                          ((INSTANCE) == TIM4)   || \
19694                                          ((INSTANCE) == TIM5)   || \
19695                                          ((INSTANCE) == TIM8)   || \
19696                                          ((INSTANCE) == TIM15))
19697 
19698 /************ TIM Instances : at least 3 capture/compare channels *************/
19699 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
19700                                          ((INSTANCE) == TIM2)   || \
19701                                          ((INSTANCE) == TIM3)   || \
19702                                          ((INSTANCE) == TIM4)   || \
19703                                          ((INSTANCE) == TIM5)   || \
19704                                          ((INSTANCE) == TIM8))
19705 
19706 /************ TIM Instances : at least 4 capture/compare channels *************/
19707 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
19708                                          ((INSTANCE) == TIM2)   || \
19709                                          ((INSTANCE) == TIM3)   || \
19710                                          ((INSTANCE) == TIM4)   || \
19711                                          ((INSTANCE) == TIM5)   || \
19712                                          ((INSTANCE) == TIM8))
19713 
19714 /****************** TIM Instances : at least 5 capture/compare channels *******/
19715 #define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
19716                                          ((INSTANCE) == TIM8))
19717 
19718 /****************** TIM Instances : at least 6 capture/compare channels *******/
19719 #define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
19720                                          ((INSTANCE) == TIM8))
19721 
19722 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
19723 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
19724                                             ((INSTANCE) == TIM8)   || \
19725                                             ((INSTANCE) == TIM15)  || \
19726                                             ((INSTANCE) == TIM16)  || \
19727                                             ((INSTANCE) == TIM17))
19728 
19729 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
19730 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
19731                                             ((INSTANCE) == TIM2)   || \
19732                                             ((INSTANCE) == TIM3)   || \
19733                                             ((INSTANCE) == TIM4)   || \
19734                                             ((INSTANCE) == TIM5)   || \
19735                                             ((INSTANCE) == TIM6)   || \
19736                                             ((INSTANCE) == TIM7)   || \
19737                                             ((INSTANCE) == TIM8)   || \
19738                                             ((INSTANCE) == TIM15)  || \
19739                                             ((INSTANCE) == TIM16)  || \
19740                                             ((INSTANCE) == TIM17))
19741 
19742 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
19743 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
19744                                             ((INSTANCE) == TIM2)   || \
19745                                             ((INSTANCE) == TIM3)   || \
19746                                             ((INSTANCE) == TIM4)   || \
19747                                             ((INSTANCE) == TIM5)   || \
19748                                             ((INSTANCE) == TIM8)   || \
19749                                             ((INSTANCE) == TIM15)  || \
19750                                             ((INSTANCE) == TIM16)  || \
19751                                             ((INSTANCE) == TIM17))
19752 
19753 /******************** TIM Instances : DMA burst feature ***********************/
19754 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
19755                                             ((INSTANCE) == TIM2)   || \
19756                                             ((INSTANCE) == TIM3)   || \
19757                                             ((INSTANCE) == TIM4)   || \
19758                                             ((INSTANCE) == TIM5)   || \
19759                                             ((INSTANCE) == TIM8)   || \
19760                                             ((INSTANCE) == TIM15)  || \
19761                                             ((INSTANCE) == TIM16)  || \
19762                                             ((INSTANCE) == TIM17))
19763 
19764 /******************* TIM Instances : output(s) available **********************/
19765 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
19766     ((((INSTANCE) == TIM1) &&                  \
19767      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19768       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19769       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19770       ((CHANNEL) == TIM_CHANNEL_4) ||          \
19771       ((CHANNEL) == TIM_CHANNEL_5) ||          \
19772       ((CHANNEL) == TIM_CHANNEL_6)))           \
19773      ||                                        \
19774      (((INSTANCE) == TIM2) &&                  \
19775      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19776       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19777       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19778       ((CHANNEL) == TIM_CHANNEL_4)))           \
19779      ||                                        \
19780      (((INSTANCE) == TIM3) &&                  \
19781      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19782       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19783       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19784       ((CHANNEL) == TIM_CHANNEL_4)))           \
19785      ||                                        \
19786      (((INSTANCE) == TIM4) &&                  \
19787      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19788       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19789       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19790       ((CHANNEL) == TIM_CHANNEL_4)))           \
19791      ||                                        \
19792      (((INSTANCE) == TIM5) &&                  \
19793      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19794       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19795       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19796       ((CHANNEL) == TIM_CHANNEL_4)))           \
19797      ||                                        \
19798      (((INSTANCE) == TIM8) &&                  \
19799      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19800       ((CHANNEL) == TIM_CHANNEL_2) ||          \
19801       ((CHANNEL) == TIM_CHANNEL_3) ||          \
19802       ((CHANNEL) == TIM_CHANNEL_4) ||          \
19803       ((CHANNEL) == TIM_CHANNEL_5) ||          \
19804       ((CHANNEL) == TIM_CHANNEL_6)))           \
19805      ||                                        \
19806      (((INSTANCE) == TIM15) &&                 \
19807      (((CHANNEL) == TIM_CHANNEL_1) ||          \
19808       ((CHANNEL) == TIM_CHANNEL_2)))           \
19809      ||                                        \
19810      (((INSTANCE) == TIM16) &&                 \
19811      (((CHANNEL) == TIM_CHANNEL_1)))           \
19812      ||                                        \
19813      (((INSTANCE) == TIM17) &&                 \
19814       (((CHANNEL) == TIM_CHANNEL_1))))
19815 
19816 /****************** TIM Instances : supporting complementary output(s) ********/
19817 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
19818    ((((INSTANCE) == TIM1) &&                    \
19819      (((CHANNEL) == TIM_CHANNEL_1) ||           \
19820       ((CHANNEL) == TIM_CHANNEL_2) ||           \
19821       ((CHANNEL) == TIM_CHANNEL_3)))            \
19822     ||                                          \
19823     (((INSTANCE) == TIM8) &&                    \
19824      (((CHANNEL) == TIM_CHANNEL_1) ||           \
19825       ((CHANNEL) == TIM_CHANNEL_2) ||           \
19826       ((CHANNEL) == TIM_CHANNEL_3)))            \
19827     ||                                          \
19828     (((INSTANCE) == TIM15) &&                   \
19829      ((CHANNEL) == TIM_CHANNEL_1))              \
19830     ||                                          \
19831     (((INSTANCE) == TIM16) &&                   \
19832      ((CHANNEL) == TIM_CHANNEL_1))              \
19833     ||                                          \
19834     (((INSTANCE) == TIM17) &&                   \
19835      ((CHANNEL) == TIM_CHANNEL_1)))
19836 
19837 /****************** TIM Instances : supporting clock division *****************/
19838 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
19839                                                     ((INSTANCE) == TIM2)    || \
19840                                                     ((INSTANCE) == TIM3)    || \
19841                                                     ((INSTANCE) == TIM4)    || \
19842                                                     ((INSTANCE) == TIM5)    || \
19843                                                     ((INSTANCE) == TIM8)    || \
19844                                                     ((INSTANCE) == TIM15)   || \
19845                                                     ((INSTANCE) == TIM16)   || \
19846                                                     ((INSTANCE) == TIM17))
19847 
19848 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
19849 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19850                                                         ((INSTANCE) == TIM2) || \
19851                                                         ((INSTANCE) == TIM3) || \
19852                                                         ((INSTANCE) == TIM4) || \
19853                                                         ((INSTANCE) == TIM5) || \
19854                                                         ((INSTANCE) == TIM8) || \
19855                                                         ((INSTANCE) == TIM15))
19856 
19857 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
19858 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19859                                                         ((INSTANCE) == TIM2) || \
19860                                                         ((INSTANCE) == TIM3) || \
19861                                                         ((INSTANCE) == TIM4) || \
19862                                                         ((INSTANCE) == TIM5) || \
19863                                                         ((INSTANCE) == TIM8))
19864 
19865 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
19866 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
19867                                                         ((INSTANCE) == TIM2) || \
19868                                                         ((INSTANCE) == TIM3) || \
19869                                                         ((INSTANCE) == TIM4) || \
19870                                                         ((INSTANCE) == TIM5) || \
19871                                                         ((INSTANCE) == TIM8) || \
19872                                                         ((INSTANCE) == TIM15))
19873 
19874 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
19875 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
19876                                                         ((INSTANCE) == TIM2) || \
19877                                                         ((INSTANCE) == TIM3) || \
19878                                                         ((INSTANCE) == TIM4) || \
19879                                                         ((INSTANCE) == TIM5) || \
19880                                                         ((INSTANCE) == TIM8) || \
19881                                                         ((INSTANCE) == TIM15))
19882 
19883 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
19884 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
19885                                                      ((INSTANCE) == TIM8))
19886 
19887 /****************** TIM Instances : supporting commutation event generation ***/
19888 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
19889                                                      ((INSTANCE) == TIM8)   || \
19890                                                      ((INSTANCE) == TIM15)  || \
19891                                                      ((INSTANCE) == TIM16)  || \
19892                                                      ((INSTANCE) == TIM17))
19893 
19894 /****************** TIM Instances : supporting counting mode selection ********/
19895 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
19896                                                         ((INSTANCE) == TIM2) || \
19897                                                         ((INSTANCE) == TIM3) || \
19898                                                         ((INSTANCE) == TIM4) || \
19899                                                         ((INSTANCE) == TIM5) || \
19900                                                         ((INSTANCE) == TIM8))
19901 
19902 /****************** TIM Instances : supporting encoder interface **************/
19903 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
19904                                                       ((INSTANCE) == TIM2)  || \
19905                                                       ((INSTANCE) == TIM3)  || \
19906                                                       ((INSTANCE) == TIM4)  || \
19907                                                       ((INSTANCE) == TIM5)  || \
19908                                                       ((INSTANCE) == TIM8))
19909 
19910 /****************** TIM Instances : supporting Hall sensor interface **********/
19911 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
19912                                                          ((INSTANCE) == TIM2)   || \
19913                                                          ((INSTANCE) == TIM3)   || \
19914                                                          ((INSTANCE) == TIM4)   || \
19915                                                          ((INSTANCE) == TIM5)   || \
19916                                                          ((INSTANCE) == TIM8))
19917 
19918 /**************** TIM Instances : external trigger input available ************/
19919 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
19920                                             ((INSTANCE) == TIM2)  || \
19921                                             ((INSTANCE) == TIM3)  || \
19922                                             ((INSTANCE) == TIM4)  || \
19923                                             ((INSTANCE) == TIM5)  || \
19924                                             ((INSTANCE) == TIM8))
19925 
19926 /************* TIM Instances : supporting ETR source selection ***************/
19927 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
19928                                              ((INSTANCE) == TIM2)  || \
19929                                              ((INSTANCE) == TIM3)  || \
19930                                              ((INSTANCE) == TIM8))
19931 
19932 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
19933 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
19934                                             ((INSTANCE) == TIM2)  || \
19935                                             ((INSTANCE) == TIM3)  || \
19936                                             ((INSTANCE) == TIM4)  || \
19937                                             ((INSTANCE) == TIM5)  || \
19938                                             ((INSTANCE) == TIM6)  || \
19939                                             ((INSTANCE) == TIM7)  || \
19940                                             ((INSTANCE) == TIM8)  || \
19941                                             ((INSTANCE) == TIM15))
19942 
19943 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
19944 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
19945                                             ((INSTANCE) == TIM2)  || \
19946                                             ((INSTANCE) == TIM3)  || \
19947                                             ((INSTANCE) == TIM4)  || \
19948                                             ((INSTANCE) == TIM5)  || \
19949                                             ((INSTANCE) == TIM8)  || \
19950                                             ((INSTANCE) == TIM15))
19951 
19952 /****************** TIM Instances : supporting OCxREF clear *******************/
19953 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
19954                                                        ((INSTANCE) == TIM2) || \
19955                                                        ((INSTANCE) == TIM3) || \
19956                                                        ((INSTANCE) == TIM4) || \
19957                                                        ((INSTANCE) == TIM5) || \
19958                                                        ((INSTANCE) == TIM8))
19959 
19960 /****************** TIM Instances : remapping capability **********************/
19961 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
19962                                             ((INSTANCE) == TIM2)  || \
19963                                             ((INSTANCE) == TIM3)  || \
19964                                             ((INSTANCE) == TIM8)  || \
19965                                             ((INSTANCE) == TIM15) || \
19966                                             ((INSTANCE) == TIM16) || \
19967                                             ((INSTANCE) == TIM17))
19968 
19969 /****************** TIM Instances : supporting repetition counter *************/
19970 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
19971                                                        ((INSTANCE) == TIM8)  || \
19972                                                        ((INSTANCE) == TIM15) || \
19973                                                        ((INSTANCE) == TIM16) || \
19974                                                        ((INSTANCE) == TIM17))
19975 
19976 /****************** TIM Instances : supporting synchronization ****************/
19977 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)  IS_TIM_MASTER_INSTANCE(INSTANCE)
19978 
19979 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
19980 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
19981                                             ((INSTANCE) == TIM8))
19982 
19983 /******************* TIM Instances : Timer input XOR function *****************/
19984 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
19985                                             ((INSTANCE) == TIM2)   || \
19986                                             ((INSTANCE) == TIM3)   || \
19987                                             ((INSTANCE) == TIM4)   || \
19988                                             ((INSTANCE) == TIM5)   || \
19989                                             ((INSTANCE) == TIM8)   || \
19990                                             ((INSTANCE) == TIM15))
19991 
19992 /****************** TIM Instances : Advanced timer instances *******************/
19993 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
19994                                                   ((INSTANCE) == TIM8))
19995 
19996 /****************************** TSC Instances *********************************/
19997 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
19998 
19999 /******************** USART Instances : Synchronous mode **********************/
20000 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20001                                      ((INSTANCE) == USART2) || \
20002                                      ((INSTANCE) == USART3))
20003 
20004 /******************** UART Instances : Asynchronous mode **********************/
20005 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20006                                     ((INSTANCE) == USART2) || \
20007                                     ((INSTANCE) == USART3) || \
20008                                     ((INSTANCE) == UART4)  || \
20009                                     ((INSTANCE) == UART5))
20010 
20011 /****************** UART Instances : Auto Baud Rate detection ****************/
20012 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20013                                                             ((INSTANCE) == USART2) || \
20014                                                             ((INSTANCE) == USART3) || \
20015                                                             ((INSTANCE) == UART4)  || \
20016                                                             ((INSTANCE) == UART5))
20017 
20018 /****************** UART Instances : Driver Enable *****************/
20019 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
20020                                                       ((INSTANCE) == USART2) || \
20021                                                       ((INSTANCE) == USART3) || \
20022                                                       ((INSTANCE) == UART4)  || \
20023                                                       ((INSTANCE) == UART5)  || \
20024                                                       ((INSTANCE) == LPUART1))
20025 
20026 /******************** UART Instances : Half-Duplex mode **********************/
20027 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
20028                                                  ((INSTANCE) == USART2) || \
20029                                                  ((INSTANCE) == USART3) || \
20030                                                  ((INSTANCE) == UART4)  || \
20031                                                  ((INSTANCE) == UART5)  || \
20032                                                  ((INSTANCE) == LPUART1))
20033 
20034 /****************** UART Instances : Hardware Flow control ********************/
20035 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20036                                            ((INSTANCE) == USART2) || \
20037                                            ((INSTANCE) == USART3) || \
20038                                            ((INSTANCE) == UART4)  || \
20039                                            ((INSTANCE) == UART5)  || \
20040                                            ((INSTANCE) == LPUART1))
20041 
20042 /******************** UART Instances : LIN mode **********************/
20043 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
20044                                           ((INSTANCE) == USART2) || \
20045                                           ((INSTANCE) == USART3) || \
20046                                           ((INSTANCE) == UART4)  || \
20047                                           ((INSTANCE) == UART5))
20048 
20049 /******************** UART Instances : Wake-up from Stop mode **********************/
20050 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
20051                                                       ((INSTANCE) == USART2) || \
20052                                                       ((INSTANCE) == USART3) || \
20053                                                       ((INSTANCE) == UART4)  || \
20054                                                       ((INSTANCE) == UART5)  || \
20055                                                       ((INSTANCE) == LPUART1))
20056 
20057 /*********************** UART Instances : IRDA mode ***************************/
20058 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20059                                     ((INSTANCE) == USART2) || \
20060                                     ((INSTANCE) == USART3) || \
20061                                     ((INSTANCE) == UART4)  || \
20062                                     ((INSTANCE) == UART5))
20063 
20064 /********************* USART Instances : Smard card mode ***********************/
20065 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20066                                          ((INSTANCE) == USART2) || \
20067                                          ((INSTANCE) == USART3))
20068 
20069 /******************** LPUART Instance *****************************************/
20070 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
20071 
20072 /****************************** IWDG Instances ********************************/
20073 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
20074 
20075 /****************************** WWDG Instances ********************************/
20076 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
20077 
20078 /**
20079   * @}
20080   */
20081 
20082 
20083 /******************************************************************************/
20084 /*  For a painless codes migration between the STM32L4xx device product       */
20085 /*  lines, the aliases defined below are put in place to overcome the         */
20086 /*  differences in the interrupt handlers and IRQn definitions.               */
20087 /*  No need to update developed interrupt code when moving across             */
20088 /*  product lines within the same STM32L4 Family                              */
20089 /******************************************************************************/
20090 
20091 /* Aliases for __IRQn */
20092 #define ADC1_IRQn                      ADC1_2_IRQn
20093 #define TIM1_TRG_COM_IRQn              TIM1_TRG_COM_TIM17_IRQn
20094 #define TIM8_IRQn                      TIM8_UP_IRQn
20095 #define RNG_IRQn                       HASH_RNG_IRQn
20096 #define HASH_CRS_IRQn                  CRS_IRQn
20097 #define DFSDM0_IRQn                    DFSDM1_FLT0_IRQn
20098 #define DFSDM1_IRQn                    DFSDM1_FLT1_IRQn
20099 #define DFSDM2_IRQn                    DFSDM1_FLT2_IRQn
20100 #define DFSDM3_IRQn                    DFSDM1_FLT3_IRQn
20101 
20102 /* Aliases for __IRQHandler */
20103 #define ADC1_IRQHandler                ADC1_2_IRQHandler
20104 #define TIM1_TRG_COM_IRQHandler        TIM1_TRG_COM_TIM17_IRQHandler
20105 #define TIM8_IRQHandler                TIM8_UP_IRQHandler
20106 #define RNG_IRQHandler                 HASH_RNG_IRQHandler
20107 #define HASH_CRS_IRQHandler            CRS_IRQHandler
20108 #define DFSDM0_IRQHandler              DFSDM1_FLT0_IRQHandler
20109 #define DFSDM1_IRQHandler              DFSDM1_FLT1_IRQHandler
20110 #define DFSDM2_IRQHandler              DFSDM1_FLT2_IRQHandler
20111 #define DFSDM3_IRQHandler              DFSDM1_FLT3_IRQHandler
20112 
20113 #ifdef __cplusplus
20114 }
20115 #endif /* __cplusplus */
20116 
20117 #endif /* __STM32L4A6xx_H */
20118 
20119 /**
20120   * @}
20121   */
20122 
20123   /**
20124   * @}
20125   */
20126 
20127 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
20128