| /external/llvm/lib/Target/X86/ |
| D | X86MachineFunctionInfo.cpp | 23 for (const MCPhysReg *CSR = in setRestoreBasePointer() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86MachineFunctionInfo.cpp | 23 for (const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs(); in setRestoreBasePointer() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 58 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs(); in runOnMachineFunction() local
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| D | LiveRegUnits.cpp | 88 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) in addCalleeSavedRegs() local
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| D | MachineFrameInfo.cpp | 124 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; in getPristineRegs() local
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| D | LivePhysRegs.cpp | 175 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) in addCalleeSavedRegs() local
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| D | MachineRegisterInfo.cpp | 620 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in disableCalleeSavedRegister() local
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| D | RegAllocPBQP.cpp | 570 const MCPhysReg *CSR = MF.getRegInfo().getCalleeSavedRegs(); in isACalleeSavedRegister() local
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| D | RegAllocGreedy.cpp | 1095 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg() local
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| /external/llvm/lib/CodeGen/ |
| D | RegisterClassInfo.cpp | 51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction() local
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| D | LivePhysRegs.cpp | 154 for (const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in addPristines() local
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| D | MachineFunction.cpp | 662 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in getPristineRegs() local
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| D | RegAllocPBQP.cpp | 554 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF); in isACalleeSavedRegister() local
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| D | RegAllocGreedy.cpp | 847 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); in isUnusedCalleeSavedReg() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonGenExtract.cpp | 100 ConstantInt *CSL = nullptr, *CSR = nullptr, *CM = nullptr; in INITIALIZE_PASS_DEPENDENCY() local
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| D | HexagonVLIWPacketizer.cpp | 345 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in doesModifyCalleeSavedReg() local
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| D | HexagonFrameLowering.cpp | 282 static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, in needsStackFrame()
435 BitVector CSR(Hexagon::NUM_TARGET_REGS); in findShrunkPrologEpilog() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenExtract.cpp | 87 ConstantInt *CSL = 0, *CSR = 0, *CM = 0; in INITIALIZE_PASS_DEPENDENCY() local
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| D | HexagonVLIWPacketizer.cpp | 319 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR) in doesModifyCalleeSavedReg() local
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| D | HexagonFrameLowering.cpp | 241 bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, in needsStackFrame()
376 BitVector CSR(Hexagon::NUM_TARGET_REGS); in findShrunkPrologEpilog() local
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| /external/perfetto/src/trace_processor/prelude/functions/ |
| D | to_ftrace.cc | 231 using CSR = protos::pbzero::ClockSetRateFtraceEvent; in SerializeArgs() typedef
238 using CSR = protos::pbzero::ClkSetRateFtraceEvent; in SerializeArgs() typedef
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| /external/llvm/include/llvm/ADT/ |
| D | Triple.h | 134 CSR, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ADT/ |
| D | Triple.h | 149 CSR, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
| D | FunctionComparator.cpp | 573 auto CSR = CallSite(const_cast<Instruction *>(R)); in cmpOperations() local
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| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ |
| D | stm32l4a6xx.h | 248 …__IO uint32_t CSR; /*!< ADC common status register, Address offset: AD… member
344 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ member
349 …__IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several … member
702 …__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset:… member
709 …__IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPA… member
812 …__IO uint32_t CSR; /*!< RCC clock control & status register, … member
1067 …__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 … member
1127 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ member
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