1 //===- llvm/InlineAsm.h - Class to represent inline asm strings -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This class represents the inline asm strings, which are Value*'s that are 10 // used as the callee operand of call instructions. InlineAsm's are uniqued 11 // like constants, and created via InlineAsm::get(...). 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_IR_INLINEASM_H 16 #define LLVM_IR_INLINEASM_H 17 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/IR/Value.h" 20 #include <cassert> 21 #include <string> 22 #include <vector> 23 24 namespace llvm { 25 26 class FunctionType; 27 class PointerType; 28 template <class ConstantClass> class ConstantUniqueMap; 29 30 class InlineAsm final : public Value { 31 public: 32 enum AsmDialect { 33 AD_ATT, 34 AD_Intel 35 }; 36 37 private: 38 friend struct InlineAsmKeyType; 39 friend class ConstantUniqueMap<InlineAsm>; 40 41 std::string AsmString, Constraints; 42 FunctionType *FTy; 43 bool HasSideEffects; 44 bool IsAlignStack; 45 AsmDialect Dialect; 46 47 InlineAsm(FunctionType *Ty, const std::string &AsmString, 48 const std::string &Constraints, bool hasSideEffects, 49 bool isAlignStack, AsmDialect asmDialect); 50 51 /// When the ConstantUniqueMap merges two types and makes two InlineAsms 52 /// identical, it destroys one of them with this method. 53 void destroyConstant(); 54 55 public: 56 InlineAsm(const InlineAsm &) = delete; 57 InlineAsm &operator=(const InlineAsm &) = delete; 58 59 /// InlineAsm::get - Return the specified uniqued inline asm string. 60 /// 61 static InlineAsm *get(FunctionType *Ty, StringRef AsmString, 62 StringRef Constraints, bool hasSideEffects, 63 bool isAlignStack = false, 64 AsmDialect asmDialect = AD_ATT); 65 hasSideEffects()66 bool hasSideEffects() const { return HasSideEffects; } isAlignStack()67 bool isAlignStack() const { return IsAlignStack; } getDialect()68 AsmDialect getDialect() const { return Dialect; } 69 70 /// getType - InlineAsm's are always pointers. 71 /// getType()72 PointerType *getType() const { 73 return reinterpret_cast<PointerType*>(Value::getType()); 74 } 75 76 /// getFunctionType - InlineAsm's are always pointers to functions. 77 /// 78 FunctionType *getFunctionType() const; 79 getAsmString()80 const std::string &getAsmString() const { return AsmString; } getConstraintString()81 const std::string &getConstraintString() const { return Constraints; } 82 83 /// Verify - This static method can be used by the parser to check to see if 84 /// the specified constraint string is legal for the type. This returns true 85 /// if legal, false if not. 86 /// 87 static bool Verify(FunctionType *Ty, StringRef Constraints); 88 89 // Constraint String Parsing 90 enum ConstraintPrefix { 91 isInput, // 'x' 92 isOutput, // '=x' 93 isClobber // '~x' 94 }; 95 96 using ConstraintCodeVector = std::vector<std::string>; 97 98 struct SubConstraintInfo { 99 /// MatchingInput - If this is not -1, this is an output constraint where an 100 /// input constraint is required to match it (e.g. "0"). The value is the 101 /// constraint number that matches this one (for example, if this is 102 /// constraint #0 and constraint #4 has the value "0", this will be 4). 103 int MatchingInput = -1; 104 105 /// Code - The constraint code, either the register name (in braces) or the 106 /// constraint letter/number. 107 ConstraintCodeVector Codes; 108 109 /// Default constructor. 110 SubConstraintInfo() = default; 111 }; 112 113 using SubConstraintInfoVector = std::vector<SubConstraintInfo>; 114 struct ConstraintInfo; 115 using ConstraintInfoVector = std::vector<ConstraintInfo>; 116 117 struct ConstraintInfo { 118 /// Type - The basic type of the constraint: input/output/clobber 119 /// 120 ConstraintPrefix Type = isInput; 121 122 /// isEarlyClobber - "&": output operand writes result before inputs are all 123 /// read. This is only ever set for an output operand. 124 bool isEarlyClobber = false; 125 126 /// MatchingInput - If this is not -1, this is an output constraint where an 127 /// input constraint is required to match it (e.g. "0"). The value is the 128 /// constraint number that matches this one (for example, if this is 129 /// constraint #0 and constraint #4 has the value "0", this will be 4). 130 int MatchingInput = -1; 131 132 /// hasMatchingInput - Return true if this is an output constraint that has 133 /// a matching input constraint. hasMatchingInputConstraintInfo134 bool hasMatchingInput() const { return MatchingInput != -1; } 135 136 /// isCommutative - This is set to true for a constraint that is commutative 137 /// with the next operand. 138 bool isCommutative = false; 139 140 /// isIndirect - True if this operand is an indirect operand. This means 141 /// that the address of the source or destination is present in the call 142 /// instruction, instead of it being returned or passed in explicitly. This 143 /// is represented with a '*' in the asm string. 144 bool isIndirect = false; 145 146 /// Code - The constraint code, either the register name (in braces) or the 147 /// constraint letter/number. 148 ConstraintCodeVector Codes; 149 150 /// isMultipleAlternative - '|': has multiple-alternative constraints. 151 bool isMultipleAlternative = false; 152 153 /// multipleAlternatives - If there are multiple alternative constraints, 154 /// this array will contain them. Otherwise it will be empty. 155 SubConstraintInfoVector multipleAlternatives; 156 157 /// The currently selected alternative constraint index. 158 unsigned currentAlternativeIndex = 0; 159 160 /// Default constructor. 161 ConstraintInfo() = default; 162 163 /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the 164 /// fields in this structure. If the constraint string is not understood, 165 /// return true, otherwise return false. 166 bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar); 167 168 /// selectAlternative - Point this constraint to the alternative constraint 169 /// indicated by the index. 170 void selectAlternative(unsigned index); 171 }; 172 173 /// ParseConstraints - Split up the constraint string into the specific 174 /// constraints and their prefixes. If this returns an empty vector, and if 175 /// the constraint string itself isn't empty, there was an error parsing. 176 static ConstraintInfoVector ParseConstraints(StringRef ConstraintString); 177 178 /// ParseConstraints - Parse the constraints of this inlineasm object, 179 /// returning them the same way that ParseConstraints(str) does. ParseConstraints()180 ConstraintInfoVector ParseConstraints() const { 181 return ParseConstraints(Constraints); 182 } 183 184 // Methods for support type inquiry through isa, cast, and dyn_cast: classof(const Value * V)185 static bool classof(const Value *V) { 186 return V->getValueID() == Value::InlineAsmVal; 187 } 188 189 // These are helper methods for dealing with flags in the INLINEASM SDNode 190 // in the backend. 191 // 192 // The encoding of the flag word is currently: 193 // Bits 2-0 - A Kind_* value indicating the kind of the operand. 194 // Bits 15-3 - The number of SDNode operands associated with this inline 195 // assembly operand. 196 // If bit 31 is set: 197 // Bit 30-16 - The operand number that this operand must match. 198 // When bits 2-0 are Kind_Mem, the Constraint_* value must be 199 // obtained from the flags for this operand number. 200 // Else if bits 2-0 are Kind_Mem: 201 // Bit 30-16 - A Constraint_* value indicating the original constraint 202 // code. 203 // Else: 204 // Bit 30-16 - The register class ID to use for the operand. 205 206 // Fixed operands on an INLINEASM SDNode. 207 static constexpr uint32_t Op_InputChain = 0; 208 static constexpr uint32_t Op_AsmString = 1; 209 static constexpr uint32_t Op_MDNode = 2; 210 static constexpr uint32_t Op_ExtraInfo = 3; // HasSideEffects, IsAlignStack, 211 // AsmDialect. 212 static constexpr uint32_t Op_FirstOperand = 4; 213 214 // Fixed operands on an INLINEASM MachineInstr. 215 static constexpr uint32_t MIOp_AsmString = 0; 216 static constexpr uint32_t MIOp_ExtraInfo = 1; // HasSideEffects, 217 // IsAlignStack, AsmDialect. 218 static constexpr uint32_t MIOp_FirstOperand = 2; 219 220 // Interpretation of the MIOp_ExtraInfo bit field. 221 static constexpr uint32_t Extra_HasSideEffects = 1; 222 static constexpr uint32_t Extra_IsAlignStack = 2; 223 static constexpr uint32_t Extra_AsmDialect = 4; 224 static constexpr uint32_t Extra_MayLoad = 8; 225 static constexpr uint32_t Extra_MayStore = 16; 226 static constexpr uint32_t Extra_IsConvergent = 32; 227 228 // Inline asm operands map to multiple SDNode / MachineInstr operands. 229 // The first operand is an immediate describing the asm operand, the low 230 // bits is the kind: 231 static constexpr uint32_t Kind_RegUse = 1; // Input register, "r". 232 static constexpr uint32_t Kind_RegDef = 2; // Output register, "=r". 233 static constexpr uint32_t Kind_RegDefEarlyClobber = 3; 234 // Early-clobber output register, 235 // "=&r". 236 static constexpr uint32_t Kind_Clobber = 4; // Clobbered register, "~r". 237 static constexpr uint32_t Kind_Imm = 5; // Immediate. 238 static constexpr uint32_t Kind_Mem = 6; // Memory operand, "m". 239 240 // Memory constraint codes. 241 // These could be tablegenerated but there's little need to do that since 242 // there's plenty of space in the encoding to support the union of all 243 // constraint codes for all targets. 244 static constexpr uint32_t Constraint_Unknown = 0; 245 static constexpr uint32_t Constraint_es = 1; 246 static constexpr uint32_t Constraint_i = 2; 247 static constexpr uint32_t Constraint_m = 3; 248 static constexpr uint32_t Constraint_o = 4; 249 static constexpr uint32_t Constraint_v = 5; 250 static constexpr uint32_t Constraint_A = 6; 251 static constexpr uint32_t Constraint_Q = 7; 252 static constexpr uint32_t Constraint_R = 8; 253 static constexpr uint32_t Constraint_S = 9; 254 static constexpr uint32_t Constraint_T = 10; 255 static constexpr uint32_t Constraint_Um = 11; 256 static constexpr uint32_t Constraint_Un = 12; 257 static constexpr uint32_t Constraint_Uq = 13; 258 static constexpr uint32_t Constraint_Us = 14; 259 static constexpr uint32_t Constraint_Ut = 15; 260 static constexpr uint32_t Constraint_Uv = 16; 261 static constexpr uint32_t Constraint_Uy = 17; 262 static constexpr uint32_t Constraint_X = 18; 263 static constexpr uint32_t Constraint_Z= 19; 264 static constexpr uint32_t Constraint_ZC = 20; 265 static constexpr uint32_t Constraint_Zy = 21; 266 static constexpr uint32_t Constraints_Max = Constraint_Zy; 267 static constexpr uint32_t Constraints_ShiftAmount = 16; 268 269 static constexpr uint32_t Flag_MatchingOperand = 0x80000000; 270 getFlagWord(unsigned Kind,unsigned NumOps)271 static unsigned getFlagWord(unsigned Kind, unsigned NumOps) { 272 assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!"); 273 assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind"); 274 return Kind | (NumOps << 3); 275 } 276 isRegDefKind(unsigned Flag)277 static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;} isImmKind(unsigned Flag)278 static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; } isMemKind(unsigned Flag)279 static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; } isRegDefEarlyClobberKind(unsigned Flag)280 static bool isRegDefEarlyClobberKind(unsigned Flag) { 281 return getKind(Flag) == Kind_RegDefEarlyClobber; 282 } isClobberKind(unsigned Flag)283 static bool isClobberKind(unsigned Flag) { 284 return getKind(Flag) == Kind_Clobber; 285 } 286 287 /// getFlagWordForMatchingOp - Augment an existing flag word returned by 288 /// getFlagWord with information indicating that this input operand is tied 289 /// to a previous output operand. getFlagWordForMatchingOp(unsigned InputFlag,unsigned MatchedOperandNo)290 static unsigned getFlagWordForMatchingOp(unsigned InputFlag, 291 unsigned MatchedOperandNo) { 292 assert(MatchedOperandNo <= 0x7fff && "Too big matched operand"); 293 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data"); 294 return InputFlag | Flag_MatchingOperand | (MatchedOperandNo << 16); 295 } 296 297 /// getFlagWordForRegClass - Augment an existing flag word returned by 298 /// getFlagWord with the required register class for the following register 299 /// operands. 300 /// A tied use operand cannot have a register class, use the register class 301 /// from the def operand instead. getFlagWordForRegClass(unsigned InputFlag,unsigned RC)302 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) { 303 // Store RC + 1, reserve the value 0 to mean 'no register class'. 304 ++RC; 305 assert(!isImmKind(InputFlag) && "Immediates cannot have a register class"); 306 assert(!isMemKind(InputFlag) && "Memory operand cannot have a register class"); 307 assert(RC <= 0x7fff && "Too large register class ID"); 308 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data"); 309 return InputFlag | (RC << 16); 310 } 311 312 /// Augment an existing flag word returned by getFlagWord with the constraint 313 /// code for a memory constraint. getFlagWordForMem(unsigned InputFlag,unsigned Constraint)314 static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) { 315 assert(isMemKind(InputFlag) && "InputFlag is not a memory constraint!"); 316 assert(Constraint <= 0x7fff && "Too large a memory constraint ID"); 317 assert(Constraint <= Constraints_Max && "Unknown constraint ID"); 318 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data"); 319 return InputFlag | (Constraint << Constraints_ShiftAmount); 320 } 321 convertMemFlagWordToMatchingFlagWord(unsigned InputFlag)322 static unsigned convertMemFlagWordToMatchingFlagWord(unsigned InputFlag) { 323 assert(isMemKind(InputFlag)); 324 return InputFlag & ~(0x7fff << Constraints_ShiftAmount); 325 } 326 getKind(unsigned Flags)327 static unsigned getKind(unsigned Flags) { 328 return Flags & 7; 329 } 330 getMemoryConstraintID(unsigned Flag)331 static unsigned getMemoryConstraintID(unsigned Flag) { 332 assert(isMemKind(Flag)); 333 return (Flag >> Constraints_ShiftAmount) & 0x7fff; 334 } 335 336 /// getNumOperandRegisters - Extract the number of registers field from the 337 /// inline asm operand flag. getNumOperandRegisters(unsigned Flag)338 static unsigned getNumOperandRegisters(unsigned Flag) { 339 return (Flag & 0xffff) >> 3; 340 } 341 342 /// isUseOperandTiedToDef - Return true if the flag of the inline asm 343 /// operand indicates it is an use operand that's matched to a def operand. isUseOperandTiedToDef(unsigned Flag,unsigned & Idx)344 static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) { 345 if ((Flag & Flag_MatchingOperand) == 0) 346 return false; 347 Idx = (Flag & ~Flag_MatchingOperand) >> 16; 348 return true; 349 } 350 351 /// hasRegClassConstraint - Returns true if the flag contains a register 352 /// class constraint. Sets RC to the register class ID. hasRegClassConstraint(unsigned Flag,unsigned & RC)353 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) { 354 if (Flag & Flag_MatchingOperand) 355 return false; 356 unsigned High = Flag >> 16; 357 // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise 358 // stores RC + 1. 359 if (!High) 360 return false; 361 RC = High - 1; 362 return true; 363 } 364 }; 365 366 } // end namespace llvm 367 368 #endif // LLVM_IR_INLINEASM_H 369