1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #if !defined(PLAT_TZC400_H) && defined(IMAGE_BL2) 9 #define PLAT_TZC400_H 10 11 #include <tzc400.h> 12 13 /* Structure to configure TZC Regions' boundaries and attributes. */ 14 struct tzc400_reg { 15 uint8_t reg_filter_en; 16 unsigned long long start_addr; 17 unsigned long long end_addr; 18 unsigned int sec_attr; 19 unsigned int nsaid_permissions; 20 }; 21 22 #define TZC_REGION_NS_NONE 0x00000000U 23 24 /* NXP Platforms do not support NS Access ID (NSAID) based non-secure access. 25 * Supports only non secure through generic NS ACCESS ID 26 */ 27 #define TZC_NS_ACCESS_ID 0xFFFFFFFFU 28 29 /* Number of DRAM regions to be configured 30 * for the platform can be over-written. 31 * 32 * Array tzc400_reg_list too, needs be over-written 33 * if there is any changes to default DRAM region 34 * configuration. 35 */ 36 #ifndef MAX_NUM_TZC_REGION 37 /* 3 regions: 38 * Region 0(default), 39 * Region 1 (DRAM0, Secure Memory), 40 * Region 2 (DRAM0, Shared memory) 41 */ 42 #define MAX_NUM_TZC_REGION NUM_DRAM_REGIONS + 3 43 #define DEFAULT_TZASC_CONFIG 1 44 #endif 45 46 void mem_access_setup(uintptr_t base, uint32_t total_regions, 47 struct tzc400_reg *tzc400_reg_list); 48 int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list, 49 int dram_idx, int list_idx, 50 uint64_t dram_start_addr, 51 uint64_t dram_size, 52 uint32_t secure_dram_sz, 53 uint32_t shrd_dram_sz); 54 55 #endif /* PLAT_TZC400_H */ 56