1 /* 2 * Copyright 2010-2023 NXP 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 #ifndef _PHNXPNCIHAL_H_ 17 #define _PHNXPNCIHAL_H_ 18 19 #include <hardware/nfc.h> 20 #include <phNxpNciHal_utils.h> 21 #include "NxpMfcReader.h" 22 #include "NxpNfcCapability.h" 23 #ifdef NXP_BOOTTIME_UPDATE 24 #include "eSEClientIntf.h" 25 #endif 26 27 #include "eSEClientExtns.h" 28 #include "phNxpNciHal_IoctlOperations.h" 29 30 /********************* Definitions and structures *****************************/ 31 #define MAX_RETRY_COUNT 5 32 #define NCI_MAX_DATA_LEN 300 33 #define NCI_POLL_DURATION 500 34 #define HAL_NFC_ENABLE_I2C_FRAGMENTATION_EVT 0x07 35 #undef P2P_PRIO_LOGIC_HAL_IMP 36 #define NCI_VERSION_2_0 0x20 37 #define NCI_VERSION_1_1 0x11 38 #define NCI_VERSION_1_0 0x10 39 #define NCI_VERSION_UNKNOWN 0x00 40 #define SNXXX_NXP_AUTH_TIMEOUT_BUF_LEN 0x05 41 #define PN557_NXP_AUTH_TIMEOUT_BUF_LEN 0x0C 42 #define SN1XX_ROM_VERSION 0x01 43 #define SN1XX_FW_MAJOR_VERSION 0x10 44 #define SN2XX_ROM_VERSION 0x01 45 #define SN2XX_FW_MAJOR_VERSION 0x01 46 47 /*Mem alloc with 8 byte alignment*/ 48 #define size_align(sz) ((((sz)-1) | 7) + 1) 49 #define nxp_malloc(size) malloc(size_align((size))) 50 51 typedef void(phNxpNciHal_control_granted_callback_t)(); 52 53 /*ROM CODE VERSION FW*/ 54 #define FW_MOBILE_ROM_VERSION_PN551 0x10 55 #define FW_MOBILE_ROM_VERSION_PN553 0x11 56 #define FW_MOBILE_ROM_VERSION_PN557 0x12 57 #define NCI_CMDRESP_MAX_BUFF_SIZE_SNXXX (0x22AU) 58 #define NCI_CMDRESP_MAX_BUFF_SIZE_PN557 (0x102U) 59 60 #define FW_DBG_REASON_AVAILABLE (0xA3) 61 62 #define HOST_ID 0x00 63 #define ESE_ID 0x01 64 #define UICC1_ID 0x02 65 #define UICC2_ID 0x04 66 #define UICC3_ID 0x08 67 /* NCI Data */ 68 69 //#define NCI_MT_CMD 0x20 70 //#define NCI_MT_RSP 0x40 71 //#define NCI_MT_NTF 0x60 72 73 #define CORE_RESET_TRIGGER_TYPE_CORE_RESET_CMD_RECEIVED 0x02 74 #define CORE_RESET_TRIGGER_TYPE_POWERED_ON 0x01 75 #define NCI2_0_CORE_RESET_TRIGGER_TYPE_OVER_TEMPERATURE ((uint8_t)0xA1) 76 #define CORE_RESET_TRIGGER_TYPE_UNRECOVERABLE_ERROR 0x00 77 #define CORE_RESET_TRIGGER_TYPE_FW_ASSERT ((uint8_t)0xA0) 78 #define CORE_RESET_TRIGGER_TYPE_WATCHDOG_RESET ((uint8_t)0xA3) 79 #define CORE_RESET_TRIGGER_TYPE_INPUT_CLOCK_LOST ((uint8_t)0xA4) 80 //#define NCI_MSG_CORE_RESET 0x00 81 //#define NCI_MSG_CORE_INIT 0x01 82 #define NCI_MT_MASK 0xE0 83 #define NCI_OID_MASK 0x3F 84 /* GID: Group Identifier (byte 0) */ 85 #define NCI_GID_MASK 0x0F 86 #define ORIG_NXPHAL 0x01 87 #define ORIG_LIBNFC 0x02 88 #define NXP_PROPCMD_GID 0x2F 89 #define NXP_FLUSH_SRAM_AO_TO_FLASH 0x21 90 #define NXP_CORE_GET_CONFIG_CMD 0x03 91 #define NXP_CORE_SET_CONFIG_CMD 0x02 92 #define NXP_MAX_CONFIG_STRING_LEN 260 93 #define NCI_HEADER_SIZE 3 94 95 typedef struct nci_data { 96 uint16_t len; 97 uint8_t p_data[NCI_MAX_DATA_LEN]; 98 } nci_data_t; 99 100 typedef enum { 101 HAL_STATUS_CLOSE = 0, 102 HAL_STATUS_OPEN, 103 HAL_STATUS_MIN_OPEN 104 } phNxpNci_HalStatus; 105 106 typedef enum { 107 HAL_NFC_FW_UPDATE_INVALID = 0x00, 108 HAL_NFC_FW_UPDATE_START, 109 HAL_NFC_FW_UPDATE_SCUCCESS, 110 HAL_NFC_FW_UPDATE_FAILED, 111 } HalNfcFwUpdateStatus; 112 113 typedef enum { 114 GPIO_UNKNOWN = 0x00, 115 GPIO_STORE = 0x01, 116 GPIO_STORE_DONE = 0x02, 117 GPIO_RESTORE = 0x10, 118 GPIO_RESTORE_DONE = 0x20, 119 GPIO_CLEAR = 0xFF 120 } phNxpNciHal_GpioInfoState; 121 #ifdef NXP_BOOTTIME_UPDATE 122 extern ese_update_state_t ese_update; 123 #endif 124 typedef struct phNxpNciGpioInfo { 125 phNxpNciHal_GpioInfoState state; 126 uint8_t values[2]; 127 } phNxpNciGpioInfo_t; 128 129 /* Macros to enable and disable extensions */ 130 #define HAL_ENABLE_EXT() (nxpncihal_ctrl.hal_ext_enabled = 1) 131 #define HAL_DISABLE_EXT() (nxpncihal_ctrl.hal_ext_enabled = 0) 132 typedef struct phNxpNciInfo { 133 uint8_t nci_version; 134 bool_t wait_for_ntf; 135 uint8_t lastResetNtfReason; 136 } phNxpNciInfo_t; 137 /* NCI Control structure */ 138 typedef struct phNxpNciHal_Control { 139 phNxpNci_HalStatus halStatus; /* Indicate if hal is open or closed */ 140 pthread_t client_thread; /* Integration thread handle */ 141 uint8_t thread_running; /* Thread running if set to 1, else set to 0 */ 142 phLibNfc_sConfig_t gDrvCfg; /* Driver config data */ 143 144 /* Rx data */ 145 uint8_t* p_rx_data; 146 uint16_t rx_data_len; 147 148 /* Rx data */ 149 uint8_t* p_rx_ese_data; 150 uint16_t rx_ese_data_len; 151 152 /* libnfc-nci callbacks */ 153 nfc_stack_callback_t* p_nfc_stack_cback; 154 nfc_stack_data_callback_t* p_nfc_stack_data_cback; 155 156 /* control granted callback */ 157 phNxpNciHal_control_granted_callback_t* p_control_granted_cback; 158 159 /* HAL open status */ 160 bool_t hal_open_status; 161 162 /* HAL extensions */ 163 uint8_t hal_ext_enabled; 164 165 /* Waiting semaphore */ 166 phNxpNciHal_Sem_t ext_cb_data; 167 sem_t syncSpiNfc; 168 169 uint16_t cmd_len; 170 uint8_t p_cmd_data[NCI_MAX_DATA_LEN]; 171 uint16_t rsp_len; 172 uint8_t p_rsp_data[NCI_MAX_DATA_LEN]; 173 174 /* retry count used to force download */ 175 uint16_t retry_cnt; 176 uint8_t read_retry_cnt; 177 phNxpNciInfo_t nci_info; 178 uint8_t hal_boot_mode; 179 bool_t isCoreRstForFwDnld; 180 /* to store and restore gpio values */ 181 phNxpNciGpioInfo_t phNxpNciGpioInfo; 182 tNFC_chipType chipType; 183 bool_t power_reset_triggered; 184 bool_t isUlpdetModeEnabled; 185 } phNxpNciHal_Control_t; 186 187 typedef struct { 188 uint8_t fw_update_reqd; 189 uint8_t rf_update_reqd; 190 } phNxpNciHal_FwRfupdateInfo_t; 191 192 typedef struct phNxpNciClock { 193 bool_t isClockSet; 194 uint8_t p_rx_data[20]; 195 bool_t issetConfig; 196 } phNxpNciClock_t; 197 198 typedef struct phNxpNciRfSetting { 199 bool_t isGetRfSetting; 200 uint8_t p_rx_data[20]; 201 } phNxpNciRfSetting_t; 202 203 typedef struct phNxpNciMwEepromArea { 204 bool_t isGetEepromArea; 205 uint8_t p_rx_data[32]; 206 } phNxpNciMwEepromArea_t; 207 208 enum { SE_TYPE_ESE, SE_TYPE_UICC, SE_TYPE_UICC2, NUM_SE_TYPES }; 209 210 typedef void (*fpVerInfoStoreInEeprom_t)(); 211 typedef int (*fpVerifyCscEfsTest_t)(char* nfcc_csc, char* rffilepath, 212 char* fwfilepath); 213 typedef int (*fpRegRfFwDndl_t)(uint8_t* fw_update_req, uint8_t* rf_update_req, 214 uint8_t skipEEPROMRead); 215 typedef int (*fpPropConfCover_t)(bool attached, int type); 216 void phNxpNciHal_initializeRegRfFwDnld(); 217 void phNxpNciHal_deinitializeRegRfFwDnld(); 218 /*set config management*/ 219 220 #define TOTAL_DURATION 0x00 221 #define ATR_REQ_GEN_BYTES_POLL 0x29 222 #define ATR_REQ_GEN_BYTES_LIS 0x61 223 #define LEN_WT 0x60 224 225 /*PN557 Ven Pin Configuration*/ 226 227 #define PN557_VEN_CFG_VALUE 0x01 228 #define PN557_VEN_CFG_PULLDOWN 0x02 229 #define PN557_VEN_CFG_DEFAULT 0x03 230 231 /*Whenever a new get cfg need to be sent, 232 * array must be updated with defined config type*/ 233 static const uint8_t get_cfg_arr[] = {TOTAL_DURATION, ATR_REQ_GEN_BYTES_POLL, 234 ATR_REQ_GEN_BYTES_LIS, LEN_WT}; 235 236 //#define NXP_NFC_SET_CONFIG_PARAM_EXT 0xA0 237 //#define NXP_NFC_PARAM_ID_SWP2 0xD4 238 //#define NXP_NFC_PARAM_ID_SWPUICC3 0xDC 239 typedef enum { 240 EEPROM_RF_CFG, 241 EEPROM_FW_DWNLD, 242 EEPROM_WIREDMODE_RESUME_TIMEOUT, 243 EEPROM_ESE_SVDD_POWER, 244 EEPROM_ESE_POWER_EXT_PMU, 245 EEPROM_PROP_ROUTING, 246 EEPROM_ESE_SESSION_ID, 247 EEPROM_SWP1_INTF, 248 EEPROM_SWP1A_INTF, 249 EEPROM_SWP2_INTF, 250 EEPROM_FLASH_UPDATE, 251 EEPROM_AUTH_CMD_TIMEOUT, 252 EEPROM_GUARD_TIMER, 253 EEPROM_T4T_NFCEE_ENABLE, 254 EEPROM_AUTONOMOUS_MODE, 255 EEPROM_CE_PHONE_OFF_CFG, 256 EEPROM_ENABLE_VEN_CFG, 257 EEPROM_ISODEP_MERGE_SAK, 258 EEPROM_SRD_TIMEOUT, 259 EEPROM_UICC1_SESSION_ID, 260 EEPROM_UICC2_SESSION_ID, 261 EEPROM_CE_ACT_NTF, 262 EEPROM_UICC_HCI_CE_STATE, 263 EEPROM_EXT_FIELD_DETECT_MODE, 264 EEPROM_CONF_GPIO_CTRL, 265 EEPROM_SET_GPIO_VALUE, 266 EEPROM_POWER_TRACKER_ENABLE 267 } phNxpNci_EEPROM_request_type_t; 268 269 typedef struct phNxpNci_EEPROM_info { 270 uint8_t request_mode; 271 phNxpNci_EEPROM_request_type_t request_type; 272 uint8_t update_mode; 273 uint8_t* buffer; 274 uint8_t bufflen; 275 } phNxpNci_EEPROM_info_t; 276 277 typedef struct phNxpNci_getCfg_info { 278 bool_t isGetcfg; 279 uint8_t total_duration[4]; 280 uint8_t total_duration_len; 281 uint8_t atr_req_gen_bytes[48]; 282 uint8_t atr_req_gen_bytes_len; 283 uint8_t atr_res_gen_bytes[48]; 284 uint8_t atr_res_gen_bytes_len; 285 uint8_t pmid_wt[3]; 286 uint8_t pmid_wt_len; 287 uint8_t auth_cmd_timeout[PN557_NXP_AUTH_TIMEOUT_BUF_LEN]; 288 uint8_t auth_cmd_timeoutlen; 289 } phNxpNci_getCfg_info_t; 290 typedef enum { 291 NFC_FORUM_PROFILE, 292 EMV_CO_PROFILE, 293 SRD_PROFILE, 294 INVALID_PROFILe 295 } phNxpNciProfile_t; 296 /* NXP Poll Profile control structure */ 297 typedef struct phNxpNciProfile_Control { 298 phNxpNciProfile_t profile_type; 299 uint8_t bClkSrcVal; /* Holds the System clock source read from config file */ 300 uint8_t 301 bClkFreqVal; /* Holds the System clock frequency read from config file */ 302 uint8_t bTimeout; /* Holds the Timeout Value */ 303 uint8_t clkReqDelay; /* Holds default delay time before start clock request*/ 304 } phNxpNciProfile_Control_t; 305 306 /* Internal messages to handle callbacks */ 307 #define NCI_HAL_OPEN_CPLT_MSG 0x411 308 #define NCI_HAL_CLOSE_CPLT_MSG 0x412 309 #define NCI_HAL_POST_INIT_CPLT_MSG 0x413 310 #define NCI_HAL_PRE_DISCOVER_CPLT_MSG 0x414 311 #define NCI_HAL_ERROR_MSG 0x415 312 #define NCI_HAL_HCI_NETWORK_RESET_MSG 0x416 313 #define NCI_HAL_RX_MSG 0xF01 314 #define HAL_NFC_FW_UPDATE_STATUS_EVT 0x0A 315 316 #define NCIHAL_CMD_CODE_LEN_BYTE_OFFSET (2U) 317 #define NCIHAL_CMD_CODE_BYTE_LEN (3U) 318 319 /******************** NCI HAL exposed functions *******************************/ 320 int phNxpNciHal_check_ncicmd_write_window(uint16_t cmd_len, uint8_t* p_cmd); 321 void phNxpNciHal_request_control(void); 322 void phNxpNciHal_release_control(void); 323 NFCSTATUS phNxpNciHal_send_get_cfgs(); 324 int phNxpNciHal_write_unlocked(uint16_t data_len, const uint8_t* p_data, 325 int origin); 326 NFCSTATUS request_EEPROM(phNxpNci_EEPROM_info_t* mEEPROM_info); 327 int phNxpNciHal_check_config_parameter(); 328 NFCSTATUS phNxpNciHal_fw_download(uint8_t seq_handler_offset = 0, 329 bool bIsNfccDlState = false); 330 NFCSTATUS phNxpNciHal_nfcc_core_reset_init(bool keep_config = false); 331 int phNxpNciHal_fw_mw_ver_check(); 332 NFCSTATUS phNxpNciHal_check_clock_config(void); 333 NFCSTATUS phNxpNciHal_china_tianjin_rf_setting(void); 334 NFCSTATUS phNxpNciHal_CheckValidFwVersion(void); 335 336 NFCSTATUS phNxpNciHal_send_nfcee_pwr_cntl_cmd(uint8_t type); 337 /******************************************************************************* 338 ** 339 ** Function phNxpNciHal_configFeatureList 340 ** 341 ** Description Configures the featureList based on chip type 342 ** HW Version information number will provide chipType. 343 ** HW Version can be obtained from CORE_INIT_RESPONSE(NCI 1.0) 344 ** or CORE_RST_NTF(NCI 2.0) 345 ** 346 ** Parameters CORE_INIT_RESPONSE/CORE_RST_NTF, len 347 ** 348 ** Returns none 349 *******************************************************************************/ 350 void phNxpNciHal_configFeatureList(uint8_t* init_rsp, uint16_t rsp_len); 351 352 /****************************************************************************** 353 * Function phNxpNciHal_read_and_update_se_state 354 * 355 * Description This will read NFCEE status from system properties 356 * and update to NFCC to enable/disable. 357 * 358 * Returns none 359 * 360 ******************************************************************************/ 361 void phNxpNciHal_read_and_update_se_state(); 362 363 /****************************************************************************** 364 * Function phNxpNciHal_Abort 365 * 366 * Description This will post the message to the upper layer 367 * using the callback p_nfc_stack_cback_backup. 368 * 369 * Returns none 370 * 371 ******************************************************************************/ 372 extern bool phNxpNciHal_Abort(); 373 /****************************************************************************** 374 * Function phNxpNciHal_read_fw_dw_status 375 * 376 * Description This will read the value of fw download status flag 377 * from eeprom 378 * 379 * Parameters value - this parameter will be updated with the flag 380 * value from eeprom. 381 * 382 * Returns status of the read 383 * 384 ******************************************************************************/ 385 NFCSTATUS phNxpNciHal_read_fw_dw_status(uint8_t& value); 386 387 /****************************************************************************** 388 * Function phNxpNciHal_write_fw_dw_status 389 * 390 * Description This will update value of fw download status flag 391 * to eeprom 392 * 393 * Parameters value - this value will be updated to eeprom flag. 394 * 395 * Returns status of the write 396 * 397 ******************************************************************************/ 398 NFCSTATUS phNxpNciHal_write_fw_dw_status(uint8_t value); 399 400 /****************************************************************************** 401 * Function phNxpNciHal_save_uicc_params 402 * 403 * Description This will read the UICC HCI param values 404 * from eeprom and store in global variable 405 * 406 * Returns status of the read 407 * 408 ******************************************************************************/ 409 NFCSTATUS phNxpNciHal_save_uicc_params(); 410 411 /****************************************************************************** 412 * Function phNxpNciHal_restore_uicc_params 413 * 414 * Description This will set the UICC HCI param values 415 * back to eeprom from global variable 416 * 417 * Returns status of the read 418 * 419 ******************************************************************************/ 420 NFCSTATUS phNxpNciHal_restore_uicc_params(); 421 422 #endif /* _PHNXPNCIHAL_H_ */ 423