1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOC_H 8 #define SOC_H 9 10 /* Chassis specific defines - common across SoC's of a particular platform */ 11 #include <dcfg_lsch3.h> 12 #include <soc_default_base_addr.h> 13 #include <soc_default_helper_macros.h> 14 15 /* 16 * SVR Definition of LS1028A 17 * (not include major and minor rev) 18 * These info is listed in Table B-6. DCFG differences 19 * between LS1028A and LS1027A of LS1028ARM(Reference Manual) 20 */ 21 #define SVR_LS1017AN 0x870B25 22 #define SVR_LS1017AE 0x870B24 23 #define SVR_LS1018AN 0x870B21 24 #define SVR_LS1018AE 0x870B20 25 #define SVR_LS1027AN 0x870B05 26 #define SVR_LS1027AE 0x870B04 27 #define SVR_LS1028AN 0x870B01 28 #define SVR_LS1028AE 0x870B00 29 30 /* Number of cores in platform */ 31 #define PLATFORM_CORE_COUNT 2 32 #define NUMBER_OF_CLUSTERS 1 33 #define CORES_PER_CLUSTER 2 34 35 /* Set to 0 if the clusters are not symmetrical */ 36 #define SYMMETRICAL_CLUSTERS 1 37 38 #define NUM_DRAM_REGIONS 3 39 40 #define NXP_DRAM0_ADDR 0x80000000 41 #define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2GB */ 42 43 #define NXP_DRAM1_ADDR 0x2080000000 44 #define NXP_DRAM1_MAX_SIZE 0x1F80000000 /* 126G */ 45 46 #define NXP_DRAM2_ADDR 0x6000000000 47 #define NXP_DRAM2_MAX_SIZE 0x2000000000 /* 128G */ 48 49 /* DRAM0 Size defined in platform_def.h */ 50 #define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE 51 52 /* CCSR space memory Map */ 53 #undef NXP_UART_ADDR 54 #define NXP_UART_ADDR 0x021C0500 55 56 #undef NXP_UART1_ADDR 57 #define NXP_UART1_ADDR 0x021C0600 58 59 #undef NXP_WDOG1_TZ_ADDR 60 #define NXP_WDOG1_TZ_ADDR 0x023C0000 61 62 #undef NXP_GICR_ADDR 63 #define NXP_GICR_ADDR 0x06040000 64 65 #undef NXP_GICR_SGI_ADDR 66 #define NXP_GICR_SGI_ADDR 0x06050000 67 68 /* EPU register offsets and values */ 69 #define EPU_EPGCR_OFFSET 0x0 70 #define EPU_EPIMCR10_OFFSET 0x128 71 #define EPU_EPCTR10_OFFSET 0xa28 72 #define EPU_EPCCR10_OFFSET 0x828 73 #define EPU_EPCCR10_VAL 0xb2800000 74 #define EPU_EPIMCR10_VAL 0xba000000 75 #define EPU_EPCTR10_VAL 0x0 76 #define EPU_EPGCR_VAL (1 << 31) 77 78 /* PORSR1 */ 79 #define PORSR1_RCW_MASK 0x07800000 80 #define PORSR1_RCW_SHIFT 23 81 82 #define SDHC1_VAL 0x8 83 #define SDHC2_VAL 0x9 84 #define I2C1_VAL 0xa 85 #define FLEXSPI_NAND2K_VAL 0xc 86 #define FLEXSPI_NAND4K_VAL 0xd 87 #define FLEXSPI_NOR 0xf 88 89 /* 90 * Required LS standard platform porting definitions 91 * for CCI-400 92 */ 93 #define NXP_CCI_CLUSTER0_SL_IFACE_IX 4 94 95 /* Defines required for using XLAT tables from ARM common code */ 96 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40) 97 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40) 98 99 /* Clock Divisors */ 100 #define NXP_PLATFORM_CLK_DIVIDER 1 101 #define NXP_UART_CLK_DIVIDER 2 102 103 /* dcfg register offsets and values */ 104 #define DCFG_DEVDISR2_ENETC (1 << 31) 105 106 #define MPIDR_AFFINITY0_MASK 0x00FF 107 #define MPIDR_AFFINITY1_MASK 0xFF00 108 #define CPUECTLR_DISABLE_TWALK_PREFETCH 0x4000000000 109 #define CPUECTLR_INS_PREFETCH_MASK 0x1800000000 110 #define CPUECTLR_DAT_PREFETCH_MASK 0x0300000000 111 #define OSDLR_EL1_DLK_LOCK 0x1 112 #define CNTP_CTL_EL0_EN 0x1 113 #define CNTP_CTL_EL0_IMASK 0x2 114 115 #define SYSTEM_PWR_DOMAINS 1 116 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 117 NUMBER_OF_CLUSTERS + \ 118 SYSTEM_PWR_DOMAINS) 119 120 /* Power state coordination occurs at the system level */ 121 #define PLAT_PD_COORD_LVL MPIDR_AFFLVL2 122 #define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL 123 124 /* Local power state for power domains in Run state */ 125 #define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN 126 127 /* define retention state */ 128 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) 129 #define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE 130 131 /* define power-down state */ 132 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) 133 #define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE 134 135 /* One cache line needed for bakery locks on ARM platforms */ 136 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 137 138 #ifndef __ASSEMBLER__ 139 /* CCI slave interfaces */ 140 static const int cci_map[] = { 141 NXP_CCI_CLUSTER0_SL_IFACE_IX, 142 }; 143 void soc_init_lowlevel(void); 144 void soc_init_percpu(void); 145 void _soc_set_start_addr(unsigned long addr); 146 void _set_platform_security(void); 147 #endif 148 149 #endif /* SOC_H */ 150