1 //===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by 2 // combiner ------*- C++ -*-===// 3 // 4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 5 // See https://llvm.org/LICENSE.txt for license information. 6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines instruction pattern supported by combiner 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H 15 #define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H 16 17 namespace llvm { 18 19 /// These are instruction patterns matched by the machine combiner pass. 20 enum class MachineCombinerPattern { 21 // These are commutative variants for reassociating a computation chain. See 22 // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp. 23 REASSOC_AX_BY, 24 REASSOC_AX_YB, 25 REASSOC_XA_BY, 26 REASSOC_XA_YB, 27 28 // These are multiply-add patterns matched by the AArch64 machine combiner. 29 MULADDW_OP1, 30 MULADDW_OP2, 31 MULSUBW_OP1, 32 MULSUBW_OP2, 33 MULADDWI_OP1, 34 MULSUBWI_OP1, 35 MULADDX_OP1, 36 MULADDX_OP2, 37 MULSUBX_OP1, 38 MULSUBX_OP2, 39 MULADDXI_OP1, 40 MULSUBXI_OP1, 41 // NEON integers vectors 42 MULADDv8i8_OP1, 43 MULADDv8i8_OP2, 44 MULADDv16i8_OP1, 45 MULADDv16i8_OP2, 46 MULADDv4i16_OP1, 47 MULADDv4i16_OP2, 48 MULADDv8i16_OP1, 49 MULADDv8i16_OP2, 50 MULADDv2i32_OP1, 51 MULADDv2i32_OP2, 52 MULADDv4i32_OP1, 53 MULADDv4i32_OP2, 54 55 MULSUBv8i8_OP1, 56 MULSUBv8i8_OP2, 57 MULSUBv16i8_OP1, 58 MULSUBv16i8_OP2, 59 MULSUBv4i16_OP1, 60 MULSUBv4i16_OP2, 61 MULSUBv8i16_OP1, 62 MULSUBv8i16_OP2, 63 MULSUBv2i32_OP1, 64 MULSUBv2i32_OP2, 65 MULSUBv4i32_OP1, 66 MULSUBv4i32_OP2, 67 68 MULADDv4i16_indexed_OP1, 69 MULADDv4i16_indexed_OP2, 70 MULADDv8i16_indexed_OP1, 71 MULADDv8i16_indexed_OP2, 72 MULADDv2i32_indexed_OP1, 73 MULADDv2i32_indexed_OP2, 74 MULADDv4i32_indexed_OP1, 75 MULADDv4i32_indexed_OP2, 76 77 MULSUBv4i16_indexed_OP1, 78 MULSUBv4i16_indexed_OP2, 79 MULSUBv8i16_indexed_OP1, 80 MULSUBv8i16_indexed_OP2, 81 MULSUBv2i32_indexed_OP1, 82 MULSUBv2i32_indexed_OP2, 83 MULSUBv4i32_indexed_OP1, 84 MULSUBv4i32_indexed_OP2, 85 86 // Floating Point 87 FMULADDH_OP1, 88 FMULADDH_OP2, 89 FMULSUBH_OP1, 90 FMULSUBH_OP2, 91 FMULADDS_OP1, 92 FMULADDS_OP2, 93 FMULSUBS_OP1, 94 FMULSUBS_OP2, 95 FMULADDD_OP1, 96 FMULADDD_OP2, 97 FMULSUBD_OP1, 98 FMULSUBD_OP2, 99 FNMULSUBH_OP1, 100 FNMULSUBS_OP1, 101 FNMULSUBD_OP1, 102 FMLAv1i32_indexed_OP1, 103 FMLAv1i32_indexed_OP2, 104 FMLAv1i64_indexed_OP1, 105 FMLAv1i64_indexed_OP2, 106 FMLAv4f16_OP1, 107 FMLAv4f16_OP2, 108 FMLAv8f16_OP1, 109 FMLAv8f16_OP2, 110 FMLAv2f32_OP2, 111 FMLAv2f32_OP1, 112 FMLAv2f64_OP1, 113 FMLAv2f64_OP2, 114 FMLAv4i16_indexed_OP1, 115 FMLAv4i16_indexed_OP2, 116 FMLAv8i16_indexed_OP1, 117 FMLAv8i16_indexed_OP2, 118 FMLAv2i32_indexed_OP1, 119 FMLAv2i32_indexed_OP2, 120 FMLAv2i64_indexed_OP1, 121 FMLAv2i64_indexed_OP2, 122 FMLAv4f32_OP1, 123 FMLAv4f32_OP2, 124 FMLAv4i32_indexed_OP1, 125 FMLAv4i32_indexed_OP2, 126 FMLSv1i32_indexed_OP2, 127 FMLSv1i64_indexed_OP2, 128 FMLSv4f16_OP1, 129 FMLSv4f16_OP2, 130 FMLSv8f16_OP1, 131 FMLSv8f16_OP2, 132 FMLSv2f32_OP1, 133 FMLSv2f32_OP2, 134 FMLSv2f64_OP1, 135 FMLSv2f64_OP2, 136 FMLSv4i16_indexed_OP1, 137 FMLSv4i16_indexed_OP2, 138 FMLSv8i16_indexed_OP1, 139 FMLSv8i16_indexed_OP2, 140 FMLSv2i32_indexed_OP1, 141 FMLSv2i32_indexed_OP2, 142 FMLSv2i64_indexed_OP1, 143 FMLSv2i64_indexed_OP2, 144 FMLSv4f32_OP1, 145 FMLSv4f32_OP2, 146 FMLSv4i32_indexed_OP1, 147 FMLSv4i32_indexed_OP2 148 }; 149 150 } // end namespace llvm 151 152 #endif 153