1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef PLAT_GICV3_H 9 #define PLAT_GICV3_H 10 11 #include <drivers/arm/gicv3.h> 12 13 /* offset between redistributors */ 14 #define GIC_RD_OFFSET 0x00020000 15 /* offset between SGI's */ 16 #define GIC_SGI_OFFSET 0x00020000 17 /* offset from rd base to sgi base */ 18 #define GIC_RD_2_SGI_OFFSET 0x00010000 19 20 /* register offsets */ 21 #define GICD_CTLR_OFFSET 0x0 22 #define GICD_CLR_SPI_SR 0x58 23 #define GICD_IGROUPR_2 0x88 24 #define GICD_ISENABLER_2 0x108 25 #define GICD_ICENABLER_2 0x188 26 #define GICD_ICPENDR_2 0x288 27 #define GICD_ICACTIVER_2 0x388 28 #define GICD_IPRIORITYR_22 0x458 29 #define GICD_ICFGR_5 0xC14 30 #define GICD_IGRPMODR_2 0xD08 31 32 #define GICD_IROUTER60_OFFSET 0x61e0 33 #define GICD_IROUTER76_OFFSET 0x6260 34 #define GICD_IROUTER89_OFFSET 0x62C8 35 #define GICD_IROUTER112_OFFSET 0x6380 36 #define GICD_IROUTER113_OFFSET 0x6388 37 38 #define GICR_ICENABLER0_OFFSET 0x180 39 #define GICR_CTLR_OFFSET 0x0 40 #define GICR_IGROUPR0_OFFSET 0x80 41 #define GICR_IGRPMODR0_OFFSET 0xD00 42 #define GICR_IPRIORITYR3_OFFSET 0x40C 43 #define GICR_ICPENDR0_OFFSET 0x280 44 #define GICR_ISENABLER0_OFFSET 0x100 45 #define GICR_TYPER_OFFSET 0x8 46 #define GICR_WAKER_OFFSET 0x14 47 #define GICR_ICACTIVER0_OFFSET 0x380 48 #define GICR_ICFGR0_OFFSET 0xC00 49 50 /* bitfield masks */ 51 #define GICD_CTLR_EN_GRP_MASK 0x7 52 #define GICD_CTLR_EN_GRP_1NS 0x2 53 #define GICD_CTLR_EN_GRP_1S 0x4 54 #define GICD_CTLR_EN_GRP_0 0x1 55 #define GICD_CTLR_ARE_S_MASK 0x10 56 #define GICD_CTLR_RWP 0x80000000 57 58 #define GICR_ICENABLER0_SGI15 0x00008000 59 #define GICR_CTLR_RWP 0x8 60 #define GICR_CTLR_DPG0_MASK 0x2000000 61 #define GICR_IGROUPR0_SGI15 0x00008000 62 #define GICR_IGRPMODR0_SGI15 0x00008000 63 #define GICR_ISENABLER0_SGI15 0x00008000 64 #define GICR_IPRIORITYR3_SGI15_MASK 0xFF000000 65 #define GICR_ICPENDR0_SGI15 0x8000 66 67 #define GIC_SPI_89_MASK 0x02000000 68 #define GIC_SPI89_PRIORITY_MASK 0xFF00 69 #define GIC_IRM_SPI89 0x80000000 70 71 #define GICD_IROUTER_VALUE 0x100 72 #define GICR_WAKER_SLEEP_BIT 0x2 73 #define GICR_WAKER_ASLEEP (1 << 2 | 1 << 1) 74 75 #define ICC_SRE_EL3_SRE 0x1 76 #define ICC_IGRPEN0_EL1_EN 0x1 77 #define ICC_CTLR_EL3_CBPR_EL1S 0x1 78 #define ICC_CTLR_EL3_RM 0x20 79 #define ICC_CTLR_EL3_EOIMODE_EL3 0x4 80 #define ICC_CTLR_EL3_PMHE 0x40 81 #define ICC_PMR_EL1_P_FILTER 0xFF 82 #define ICC_IAR0_EL1_SGI15 0xF 83 #define ICC_SGI0R_EL1_INTID 0x0F000000 84 #define ICC_IAR0_INTID_SPI_89 0x59 85 86 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_SRE_EL3 S3_6_C12_C12_5 89 #define ICC_CTLR_EL3 S3_6_C12_C12_4 90 #define ICC_SRE_EL2 S3_4_C12_C9_5 91 #define ICC_CTLR_EL1 S3_0_C12_C12_4 92 93 #ifndef __ASSEMBLER__ 94 95 /* GIC common API's */ 96 typedef unsigned int (*my_core_pos_fn)(void); 97 98 void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr, 99 const uintptr_t nxp_gicr_addr, 100 uint8_t plat_core_count, 101 interrupt_prop_t *ls_interrupt_props, 102 uint8_t ls_interrupt_prop_count, 103 uintptr_t *target_mask_array, 104 mpidr_hash_fn mpidr_to_core_pos); 105 //void plat_ls_gic_driver_init(void); 106 void plat_ls_gic_init(void); 107 void plat_ls_gic_cpuif_enable(void); 108 void plat_ls_gic_cpuif_disable(void); 109 void plat_ls_gic_redistif_on(void); 110 void plat_ls_gic_redistif_off(void); 111 void plat_gic_pcpu_init(void); 112 #endif 113 114 #endif /* PLAT_GICV3_H */ 115