1 /*
2 * Copyright (C) 2011 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef ART_LIBARTBASE_ARCH_INSTRUCTION_SET_H_
18 #define ART_LIBARTBASE_ARCH_INSTRUCTION_SET_H_
19
20 #include <iosfwd>
21 #include <string>
22 #include <vector>
23
24 #include "base/enums.h"
25 #include "base/macros.h"
26
27 namespace art {
28
29 enum class InstructionSet {
30 kNone,
31 kArm,
32 kArm64,
33 kThumb2,
34 kRiscv64,
35 kX86,
36 kX86_64,
37 kLast = kX86_64
38 };
39 std::ostream& operator<<(std::ostream& os, InstructionSet rhs);
40
41 #if defined(__arm__)
42 static constexpr InstructionSet kRuntimeISA = InstructionSet::kArm;
43 #elif defined(__aarch64__)
44 static constexpr InstructionSet kRuntimeISA = InstructionSet::kArm64;
45 #elif defined (__riscv)
46 static constexpr InstructionSet kRuntimeISA = InstructionSet::kRiscv64;
47 #elif defined(__i386__)
48 static constexpr InstructionSet kRuntimeISA = InstructionSet::kX86;
49 #elif defined(__x86_64__)
50 static constexpr InstructionSet kRuntimeISA = InstructionSet::kX86_64;
51 #else
52 static constexpr InstructionSet kRuntimeISA = InstructionSet::kNone;
53 #endif
54
55 // Architecture-specific pointer sizes
56 static constexpr PointerSize kArmPointerSize = PointerSize::k32;
57 static constexpr PointerSize kArm64PointerSize = PointerSize::k64;
58 static constexpr PointerSize kRiscv64PointerSize = PointerSize::k64;
59 static constexpr PointerSize kX86PointerSize = PointerSize::k32;
60 static constexpr PointerSize kX86_64PointerSize = PointerSize::k64;
61
62 // ARM64 default SVE vector length.
63 static constexpr size_t kArm64DefaultSVEVectorLength = 256;
64
65 // Code alignment (used for the first instruction of a subroutine, such as an entrypoint).
66 // This is the recommended alignment for maximum performance.
67 // ARM processors require code to be 4-byte aligned, but ARM ELF requires 8.
68 static constexpr size_t kArmCodeAlignment = 8;
69 static constexpr size_t kArm64CodeAlignment = 16;
70 static constexpr size_t kRiscv64CodeAlignment = 16;
71 static constexpr size_t kX86CodeAlignment = 16;
72
73 // Instruction alignment (every instruction must be aligned at this boundary). This differs from
74 // code alignment, which applies only to the first instruction of a subroutine.
75 // Android requires the RISC-V compressed instruction extension, and that allows
76 // *all* instructions (not just compressed ones) to be 2-byte aligned rather
77 // than the usual 4-byte alignment requirement.
78 static constexpr size_t kThumb2InstructionAlignment = 2;
79 static constexpr size_t kArm64InstructionAlignment = 4;
80 static constexpr size_t kRiscv64InstructionAlignment = 2;
81 static constexpr size_t kX86InstructionAlignment = 1;
82 static constexpr size_t kX86_64InstructionAlignment = 1;
83
84 const char* GetInstructionSetString(InstructionSet isa);
85
86 // Note: Returns kNone when the string cannot be parsed to a known value.
87 InstructionSet GetInstructionSetFromString(const char* instruction_set);
88
89 // Fatal logging out of line to keep the header clean of logging.h.
90 NO_RETURN void InstructionSetAbort(InstructionSet isa);
91
GetInstructionSetPointerSize(InstructionSet isa)92 constexpr PointerSize GetInstructionSetPointerSize(InstructionSet isa) {
93 switch (isa) {
94 case InstructionSet::kArm:
95 // Fall-through.
96 case InstructionSet::kThumb2:
97 return kArmPointerSize;
98 case InstructionSet::kArm64:
99 return kArm64PointerSize;
100 case InstructionSet::kRiscv64:
101 return kRiscv64PointerSize;
102 case InstructionSet::kX86:
103 return kX86PointerSize;
104 case InstructionSet::kX86_64:
105 return kX86_64PointerSize;
106
107 case InstructionSet::kNone:
108 break;
109 }
110 InstructionSetAbort(isa);
111 }
112
IsValidInstructionSet(InstructionSet isa)113 constexpr bool IsValidInstructionSet(InstructionSet isa) {
114 switch (isa) {
115 case InstructionSet::kArm:
116 case InstructionSet::kThumb2:
117 case InstructionSet::kArm64:
118 case InstructionSet::kRiscv64:
119 case InstructionSet::kX86:
120 case InstructionSet::kX86_64:
121 return true;
122
123 case InstructionSet::kNone:
124 return false;
125 }
126 return false;
127 }
128
GetInstructionSetInstructionAlignment(InstructionSet isa)129 constexpr size_t GetInstructionSetInstructionAlignment(InstructionSet isa) {
130 switch (isa) {
131 case InstructionSet::kArm:
132 // Fall-through.
133 case InstructionSet::kThumb2:
134 return kThumb2InstructionAlignment;
135 case InstructionSet::kArm64:
136 return kArm64InstructionAlignment;
137 case InstructionSet::kRiscv64:
138 return kRiscv64InstructionAlignment;
139 case InstructionSet::kX86:
140 return kX86InstructionAlignment;
141 case InstructionSet::kX86_64:
142 return kX86_64InstructionAlignment;
143
144 case InstructionSet::kNone:
145 break;
146 }
147 InstructionSetAbort(isa);
148 }
149
GetInstructionSetCodeAlignment(InstructionSet isa)150 constexpr size_t GetInstructionSetCodeAlignment(InstructionSet isa) {
151 switch (isa) {
152 case InstructionSet::kArm:
153 // Fall-through.
154 case InstructionSet::kThumb2:
155 return kArmCodeAlignment;
156 case InstructionSet::kArm64:
157 return kArm64CodeAlignment;
158 case InstructionSet::kRiscv64:
159 return kRiscv64CodeAlignment;
160 case InstructionSet::kX86:
161 // Fall-through.
162 case InstructionSet::kX86_64:
163 return kX86CodeAlignment;
164
165 case InstructionSet::kNone:
166 break;
167 }
168 InstructionSetAbort(isa);
169 }
170
171 // Returns the difference between the code address and a usable PC.
172 // Mainly to cope with `kThumb2` where the lower bit must be set.
GetInstructionSetEntryPointAdjustment(InstructionSet isa)173 constexpr size_t GetInstructionSetEntryPointAdjustment(InstructionSet isa) {
174 switch (isa) {
175 case InstructionSet::kArm:
176 case InstructionSet::kArm64:
177 case InstructionSet::kRiscv64:
178 case InstructionSet::kX86:
179 case InstructionSet::kX86_64:
180 return 0;
181 case InstructionSet::kThumb2: {
182 // +1 to set the low-order bit so a BLX will switch to Thumb mode
183 return 1;
184 }
185
186 case InstructionSet::kNone:
187 break;
188 }
189 InstructionSetAbort(isa);
190 }
191
Is64BitInstructionSet(InstructionSet isa)192 constexpr bool Is64BitInstructionSet(InstructionSet isa) {
193 switch (isa) {
194 case InstructionSet::kArm:
195 case InstructionSet::kThumb2:
196 case InstructionSet::kX86:
197 return false;
198
199 case InstructionSet::kArm64:
200 case InstructionSet::kRiscv64:
201 case InstructionSet::kX86_64:
202 return true;
203
204 case InstructionSet::kNone:
205 break;
206 }
207 InstructionSetAbort(isa);
208 }
209
InstructionSetPointerSize(InstructionSet isa)210 constexpr PointerSize InstructionSetPointerSize(InstructionSet isa) {
211 return Is64BitInstructionSet(isa) ? PointerSize::k64 : PointerSize::k32;
212 }
213
GetBytesPerGprSpillLocation(InstructionSet isa)214 constexpr size_t GetBytesPerGprSpillLocation(InstructionSet isa) {
215 switch (isa) {
216 case InstructionSet::kArm:
217 // Fall-through.
218 case InstructionSet::kThumb2:
219 return 4;
220 case InstructionSet::kArm64:
221 return 8;
222 case InstructionSet::kRiscv64:
223 return 8;
224 case InstructionSet::kX86:
225 return 4;
226 case InstructionSet::kX86_64:
227 return 8;
228
229 case InstructionSet::kNone:
230 break;
231 }
232 InstructionSetAbort(isa);
233 }
234
GetBytesPerFprSpillLocation(InstructionSet isa)235 constexpr size_t GetBytesPerFprSpillLocation(InstructionSet isa) {
236 switch (isa) {
237 case InstructionSet::kArm:
238 // Fall-through.
239 case InstructionSet::kThumb2:
240 return 4;
241 case InstructionSet::kArm64:
242 return 8;
243 case InstructionSet::kRiscv64:
244 return 8;
245 case InstructionSet::kX86:
246 return 8;
247 case InstructionSet::kX86_64:
248 return 8;
249
250 case InstructionSet::kNone:
251 break;
252 }
253 InstructionSetAbort(isa);
254 }
255
256 // Returns the instruction sets supported by the device, or an empty list on failure.
257 std::vector<InstructionSet> GetSupportedInstructionSets(std::string* error_msg);
258
259 namespace instruction_set_details {
260
261 #if !defined(ART_STACK_OVERFLOW_GAP_arm) || !defined(ART_STACK_OVERFLOW_GAP_arm64) || \
262 !defined(ART_STACK_OVERFLOW_GAP_riscv64) || \
263 !defined(ART_STACK_OVERFLOW_GAP_x86) || !defined(ART_STACK_OVERFLOW_GAP_x86_64)
264 #error "Missing defines for stack overflow gap"
265 #endif
266
267 static constexpr size_t kArmStackOverflowReservedBytes = ART_STACK_OVERFLOW_GAP_arm;
268 static constexpr size_t kArm64StackOverflowReservedBytes = ART_STACK_OVERFLOW_GAP_arm64;
269 static constexpr size_t kRiscv64StackOverflowReservedBytes = ART_STACK_OVERFLOW_GAP_riscv64;
270 static constexpr size_t kX86StackOverflowReservedBytes = ART_STACK_OVERFLOW_GAP_x86;
271 static constexpr size_t kX86_64StackOverflowReservedBytes = ART_STACK_OVERFLOW_GAP_x86_64;
272
273 NO_RETURN void GetStackOverflowReservedBytesFailure(const char* error_msg);
274
275 } // namespace instruction_set_details
276
277 ALWAYS_INLINE
GetStackOverflowReservedBytes(InstructionSet isa)278 constexpr size_t GetStackOverflowReservedBytes(InstructionSet isa) {
279 switch (isa) {
280 case InstructionSet::kArm: // Intentional fall-through.
281 case InstructionSet::kThumb2:
282 return instruction_set_details::kArmStackOverflowReservedBytes;
283
284 case InstructionSet::kArm64:
285 return instruction_set_details::kArm64StackOverflowReservedBytes;
286
287 case InstructionSet::kRiscv64:
288 return instruction_set_details::kRiscv64StackOverflowReservedBytes;
289
290 case InstructionSet::kX86:
291 return instruction_set_details::kX86StackOverflowReservedBytes;
292
293 case InstructionSet::kX86_64:
294 return instruction_set_details::kX86_64StackOverflowReservedBytes;
295
296 case InstructionSet::kNone:
297 instruction_set_details::GetStackOverflowReservedBytesFailure(
298 "kNone has no stack overflow size");
299 }
300 instruction_set_details::GetStackOverflowReservedBytesFailure("Unknown instruction set");
301 }
302
303 // The following definitions create return types for two word-sized entities that will be passed
304 // in registers so that memory operations for the interface trampolines can be avoided. The entities
305 // are the resolved method and the pointer to the code to be invoked.
306 //
307 // On x86 and ARM32, this is given for a *scalar* 64bit value. The definition thus *must* be
308 // uint64_t or long long int.
309 //
310 // On x86_64 and ARM64, structs are decomposed for allocation, so we can create a structs of
311 // two size_t-sized values.
312 //
313 // We need two operations:
314 //
315 // 1) A flag value that signals failure. The assembly stubs expect the lower part to be "0".
316 // GetTwoWordFailureValue() will return a value that has lower part == 0.
317 //
318 // 2) A value that combines two word-sized values.
319 // GetTwoWordSuccessValue() constructs this.
320 //
321 // IMPORTANT: If you use this to transfer object pointers, it is your responsibility to ensure
322 // that the object does not move or the value is updated. Simple use of this is NOT SAFE
323 // when the garbage collector can move objects concurrently. Ensure that required locks
324 // are held when using!
325
326 #if defined(__i386__) || defined(__arm__)
327 using TwoWordReturn = uint64_t;
328
329 // Encodes method_ptr==nullptr and code_ptr==nullptr
GetTwoWordFailureValue()330 static inline constexpr TwoWordReturn GetTwoWordFailureValue() {
331 return 0;
332 }
333
334 // Use the lower 32b for the method pointer and the upper 32b for the code pointer.
GetTwoWordSuccessValue(uintptr_t hi,uintptr_t lo)335 static inline constexpr TwoWordReturn GetTwoWordSuccessValue(uintptr_t hi, uintptr_t lo) {
336 static_assert(sizeof(uint32_t) == sizeof(uintptr_t), "Unexpected size difference");
337 uint32_t lo32 = lo;
338 uint64_t hi64 = static_cast<uint64_t>(hi);
339 return ((hi64 << 32) | lo32);
340 }
341
342 #elif defined(__x86_64__) || defined(__aarch64__) || defined(__riscv)
343
344 // Note: TwoWordReturn can't be constexpr for 64-bit targets. We'd need a constexpr constructor,
345 // which would violate C-linkage in the entrypoint functions.
346
347 struct TwoWordReturn {
348 uintptr_t lo;
349 uintptr_t hi;
350 };
351
352 // Encodes method_ptr==nullptr. Leaves random value in code pointer.
GetTwoWordFailureValue()353 static inline TwoWordReturn GetTwoWordFailureValue() {
354 TwoWordReturn ret;
355 ret.lo = 0;
356 return ret;
357 }
358
359 // Write values into their respective members.
GetTwoWordSuccessValue(uintptr_t hi,uintptr_t lo)360 static inline TwoWordReturn GetTwoWordSuccessValue(uintptr_t hi, uintptr_t lo) {
361 TwoWordReturn ret;
362 ret.lo = lo;
363 ret.hi = hi;
364 return ret;
365 }
366 #else
367 #error "Unsupported architecture"
368 #endif
369
370 } // namespace art
371
372 #endif // ART_LIBARTBASE_ARCH_INSTRUCTION_SET_H_
373