| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 810 Register HiReg = HiOperand.getReg(); in emitCombineRI() local
861 Register HiReg = HiOperand.getReg(); in emitCombineRR() local
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| D | HexagonFrameLowering.cpp | 976 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 783 unsigned HiReg = HiOperand.getReg(); in emitCombineRI() local
834 unsigned HiReg = HiOperand.getReg(); in emitCombineRR() local
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| D | HexagonFrameLowering.cpp | 826 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::subreg_hireg); in insertCFIInstructionsAt() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 814 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| D | MipsSEFrameLowering.cpp | 309 Register HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| D | MipsSEFrameLowering.cpp | 285 unsigned HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 1136 Register HiReg = MI.getOperand(1).getReg(); in emitReadCycleWidePseudo() local
1172 Register HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
1205 Register HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2184 unsigned SrcReg, LoReg, HiReg; in Select() local
2341 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 1465 Register HiReg = MRI->createVirtualRegister(RC); in selectG_CONSTANT() local
1674 Register HiReg = MRI->createVirtualRegister(&RegRC); in selectG_PTR_MASK() local
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| D | SILoadStoreOptimizer.cpp | 187 unsigned HiReg = 0; member
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 4790 unsigned SrcReg, LoReg, HiReg; in Select() local
4885 unsigned LoReg, HiReg, ClrReg; in Select() local
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 6102 unsigned Reg, unsigned HiReg, in checkLowRegisterList()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 7177 unsigned Reg, unsigned HiReg, in checkLowRegisterList()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 9054 unsigned HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 11342 Register HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
|