1VIXL Supported Instruction List 2=============================== 3 4This is a list of the AArch64 instructions supported by the VIXL assembler, 5disassembler and simulator. The simulator may not support all floating point 6operations to the precision required by AArch64 - please check the simulator 7source code for details. 8 9#### AAch64 integer instructions #### 10[a](#integer-a) [b](#integer-b) [c](#integer-c) [d](#integer-d) [e](#integer-e) [h](#integer-h) [i](#integer-i) [l](#integer-l) [m](#integer-m) [n](#integer-n) [o](#integer-o) [p](#integer-p) [r](#integer-r) [s](#integer-s) [t](#integer-t) [u](#integer-u) [x](#integer-x) 11 12#### AArch64 floating point and NEON instructions #### 13[a](#float-a) [b](#float-b) [c](#float-c) [d](#float-d) [e](#float-e) [f](#float-f) [i](#float-i) [l](#float-l) [m](#float-m) [n](#float-n) [o](#float-o) [p](#float-p) [r](#float-r) [s](#float-s) [t](#float-t) [u](#float-u) [x](#float-x) [z](#float-z) 14 15#### AArch64 Scalable Vector Extension (SVE) instructions #### 16[a](#sve-a) [b](#sve-b) [c](#sve-c) [d](#sve-d) [e](#sve-e) [f](#sve-f) [h](#sve-h) [i](#sve-i) [l](#sve-l) [m](#sve-m) [n](#sve-n) [o](#sve-o) [p](#sve-p) [r](#sve-r) [s](#sve-s) [t](#sve-t) [u](#sve-u) [w](#sve-w) [x](#sve-x) [z](#sve-z) 17 18#### Additional or pseudo instructions #### 19[b](#pseudo-b) [d](#pseudo-d) [p](#pseudo-p) 20 21___ 22 23AArch64 integer instructions 24---------------------------- 25 26<a id="integer-a"> 27 28### ADC ### 29 30Add with carry bit. 31 32 void adc(const Register& rd, const Register& rn, const Operand& operand) 33 34 35### ADCS ### 36 37Add with carry bit and update status flags. 38 39 void adcs(const Register& rd, const Register& rn, const Operand& operand) 40 41 42### ADD ### 43 44Add. 45 46 void add(const Register& rd, const Register& rn, const Operand& operand) 47 48 49### ADDS ### 50 51Add and update status flags. 52 53 void adds(const Register& rd, const Register& rn, const Operand& operand) 54 55 56### ADR ### 57 58Calculate the address of a PC offset. 59 60 void adr(const Register& xd, int64_t imm21) 61 62 63### ADR ### 64 65Calculate the address of a label. 66 67 void adr(const Register& xd, Label* label) 68 69 70### ADRP ### 71 72Calculate the page address of a PC offset. 73 74 void adrp(const Register& xd, int64_t imm21) 75 76 77### ADRP ### 78 79Calculate the page address of a label. 80 81 void adrp(const Register& xd, Label* label) 82 83 84### AND ### 85 86Bitwise and (A & B). 87 88 void and_(const Register& rd, const Register& rn, const Operand& operand) 89 90 91### ANDS ### 92 93Bitwise and (A & B) and update status flags. 94 95 void ands(const Register& rd, const Register& rn, const Operand& operand) 96 97 98### ASR ### 99 100Arithmetic shift right. 101 102 void asr(const Register& rd, const Register& rn, unsigned shift) 103 104 105### ASRV ### 106 107Arithmetic shift right by variable. 108 109 void asrv(const Register& rd, const Register& rn, const Register& rm) 110 111 112### AUTDA ### 113 114Authenticate Data address, using key A _(Armv8.3)_. 115 116 void autda(const Register& xd, const Register& xn) 117 118 119### AUTDB ### 120 121Authenticate Data address, using key B _(Armv8.3)_. 122 123 void autdb(const Register& xd, const Register& xn) 124 125 126### AUTDZA ### 127 128Authenticate Data address, using key A and a modifier of zero _(Armv8.3)_. 129 130 void autdza(const Register& xd) 131 132 133### AUTDZB ### 134 135Authenticate Data address, using key B and a modifier of zero _(Armv8.3)_. 136 137 void autdzb(const Register& xd) 138 139 140### AUTIA ### 141 142Authenticate Instruction address, using key A _(Armv8.3)_. 143 144 void autia(const Register& xd, const Register& xn) 145 146 147### AUTIA1716 ### 148 149Authenticate Instruction address, using key A, with address in x17 and modifier in x16 _(Armv8.3)_. 150 151 void autia1716() 152 153 154### AUTIASP ### 155 156Authenticate Instruction address, using key A, with address in LR and modifier in SP _(Armv8.3)_. 157 158 void autiasp() 159 160 161### AUTIAZ ### 162 163Authenticate Instruction address, using key A, with address in LR and a modifier of zero _(Armv8.3)_. 164 165 void autiaz() 166 167 168### AUTIB ### 169 170Authenticate Instruction address, using key B _(Armv8.3)_. 171 172 void autib(const Register& xd, const Register& xn) 173 174 175### AUTIB1716 ### 176 177Authenticate Instruction address, using key B, with address in x17 and modifier in x16 _(Armv8.3)_. 178 179 void autib1716() 180 181 182### AUTIBSP ### 183 184Authenticate Instruction address, using key B, with address in LR and modifier in SP _(Armv8.3)_. 185 186 void autibsp() 187 188 189### AUTIBZ ### 190 191Authenticate Instruction address, using key B, with address in LR and a modifier of zero _(Armv8.3)_. 192 193 void autibz() 194 195 196### AUTIZA ### 197 198Authenticate Instruction address, using key A and a modifier of zero _(Armv8.3)_. 199 200 void autiza(const Register& xd) 201 202 203### AUTIZB ### 204 205Authenticate Instruction address, using key B and a modifier of zero _(Armv8.3)_. 206 207 void autizb(const Register& xd) 208 209 210### AXFLAG ### 211 212Convert floating-point condition flags from Arm format to alternative format _(Armv8.5)_. 213 214 void axflag() 215 216 217<a id="integer-b"> 218 219### B ### 220 221Conditional branch to PC offset. 222 223 void b(int64_t imm19, Condition cond) 224 225 226### B ### 227 228Conditional branch to label. 229 230 void b(Label* label, Condition cond) 231 232 233### B ### 234 235Unconditional branch to PC offset. 236 237 void b(int64_t imm26) 238 239 240### B ### 241 242Unconditional branch to label. 243 244 void b(Label* label) 245 246 247### BFC ### 248 249Bitfield clear _(Armv8.2)_. 250 251 void bfc(const Register& rd, unsigned lsb, unsigned width) 252 253 254### BFI ### 255 256Bitfield insert. 257 258 void bfi(const Register& rd, 259 const Register& rn, 260 unsigned lsb, 261 unsigned width) 262 263 264### BFM ### 265 266Bitfield move. 267 268 void bfm(const Register& rd, 269 const Register& rn, 270 unsigned immr, 271 unsigned imms) 272 273 274### BFXIL ### 275 276Bitfield extract and insert low. 277 278 void bfxil(const Register& rd, 279 const Register& rn, 280 unsigned lsb, 281 unsigned width) 282 283 284### BIC ### 285 286Bit clear (A & ~B). 287 288 void bic(const Register& rd, const Register& rn, const Operand& operand) 289 290 291### BICS ### 292 293Bit clear (A & ~B) and update status flags. 294 295 void bics(const Register& rd, const Register& rn, const Operand& operand) 296 297 298### BL ### 299 300Branch with link to PC offset. 301 302 void bl(int64_t imm26) 303 304 305### BL ### 306 307Branch with link to label. 308 309 void bl(Label* label) 310 311 312### BLR ### 313 314Branch with link to register. 315 316 void blr(const Register& xn) 317 318 319### BLRAA ### 320 321Branch with link to register, with pointer authentication. Using key A _(Armv8.3)_. 322 323 void blraa(const Register& xn, const Register& xm) 324 325 326### BLRAAZ ### 327 328Branch with link to register, with pointer authentication. Using key A and a modifier of zero _(Armv8.3)_. 329 330 void blraaz(const Register& xn) 331 332 333### BLRAB ### 334 335Branch with link to register, with pointer authentication. Using key B _(Armv8.3)_. 336 337 void blrab(const Register& xn, const Register& xm) 338 339 340### BLRABZ ### 341 342Branch with link to register, with pointer authentication. Using key B and a modifier of zero _(Armv8.3)_. 343 344 void blrabz(const Register& xn) 345 346 347### BR ### 348 349Branch to register. 350 351 void br(const Register& xn) 352 353 354### BRAA ### 355 356Branch to register, with pointer authentication. Using key A _(Armv8.3)_. 357 358 void braa(const Register& xn, const Register& xm) 359 360 361### BRAAZ ### 362 363Branch to register, with pointer authentication. Using key A and a modifier of zero _(Armv8.3)_. 364 365 void braaz(const Register& xn) 366 367 368### BRAB ### 369 370Branch to register, with pointer authentication. Using key B _(Armv8.3)_. 371 372 void brab(const Register& xn, const Register& xm) 373 374 375### BRABZ ### 376 377Branch to register, with pointer authentication. Using key B and a modifier of zero _(Armv8.3)_. 378 379 void brabz(const Register& xn) 380 381 382### BRK ### 383 384Monitor debug-mode breakpoint. 385 386 void brk(int code) 387 388 389### BTI ### 390 391Branch target identification. 392 393 void bti(BranchTargetIdentifier id) 394 395 396<a id="integer-c"> 397 398### CAS ### 399 400Compare and Swap word or doubleword in memory _(Armv8.1)_. 401 402 void cas(const Register& rs, const Register& rt, const MemOperand& src) 403 404 405### CASA ### 406 407Compare and Swap word or doubleword in memory _(Armv8.1)_. 408 409 void casa(const Register& rs, const Register& rt, const MemOperand& src) 410 411 412### CASAB ### 413 414Compare and Swap byte in memory _(Armv8.1)_. 415 416 void casab(const Register& rs, const Register& rt, const MemOperand& src) 417 418 419### CASAH ### 420 421Compare and Swap halfword in memory _(Armv8.1)_. 422 423 void casah(const Register& rs, const Register& rt, const MemOperand& src) 424 425 426### CASAL ### 427 428Compare and Swap word or doubleword in memory _(Armv8.1)_. 429 430 void casal(const Register& rs, const Register& rt, const MemOperand& src) 431 432 433### CASALB ### 434 435Compare and Swap byte in memory _(Armv8.1)_. 436 437 void casalb(const Register& rs, const Register& rt, const MemOperand& src) 438 439 440### CASALH ### 441 442Compare and Swap halfword in memory _(Armv8.1)_. 443 444 void casalh(const Register& rs, const Register& rt, const MemOperand& src) 445 446 447### CASB ### 448 449Compare and Swap byte in memory _(Armv8.1)_. 450 451 void casb(const Register& rs, const Register& rt, const MemOperand& src) 452 453 454### CASH ### 455 456Compare and Swap halfword in memory _(Armv8.1)_. 457 458 void cash(const Register& rs, const Register& rt, const MemOperand& src) 459 460 461### CASL ### 462 463Compare and Swap word or doubleword in memory _(Armv8.1)_. 464 465 void casl(const Register& rs, const Register& rt, const MemOperand& src) 466 467 468### CASLB ### 469 470Compare and Swap byte in memory _(Armv8.1)_. 471 472 void caslb(const Register& rs, const Register& rt, const MemOperand& src) 473 474 475### CASLH ### 476 477Compare and Swap halfword in memory _(Armv8.1)_. 478 479 void caslh(const Register& rs, const Register& rt, const MemOperand& src) 480 481 482### CASP ### 483 484Compare and Swap Pair of words or doublewords in memory _(Armv8.1)_. 485 486 void casp(const Register& rs, 487 const Register& rs2, 488 const Register& rt, 489 const Register& rt2, 490 const MemOperand& src) 491 492 493### CASPA ### 494 495Compare and Swap Pair of words or doublewords in memory _(Armv8.1)_. 496 497 void caspa(const Register& rs, 498 const Register& rs2, 499 const Register& rt, 500 const Register& rt2, 501 const MemOperand& src) 502 503 504### CASPAL ### 505 506Compare and Swap Pair of words or doublewords in memory _(Armv8.1)_. 507 508 void caspal(const Register& rs, 509 const Register& rs2, 510 const Register& rt, 511 const Register& rt2, 512 const MemOperand& src) 513 514 515### CASPL ### 516 517Compare and Swap Pair of words or doublewords in memory _(Armv8.1)_. 518 519 void caspl(const Register& rs, 520 const Register& rs2, 521 const Register& rt, 522 const Register& rt2, 523 const MemOperand& src) 524 525 526### CBNZ ### 527 528Compare and branch to PC offset if not zero. 529 530 void cbnz(const Register& rt, int64_t imm19) 531 532 533### CBNZ ### 534 535Compare and branch to label if not zero. 536 537 void cbnz(const Register& rt, Label* label) 538 539 540### CBZ ### 541 542Compare and branch to PC offset if zero. 543 544 void cbz(const Register& rt, int64_t imm19) 545 546 547### CBZ ### 548 549Compare and branch to label if zero. 550 551 void cbz(const Register& rt, Label* label) 552 553 554### CCMN ### 555 556Conditional compare negative. 557 558 void ccmn(const Register& rn, 559 const Operand& operand, 560 StatusFlags nzcv, 561 Condition cond) 562 563 564### CCMP ### 565 566Conditional compare. 567 568 void ccmp(const Register& rn, 569 const Operand& operand, 570 StatusFlags nzcv, 571 Condition cond) 572 573 574### CFINV ### 575 576Invert carry flag _(Armv8.4)_. 577 578 void cfinv() 579 580 581### CINC ### 582 583Conditional increment: rd = cond ? rn + 1 : rn. 584 585 void cinc(const Register& rd, const Register& rn, Condition cond) 586 587 588### CINV ### 589 590Conditional invert: rd = cond ? ~rn : rn. 591 592 void cinv(const Register& rd, const Register& rn, Condition cond) 593 594 595### CLREX ### 596 597Clear exclusive monitor. 598 599 void clrex(int imm4 = 0xf) 600 601 602### CLS ### 603 604Count leading sign bits. 605 606 void cls(const Register& rd, const Register& rn) 607 608 609### CLZ ### 610 611Count leading zeroes. 612 613 void clz(const Register& rd, const Register& rn) 614 615 616### CMN ### 617 618Compare negative. 619 620 void cmn(const Register& rn, const Operand& operand) 621 622 623### CMP ### 624 625Compare. 626 627 void cmp(const Register& rn, const Operand& operand) 628 629 630### CNEG ### 631 632Conditional negate: rd = cond ? -rn : rn. 633 634 void cneg(const Register& rd, const Register& rn, Condition cond) 635 636 637### CRC32B ### 638 639CRC-32 checksum from byte. 640 641 void crc32b(const Register& wd, const Register& wn, const Register& wm) 642 643 644### CRC32CB ### 645 646CRC-32 C checksum from byte. 647 648 void crc32cb(const Register& wd, const Register& wn, const Register& wm) 649 650 651### CRC32CH ### 652 653CRC-32 C checksum from half-word. 654 655 void crc32ch(const Register& wd, const Register& wn, const Register& wm) 656 657 658### CRC32CW ### 659 660CRC-32 C checksum from word. 661 662 void crc32cw(const Register& wd, const Register& wn, const Register& wm) 663 664 665### CRC32CX ### 666 667CRC-32C checksum from double word. 668 669 void crc32cx(const Register& wd, const Register& wn, const Register& xm) 670 671 672### CRC32H ### 673 674CRC-32 checksum from half-word. 675 676 void crc32h(const Register& wd, const Register& wn, const Register& wm) 677 678 679### CRC32W ### 680 681CRC-32 checksum from word. 682 683 void crc32w(const Register& wd, const Register& wn, const Register& wm) 684 685 686### CRC32X ### 687 688CRC-32 checksum from double word. 689 690 void crc32x(const Register& wd, const Register& wn, const Register& xm) 691 692 693### CSDB ### 694 695Conditional speculation dependency barrier. 696 697 void csdb() 698 699 700### CSEL ### 701 702Conditional select: rd = cond ? rn : rm. 703 704 void csel(const Register& rd, 705 const Register& rn, 706 const Register& rm, 707 Condition cond) 708 709 710### CSET ### 711 712Conditional set: rd = cond ? 1 : 0. 713 714 void cset(const Register& rd, Condition cond) 715 716 717### CSETM ### 718 719Conditional set mask: rd = cond ? -1 : 0. 720 721 void csetm(const Register& rd, Condition cond) 722 723 724### CSINC ### 725 726Conditional select increment: rd = cond ? rn : rm + 1. 727 728 void csinc(const Register& rd, 729 const Register& rn, 730 const Register& rm, 731 Condition cond) 732 733 734### CSINV ### 735 736Conditional select inversion: rd = cond ? rn : ~rm. 737 738 void csinv(const Register& rd, 739 const Register& rn, 740 const Register& rm, 741 Condition cond) 742 743 744### CSNEG ### 745 746Conditional select negation: rd = cond ? rn : -rm. 747 748 void csneg(const Register& rd, 749 const Register& rn, 750 const Register& rm, 751 Condition cond) 752 753 754<a id="integer-d"> 755 756### DC ### 757 758System data cache operation. 759 760 void dc(DataCacheOp op, const Register& rt) 761 762 763### DMB ### 764 765Data memory barrier. 766 767 void dmb(BarrierDomain domain, BarrierType type) 768 769 770### DSB ### 771 772Data synchronization barrier. 773 774 void dsb(BarrierDomain domain, BarrierType type) 775 776 777<a id="integer-e"> 778 779### EON ### 780 781Bitwise enor/xnor (A ^ ~B). 782 783 void eon(const Register& rd, const Register& rn, const Operand& operand) 784 785 786### EOR ### 787 788Bitwise eor/xor (A ^ B). 789 790 void eor(const Register& rd, const Register& rn, const Operand& operand) 791 792 793### ESB ### 794 795Error synchronization barrier. 796 797 void esb() 798 799 800### EXTR ### 801 802Extract. 803 804 void extr(const Register& rd, 805 const Register& rn, 806 const Register& rm, 807 unsigned lsb) 808 809 810<a id="integer-h"> 811 812### HINT ### 813 814System hint (named type). 815 816 void hint(SystemHint code) 817 818 819### HINT ### 820 821System hint (numbered type). 822 823 void hint(int imm7) 824 825 826### HLT ### 827 828Halting debug-mode breakpoint. 829 830 void hlt(int code) 831 832 833<a id="integer-i"> 834 835### IC ### 836 837System instruction cache operation. 838 839 void ic(InstructionCacheOp op, const Register& rt) 840 841 842### ISB ### 843 844Instruction synchronization barrier. 845 846 void isb() 847 848 849<a id="integer-l"> 850 851### LDADD ### 852 853Atomic add on word or doubleword in memory _(Armv8.1)_ 854 855 void ldadd(const Register& rs, const Register& rt, const MemOperand& src) 856 857 858### LDADDA ### 859 860Atomic add on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_ 861 862 void ldadda(const Register& rs, const Register& rt, const MemOperand& src) 863 864 865### LDADDAB ### 866 867Atomic add on byte in memory, with Load-acquire semantics _(Armv8.1)_ 868 869 void ldaddab(const Register& rs, const Register& rt, const MemOperand& src) 870 871 872### LDADDAH ### 873 874Atomic add on halfword in memory, with Load-acquire semantics _(Armv8.1)_ 875 876 void ldaddah(const Register& rs, const Register& rt, const MemOperand& src) 877 878 879### LDADDAL ### 880 881Atomic add on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 882 883 void ldaddal(const Register& rs, const Register& rt, const MemOperand& src) 884 885 886### LDADDALB ### 887 888Atomic add on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 889 890 void ldaddalb(const Register& rs, const Register& rt, const MemOperand& src) 891 892 893### LDADDALH ### 894 895Atomic add on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 896 897 void ldaddalh(const Register& rs, const Register& rt, const MemOperand& src) 898 899 900### LDADDB ### 901 902Atomic add on byte in memory _(Armv8.1)_ 903 904 void ldaddb(const Register& rs, const Register& rt, const MemOperand& src) 905 906 907### LDADDH ### 908 909Atomic add on halfword in memory _(Armv8.1)_ 910 911 void ldaddh(const Register& rs, const Register& rt, const MemOperand& src) 912 913 914### LDADDL ### 915 916Atomic add on word or doubleword in memory, with Store-release semantics _(Armv8.1)_ 917 918 void ldaddl(const Register& rs, const Register& rt, const MemOperand& src) 919 920 921### LDADDLB ### 922 923Atomic add on byte in memory, with Store-release semantics _(Armv8.1)_ 924 925 void ldaddlb(const Register& rs, const Register& rt, const MemOperand& src) 926 927 928### LDADDLH ### 929 930Atomic add on halfword in memory, with Store-release semantics _(Armv8.1)_ 931 932 void ldaddlh(const Register& rs, const Register& rt, const MemOperand& src) 933 934 935### LDAPR ### 936 937Load-Acquire RCpc Register word or doubleword _(Armv8.3)_ 938 939 void ldapr(const Register& rt, const MemOperand& src) 940 941 942### LDAPRB ### 943 944Load-Acquire RCpc Register byte _(Armv8.3)_ 945 946 void ldaprb(const Register& rt, const MemOperand& src) 947 948 949### LDAPRH ### 950 951Load-Acquire RCpc Register halfword _(Armv8.3)_ 952 953 void ldaprh(const Register& rt, const MemOperand& src) 954 955 956### LDAPUR ### 957 958Load-acquire RCpc Register word or double-word (with unscaled offset) _(Armv8.4)_. 959 960 void ldapur(const Register& rt, const MemOperand& src) 961 962 963### LDAPURB ### 964 965Load-acquire RCpc Register byte (with unscaled offset) _(Armv8.4)_. 966 967 void ldapurb(const Register& rt, const MemOperand& src) 968 969 970### LDAPURH ### 971 972Load-acquire RCpc Register half-word (with unscaled offset) _(Armv8.4)_. 973 974 void ldapurh(const Register& rt, const MemOperand& src) 975 976 977### LDAPURSB ### 978 979Load-acquire RCpc Register signed byte (with unscaled offset) _(Armv8.4)_. 980 981 void ldapursb(const Register& rt, const MemOperand& src) 982 983 984### LDAPURSH ### 985 986Load-acquire RCpc Register signed half-word (with unscaled offset) _(Armv8.4)_. 987 988 void ldapursh(const Register& rt, const MemOperand& src) 989 990 991### LDAPURSW ### 992 993Load-acquire RCpc Register signed word (with unscaled offset) _(Armv8.4)_. 994 995 void ldapursw(const Register& xt, const MemOperand& src) 996 997 998### LDAR ### 999 1000Load-acquire register. 1001 1002 void ldar(const Register& rt, const MemOperand& src) 1003 1004 1005### LDARB ### 1006 1007Load-acquire byte. 1008 1009 void ldarb(const Register& rt, const MemOperand& src) 1010 1011 1012### LDARH ### 1013 1014Load-acquire half-word. 1015 1016 void ldarh(const Register& rt, const MemOperand& src) 1017 1018 1019### LDAXP ### 1020 1021Load-acquire exclusive register pair. 1022 1023 void ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) 1024 1025 1026### LDAXR ### 1027 1028Load-acquire exclusive register. 1029 1030 void ldaxr(const Register& rt, const MemOperand& src) 1031 1032 1033### LDAXRB ### 1034 1035Load-acquire exclusive byte. 1036 1037 void ldaxrb(const Register& rt, const MemOperand& src) 1038 1039 1040### LDAXRH ### 1041 1042Load-acquire exclusive half-word. 1043 1044 void ldaxrh(const Register& rt, const MemOperand& src) 1045 1046 1047### LDCLR ### 1048 1049Atomic bit clear on word or doubleword in memory _(Armv8.1)_ 1050 1051 void ldclr(const Register& rs, const Register& rt, const MemOperand& src) 1052 1053 1054### LDCLRA ### 1055 1056Atomic bit clear on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_ 1057 1058 void ldclra(const Register& rs, const Register& rt, const MemOperand& src) 1059 1060 1061### LDCLRAB ### 1062 1063Atomic bit clear on byte in memory, with Load-acquire semantics _(Armv8.1)_ 1064 1065 void ldclrab(const Register& rs, const Register& rt, const MemOperand& src) 1066 1067 1068### LDCLRAH ### 1069 1070Atomic bit clear on halfword in memory, with Load-acquire semantics _(Armv8.1)_ 1071 1072 void ldclrah(const Register& rs, const Register& rt, const MemOperand& src) 1073 1074 1075### LDCLRAL ### 1076 1077Atomic bit clear on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1078 1079 void ldclral(const Register& rs, const Register& rt, const MemOperand& src) 1080 1081 1082### LDCLRALB ### 1083 1084Atomic bit clear on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1085 1086 void ldclralb(const Register& rs, const Register& rt, const MemOperand& src) 1087 1088 1089### LDCLRALH ### 1090 1091Atomic bit clear on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1092 1093 void ldclralh(const Register& rs, const Register& rt, const MemOperand& src) 1094 1095 1096### LDCLRB ### 1097 1098Atomic bit clear on byte in memory _(Armv8.1)_ 1099 1100 void ldclrb(const Register& rs, const Register& rt, const MemOperand& src) 1101 1102 1103### LDCLRH ### 1104 1105Atomic bit clear on halfword in memory _(Armv8.1)_ 1106 1107 void ldclrh(const Register& rs, const Register& rt, const MemOperand& src) 1108 1109 1110### LDCLRL ### 1111 1112Atomic bit clear on word or doubleword in memory, with Store-release semantics _(Armv8.1)_ 1113 1114 void ldclrl(const Register& rs, const Register& rt, const MemOperand& src) 1115 1116 1117### LDCLRLB ### 1118 1119Atomic bit clear on byte in memory, with Store-release semantics _(Armv8.1)_ 1120 1121 void ldclrlb(const Register& rs, const Register& rt, const MemOperand& src) 1122 1123 1124### LDCLRLH ### 1125 1126Atomic bit clear on halfword in memory, with Store-release semantics _(Armv8.1)_ 1127 1128 void ldclrlh(const Register& rs, const Register& rt, const MemOperand& src) 1129 1130 1131### LDEOR ### 1132 1133Atomic exclusive OR on word or doubleword in memory _(Armv8.1)_ 1134 1135 void ldeor(const Register& rs, const Register& rt, const MemOperand& src) 1136 1137 1138### LDEORA ### 1139 1140Atomic exclusive OR on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_ 1141 1142 void ldeora(const Register& rs, const Register& rt, const MemOperand& src) 1143 1144 1145### LDEORAB ### 1146 1147Atomic exclusive OR on byte in memory, with Load-acquire semantics _(Armv8.1)_ 1148 1149 void ldeorab(const Register& rs, const Register& rt, const MemOperand& src) 1150 1151 1152### LDEORAH ### 1153 1154Atomic exclusive OR on halfword in memory, with Load-acquire semantics _(Armv8.1)_ 1155 1156 void ldeorah(const Register& rs, const Register& rt, const MemOperand& src) 1157 1158 1159### LDEORAL ### 1160 1161Atomic exclusive OR on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1162 1163 void ldeoral(const Register& rs, const Register& rt, const MemOperand& src) 1164 1165 1166### LDEORALB ### 1167 1168Atomic exclusive OR on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1169 1170 void ldeoralb(const Register& rs, const Register& rt, const MemOperand& src) 1171 1172 1173### LDEORALH ### 1174 1175Atomic exclusive OR on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1176 1177 void ldeoralh(const Register& rs, const Register& rt, const MemOperand& src) 1178 1179 1180### LDEORB ### 1181 1182Atomic exclusive OR on byte in memory _(Armv8.1)_ 1183 1184 void ldeorb(const Register& rs, const Register& rt, const MemOperand& src) 1185 1186 1187### LDEORH ### 1188 1189Atomic exclusive OR on halfword in memory _(Armv8.1)_ 1190 1191 void ldeorh(const Register& rs, const Register& rt, const MemOperand& src) 1192 1193 1194### LDEORL ### 1195 1196Atomic exclusive OR on word or doubleword in memory, with Store-release semantics _(Armv8.1)_ 1197 1198 void ldeorl(const Register& rs, const Register& rt, const MemOperand& src) 1199 1200 1201### LDEORLB ### 1202 1203Atomic exclusive OR on byte in memory, with Store-release semantics _(Armv8.1)_ 1204 1205 void ldeorlb(const Register& rs, const Register& rt, const MemOperand& src) 1206 1207 1208### LDEORLH ### 1209 1210Atomic exclusive OR on halfword in memory, with Store-release semantics _(Armv8.1)_ 1211 1212 void ldeorlh(const Register& rs, const Register& rt, const MemOperand& src) 1213 1214 1215### LDLAR ### 1216 1217Load LORelease register _(Armv8.1)_. 1218 1219 void ldlar(const Register& rt, const MemOperand& src) 1220 1221 1222### LDLARB ### 1223 1224Load LORelease byte _(Armv8.1)_. 1225 1226 void ldlarb(const Register& rt, const MemOperand& src) 1227 1228 1229### LDLARH ### 1230 1231Load LORelease half-word _(Armv8.1)_. 1232 1233 void ldlarh(const Register& rt, const MemOperand& src) 1234 1235 1236### LDNP ### 1237 1238Load integer or FP register pair, non-temporal. 1239 1240 void ldnp(const CPURegister& rt, 1241 const CPURegister& rt2, 1242 const MemOperand& src) 1243 1244 1245### LDP ### 1246 1247Load integer or FP register pair. 1248 1249 void ldp(const CPURegister& rt, 1250 const CPURegister& rt2, 1251 const MemOperand& src) 1252 1253 1254### LDPSW ### 1255 1256Load word pair with sign extension. 1257 1258 void ldpsw(const Register& xt, const Register& xt2, const MemOperand& src) 1259 1260 1261### LDR ### 1262 1263Load integer or FP register from literal pool. 1264 1265 void ldr(const CPURegister& rt, RawLiteral* literal) 1266 1267 1268### LDR ### 1269 1270Load integer or FP register from pc + imm19 << 2. 1271 1272 void ldr(const CPURegister& rt, int64_t imm19) 1273 1274 1275### LDR ### 1276 1277Load integer or FP register. 1278 1279 void ldr(const CPURegister& rt, 1280 const MemOperand& src, 1281 LoadStoreScalingOption option = PreferScaledOffset) 1282 1283 1284### LDRAA ### 1285 1286Load double-word with pointer authentication, using data key A and a modifier of zero _(Armv8.3)_. 1287 1288 void ldraa(const Register& xt, const MemOperand& src) 1289 1290 1291### LDRAB ### 1292 1293Load double-word with pointer authentication, using data key B and a modifier of zero _(Armv8.3)_. 1294 1295 void ldrab(const Register& xt, const MemOperand& src) 1296 1297 1298### LDRB ### 1299 1300Load byte. 1301 1302 void ldrb(const Register& rt, 1303 const MemOperand& src, 1304 LoadStoreScalingOption option = PreferScaledOffset) 1305 1306 1307### LDRH ### 1308 1309Load half-word. 1310 1311 void ldrh(const Register& rt, 1312 const MemOperand& src, 1313 LoadStoreScalingOption option = PreferScaledOffset) 1314 1315 1316### LDRSB ### 1317 1318Load byte with sign extension. 1319 1320 void ldrsb(const Register& rt, 1321 const MemOperand& src, 1322 LoadStoreScalingOption option = PreferScaledOffset) 1323 1324 1325### LDRSH ### 1326 1327Load half-word with sign extension. 1328 1329 void ldrsh(const Register& rt, 1330 const MemOperand& src, 1331 LoadStoreScalingOption option = PreferScaledOffset) 1332 1333 1334### LDRSW ### 1335 1336Load word with sign extension from literal pool. 1337 1338 void ldrsw(const Register& xt, RawLiteral* literal) 1339 1340 1341### LDRSW ### 1342 1343Load word with sign extension from pc + imm19 << 2. 1344 1345 void ldrsw(const Register& xt, int64_t imm19) 1346 1347 1348### LDRSW ### 1349 1350Load word with sign extension. 1351 1352 void ldrsw(const Register& xt, 1353 const MemOperand& src, 1354 LoadStoreScalingOption option = PreferScaledOffset) 1355 1356 1357### LDSET ### 1358 1359Atomic bit set on word or doubleword in memory _(Armv8.1)_ 1360 1361 void ldset(const Register& rs, const Register& rt, const MemOperand& src) 1362 1363 1364### LDSETA ### 1365 1366Atomic bit set on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_ 1367 1368 void ldseta(const Register& rs, const Register& rt, const MemOperand& src) 1369 1370 1371### LDSETAB ### 1372 1373Atomic bit set on byte in memory, with Load-acquire semantics _(Armv8.1)_ 1374 1375 void ldsetab(const Register& rs, const Register& rt, const MemOperand& src) 1376 1377 1378### LDSETAH ### 1379 1380Atomic bit set on halfword in memory, with Load-acquire semantics _(Armv8.1)_ 1381 1382 void ldsetah(const Register& rs, const Register& rt, const MemOperand& src) 1383 1384 1385### LDSETAL ### 1386 1387Atomic bit set on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1388 1389 void ldsetal(const Register& rs, const Register& rt, const MemOperand& src) 1390 1391 1392### LDSETALB ### 1393 1394Atomic bit set on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1395 1396 void ldsetalb(const Register& rs, const Register& rt, const MemOperand& src) 1397 1398 1399### LDSETALH ### 1400 1401Atomic bit set on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1402 1403 void ldsetalh(const Register& rs, const Register& rt, const MemOperand& src) 1404 1405 1406### LDSETB ### 1407 1408Atomic bit set on byte in memory _(Armv8.1)_ 1409 1410 void ldsetb(const Register& rs, const Register& rt, const MemOperand& src) 1411 1412 1413### LDSETH ### 1414 1415Atomic bit set on halfword in memory _(Armv8.1)_ 1416 1417 void ldseth(const Register& rs, const Register& rt, const MemOperand& src) 1418 1419 1420### LDSETL ### 1421 1422Atomic bit set on word or doubleword in memory, with Store-release semantics _(Armv8.1)_ 1423 1424 void ldsetl(const Register& rs, const Register& rt, const MemOperand& src) 1425 1426 1427### LDSETLB ### 1428 1429Atomic bit set on byte in memory, with Store-release semantics _(Armv8.1)_ 1430 1431 void ldsetlb(const Register& rs, const Register& rt, const MemOperand& src) 1432 1433 1434### LDSETLH ### 1435 1436Atomic bit set on halfword in memory, with Store-release semantics _(Armv8.1)_ 1437 1438 void ldsetlh(const Register& rs, const Register& rt, const MemOperand& src) 1439 1440 1441### LDSMAX ### 1442 1443Atomic signed maximum on word or doubleword in memory _(Armv8.1)_ 1444 1445 void ldsmax(const Register& rs, const Register& rt, const MemOperand& src) 1446 1447 1448### LDSMAXA ### 1449 1450Atomic signed maximum on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_ 1451 1452 void ldsmaxa(const Register& rs, const Register& rt, const MemOperand& src) 1453 1454 1455### LDSMAXAB ### 1456 1457Atomic signed maximum on byte in memory, with Load-acquire semantics _(Armv8.1)_ 1458 1459 void ldsmaxab(const Register& rs, const Register& rt, const MemOperand& src) 1460 1461 1462### LDSMAXAH ### 1463 1464Atomic signed maximum on halfword in memory, with Load-acquire semantics _(Armv8.1)_ 1465 1466 void ldsmaxah(const Register& rs, const Register& rt, const MemOperand& src) 1467 1468 1469### LDSMAXAL ### 1470 1471Atomic signed maximum on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1472 1473 void ldsmaxal(const Register& rs, const Register& rt, const MemOperand& src) 1474 1475 1476### LDSMAXALB ### 1477 1478Atomic signed maximum on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1479 1480 void ldsmaxalb(const Register& rs, const Register& rt, const MemOperand& src) 1481 1482 1483### LDSMAXALH ### 1484 1485Atomic signed maximum on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1486 1487 void ldsmaxalh(const Register& rs, const Register& rt, const MemOperand& src) 1488 1489 1490### LDSMAXB ### 1491 1492Atomic signed maximum on byte in memory _(Armv8.1)_ 1493 1494 void ldsmaxb(const Register& rs, const Register& rt, const MemOperand& src) 1495 1496 1497### LDSMAXH ### 1498 1499Atomic signed maximum on halfword in memory _(Armv8.1)_ 1500 1501 void ldsmaxh(const Register& rs, const Register& rt, const MemOperand& src) 1502 1503 1504### LDSMAXL ### 1505 1506Atomic signed maximum on word or doubleword in memory, with Store-release semantics _(Armv8.1)_ 1507 1508 void ldsmaxl(const Register& rs, const Register& rt, const MemOperand& src) 1509 1510 1511### LDSMAXLB ### 1512 1513Atomic signed maximum on byte in memory, with Store-release semantics _(Armv8.1)_ 1514 1515 void ldsmaxlb(const Register& rs, const Register& rt, const MemOperand& src) 1516 1517 1518### LDSMAXLH ### 1519 1520Atomic signed maximum on halfword in memory, with Store-release semantics _(Armv8.1)_ 1521 1522 void ldsmaxlh(const Register& rs, const Register& rt, const MemOperand& src) 1523 1524 1525### LDSMIN ### 1526 1527Atomic signed minimum on word or doubleword in memory _(Armv8.1)_ 1528 1529 void ldsmin(const Register& rs, const Register& rt, const MemOperand& src) 1530 1531 1532### LDSMINA ### 1533 1534Atomic signed minimum on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_ 1535 1536 void ldsmina(const Register& rs, const Register& rt, const MemOperand& src) 1537 1538 1539### LDSMINAB ### 1540 1541Atomic signed minimum on byte in memory, with Load-acquire semantics _(Armv8.1)_ 1542 1543 void ldsminab(const Register& rs, const Register& rt, const MemOperand& src) 1544 1545 1546### LDSMINAH ### 1547 1548Atomic signed minimum on halfword in memory, with Load-acquire semantics _(Armv8.1)_ 1549 1550 void ldsminah(const Register& rs, const Register& rt, const MemOperand& src) 1551 1552 1553### LDSMINAL ### 1554 1555Atomic signed minimum on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1556 1557 void ldsminal(const Register& rs, const Register& rt, const MemOperand& src) 1558 1559 1560### LDSMINALB ### 1561 1562Atomic signed minimum on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1563 1564 void ldsminalb(const Register& rs, const Register& rt, const MemOperand& src) 1565 1566 1567### LDSMINALH ### 1568 1569Atomic signed minimum on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1570 1571 void ldsminalh(const Register& rs, const Register& rt, const MemOperand& src) 1572 1573 1574### LDSMINB ### 1575 1576Atomic signed minimum on byte in memory _(Armv8.1)_ 1577 1578 void ldsminb(const Register& rs, const Register& rt, const MemOperand& src) 1579 1580 1581### LDSMINH ### 1582 1583Atomic signed minimum on halfword in memory _(Armv8.1)_ 1584 1585 void ldsminh(const Register& rs, const Register& rt, const MemOperand& src) 1586 1587 1588### LDSMINL ### 1589 1590Atomic signed minimum on word or doubleword in memory, with Store-release semantics _(Armv8.1)_ 1591 1592 void ldsminl(const Register& rs, const Register& rt, const MemOperand& src) 1593 1594 1595### LDSMINLB ### 1596 1597Atomic signed minimum on byte in memory, with Store-release semantics _(Armv8.1)_ 1598 1599 void ldsminlb(const Register& rs, const Register& rt, const MemOperand& src) 1600 1601 1602### LDSMINLH ### 1603 1604Atomic signed minimum on halfword in memory, with Store-release semantics _(Armv8.1)_ 1605 1606 void ldsminlh(const Register& rs, const Register& rt, const MemOperand& src) 1607 1608 1609### LDUMAX ### 1610 1611Atomic unsigned maximum on word or doubleword in memory _(Armv8.1)_ 1612 1613 void ldumax(const Register& rs, const Register& rt, const MemOperand& src) 1614 1615 1616### LDUMAXA ### 1617 1618Atomic unsigned maximum on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_ 1619 1620 void ldumaxa(const Register& rs, const Register& rt, const MemOperand& src) 1621 1622 1623### LDUMAXAB ### 1624 1625Atomic unsigned maximum on byte in memory, with Load-acquire semantics _(Armv8.1)_ 1626 1627 void ldumaxab(const Register& rs, const Register& rt, const MemOperand& src) 1628 1629 1630### LDUMAXAH ### 1631 1632Atomic unsigned maximum on halfword in memory, with Load-acquire semantics _(Armv8.1)_ 1633 1634 void ldumaxah(const Register& rs, const Register& rt, const MemOperand& src) 1635 1636 1637### LDUMAXAL ### 1638 1639Atomic unsigned maximum on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1640 1641 void ldumaxal(const Register& rs, const Register& rt, const MemOperand& src) 1642 1643 1644### LDUMAXALB ### 1645 1646Atomic unsigned maximum on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1647 1648 void ldumaxalb(const Register& rs, const Register& rt, const MemOperand& src) 1649 1650 1651### LDUMAXALH ### 1652 1653Atomic unsigned maximum on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1654 1655 void ldumaxalh(const Register& rs, const Register& rt, const MemOperand& src) 1656 1657 1658### LDUMAXB ### 1659 1660Atomic unsigned maximum on byte in memory _(Armv8.1)_ 1661 1662 void ldumaxb(const Register& rs, const Register& rt, const MemOperand& src) 1663 1664 1665### LDUMAXH ### 1666 1667Atomic unsigned maximum on halfword in memory _(Armv8.1)_ 1668 1669 void ldumaxh(const Register& rs, const Register& rt, const MemOperand& src) 1670 1671 1672### LDUMAXL ### 1673 1674Atomic unsigned maximum on word or doubleword in memory, with Store-release semantics _(Armv8.1)_ 1675 1676 void ldumaxl(const Register& rs, const Register& rt, const MemOperand& src) 1677 1678 1679### LDUMAXLB ### 1680 1681Atomic unsigned maximum on byte in memory, with Store-release semantics _(Armv8.1)_ 1682 1683 void ldumaxlb(const Register& rs, const Register& rt, const MemOperand& src) 1684 1685 1686### LDUMAXLH ### 1687 1688Atomic unsigned maximum on halfword in memory, with Store-release semantics _(Armv8.1)_ 1689 1690 void ldumaxlh(const Register& rs, const Register& rt, const MemOperand& src) 1691 1692 1693### LDUMIN ### 1694 1695Atomic unsigned minimum on word or doubleword in memory _(Armv8.1)_ 1696 1697 void ldumin(const Register& rs, const Register& rt, const MemOperand& src) 1698 1699 1700### LDUMINA ### 1701 1702Atomic unsigned minimum on word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_ 1703 1704 void ldumina(const Register& rs, const Register& rt, const MemOperand& src) 1705 1706 1707### LDUMINAB ### 1708 1709Atomic unsigned minimum on byte in memory, with Load-acquire semantics _(Armv8.1)_ 1710 1711 void lduminab(const Register& rs, const Register& rt, const MemOperand& src) 1712 1713 1714### LDUMINAH ### 1715 1716Atomic unsigned minimum on halfword in memory, with Load-acquire semantics _(Armv8.1)_ 1717 1718 void lduminah(const Register& rs, const Register& rt, const MemOperand& src) 1719 1720 1721### LDUMINAL ### 1722 1723Atomic unsigned minimum on word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1724 1725 void lduminal(const Register& rs, const Register& rt, const MemOperand& src) 1726 1727 1728### LDUMINALB ### 1729 1730Atomic unsigned minimum on byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1731 1732 void lduminalb(const Register& rs, const Register& rt, const MemOperand& src) 1733 1734 1735### LDUMINALH ### 1736 1737Atomic unsigned minimum on halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 1738 1739 void lduminalh(const Register& rs, const Register& rt, const MemOperand& src) 1740 1741 1742### LDUMINB ### 1743 1744Atomic unsigned minimum on byte in memory _(Armv8.1)_ 1745 1746 void lduminb(const Register& rs, const Register& rt, const MemOperand& src) 1747 1748 1749### LDUMINH ### 1750 1751Atomic unsigned minimum on halfword in memory _(Armv8.1)_ 1752 1753 void lduminh(const Register& rs, const Register& rt, const MemOperand& src) 1754 1755 1756### LDUMINL ### 1757 1758Atomic unsigned minimum on word or doubleword in memory, with Store-release semantics _(Armv8.1)_ 1759 1760 void lduminl(const Register& rs, const Register& rt, const MemOperand& src) 1761 1762 1763### LDUMINLB ### 1764 1765Atomic unsigned minimum on byte in memory, with Store-release semantics _(Armv8.1)_ 1766 1767 void lduminlb(const Register& rs, const Register& rt, const MemOperand& src) 1768 1769 1770### LDUMINLH ### 1771 1772Atomic unsigned minimum on halfword in memory, with Store-release semantics _(Armv8.1)_ 1773 1774 void lduminlh(const Register& rs, const Register& rt, const MemOperand& src) 1775 1776 1777### LDUR ### 1778 1779Load integer or FP register (with unscaled offset). 1780 1781 void ldur(const CPURegister& rt, 1782 const MemOperand& src, 1783 LoadStoreScalingOption option = PreferUnscaledOffset) 1784 1785 1786### LDURB ### 1787 1788Load byte (with unscaled offset). 1789 1790 void ldurb(const Register& rt, 1791 const MemOperand& src, 1792 LoadStoreScalingOption option = PreferUnscaledOffset) 1793 1794 1795### LDURH ### 1796 1797Load half-word (with unscaled offset). 1798 1799 void ldurh(const Register& rt, 1800 const MemOperand& src, 1801 LoadStoreScalingOption option = PreferUnscaledOffset) 1802 1803 1804### LDURSB ### 1805 1806Load byte with sign extension (and unscaled offset). 1807 1808 void ldursb(const Register& rt, 1809 const MemOperand& src, 1810 LoadStoreScalingOption option = PreferUnscaledOffset) 1811 1812 1813### LDURSH ### 1814 1815Load half-word with sign extension (and unscaled offset). 1816 1817 void ldursh(const Register& rt, 1818 const MemOperand& src, 1819 LoadStoreScalingOption option = PreferUnscaledOffset) 1820 1821 1822### LDURSW ### 1823 1824Load word with sign extension. 1825 1826 void ldursw(const Register& xt, 1827 const MemOperand& src, 1828 LoadStoreScalingOption option = PreferUnscaledOffset) 1829 1830 1831### LDXP ### 1832 1833Load exclusive register pair. 1834 1835 void ldxp(const Register& rt, const Register& rt2, const MemOperand& src) 1836 1837 1838### LDXR ### 1839 1840Load exclusive register. 1841 1842 void ldxr(const Register& rt, const MemOperand& src) 1843 1844 1845### LDXRB ### 1846 1847Load exclusive byte. 1848 1849 void ldxrb(const Register& rt, const MemOperand& src) 1850 1851 1852### LDXRH ### 1853 1854Load exclusive half-word. 1855 1856 void ldxrh(const Register& rt, const MemOperand& src) 1857 1858 1859### LSL ### 1860 1861Logical shift left. 1862 1863 void lsl(const Register& rd, const Register& rn, unsigned shift) 1864 1865 1866### LSLV ### 1867 1868Logical shift left by variable. 1869 1870 void lslv(const Register& rd, const Register& rn, const Register& rm) 1871 1872 1873### LSR ### 1874 1875Logical shift right. 1876 1877 void lsr(const Register& rd, const Register& rn, unsigned shift) 1878 1879 1880### LSRV ### 1881 1882Logical shift right by variable. 1883 1884 void lsrv(const Register& rd, const Register& rn, const Register& rm) 1885 1886 1887<a id="integer-m"> 1888 1889### MADD ### 1890 1891Multiply and accumulate. 1892 1893 void madd(const Register& rd, 1894 const Register& rn, 1895 const Register& rm, 1896 const Register& ra) 1897 1898 1899### MNEG ### 1900 1901Negated multiply. 1902 1903 void mneg(const Register& rd, const Register& rn, const Register& rm) 1904 1905 1906### MOV ### 1907 1908Move immediate, aliases for movz, movn, orr. 1909 1910 void mov(const Register& rd, uint64_t imm) 1911 1912 1913### MOV ### 1914 1915Move register to register. 1916 1917 void mov(const Register& rd, const Register& rn) 1918 1919 1920### MOVK ### 1921 1922Move immediate and keep. 1923 1924 void movk(const Register& rd, uint64_t imm, int shift = -1) 1925 1926 1927### MOVN ### 1928 1929Move inverted immediate. 1930 1931 void movn(const Register& rd, uint64_t imm, int shift = -1) 1932 1933 1934### MOVZ ### 1935 1936Move immediate. 1937 1938 void movz(const Register& rd, uint64_t imm, int shift = -1) 1939 1940 1941### MRS ### 1942 1943Move to register from system register. 1944 1945 void mrs(const Register& xt, SystemRegister sysreg) 1946 1947 1948### MSR ### 1949 1950Move from register to system register. 1951 1952 void msr(SystemRegister sysreg, const Register& xt) 1953 1954 1955### MSUB ### 1956 1957Multiply and subtract. 1958 1959 void msub(const Register& rd, 1960 const Register& rn, 1961 const Register& rm, 1962 const Register& ra) 1963 1964 1965### MUL ### 1966 1967Multiply. 1968 1969 void mul(const Register& rd, const Register& rn, const Register& rm) 1970 1971 1972### MVN ### 1973 1974Move inverted operand to register. 1975 1976 void mvn(const Register& rd, const Operand& operand) 1977 1978 1979<a id="integer-n"> 1980 1981### NEG ### 1982 1983Negate. 1984 1985 void neg(const Register& rd, const Operand& operand) 1986 1987 1988### NEGS ### 1989 1990Negate and update status flags. 1991 1992 void negs(const Register& rd, const Operand& operand) 1993 1994 1995### NGC ### 1996 1997Negate with carry bit. 1998 1999 void ngc(const Register& rd, const Operand& operand) 2000 2001 2002### NGCS ### 2003 2004Negate with carry bit and update status flags. 2005 2006 void ngcs(const Register& rd, const Operand& operand) 2007 2008 2009### NOP ### 2010 2011No-op. 2012 2013 void nop() 2014 2015 2016<a id="integer-o"> 2017 2018### ORN ### 2019 2020Bitwise nor (A | ~B). 2021 2022 void orn(const Register& rd, const Register& rn, const Operand& operand) 2023 2024 2025### ORR ### 2026 2027Bitwise or (A | B). 2028 2029 void orr(const Register& rd, const Register& rn, const Operand& operand) 2030 2031 2032<a id="integer-p"> 2033 2034### PACDA ### 2035 2036Pointer Authentication Code for Data address, using key A _(Armv8.3)_. 2037 2038 void pacda(const Register& xd, const Register& xn) 2039 2040 2041### PACDB ### 2042 2043Pointer Authentication Code for Data address, using key B _(Armv8.3)_. 2044 2045 void pacdb(const Register& xd, const Register& xn) 2046 2047 2048### PACDZA ### 2049 2050Pointer Authentication Code for Data address, using key A and a modifier of zero _(Armv8.3)_. 2051 2052 void pacdza(const Register& xd) 2053 2054 2055### PACDZB ### 2056 2057Pointer Authentication Code for Data address, using key B and a modifier of zero _(Armv8.3)_. 2058 2059 void pacdzb(const Register& xd) 2060 2061 2062### PACGA ### 2063 2064Pointer Authentication Code, using Generic key _(Armv8.3)_. 2065 2066 void pacga(const Register& xd, const Register& xn, const Register& xm) 2067 2068 2069### PACIA ### 2070 2071Pointer Authentication Code for Instruction address, using key A _(Armv8.3)_. 2072 2073 void pacia(const Register& xd, const Register& rn) 2074 2075 2076### PACIA1716 ### 2077 2078Pointer Authentication Code for Instruction address, using key A, with address in x17 and modifier in x16 _(Armv8.3)_. 2079 2080 void pacia1716() 2081 2082 2083### PACIASP ### 2084 2085Pointer Authentication Code for Instruction address, using key A, with address in LR and modifier in SP _(Armv8.3)_. 2086 2087 void paciasp() 2088 2089 2090### PACIAZ ### 2091 2092Pointer Authentication Code for Instruction address, using key A, with address in LR and a modifier of zero _(Armv8.3)_. 2093 2094 void paciaz() 2095 2096 2097### PACIB ### 2098 2099Pointer Authentication Code for Instruction address, using key B _(Armv8.3)_. 2100 2101 void pacib(const Register& xd, const Register& xn) 2102 2103 2104### PACIB1716 ### 2105 2106Pointer Authentication Code for Instruction address, using key B, with address in x17 and modifier in x16 _(Armv8.3)_. 2107 2108 void pacib1716() 2109 2110 2111### PACIBSP ### 2112 2113Pointer Authentication Code for Instruction address, using key B, with address in LR and modifier in SP _(Armv8.3)_. 2114 2115 void pacibsp() 2116 2117 2118### PACIBZ ### 2119 2120Pointer Authentication Code for Instruction address, using key B, with address in LR and a modifier of zero _(Armv8.3)_. 2121 2122 void pacibz() 2123 2124 2125### PACIZA ### 2126 2127Pointer Authentication Code for Instruction address, using key A and a modifier of zero _(Armv8.3)_. 2128 2129 void paciza(const Register& xd) 2130 2131 2132### PACIZB ### 2133 2134Pointer Authentication Code for Instruction address, using key B and a modifier of zero _(Armv8.3)_. 2135 2136 void pacizb(const Register& xd) 2137 2138 2139### PRFM ### 2140 2141Prefetch from pc + imm19 << 2 (allowing unallocated hints). 2142 2143 void prfm(int op, int64_t imm19) 2144 2145 2146### PRFM ### 2147 2148Prefetch from pc + imm19 << 2. 2149 2150 void prfm(PrefetchOperation op, int64_t imm19) 2151 2152 2153### PRFM ### 2154 2155Prefetch memory (allowing unallocated hints). 2156 2157 void prfm(int op, 2158 const MemOperand& addr, 2159 LoadStoreScalingOption option = PreferScaledOffset) 2160 2161 2162### PRFM ### 2163 2164Prefetch memory in the literal pool (allowing unallocated hints). 2165 2166 void prfm(int op, RawLiteral* literal) 2167 2168 2169### PRFM ### 2170 2171Prefetch memory in the literal pool. 2172 2173 void prfm(PrefetchOperation op, RawLiteral* literal) 2174 2175 2176### PRFM ### 2177 2178Prefetch memory. 2179 2180 void prfm(PrefetchOperation op, 2181 const MemOperand& addr, 2182 LoadStoreScalingOption option = PreferScaledOffset) 2183 2184 2185### PRFUM ### 2186 2187Prefetch memory (with unscaled offset). 2188 2189 void prfum(PrefetchOperation op, 2190 const MemOperand& addr, 2191 LoadStoreScalingOption option = PreferUnscaledOffset) 2192 2193 2194### PRFUM ### 2195 2196Prefetch memory (with unscaled offset, allowing unallocated hints). 2197 2198 void prfum(int op, 2199 const MemOperand& addr, 2200 LoadStoreScalingOption option = PreferUnscaledOffset) 2201 2202 2203<a id="integer-r"> 2204 2205### RBIT ### 2206 2207Bit reverse. 2208 2209 void rbit(const Register& rd, const Register& rn) 2210 2211 2212### RET ### 2213 2214Branch to register with return hint. 2215 2216 void ret(const Register& xn = lr) 2217 2218 2219### RETAA ### 2220 2221Return from subroutine, with pointer authentication. Using key A _(Armv8.3)_. 2222 2223 void retaa() 2224 2225 2226### RETAB ### 2227 2228Return from subroutine, with pointer authentication. Using key B _(Armv8.3)_. 2229 2230 void retab() 2231 2232 2233### REV ### 2234 2235Reverse bytes. 2236 2237 void rev(const Register& rd, const Register& rn) 2238 2239 2240### REV16 ### 2241 2242Reverse bytes in 16-bit half words. 2243 2244 void rev16(const Register& rd, const Register& rn) 2245 2246 2247### REV32 ### 2248 2249Reverse bytes in 32-bit words. 2250 2251 void rev32(const Register& xd, const Register& xn) 2252 2253 2254### REV64 ### 2255 2256Reverse bytes in 64-bit general purpose register, an alias for rev _(Armv8.2)_. 2257 2258 void rev64(const Register& xd, const Register& xn) 2259 2260 2261### RMIF ### 2262 2263Rotate register right and insert into NZCV flags under the control of a mask _(Armv8.4)_. 2264 2265 void rmif(const Register& xn, unsigned rotation, StatusFlags flags) 2266 2267 2268### ROR ### 2269 2270Rotate right. 2271 2272 void ror(const Register& rd, const Register& rs, unsigned shift) 2273 2274 2275### RORV ### 2276 2277Rotate right by variable. 2278 2279 void rorv(const Register& rd, const Register& rn, const Register& rm) 2280 2281 2282<a id="integer-s"> 2283 2284### SBC ### 2285 2286Subtract with carry bit. 2287 2288 void sbc(const Register& rd, const Register& rn, const Operand& operand) 2289 2290 2291### SBCS ### 2292 2293Subtract with carry bit and update status flags. 2294 2295 void sbcs(const Register& rd, const Register& rn, const Operand& operand) 2296 2297 2298### SBFIZ ### 2299 2300Signed bitfield insert with zero at right. 2301 2302 void sbfiz(const Register& rd, 2303 const Register& rn, 2304 unsigned lsb, 2305 unsigned width) 2306 2307 2308### SBFM ### 2309 2310Signed bitfield move. 2311 2312 void sbfm(const Register& rd, 2313 const Register& rn, 2314 unsigned immr, 2315 unsigned imms) 2316 2317 2318### SBFX ### 2319 2320Signed bitfield extract. 2321 2322 void sbfx(const Register& rd, 2323 const Register& rn, 2324 unsigned lsb, 2325 unsigned width) 2326 2327 2328### SDIV ### 2329 2330Signed integer divide. 2331 2332 void sdiv(const Register& rd, const Register& rn, const Register& rm) 2333 2334 2335### SETF16 ### 2336 2337Set NZCV flags from register, treated as an 16-bit value _(Armv8.4)_. 2338 2339 void setf16(const Register& rn) 2340 2341 2342### SETF8 ### 2343 2344Set NZCV flags from register, treated as an 8-bit value _(Armv8.4)_. 2345 2346 void setf8(const Register& rn) 2347 2348 2349### SMADDL ### 2350 2351Signed long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 2352 2353 void smaddl(const Register& xd, 2354 const Register& wn, 2355 const Register& wm, 2356 const Register& xa) 2357 2358 2359### SMSUBL ### 2360 2361Signed long multiply and subtract: 64 - (32 x 32) -> 64-bit. 2362 2363 void smsubl(const Register& xd, 2364 const Register& wn, 2365 const Register& wm, 2366 const Register& xa) 2367 2368 2369### SMULH ### 2370 2371Signed multiply high: 64 x 64 -> 64-bit <127:64>. 2372 2373 void smulh(const Register& xd, const Register& xn, const Register& xm) 2374 2375 2376### SMULL ### 2377 2378Signed long multiply: 32 x 32 -> 64-bit. 2379 2380 void smull(const Register& xd, const Register& wn, const Register& wm) 2381 2382 2383### STADD ### 2384 2385Atomic add on word or doubleword in memory, without return. _(Armv8.1)_ 2386 2387 void stadd(const Register& rs, const MemOperand& src) 2388 2389 2390### STADDB ### 2391 2392Atomic add on byte in memory, without return. _(Armv8.1)_ 2393 2394 void staddb(const Register& rs, const MemOperand& src) 2395 2396 2397### STADDH ### 2398 2399Atomic add on halfword in memory, without return. _(Armv8.1)_ 2400 2401 void staddh(const Register& rs, const MemOperand& src) 2402 2403 2404### STADDL ### 2405 2406Atomic add on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2407 2408 void staddl(const Register& rs, const MemOperand& src) 2409 2410 2411### STADDLB ### 2412 2413Atomic add on byte in memory, with Store-release semantics and without return. _(Armv8.1)_ 2414 2415 void staddlb(const Register& rs, const MemOperand& src) 2416 2417 2418### STADDLH ### 2419 2420Atomic add on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2421 2422 void staddlh(const Register& rs, const MemOperand& src) 2423 2424 2425### STCLR ### 2426 2427Atomic bit clear on word or doubleword in memory, without return. _(Armv8.1)_ 2428 2429 void stclr(const Register& rs, const MemOperand& src) 2430 2431 2432### STCLRB ### 2433 2434Atomic bit clear on byte in memory, without return. _(Armv8.1)_ 2435 2436 void stclrb(const Register& rs, const MemOperand& src) 2437 2438 2439### STCLRH ### 2440 2441Atomic bit clear on halfword in memory, without return. _(Armv8.1)_ 2442 2443 void stclrh(const Register& rs, const MemOperand& src) 2444 2445 2446### STCLRL ### 2447 2448Atomic bit clear on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2449 2450 void stclrl(const Register& rs, const MemOperand& src) 2451 2452 2453### STCLRLB ### 2454 2455Atomic bit clear on byte in memory, with Store-release semantics and without return. _(Armv8.1)_ 2456 2457 void stclrlb(const Register& rs, const MemOperand& src) 2458 2459 2460### STCLRLH ### 2461 2462Atomic bit clear on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2463 2464 void stclrlh(const Register& rs, const MemOperand& src) 2465 2466 2467### STEOR ### 2468 2469Atomic exclusive OR on word or doubleword in memory, without return. _(Armv8.1)_ 2470 2471 void steor(const Register& rs, const MemOperand& src) 2472 2473 2474### STEORB ### 2475 2476Atomic exclusive OR on byte in memory, without return. _(Armv8.1)_ 2477 2478 void steorb(const Register& rs, const MemOperand& src) 2479 2480 2481### STEORH ### 2482 2483Atomic exclusive OR on halfword in memory, without return. _(Armv8.1)_ 2484 2485 void steorh(const Register& rs, const MemOperand& src) 2486 2487 2488### STEORL ### 2489 2490Atomic exclusive OR on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2491 2492 void steorl(const Register& rs, const MemOperand& src) 2493 2494 2495### STEORLB ### 2496 2497Atomic exclusive OR on byte in memory, with Store-release semantics and without return. _(Armv8.1)_ 2498 2499 void steorlb(const Register& rs, const MemOperand& src) 2500 2501 2502### STEORLH ### 2503 2504Atomic exclusive OR on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2505 2506 void steorlh(const Register& rs, const MemOperand& src) 2507 2508 2509### STLLR ### 2510 2511Store LORelease register _(Armv8.1)_. 2512 2513 void stllr(const Register& rt, const MemOperand& dst) 2514 2515 2516### STLLRB ### 2517 2518Store LORelease byte _(Armv8.1)_. 2519 2520 void stllrb(const Register& rt, const MemOperand& dst) 2521 2522 2523### STLLRH ### 2524 2525Store LORelease half-word _(Armv8.1)_. 2526 2527 void stllrh(const Register& rt, const MemOperand& dst) 2528 2529 2530### STLR ### 2531 2532Store-release register. 2533 2534 void stlr(const Register& rt, const MemOperand& dst) 2535 2536 2537### STLRB ### 2538 2539Store-release byte. 2540 2541 void stlrb(const Register& rt, const MemOperand& dst) 2542 2543 2544### STLRH ### 2545 2546Store-release half-word. 2547 2548 void stlrh(const Register& rt, const MemOperand& dst) 2549 2550 2551### STLUR ### 2552 2553Store-release word or double-word (with unscaled offset) _(Armv8.4)_. 2554 2555 void stlur(const Register& rt, const MemOperand& dst) 2556 2557 2558### STLURB ### 2559 2560Store-release byte (with unscaled offset) _(Armv8.4)_. 2561 2562 void stlurb(const Register& rt, const MemOperand& dst) 2563 2564 2565### STLURH ### 2566 2567Store-release half-word (with unscaled offset) _(Armv8.4)_. 2568 2569 void stlurh(const Register& rt, const MemOperand& dst) 2570 2571 2572### STLXP ### 2573 2574Store-release exclusive register pair. 2575 2576 void stlxp(const Register& rs, 2577 const Register& rt, 2578 const Register& rt2, 2579 const MemOperand& dst) 2580 2581 2582### STLXR ### 2583 2584Store-release exclusive register. 2585 2586 void stlxr(const Register& rs, const Register& rt, const MemOperand& dst) 2587 2588 2589### STLXRB ### 2590 2591Store-release exclusive byte. 2592 2593 void stlxrb(const Register& rs, const Register& rt, const MemOperand& dst) 2594 2595 2596### STLXRH ### 2597 2598Store-release exclusive half-word. 2599 2600 void stlxrh(const Register& rs, const Register& rt, const MemOperand& dst) 2601 2602 2603### STNP ### 2604 2605Store integer or FP register pair, non-temporal. 2606 2607 void stnp(const CPURegister& rt, 2608 const CPURegister& rt2, 2609 const MemOperand& dst) 2610 2611 2612### STP ### 2613 2614Store integer or FP register pair. 2615 2616 void stp(const CPURegister& rt, 2617 const CPURegister& rt2, 2618 const MemOperand& dst) 2619 2620 2621### STR ### 2622 2623Store integer or FP register. 2624 2625 void str(const CPURegister& rt, 2626 const MemOperand& dst, 2627 LoadStoreScalingOption option = PreferScaledOffset) 2628 2629 2630### STRB ### 2631 2632Store byte. 2633 2634 void strb(const Register& rt, 2635 const MemOperand& dst, 2636 LoadStoreScalingOption option = PreferScaledOffset) 2637 2638 2639### STRH ### 2640 2641Store half-word. 2642 2643 void strh(const Register& rt, 2644 const MemOperand& dst, 2645 LoadStoreScalingOption option = PreferScaledOffset) 2646 2647 2648### STSET ### 2649 2650Atomic bit set on word or doubleword in memory, without return. _(Armv8.1)_ 2651 2652 void stset(const Register& rs, const MemOperand& src) 2653 2654 2655### STSETB ### 2656 2657Atomic bit set on byte in memory, without return. _(Armv8.1)_ 2658 2659 void stsetb(const Register& rs, const MemOperand& src) 2660 2661 2662### STSETH ### 2663 2664Atomic bit set on halfword in memory, without return. _(Armv8.1)_ 2665 2666 void stseth(const Register& rs, const MemOperand& src) 2667 2668 2669### STSETL ### 2670 2671Atomic bit set on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2672 2673 void stsetl(const Register& rs, const MemOperand& src) 2674 2675 2676### STSETLB ### 2677 2678Atomic bit set on byte in memory, with Store-release semantics and without return. _(Armv8.1)_ 2679 2680 void stsetlb(const Register& rs, const MemOperand& src) 2681 2682 2683### STSETLH ### 2684 2685Atomic bit set on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2686 2687 void stsetlh(const Register& rs, const MemOperand& src) 2688 2689 2690### STSMAX ### 2691 2692Atomic signed maximum on word or doubleword in memory, without return. _(Armv8.1)_ 2693 2694 void stsmax(const Register& rs, const MemOperand& src) 2695 2696 2697### STSMAXB ### 2698 2699Atomic signed maximum on byte in memory, without return. _(Armv8.1)_ 2700 2701 void stsmaxb(const Register& rs, const MemOperand& src) 2702 2703 2704### STSMAXH ### 2705 2706Atomic signed maximum on halfword in memory, without return. _(Armv8.1)_ 2707 2708 void stsmaxh(const Register& rs, const MemOperand& src) 2709 2710 2711### STSMAXL ### 2712 2713Atomic signed maximum on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2714 2715 void stsmaxl(const Register& rs, const MemOperand& src) 2716 2717 2718### STSMAXLB ### 2719 2720Atomic signed maximum on byte in memory, with Store-release semantics and without return. _(Armv8.1)_ 2721 2722 void stsmaxlb(const Register& rs, const MemOperand& src) 2723 2724 2725### STSMAXLH ### 2726 2727Atomic signed maximum on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2728 2729 void stsmaxlh(const Register& rs, const MemOperand& src) 2730 2731 2732### STSMIN ### 2733 2734Atomic signed minimum on word or doubleword in memory, without return. _(Armv8.1)_ 2735 2736 void stsmin(const Register& rs, const MemOperand& src) 2737 2738 2739### STSMINB ### 2740 2741Atomic signed minimum on byte in memory, without return. _(Armv8.1)_ 2742 2743 void stsminb(const Register& rs, const MemOperand& src) 2744 2745 2746### STSMINH ### 2747 2748Atomic signed minimum on halfword in memory, without return. _(Armv8.1)_ 2749 2750 void stsminh(const Register& rs, const MemOperand& src) 2751 2752 2753### STSMINL ### 2754 2755Atomic signed minimum on word or doubleword in memory, with Store-release semantics and without return. semantics _(Armv8.1)_ 2756 2757 void stsminl(const Register& rs, const MemOperand& src) 2758 2759 2760### STSMINLB ### 2761 2762Atomic signed minimum on byte in memory, with Store-release semantics and without return. _(Armv8.1)_ 2763 2764 void stsminlb(const Register& rs, const MemOperand& src) 2765 2766 2767### STSMINLH ### 2768 2769Atomic signed minimum on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2770 2771 void stsminlh(const Register& rs, const MemOperand& src) 2772 2773 2774### STUMAX ### 2775 2776Atomic unsigned maximum on word or doubleword in memory, without return. _(Armv8.1)_ 2777 2778 void stumax(const Register& rs, const MemOperand& src) 2779 2780 2781### STUMAXB ### 2782 2783Atomic unsigned maximum on byte in memory, without return. _(Armv8.1)_ 2784 2785 void stumaxb(const Register& rs, const MemOperand& src) 2786 2787 2788### STUMAXH ### 2789 2790Atomic unsigned maximum on halfword in memory, without return. _(Armv8.1)_ 2791 2792 void stumaxh(const Register& rs, const MemOperand& src) 2793 2794 2795### STUMAXL ### 2796 2797Atomic unsigned maximum on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2798 2799 void stumaxl(const Register& rs, const MemOperand& src) 2800 2801 2802### STUMAXLB ### 2803 2804Atomic unsigned maximum on byte in memory, with Store-release semantics and without return. _(Armv8.1)_ 2805 2806 void stumaxlb(const Register& rs, const MemOperand& src) 2807 2808 2809### STUMAXLH ### 2810 2811Atomic unsigned maximum on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2812 2813 void stumaxlh(const Register& rs, const MemOperand& src) 2814 2815 2816### STUMIN ### 2817 2818Atomic unsigned minimum on word or doubleword in memory, without return. _(Armv8.1)_ 2819 2820 void stumin(const Register& rs, const MemOperand& src) 2821 2822 2823### STUMINB ### 2824 2825Atomic unsigned minimum on byte in memory, without return. _(Armv8.1)_ 2826 2827 void stuminb(const Register& rs, const MemOperand& src) 2828 2829 2830### STUMINH ### 2831 2832Atomic unsigned minimum on halfword in memory, without return. _(Armv8.1)_ 2833 2834 void stuminh(const Register& rs, const MemOperand& src) 2835 2836 2837### STUMINL ### 2838 2839Atomic unsigned minimum on word or doubleword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2840 2841 void stuminl(const Register& rs, const MemOperand& src) 2842 2843 2844### STUMINLB ### 2845 2846Atomic unsigned minimum on byte in memory, with Store-release semantics and without return. _(Armv8.1)_ 2847 2848 void stuminlb(const Register& rs, const MemOperand& src) 2849 2850 2851### STUMINLH ### 2852 2853Atomic unsigned minimum on halfword in memory, with Store-release semantics and without return. _(Armv8.1)_ 2854 2855 void stuminlh(const Register& rs, const MemOperand& src) 2856 2857 2858### STUR ### 2859 2860Store integer or FP register (with unscaled offset). 2861 2862 void stur(const CPURegister& rt, 2863 const MemOperand& src, 2864 LoadStoreScalingOption option = PreferUnscaledOffset) 2865 2866 2867### STURB ### 2868 2869Store byte (with unscaled offset). 2870 2871 void sturb(const Register& rt, 2872 const MemOperand& dst, 2873 LoadStoreScalingOption option = PreferUnscaledOffset) 2874 2875 2876### STURH ### 2877 2878Store half-word (with unscaled offset). 2879 2880 void sturh(const Register& rt, 2881 const MemOperand& dst, 2882 LoadStoreScalingOption option = PreferUnscaledOffset) 2883 2884 2885### STXP ### 2886 2887Store exclusive register pair. 2888 2889 void stxp(const Register& rs, 2890 const Register& rt, 2891 const Register& rt2, 2892 const MemOperand& dst) 2893 2894 2895### STXR ### 2896 2897Store exclusive register. 2898 2899 void stxr(const Register& rs, const Register& rt, const MemOperand& dst) 2900 2901 2902### STXRB ### 2903 2904Store exclusive byte. 2905 2906 void stxrb(const Register& rs, const Register& rt, const MemOperand& dst) 2907 2908 2909### STXRH ### 2910 2911Store exclusive half-word. 2912 2913 void stxrh(const Register& rs, const Register& rt, const MemOperand& dst) 2914 2915 2916### SUB ### 2917 2918Subtract. 2919 2920 void sub(const Register& rd, const Register& rn, const Operand& operand) 2921 2922 2923### SUBS ### 2924 2925Subtract and update status flags. 2926 2927 void subs(const Register& rd, const Register& rn, const Operand& operand) 2928 2929 2930### SVC ### 2931 2932Generate exception targeting EL1. 2933 2934 void svc(int code) 2935 2936 2937### SWP ### 2938 2939Swap word or doubleword in memory _(Armv8.1)_ 2940 2941 void swp(const Register& rs, const Register& rt, const MemOperand& src) 2942 2943 2944### SWPA ### 2945 2946Swap word or doubleword in memory, with Load-acquire semantics _(Armv8.1)_ 2947 2948 void swpa(const Register& rs, const Register& rt, const MemOperand& src) 2949 2950 2951### SWPAB ### 2952 2953Swap byte in memory, with Load-acquire semantics _(Armv8.1)_ 2954 2955 void swpab(const Register& rs, const Register& rt, const MemOperand& src) 2956 2957 2958### SWPAH ### 2959 2960Swap halfword in memory, with Load-acquire semantics _(Armv8.1)_ 2961 2962 void swpah(const Register& rs, const Register& rt, const MemOperand& src) 2963 2964 2965### SWPAL ### 2966 2967Swap word or doubleword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 2968 2969 void swpal(const Register& rs, const Register& rt, const MemOperand& src) 2970 2971 2972### SWPALB ### 2973 2974Swap byte in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 2975 2976 void swpalb(const Register& rs, const Register& rt, const MemOperand& src) 2977 2978 2979### SWPALH ### 2980 2981Swap halfword in memory, with Load-acquire and Store-release semantics _(Armv8.1)_ 2982 2983 void swpalh(const Register& rs, const Register& rt, const MemOperand& src) 2984 2985 2986### SWPB ### 2987 2988Swap byte in memory _(Armv8.1)_ 2989 2990 void swpb(const Register& rs, const Register& rt, const MemOperand& src) 2991 2992 2993### SWPH ### 2994 2995Swap halfword in memory _(Armv8.1)_ 2996 2997 void swph(const Register& rs, const Register& rt, const MemOperand& src) 2998 2999 3000### SWPL ### 3001 3002Swap word or doubleword in memory, with Store-release semantics _(Armv8.1)_ 3003 3004 void swpl(const Register& rs, const Register& rt, const MemOperand& src) 3005 3006 3007### SWPLB ### 3008 3009Swap byte in memory, with Store-release semantics _(Armv8.1)_ 3010 3011 void swplb(const Register& rs, const Register& rt, const MemOperand& src) 3012 3013 3014### SWPLH ### 3015 3016Swap halfword in memory, with Store-release semantics _(Armv8.1)_ 3017 3018 void swplh(const Register& rs, const Register& rt, const MemOperand& src) 3019 3020 3021### SXTB ### 3022 3023Signed extend byte. 3024 3025 void sxtb(const Register& rd, const Register& rn) 3026 3027 3028### SXTH ### 3029 3030Signed extend halfword. 3031 3032 void sxth(const Register& rd, const Register& rn) 3033 3034 3035### SXTW ### 3036 3037Signed extend word. 3038 3039 void sxtw(const Register& rd, const Register& rn) 3040 3041 3042### SYS ### 3043 3044System instruction with pre-encoded op (op1:crn:crm:op2). 3045 3046 void sys(int op, const Register& xt = xzr) 3047 3048 3049### SYS ### 3050 3051System instruction. 3052 3053 void sys(int op1, int crn, int crm, int op2, const Register& xt = xzr) 3054 3055 3056<a id="integer-t"> 3057 3058### TBNZ ### 3059 3060Test bit and branch to PC offset if not zero. 3061 3062 void tbnz(const Register& rt, unsigned bit_pos, int64_t imm14) 3063 3064 3065### TBNZ ### 3066 3067Test bit and branch to label if not zero. 3068 3069 void tbnz(const Register& rt, unsigned bit_pos, Label* label) 3070 3071 3072### TBZ ### 3073 3074Test bit and branch to PC offset if zero. 3075 3076 void tbz(const Register& rt, unsigned bit_pos, int64_t imm14) 3077 3078 3079### TBZ ### 3080 3081Test bit and branch to label if zero. 3082 3083 void tbz(const Register& rt, unsigned bit_pos, Label* label) 3084 3085 3086### TST ### 3087 3088Bit test and set flags. 3089 3090 void tst(const Register& rn, const Operand& operand) 3091 3092 3093<a id="integer-u"> 3094 3095### UBFIZ ### 3096 3097Unsigned bitfield insert with zero at right. 3098 3099 void ubfiz(const Register& rd, 3100 const Register& rn, 3101 unsigned lsb, 3102 unsigned width) 3103 3104 3105### UBFM ### 3106 3107Unsigned bitfield move. 3108 3109 void ubfm(const Register& rd, 3110 const Register& rn, 3111 unsigned immr, 3112 unsigned imms) 3113 3114 3115### UBFX ### 3116 3117Unsigned bitfield extract. 3118 3119 void ubfx(const Register& rd, 3120 const Register& rn, 3121 unsigned lsb, 3122 unsigned width) 3123 3124 3125### UDF ### 3126 3127Generate undefined instruction exception. 3128 3129 void udf(int code) 3130 3131 3132### UDIV ### 3133 3134Unsigned integer divide. 3135 3136 void udiv(const Register& rd, const Register& rn, const Register& rm) 3137 3138 3139### UMADDL ### 3140 3141Unsigned long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 3142 3143 void umaddl(const Register& xd, 3144 const Register& wn, 3145 const Register& wm, 3146 const Register& xa) 3147 3148 3149### UMSUBL ### 3150 3151Unsigned long multiply and subtract: 64 - (32 x 32) -> 64-bit. 3152 3153 void umsubl(const Register& xd, 3154 const Register& wn, 3155 const Register& wm, 3156 const Register& xa) 3157 3158 3159### UMULH ### 3160 3161Unsigned multiply high: 64 x 64 -> 64-bit <127:64>. 3162 3163 void umulh(const Register& xd, const Register& xn, const Register& xm) 3164 3165 3166### UMULL ### 3167 3168Unsigned long multiply: 32 x 32 -> 64-bit. 3169 3170 void umull(const Register& xd, const Register& wn, const Register& wm) 3171 3172 3173### UXTB ### 3174 3175Unsigned extend byte. 3176 3177 void uxtb(const Register& rd, const Register& rn) 3178 3179 3180### UXTH ### 3181 3182Unsigned extend halfword. 3183 3184 void uxth(const Register& rd, const Register& rn) 3185 3186 3187### UXTW ### 3188 3189Unsigned extend word. 3190 3191 void uxtw(const Register& rd, const Register& rn) 3192 3193 3194<a id="integer-x"> 3195 3196### XAFLAG ### 3197 3198Convert floating-point condition flags from alternative format to Arm format _(Armv8.5)_. 3199 3200 void xaflag() 3201 3202 3203### XPACD ### 3204 3205Strip Pointer Authentication Code of Data address _(Armv8.3)_. 3206 3207 void xpacd(const Register& xd) 3208 3209 3210### XPACI ### 3211 3212Strip Pointer Authentication Code of Instruction address _(Armv8.3)_. 3213 3214 void xpaci(const Register& xd) 3215 3216 3217### XPACLRI ### 3218 3219Strip Pointer Authentication Code of Instruction address in LR _(Armv8.3)_. 3220 3221 void xpaclri() 3222 3223 3224 3225AArch64 floating point and NEON instructions 3226-------------------------------------------- 3227 3228<a id="float-a"> 3229 3230### ABS ### 3231 3232Absolute value. 3233 3234 void abs(const VRegister& vd, const VRegister& vn) 3235 3236 3237### ADD ### 3238 3239Add. 3240 3241 void add(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3242 3243 3244### ADDHN ### 3245 3246Add narrow returning high half. 3247 3248 void addhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3249 3250 3251### ADDHN2 ### 3252 3253Add narrow returning high half (second part). 3254 3255 void addhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3256 3257 3258### ADDP ### 3259 3260Add pair of elements scalar. 3261 3262 void addp(const VRegister& vd, const VRegister& vn) 3263 3264 3265### ADDP ### 3266 3267Add pairwise. 3268 3269 void addp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3270 3271 3272### ADDV ### 3273 3274Add across vector. 3275 3276 void addv(const VRegister& vd, const VRegister& vn) 3277 3278 3279### AND ### 3280 3281Bitwise and. 3282 3283 void and_(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3284 3285 3286<a id="float-b"> 3287 3288### BIC ### 3289 3290Bit clear immediate. 3291 3292 void bic(const VRegister& vd, const int imm8, const int left_shift = 0) 3293 3294 3295### BIC ### 3296 3297Bit clear. 3298 3299 void bic(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3300 3301 3302### BIF ### 3303 3304Bitwise insert if false. 3305 3306 void bif(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3307 3308 3309### BIT ### 3310 3311Bitwise insert if true. 3312 3313 void bit(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3314 3315 3316### BSL ### 3317 3318Bitwise select. 3319 3320 void bsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3321 3322 3323<a id="float-c"> 3324 3325### CLS ### 3326 3327Count leading sign bits. 3328 3329 void cls(const VRegister& vd, const VRegister& vn) 3330 3331 3332### CLZ ### 3333 3334Count leading zero bits (vector). 3335 3336 void clz(const VRegister& vd, const VRegister& vn) 3337 3338 3339### CMEQ ### 3340 3341Compare bitwise to zero. 3342 3343 void cmeq(const VRegister& vd, const VRegister& vn, int value) 3344 3345 3346### CMEQ ### 3347 3348Compare equal. 3349 3350 void cmeq(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3351 3352 3353### CMGE ### 3354 3355Compare signed greater than or equal to zero. 3356 3357 void cmge(const VRegister& vd, const VRegister& vn, int value) 3358 3359 3360### CMGE ### 3361 3362Compare signed greater than or equal. 3363 3364 void cmge(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3365 3366 3367### CMGT ### 3368 3369Compare signed greater than zero. 3370 3371 void cmgt(const VRegister& vd, const VRegister& vn, int value) 3372 3373 3374### CMGT ### 3375 3376Compare signed greater than. 3377 3378 void cmgt(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3379 3380 3381### CMHI ### 3382 3383Compare unsigned higher. 3384 3385 void cmhi(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3386 3387 3388### CMHS ### 3389 3390Compare unsigned higher or same. 3391 3392 void cmhs(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3393 3394 3395### CMLE ### 3396 3397Compare signed less than or equal to zero. 3398 3399 void cmle(const VRegister& vd, const VRegister& vn, int value) 3400 3401 3402### CMLT ### 3403 3404Compare signed less than zero. 3405 3406 void cmlt(const VRegister& vd, const VRegister& vn, int value) 3407 3408 3409### CMTST ### 3410 3411Compare bitwise test bits nonzero. 3412 3413 void cmtst(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3414 3415 3416### CNT ### 3417 3418Population count per byte. 3419 3420 void cnt(const VRegister& vd, const VRegister& vn) 3421 3422 3423<a id="float-d"> 3424 3425### DUP ### 3426 3427Duplicate general-purpose register to vector. 3428 3429 void dup(const VRegister& vd, const Register& rn) 3430 3431 3432### DUP ### 3433 3434Duplicate vector element to vector or scalar. 3435 3436 void dup(const VRegister& vd, const VRegister& vn, int vn_index) 3437 3438 3439<a id="float-e"> 3440 3441### EOR ### 3442 3443Bitwise eor. 3444 3445 void eor(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3446 3447 3448### EXT ### 3449 3450Extract vector from pair of vectors. 3451 3452 void ext(const VRegister& vd, 3453 const VRegister& vn, 3454 const VRegister& vm, 3455 int index) 3456 3457 3458<a id="float-f"> 3459 3460### FABD ### 3461 3462FP absolute difference. 3463 3464 void fabd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3465 3466 3467### FABS ### 3468 3469FP absolute. 3470 3471 void fabs(const VRegister& vd, const VRegister& vn) 3472 3473 3474### FACGE ### 3475 3476FP absolute greater than or equal. 3477 3478 void facge(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3479 3480 3481### FACGT ### 3482 3483FP absolute greater than. 3484 3485 void facgt(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3486 3487 3488### FADD ### 3489 3490FP add. 3491 3492 void fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3493 3494 3495### FADDP ### 3496 3497FP pairwise add scalar. 3498 3499 void faddp(const VRegister& vd, const VRegister& vn) 3500 3501 3502### FADDP ### 3503 3504FP pairwise add vector. 3505 3506 void faddp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3507 3508 3509### FCADD ### 3510 3511FP complex add _(Armv8.3)_. 3512 3513 void fcadd(const VRegister& vd, 3514 const VRegister& vn, 3515 const VRegister& vm, 3516 int rot) 3517 3518 3519### FCCMP ### 3520 3521FP conditional compare. 3522 3523 void fccmp(const VRegister& vn, 3524 const VRegister& vm, 3525 StatusFlags nzcv, 3526 Condition cond) 3527 3528 3529### FCCMPE ### 3530 3531FP conditional signaling compare. 3532 3533 void fccmpe(const VRegister& vn, 3534 const VRegister& vm, 3535 StatusFlags nzcv, 3536 Condition cond) 3537 3538 3539### FCMEQ ### 3540 3541FP compare equal to zero. 3542 3543 void fcmeq(const VRegister& vd, const VRegister& vn, double imm) 3544 3545 3546### FCMEQ ### 3547 3548FP compare equal. 3549 3550 void fcmeq(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3551 3552 3553### FCMGE ### 3554 3555FP greater than or equal to zero. 3556 3557 void fcmge(const VRegister& vd, const VRegister& vn, double imm) 3558 3559 3560### FCMGE ### 3561 3562FP greater than or equal. 3563 3564 void fcmge(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3565 3566 3567### FCMGT ### 3568 3569FP greater than zero. 3570 3571 void fcmgt(const VRegister& vd, const VRegister& vn, double imm) 3572 3573 3574### FCMGT ### 3575 3576FP greater than. 3577 3578 void fcmgt(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3579 3580 3581### FCMLA ### 3582 3583FP complex multiply accumulate (by element) _(Armv8.3)_. 3584 3585 void fcmla(const VRegister& vd, 3586 const VRegister& vn, 3587 const VRegister& vm, 3588 int vm_index, 3589 int rot) 3590 3591 3592### FCMLA ### 3593 3594FP complex multiply accumulate _(Armv8.3)_. 3595 3596 void fcmla(const VRegister& vd, 3597 const VRegister& vn, 3598 const VRegister& vm, 3599 int rot) 3600 3601 3602### FCMLE ### 3603 3604FP less than or equal to zero. 3605 3606 void fcmle(const VRegister& vd, const VRegister& vn, double imm) 3607 3608 3609### FCMLT ### 3610 3611FP less than to zero. 3612 3613 void fcmlt(const VRegister& vd, const VRegister& vn, double imm) 3614 3615 3616### FCMP ### 3617 3618FP compare immediate. 3619 3620 void fcmp(const VRegister& vn, double value) 3621 3622 3623### FCMP ### 3624 3625FP compare registers. 3626 3627 void fcmp(const VRegister& vn, const VRegister& vm) 3628 3629 3630### FCMPE ### 3631 3632FP signaling compare immediate. 3633 3634 void fcmpe(const VRegister& vn, double value) 3635 3636 3637### FCMPE ### 3638 3639FP signaling compare registers. 3640 3641 void fcmpe(const VRegister& vn, const VRegister& vm) 3642 3643 3644### FCSEL ### 3645 3646FP conditional select. 3647 3648 void fcsel(const VRegister& vd, 3649 const VRegister& vn, 3650 const VRegister& vm, 3651 Condition cond) 3652 3653 3654### FCVT ### 3655 3656FP convert between precisions. 3657 3658 void fcvt(const VRegister& vd, const VRegister& vn) 3659 3660 3661### FCVTAS ### 3662 3663FP convert to signed integer, nearest with ties to away. 3664 3665 void fcvtas(const Register& rd, const VRegister& vn) 3666 3667 3668### FCVTAS ### 3669 3670FP convert to signed integer, nearest with ties to away. 3671 3672 void fcvtas(const VRegister& vd, const VRegister& vn) 3673 3674 3675### FCVTAU ### 3676 3677FP convert to unsigned integer, nearest with ties to away. 3678 3679 void fcvtau(const Register& rd, const VRegister& vn) 3680 3681 3682### FCVTAU ### 3683 3684FP convert to unsigned integer, nearest with ties to away. 3685 3686 void fcvtau(const VRegister& vd, const VRegister& vn) 3687 3688 3689### FCVTL ### 3690 3691FP convert to higher precision. 3692 3693 void fcvtl(const VRegister& vd, const VRegister& vn) 3694 3695 3696### FCVTL2 ### 3697 3698FP convert to higher precision (second part). 3699 3700 void fcvtl2(const VRegister& vd, const VRegister& vn) 3701 3702 3703### FCVTMS ### 3704 3705FP convert to signed integer, round towards -infinity. 3706 3707 void fcvtms(const Register& rd, const VRegister& vn) 3708 3709 3710### FCVTMS ### 3711 3712FP convert to signed integer, round towards -infinity. 3713 3714 void fcvtms(const VRegister& vd, const VRegister& vn) 3715 3716 3717### FCVTMU ### 3718 3719FP convert to unsigned integer, round towards -infinity. 3720 3721 void fcvtmu(const Register& rd, const VRegister& vn) 3722 3723 3724### FCVTMU ### 3725 3726FP convert to unsigned integer, round towards -infinity. 3727 3728 void fcvtmu(const VRegister& vd, const VRegister& vn) 3729 3730 3731### FCVTN ### 3732 3733FP convert to lower precision. 3734 3735 void fcvtn(const VRegister& vd, const VRegister& vn) 3736 3737 3738### FCVTN2 ### 3739 3740FP convert to lower prevision (second part). 3741 3742 void fcvtn2(const VRegister& vd, const VRegister& vn) 3743 3744 3745### FCVTNS ### 3746 3747FP convert to signed integer, nearest with ties to even. 3748 3749 void fcvtns(const Register& rd, const VRegister& vn) 3750 3751 3752### FCVTNS ### 3753 3754FP convert to signed integer, nearest with ties to even. 3755 3756 void fcvtns(const VRegister& rd, const VRegister& vn) 3757 3758 3759### FCVTNU ### 3760 3761FP convert to unsigned integer, nearest with ties to even. 3762 3763 void fcvtnu(const Register& rd, const VRegister& vn) 3764 3765 3766### FCVTNU ### 3767 3768FP convert to unsigned integer, nearest with ties to even. 3769 3770 void fcvtnu(const VRegister& rd, const VRegister& vn) 3771 3772 3773### FCVTPS ### 3774 3775FP convert to signed integer, round towards +infinity. 3776 3777 void fcvtps(const Register& rd, const VRegister& vn) 3778 3779 3780### FCVTPS ### 3781 3782FP convert to signed integer, round towards +infinity. 3783 3784 void fcvtps(const VRegister& vd, const VRegister& vn) 3785 3786 3787### FCVTPU ### 3788 3789FP convert to unsigned integer, round towards +infinity. 3790 3791 void fcvtpu(const Register& rd, const VRegister& vn) 3792 3793 3794### FCVTPU ### 3795 3796FP convert to unsigned integer, round towards +infinity. 3797 3798 void fcvtpu(const VRegister& vd, const VRegister& vn) 3799 3800 3801### FCVTXN ### 3802 3803FP convert to lower precision, rounding to odd. 3804 3805 void fcvtxn(const VRegister& vd, const VRegister& vn) 3806 3807 3808### FCVTXN2 ### 3809 3810FP convert to lower precision, rounding to odd (second part). 3811 3812 void fcvtxn2(const VRegister& vd, const VRegister& vn) 3813 3814 3815### FCVTZS ### 3816 3817FP convert to signed integer or fixed-point, round towards zero. 3818 3819 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0) 3820 3821 3822### FCVTZS ### 3823 3824FP convert to signed integer or fixed-point, round towards zero. 3825 3826 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) 3827 3828 3829### FCVTZU ### 3830 3831FP convert to unsigned integer or fixed-point, round towards zero. 3832 3833 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0) 3834 3835 3836### FCVTZU ### 3837 3838FP convert to unsigned integer or fixed-point, round towards zero. 3839 3840 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) 3841 3842 3843### FDIV ### 3844 3845FP divide. 3846 3847 void fdiv(const VRegister& vd, const VRegister& fn, const VRegister& vm) 3848 3849 3850### FJCVTZS ### 3851 3852FP JavaScript convert to signed integer, rounding toward zero _(Armv8.3)_. 3853 3854 void fjcvtzs(const Register& rd, const VRegister& vn) 3855 3856 3857### FMADD ### 3858 3859FP fused multiply-add. 3860 3861 void fmadd(const VRegister& vd, 3862 const VRegister& vn, 3863 const VRegister& vm, 3864 const VRegister& va) 3865 3866 3867### FMAX ### 3868 3869FP maximum. 3870 3871 void fmax(const VRegister& vd, const VRegister& fn, const VRegister& vm) 3872 3873 3874### FMAXNM ### 3875 3876FP maximum number. 3877 3878 void fmaxnm(const VRegister& vd, const VRegister& fn, const VRegister& vm) 3879 3880 3881### FMAXNMP ### 3882 3883FP pairwise maximum number scalar. 3884 3885 void fmaxnmp(const VRegister& vd, const VRegister& vn) 3886 3887 3888### FMAXNMP ### 3889 3890FP pairwise maximum number vector. 3891 3892 void fmaxnmp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3893 3894 3895### FMAXNMV ### 3896 3897FP maximum number across vector. 3898 3899 void fmaxnmv(const VRegister& vd, const VRegister& vn) 3900 3901 3902### FMAXP ### 3903 3904FP pairwise maximum scalar. 3905 3906 void fmaxp(const VRegister& vd, const VRegister& vn) 3907 3908 3909### FMAXP ### 3910 3911FP pairwise maximum vector. 3912 3913 void fmaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3914 3915 3916### FMAXV ### 3917 3918FP maximum across vector. 3919 3920 void fmaxv(const VRegister& vd, const VRegister& vn) 3921 3922 3923### FMIN ### 3924 3925FP minimum. 3926 3927 void fmin(const VRegister& vd, const VRegister& fn, const VRegister& vm) 3928 3929 3930### FMINNM ### 3931 3932FP minimum number. 3933 3934 void fminnm(const VRegister& vd, const VRegister& fn, const VRegister& vm) 3935 3936 3937### FMINNMP ### 3938 3939FP pairwise minimum number scalar. 3940 3941 void fminnmp(const VRegister& vd, const VRegister& vn) 3942 3943 3944### FMINNMP ### 3945 3946FP pairwise minimum number vector. 3947 3948 void fminnmp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3949 3950 3951### FMINNMV ### 3952 3953FP minimum number across vector. 3954 3955 void fminnmv(const VRegister& vd, const VRegister& vn) 3956 3957 3958### FMINP ### 3959 3960FP pairwise minimum scalar. 3961 3962 void fminp(const VRegister& vd, const VRegister& vn) 3963 3964 3965### FMINP ### 3966 3967FP pairwise minimum vector. 3968 3969 void fminp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3970 3971 3972### FMINV ### 3973 3974FP minimum across vector. 3975 3976 void fminv(const VRegister& vd, const VRegister& vn) 3977 3978 3979### FMLA ### 3980 3981FP fused multiply-add to accumulator by element. 3982 3983 void fmla(const VRegister& vd, 3984 const VRegister& vn, 3985 const VRegister& vm, 3986 int vm_index) 3987 3988 3989### FMLA ### 3990 3991FP vector multiply accumulate. 3992 3993 void fmla(const VRegister& vd, const VRegister& vn, const VRegister& vm) 3994 3995 3996### FMLAL ### 3997 3998FP fused multiply-add long to accumulator by element. 3999 4000 void fmlal(const VRegister& vd, 4001 const VRegister& vn, 4002 const VRegister& vm, 4003 int vm_index) 4004 4005 4006### FMLAL ### 4007 4008FP fused multiply-add long to accumulator. 4009 4010 void fmlal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4011 4012 4013### FMLAL2 ### 4014 4015FP fused multiply-add long to accumulator (second part). 4016 4017 void fmlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4018 4019 4020### FMLAL2 ### 4021 4022FP fused multiply-add long to accumulator by element (second part). 4023 4024 void fmlal2(const VRegister& vd, 4025 const VRegister& vn, 4026 const VRegister& vm, 4027 int vm_index) 4028 4029 4030### FMLS ### 4031 4032FP fused multiply-sub from accumulator by element. 4033 4034 void fmls(const VRegister& vd, 4035 const VRegister& vn, 4036 const VRegister& vm, 4037 int vm_index) 4038 4039 4040### FMLS ### 4041 4042FP vector multiply subtract. 4043 4044 void fmls(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4045 4046 4047### FMLSL ### 4048 4049FP fused multiply-subtract long to accumulator by element. 4050 4051 void fmlsl(const VRegister& vd, 4052 const VRegister& vn, 4053 const VRegister& vm, 4054 int vm_index) 4055 4056 4057### FMLSL ### 4058 4059FP fused multiply-subtract long to accumulator. 4060 4061 void fmlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4062 4063 4064### FMLSL2 ### 4065 4066FP fused multiply-subtract long to accumulator (second part). 4067 4068 void fmlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4069 4070 4071### FMLSL2 ### 4072 4073FP fused multiply-subtract long to accumulator by element (second part). 4074 4075 void fmlsl2(const VRegister& vd, 4076 const VRegister& vn, 4077 const VRegister& vm, 4078 int vm_index) 4079 4080 4081### FMOV ### 4082 4083Move 64-bit register to top half of 128-bit FP register. 4084 4085 void fmov(const VRegister& vd, int index, const Register& rn) 4086 4087 4088### FMOV ### 4089 4090Move FP register to FP register. 4091 4092 void fmov(const VRegister& vd, const VRegister& fn) 4093 4094 4095### FMOV ### 4096 4097Move FP register to register. 4098 4099 void fmov(const Register& rd, const VRegister& fn) 4100 4101 4102### FMOV ### 4103 4104Move double precision immediate to FP register. 4105 4106 void fmov(const VRegister& vd, double imm) 4107 4108 4109### FMOV ### 4110 4111Move half precision immediate to FP register _(Armv8.2)_. 4112 4113 void fmov(const VRegister& vd, Float16 imm) 4114 4115 4116### FMOV ### 4117 4118Move register to FP register. 4119 4120 void fmov(const VRegister& vd, const Register& rn) 4121 4122 4123### FMOV ### 4124 4125Move single precision immediate to FP register. 4126 4127 void fmov(const VRegister& vd, float imm) 4128 4129 4130### FMOV ### 4131 4132Move top half of 128-bit FP register to 64-bit register. 4133 4134 void fmov(const Register& rd, const VRegister& vn, int index) 4135 4136 4137### FMSUB ### 4138 4139FP fused multiply-subtract. 4140 4141 void fmsub(const VRegister& vd, 4142 const VRegister& vn, 4143 const VRegister& vm, 4144 const VRegister& va) 4145 4146 4147### FMUL ### 4148 4149FP multiply by element. 4150 4151 void fmul(const VRegister& vd, 4152 const VRegister& vn, 4153 const VRegister& vm, 4154 int vm_index) 4155 4156 4157### FMUL ### 4158 4159FP multiply. 4160 4161 void fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4162 4163 4164### FMULX ### 4165 4166FP multiply extended by element. 4167 4168 void fmulx(const VRegister& vd, 4169 const VRegister& vn, 4170 const VRegister& vm, 4171 int vm_index) 4172 4173 4174### FMULX ### 4175 4176FP vector multiply extended. 4177 4178 void fmulx(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4179 4180 4181### FNEG ### 4182 4183FP negate. 4184 4185 void fneg(const VRegister& vd, const VRegister& vn) 4186 4187 4188### FNMADD ### 4189 4190FP fused multiply-add and negate. 4191 4192 void fnmadd(const VRegister& vd, 4193 const VRegister& vn, 4194 const VRegister& vm, 4195 const VRegister& va) 4196 4197 4198### FNMSUB ### 4199 4200FP fused multiply-subtract and negate. 4201 4202 void fnmsub(const VRegister& vd, 4203 const VRegister& vn, 4204 const VRegister& vm, 4205 const VRegister& va) 4206 4207 4208### FNMUL ### 4209 4210FP multiply-negate scalar. 4211 4212 void fnmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4213 4214 4215### FRECPE ### 4216 4217FP reciprocal estimate. 4218 4219 void frecpe(const VRegister& vd, const VRegister& vn) 4220 4221 4222### FRECPS ### 4223 4224FP reciprocal step. 4225 4226 void frecps(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4227 4228 4229### FRECPX ### 4230 4231FP reciprocal exponent scalar. 4232 4233 void frecpx(const VRegister& vd, const VRegister& vn) 4234 4235 4236### FRINT32X ### 4237 4238FP round to 32-bit integer, exact, implicit rounding _(Armv8.5)_. 4239 4240 void frint32x(const VRegister& vd, const VRegister& vn) 4241 4242 4243### FRINT32Z ### 4244 4245FP round to 32-bit integer, towards zero _(Armv8.5)_. 4246 4247 void frint32z(const VRegister& vd, const VRegister& vn) 4248 4249 4250### FRINT64X ### 4251 4252FP round to 64-bit integer, exact, implicit rounding _(Armv8.5)_. 4253 4254 void frint64x(const VRegister& vd, const VRegister& vn) 4255 4256 4257### FRINT64Z ### 4258 4259FP round to 64-bit integer, towards zero _(Armv8.5)_. 4260 4261 void frint64z(const VRegister& vd, const VRegister& vn) 4262 4263 4264### FRINTA ### 4265 4266FP round to integer, nearest with ties to away. 4267 4268 void frinta(const VRegister& vd, const VRegister& vn) 4269 4270 4271### FRINTI ### 4272 4273FP round to integer, implicit rounding. 4274 4275 void frinti(const VRegister& vd, const VRegister& vn) 4276 4277 4278### FRINTM ### 4279 4280FP round to integer, toward minus infinity. 4281 4282 void frintm(const VRegister& vd, const VRegister& vn) 4283 4284 4285### FRINTN ### 4286 4287FP round to integer, nearest with ties to even. 4288 4289 void frintn(const VRegister& vd, const VRegister& vn) 4290 4291 4292### FRINTP ### 4293 4294FP round to integer, toward plus infinity. 4295 4296 void frintp(const VRegister& vd, const VRegister& vn) 4297 4298 4299### FRINTX ### 4300 4301FP round to integer, exact, implicit rounding. 4302 4303 void frintx(const VRegister& vd, const VRegister& vn) 4304 4305 4306### FRINTZ ### 4307 4308FP round to integer, towards zero. 4309 4310 void frintz(const VRegister& vd, const VRegister& vn) 4311 4312 4313### FRSQRTE ### 4314 4315FP reciprocal square root estimate. 4316 4317 void frsqrte(const VRegister& vd, const VRegister& vn) 4318 4319 4320### FRSQRTS ### 4321 4322FP reciprocal square root step. 4323 4324 void frsqrts(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4325 4326 4327### FSQRT ### 4328 4329FP square root. 4330 4331 void fsqrt(const VRegister& vd, const VRegister& vn) 4332 4333 4334### FSUB ### 4335 4336FP subtract. 4337 4338 void fsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4339 4340 4341<a id="float-i"> 4342 4343### INS ### 4344 4345Insert vector element from another vector element. 4346 4347 void ins(const VRegister& vd, 4348 int vd_index, 4349 const VRegister& vn, 4350 int vn_index) 4351 4352 4353### INS ### 4354 4355Insert vector element from general-purpose register. 4356 4357 void ins(const VRegister& vd, int vd_index, const Register& rn) 4358 4359 4360<a id="float-l"> 4361 4362### LD1 ### 4363 4364One-element single structure load to one lane. 4365 4366 void ld1(const VRegister& vt, int lane, const MemOperand& src) 4367 4368 4369### LD1 ### 4370 4371One-element structure load to four registers. 4372 4373 void ld1(const VRegister& vt, 4374 const VRegister& vt2, 4375 const VRegister& vt3, 4376 const VRegister& vt4, 4377 const MemOperand& src) 4378 4379 4380### LD1 ### 4381 4382One-element structure load to one register. 4383 4384 void ld1(const VRegister& vt, const MemOperand& src) 4385 4386 4387### LD1 ### 4388 4389One-element structure load to three registers. 4390 4391 void ld1(const VRegister& vt, 4392 const VRegister& vt2, 4393 const VRegister& vt3, 4394 const MemOperand& src) 4395 4396 4397### LD1 ### 4398 4399One-element structure load to two registers. 4400 4401 void ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 4402 4403 4404### LD1R ### 4405 4406One-element single structure load to all lanes. 4407 4408 void ld1r(const VRegister& vt, const MemOperand& src) 4409 4410 4411### LD2 ### 4412 4413Two-element single structure load to one lane. 4414 4415 void ld2(const VRegister& vt, 4416 const VRegister& vt2, 4417 int lane, 4418 const MemOperand& src) 4419 4420 4421### LD2 ### 4422 4423Two-element structure load. 4424 4425 void ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 4426 4427 4428### LD2R ### 4429 4430Two-element single structure load to all lanes. 4431 4432 void ld2r(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 4433 4434 4435### LD3 ### 4436 4437Three-element single structure load to one lane. 4438 4439 void ld3(const VRegister& vt, 4440 const VRegister& vt2, 4441 const VRegister& vt3, 4442 int lane, 4443 const MemOperand& src) 4444 4445 4446### LD3 ### 4447 4448Three-element structure load. 4449 4450 void ld3(const VRegister& vt, 4451 const VRegister& vt2, 4452 const VRegister& vt3, 4453 const MemOperand& src) 4454 4455 4456### LD3R ### 4457 4458Three-element single structure load to all lanes. 4459 4460 void ld3r(const VRegister& vt, 4461 const VRegister& vt2, 4462 const VRegister& vt3, 4463 const MemOperand& src) 4464 4465 4466### LD4 ### 4467 4468Four-element single structure load to one lane. 4469 4470 void ld4(const VRegister& vt, 4471 const VRegister& vt2, 4472 const VRegister& vt3, 4473 const VRegister& vt4, 4474 int lane, 4475 const MemOperand& src) 4476 4477 4478### LD4 ### 4479 4480Four-element structure load. 4481 4482 void ld4(const VRegister& vt, 4483 const VRegister& vt2, 4484 const VRegister& vt3, 4485 const VRegister& vt4, 4486 const MemOperand& src) 4487 4488 4489### LD4R ### 4490 4491Four-element single structure load to all lanes. 4492 4493 void ld4r(const VRegister& vt, 4494 const VRegister& vt2, 4495 const VRegister& vt3, 4496 const VRegister& vt4, 4497 const MemOperand& src) 4498 4499 4500<a id="float-m"> 4501 4502### MLA ### 4503 4504Multiply-add by scalar element. 4505 4506 void mla(const VRegister& vd, 4507 const VRegister& vn, 4508 const VRegister& vm, 4509 int vm_index) 4510 4511 4512### MLA ### 4513 4514Multiply-add to accumulator. 4515 4516 void mla(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4517 4518 4519### MLS ### 4520 4521Multiply-subtract by scalar element. 4522 4523 void mls(const VRegister& vd, 4524 const VRegister& vn, 4525 const VRegister& vm, 4526 int vm_index) 4527 4528 4529### MLS ### 4530 4531Multiply-subtract to accumulator. 4532 4533 void mls(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4534 4535 4536### MOV ### 4537 4538Move general-purpose register to a vector element. 4539 4540 void mov(const VRegister& vd, int vd_index, const Register& rn) 4541 4542 4543### MOV ### 4544 4545Move register to register. 4546 4547 void mov(const VRegister& vd, const VRegister& vn) 4548 4549 4550### MOV ### 4551 4552Move vector element to another vector element. 4553 4554 void mov(const VRegister& vd, 4555 int vd_index, 4556 const VRegister& vn, 4557 int vn_index) 4558 4559 4560### MOV ### 4561 4562Move vector element to general-purpose register. 4563 4564 void mov(const Register& rd, const VRegister& vn, int vn_index) 4565 4566 4567### MOV ### 4568 4569Move vector element to scalar. 4570 4571 void mov(const VRegister& vd, const VRegister& vn, int vn_index) 4572 4573 4574### MOVI ### 4575 4576Vector move immediate. 4577 4578 void movi(const VRegister& vd, 4579 const uint64_t imm, 4580 Shift shift = LSL, 4581 const int shift_amount = 0) 4582 4583 4584### MUL ### 4585 4586Multiply by scalar element. 4587 4588 void mul(const VRegister& vd, 4589 const VRegister& vn, 4590 const VRegister& vm, 4591 int vm_index) 4592 4593 4594### MUL ### 4595 4596Multiply. 4597 4598 void mul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4599 4600 4601### MVN ### 4602 4603Bitwise not. 4604 4605 void mvn(const VRegister& vd, const VRegister& vn) 4606 4607 4608### MVNI ### 4609 4610Vector move inverted immediate. 4611 4612 void mvni(const VRegister& vd, 4613 const int imm8, 4614 Shift shift = LSL, 4615 const int shift_amount = 0) 4616 4617 4618<a id="float-n"> 4619 4620### NEG ### 4621 4622Negate. 4623 4624 void neg(const VRegister& vd, const VRegister& vn) 4625 4626 4627### NOT ### 4628 4629Bitwise not. 4630 4631 void not_(const VRegister& vd, const VRegister& vn) 4632 4633 4634<a id="float-o"> 4635 4636### ORN ### 4637 4638Bitwise orn. 4639 4640 void orn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4641 4642 4643### ORR ### 4644 4645Bitwise or immediate. 4646 4647 void orr(const VRegister& vd, const int imm8, const int left_shift = 0) 4648 4649 4650### ORR ### 4651 4652Bitwise or. 4653 4654 void orr(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4655 4656 4657<a id="float-p"> 4658 4659### PMUL ### 4660 4661Polynomial multiply. 4662 4663 void pmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4664 4665 4666### PMULL ### 4667 4668Polynomial multiply long. 4669 4670 void pmull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4671 4672 4673### PMULL2 ### 4674 4675Polynomial multiply long (second part). 4676 4677 void pmull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4678 4679 4680<a id="float-r"> 4681 4682### RADDHN ### 4683 4684Rounding add narrow returning high half. 4685 4686 void raddhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4687 4688 4689### RADDHN2 ### 4690 4691Rounding add narrow returning high half (second part). 4692 4693 void raddhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4694 4695 4696### RBIT ### 4697 4698Reverse bit order. 4699 4700 void rbit(const VRegister& vd, const VRegister& vn) 4701 4702 4703### REV16 ### 4704 4705Reverse elements in 16-bit halfwords. 4706 4707 void rev16(const VRegister& vd, const VRegister& vn) 4708 4709 4710### REV32 ### 4711 4712Reverse elements in 32-bit words. 4713 4714 void rev32(const VRegister& vd, const VRegister& vn) 4715 4716 4717### REV64 ### 4718 4719Reverse elements in 64-bit doublewords. 4720 4721 void rev64(const VRegister& vd, const VRegister& vn) 4722 4723 4724### RSHRN ### 4725 4726Rounding shift right narrow by immediate. 4727 4728 void rshrn(const VRegister& vd, const VRegister& vn, int shift) 4729 4730 4731### RSHRN2 ### 4732 4733Rounding shift right narrow by immediate (second part). 4734 4735 void rshrn2(const VRegister& vd, const VRegister& vn, int shift) 4736 4737 4738### RSUBHN ### 4739 4740Rounding subtract narrow returning high half. 4741 4742 void rsubhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4743 4744 4745### RSUBHN2 ### 4746 4747Rounding subtract narrow returning high half (second part). 4748 4749 void rsubhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4750 4751 4752<a id="float-s"> 4753 4754### SABA ### 4755 4756Signed absolute difference and accumulate. 4757 4758 void saba(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4759 4760 4761### SABAL ### 4762 4763Signed absolute difference and accumulate long. 4764 4765 void sabal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4766 4767 4768### SABAL2 ### 4769 4770Signed absolute difference and accumulate long (second part). 4771 4772 void sabal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4773 4774 4775### SABD ### 4776 4777Signed absolute difference. 4778 4779 void sabd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4780 4781 4782### SABDL ### 4783 4784Signed absolute difference long. 4785 4786 void sabdl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4787 4788 4789### SABDL2 ### 4790 4791Signed absolute difference long (second part). 4792 4793 void sabdl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4794 4795 4796### SADALP ### 4797 4798Signed pairwise long add and accumulate. 4799 4800 void sadalp(const VRegister& vd, const VRegister& vn) 4801 4802 4803### SADDL ### 4804 4805Signed add long. 4806 4807 void saddl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4808 4809 4810### SADDL2 ### 4811 4812Signed add long (second part). 4813 4814 void saddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4815 4816 4817### SADDLP ### 4818 4819Signed pairwise long add. 4820 4821 void saddlp(const VRegister& vd, const VRegister& vn) 4822 4823 4824### SADDLV ### 4825 4826Signed add long across vector. 4827 4828 void saddlv(const VRegister& vd, const VRegister& vn) 4829 4830 4831### SADDW ### 4832 4833Signed add wide. 4834 4835 void saddw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4836 4837 4838### SADDW2 ### 4839 4840Signed add wide (second part). 4841 4842 void saddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4843 4844 4845### SCVTF ### 4846 4847Convert signed integer or fixed point to FP. 4848 4849 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0) 4850 4851 4852### SCVTF ### 4853 4854Convert signed integer or fixed-point to FP. 4855 4856 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0) 4857 4858 4859### SDOT ### 4860 4861Signed dot product _(Armv8.2)_. 4862 4863 void sdot(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4864 4865 4866### SDOT ### 4867 4868Signed dot product by element _(Armv8.2)_. 4869 4870 void sdot(const VRegister& vd, 4871 const VRegister& vn, 4872 const VRegister& vm, 4873 int vm_index) 4874 4875 4876### SHADD ### 4877 4878Signed halving add. 4879 4880 void shadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4881 4882 4883### SHL ### 4884 4885Shift left by immediate. 4886 4887 void shl(const VRegister& vd, const VRegister& vn, int shift) 4888 4889 4890### SHLL ### 4891 4892Shift left long by element size. 4893 4894 void shll(const VRegister& vd, const VRegister& vn, int shift) 4895 4896 4897### SHLL2 ### 4898 4899Shift left long by element size (second part). 4900 4901 void shll2(const VRegister& vd, const VRegister& vn, int shift) 4902 4903 4904### SHRN ### 4905 4906Shift right narrow by immediate. 4907 4908 void shrn(const VRegister& vd, const VRegister& vn, int shift) 4909 4910 4911### SHRN2 ### 4912 4913Shift right narrow by immediate (second part). 4914 4915 void shrn2(const VRegister& vd, const VRegister& vn, int shift) 4916 4917 4918### SHSUB ### 4919 4920Signed halving sub. 4921 4922 void shsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4923 4924 4925### SLI ### 4926 4927Shift left by immediate and insert. 4928 4929 void sli(const VRegister& vd, const VRegister& vn, int shift) 4930 4931 4932### SMAX ### 4933 4934Signed maximum. 4935 4936 void smax(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4937 4938 4939### SMAXP ### 4940 4941Signed pairwise maximum. 4942 4943 void smaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4944 4945 4946### SMAXV ### 4947 4948Signed maximum across vector. 4949 4950 void smaxv(const VRegister& vd, const VRegister& vn) 4951 4952 4953### SMIN ### 4954 4955Signed minimum. 4956 4957 void smin(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4958 4959 4960### SMINP ### 4961 4962Signed minimum pairwise. 4963 4964 void sminp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4965 4966 4967### SMINV ### 4968 4969Signed minimum across vector. 4970 4971 void sminv(const VRegister& vd, const VRegister& vn) 4972 4973 4974### SMLAL ### 4975 4976Signed long multiply-add by scalar element. 4977 4978 void smlal(const VRegister& vd, 4979 const VRegister& vn, 4980 const VRegister& vm, 4981 int vm_index) 4982 4983 4984### SMLAL ### 4985 4986Signed long multiply-add. 4987 4988 void smlal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4989 4990 4991### SMLAL2 ### 4992 4993Signed long multiply-add (second part). 4994 4995 void smlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 4996 4997 4998### SMLAL2 ### 4999 5000Signed long multiply-add by scalar element (second part). 5001 5002 void smlal2(const VRegister& vd, 5003 const VRegister& vn, 5004 const VRegister& vm, 5005 int vm_index) 5006 5007 5008### SMLSL ### 5009 5010Signed long multiply-sub by scalar element. 5011 5012 void smlsl(const VRegister& vd, 5013 const VRegister& vn, 5014 const VRegister& vm, 5015 int vm_index) 5016 5017 5018### SMLSL ### 5019 5020Signed long multiply-sub. 5021 5022 void smlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5023 5024 5025### SMLSL2 ### 5026 5027Signed long multiply-sub (second part). 5028 5029 void smlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5030 5031 5032### SMLSL2 ### 5033 5034Signed long multiply-sub by scalar element (second part). 5035 5036 void smlsl2(const VRegister& vd, 5037 const VRegister& vn, 5038 const VRegister& vm, 5039 int vm_index) 5040 5041 5042### SMMLA ### 5043 5044Signed 8-bit integer matrix multiply-accumulate (vector). 5045 5046 void smmla(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5047 5048 5049### SMOV ### 5050 5051Signed move vector element to general-purpose register. 5052 5053 void smov(const Register& rd, const VRegister& vn, int vn_index) 5054 5055 5056### SMULL ### 5057 5058Signed long multiply by scalar element. 5059 5060 void smull(const VRegister& vd, 5061 const VRegister& vn, 5062 const VRegister& vm, 5063 int vm_index) 5064 5065 5066### SMULL ### 5067 5068Signed long multiply. 5069 5070 void smull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5071 5072 5073### SMULL2 ### 5074 5075Signed long multiply (second part). 5076 5077 void smull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5078 5079 5080### SMULL2 ### 5081 5082Signed long multiply by scalar element (second part). 5083 5084 void smull2(const VRegister& vd, 5085 const VRegister& vn, 5086 const VRegister& vm, 5087 int vm_index) 5088 5089 5090### SQABS ### 5091 5092Signed saturating absolute value. 5093 5094 void sqabs(const VRegister& vd, const VRegister& vn) 5095 5096 5097### SQADD ### 5098 5099Signed saturating add. 5100 5101 void sqadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5102 5103 5104### SQDMLAL ### 5105 5106Signed saturating doubling long multiply-add by element. 5107 5108 void sqdmlal(const VRegister& vd, 5109 const VRegister& vn, 5110 const VRegister& vm, 5111 int vm_index) 5112 5113 5114### SQDMLAL ### 5115 5116Signed saturating doubling long multiply-add. 5117 5118 void sqdmlal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5119 5120 5121### SQDMLAL2 ### 5122 5123Signed saturating doubling long multiply-add (second part). 5124 5125 void sqdmlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5126 5127 5128### SQDMLAL2 ### 5129 5130Signed saturating doubling long multiply-add by element (second part). 5131 5132 void sqdmlal2(const VRegister& vd, 5133 const VRegister& vn, 5134 const VRegister& vm, 5135 int vm_index) 5136 5137 5138### SQDMLSL ### 5139 5140Signed saturating doubling long multiply-sub by element. 5141 5142 void sqdmlsl(const VRegister& vd, 5143 const VRegister& vn, 5144 const VRegister& vm, 5145 int vm_index) 5146 5147 5148### SQDMLSL ### 5149 5150Signed saturating doubling long multiply-subtract. 5151 5152 void sqdmlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5153 5154 5155### SQDMLSL2 ### 5156 5157Signed saturating doubling long multiply-sub by element (second part). 5158 5159 void sqdmlsl2(const VRegister& vd, 5160 const VRegister& vn, 5161 const VRegister& vm, 5162 int vm_index) 5163 5164 5165### SQDMLSL2 ### 5166 5167Signed saturating doubling long multiply-subtract (second part). 5168 5169 void sqdmlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5170 5171 5172### SQDMULH ### 5173 5174Signed saturating doubling multiply element returning high half. 5175 5176 void sqdmulh(const VRegister& vd, 5177 const VRegister& vn, 5178 const VRegister& vm, 5179 int vm_index) 5180 5181 5182### SQDMULH ### 5183 5184Signed saturating doubling multiply returning high half. 5185 5186 void sqdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5187 5188 5189### SQDMULL ### 5190 5191Signed saturating double long multiply by element. 5192 5193 void sqdmull(const VRegister& vd, 5194 const VRegister& vn, 5195 const VRegister& vm, 5196 int vm_index) 5197 5198 5199### SQDMULL ### 5200 5201Signed saturating doubling long multiply. 5202 5203 void sqdmull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5204 5205 5206### SQDMULL2 ### 5207 5208Signed saturating double long multiply by element (second part). 5209 5210 void sqdmull2(const VRegister& vd, 5211 const VRegister& vn, 5212 const VRegister& vm, 5213 int vm_index) 5214 5215 5216### SQDMULL2 ### 5217 5218Signed saturating doubling long multiply (second part). 5219 5220 void sqdmull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5221 5222 5223### SQNEG ### 5224 5225Signed saturating negate. 5226 5227 void sqneg(const VRegister& vd, const VRegister& vn) 5228 5229 5230### SQRDMLAH ### 5231 5232Signed saturating rounding doubling multiply accumulate element returning high half _(Armv8.1)_. 5233 5234 void sqrdmlah(const VRegister& vd, 5235 const VRegister& vn, 5236 const VRegister& vm, 5237 int vm_index) 5238 5239 5240### SQRDMLAH ### 5241 5242Signed saturating rounding doubling multiply accumulate returning high half _(Armv8.1)_. 5243 5244 void sqrdmlah(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5245 5246 5247### SQRDMLSH ### 5248 5249Signed saturating rounding doubling multiply subtract element returning high half _(Armv8.1)_. 5250 5251 void sqrdmlsh(const VRegister& vd, 5252 const VRegister& vn, 5253 const VRegister& vm, 5254 int vm_index) 5255 5256 5257### SQRDMLSH ### 5258 5259Signed saturating rounding doubling multiply subtract returning high half _(Armv8.1)_. 5260 5261 void sqrdmlsh(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5262 5263 5264### SQRDMULH ### 5265 5266Signed saturating rounding doubling multiply element returning high half. 5267 5268 void sqrdmulh(const VRegister& vd, 5269 const VRegister& vn, 5270 const VRegister& vm, 5271 int vm_index) 5272 5273 5274### SQRDMULH ### 5275 5276Signed saturating rounding doubling multiply returning high half. 5277 5278 void sqrdmulh(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5279 5280 5281### SQRSHL ### 5282 5283Signed saturating rounding shift left by register. 5284 5285 void sqrshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5286 5287 5288### SQRSHRN ### 5289 5290Signed saturating rounded shift right narrow by immediate. 5291 5292 void sqrshrn(const VRegister& vd, const VRegister& vn, int shift) 5293 5294 5295### SQRSHRN2 ### 5296 5297Signed saturating rounded shift right narrow by immediate (second part). 5298 5299 void sqrshrn2(const VRegister& vd, const VRegister& vn, int shift) 5300 5301 5302### SQRSHRUN ### 5303 5304Signed sat rounded shift right unsigned narrow by immediate. 5305 5306 void sqrshrun(const VRegister& vd, const VRegister& vn, int shift) 5307 5308 5309### SQRSHRUN2 ### 5310 5311Signed sat rounded shift right unsigned narrow by immediate (second part). 5312 5313 void sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) 5314 5315 5316### SQSHL ### 5317 5318Signed saturating shift left by immediate. 5319 5320 void sqshl(const VRegister& vd, const VRegister& vn, int shift) 5321 5322 5323### SQSHL ### 5324 5325Signed saturating shift left by register. 5326 5327 void sqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5328 5329 5330### SQSHLU ### 5331 5332Signed saturating shift left unsigned by immediate. 5333 5334 void sqshlu(const VRegister& vd, const VRegister& vn, int shift) 5335 5336 5337### SQSHRN ### 5338 5339Signed saturating shift right narrow by immediate. 5340 5341 void sqshrn(const VRegister& vd, const VRegister& vn, int shift) 5342 5343 5344### SQSHRN2 ### 5345 5346Signed saturating shift right narrow by immediate (second part). 5347 5348 void sqshrn2(const VRegister& vd, const VRegister& vn, int shift) 5349 5350 5351### SQSHRUN ### 5352 5353Signed saturating shift right unsigned narrow by immediate. 5354 5355 void sqshrun(const VRegister& vd, const VRegister& vn, int shift) 5356 5357 5358### SQSHRUN2 ### 5359 5360Signed saturating shift right unsigned narrow by immediate (second part). 5361 5362 void sqshrun2(const VRegister& vd, const VRegister& vn, int shift) 5363 5364 5365### SQSUB ### 5366 5367Signed saturating subtract. 5368 5369 void sqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5370 5371 5372### SQXTN ### 5373 5374Signed saturating extract narrow. 5375 5376 void sqxtn(const VRegister& vd, const VRegister& vn) 5377 5378 5379### SQXTN2 ### 5380 5381Signed saturating extract narrow (second part). 5382 5383 void sqxtn2(const VRegister& vd, const VRegister& vn) 5384 5385 5386### SQXTUN ### 5387 5388Signed saturating extract unsigned narrow. 5389 5390 void sqxtun(const VRegister& vd, const VRegister& vn) 5391 5392 5393### SQXTUN2 ### 5394 5395Signed saturating extract unsigned narrow (second part). 5396 5397 void sqxtun2(const VRegister& vd, const VRegister& vn) 5398 5399 5400### SRHADD ### 5401 5402Signed rounding halving add. 5403 5404 void srhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5405 5406 5407### SRI ### 5408 5409Shift right by immediate and insert. 5410 5411 void sri(const VRegister& vd, const VRegister& vn, int shift) 5412 5413 5414### SRSHL ### 5415 5416Signed rounding shift left by register. 5417 5418 void srshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5419 5420 5421### SRSHR ### 5422 5423Signed rounding shift right by immediate. 5424 5425 void srshr(const VRegister& vd, const VRegister& vn, int shift) 5426 5427 5428### SRSRA ### 5429 5430Signed rounding shift right by immediate and accumulate. 5431 5432 void srsra(const VRegister& vd, const VRegister& vn, int shift) 5433 5434 5435### SSHL ### 5436 5437Signed shift left by register. 5438 5439 void sshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5440 5441 5442### SSHLL ### 5443 5444Signed shift left long by immediate. 5445 5446 void sshll(const VRegister& vd, const VRegister& vn, int shift) 5447 5448 5449### SSHLL2 ### 5450 5451Signed shift left long by immediate (second part). 5452 5453 void sshll2(const VRegister& vd, const VRegister& vn, int shift) 5454 5455 5456### SSHR ### 5457 5458Signed shift right by immediate. 5459 5460 void sshr(const VRegister& vd, const VRegister& vn, int shift) 5461 5462 5463### SSRA ### 5464 5465Signed shift right by immediate and accumulate. 5466 5467 void ssra(const VRegister& vd, const VRegister& vn, int shift) 5468 5469 5470### SSUBL ### 5471 5472Signed subtract long. 5473 5474 void ssubl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5475 5476 5477### SSUBL2 ### 5478 5479Signed subtract long (second part). 5480 5481 void ssubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5482 5483 5484### SSUBW ### 5485 5486Signed integer subtract wide. 5487 5488 void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5489 5490 5491### SSUBW2 ### 5492 5493Signed integer subtract wide (second part). 5494 5495 void ssubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5496 5497 5498### ST1 ### 5499 5500One-element single structure store from one lane. 5501 5502 void st1(const VRegister& vt, int lane, const MemOperand& src) 5503 5504 5505### ST1 ### 5506 5507One-element structure store from four registers. 5508 5509 void st1(const VRegister& vt, 5510 const VRegister& vt2, 5511 const VRegister& vt3, 5512 const VRegister& vt4, 5513 const MemOperand& src) 5514 5515 5516### ST1 ### 5517 5518One-element structure store from one register. 5519 5520 void st1(const VRegister& vt, const MemOperand& src) 5521 5522 5523### ST1 ### 5524 5525One-element structure store from three registers. 5526 5527 void st1(const VRegister& vt, 5528 const VRegister& vt2, 5529 const VRegister& vt3, 5530 const MemOperand& src) 5531 5532 5533### ST1 ### 5534 5535One-element structure store from two registers. 5536 5537 void st1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 5538 5539 5540### ST2 ### 5541 5542Two-element single structure store from two lanes. 5543 5544 void st2(const VRegister& vt, 5545 const VRegister& vt2, 5546 int lane, 5547 const MemOperand& src) 5548 5549 5550### ST2 ### 5551 5552Two-element structure store from two registers. 5553 5554 void st2(const VRegister& vt, const VRegister& vt2, const MemOperand& src) 5555 5556 5557### ST3 ### 5558 5559Three-element single structure store from three lanes. 5560 5561 void st3(const VRegister& vt, 5562 const VRegister& vt2, 5563 const VRegister& vt3, 5564 int lane, 5565 const MemOperand& src) 5566 5567 5568### ST3 ### 5569 5570Three-element structure store from three registers. 5571 5572 void st3(const VRegister& vt, 5573 const VRegister& vt2, 5574 const VRegister& vt3, 5575 const MemOperand& src) 5576 5577 5578### ST4 ### 5579 5580Four-element single structure store from four lanes. 5581 5582 void st4(const VRegister& vt, 5583 const VRegister& vt2, 5584 const VRegister& vt3, 5585 const VRegister& vt4, 5586 int lane, 5587 const MemOperand& src) 5588 5589 5590### ST4 ### 5591 5592Four-element structure store from four registers. 5593 5594 void st4(const VRegister& vt, 5595 const VRegister& vt2, 5596 const VRegister& vt3, 5597 const VRegister& vt4, 5598 const MemOperand& src) 5599 5600 5601### SUB ### 5602 5603Subtract. 5604 5605 void sub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5606 5607 5608### SUBHN ### 5609 5610Subtract narrow returning high half. 5611 5612 void subhn(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5613 5614 5615### SUBHN2 ### 5616 5617Subtract narrow returning high half (second part). 5618 5619 void subhn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5620 5621 5622### SUDOT ### 5623 5624Dot product with signed and unsigned integers (vector, by element). 5625 5626 void sudot(const VRegister& vd, 5627 const VRegister& vn, 5628 const VRegister& vm, 5629 int vm_index) 5630 5631 5632### SUQADD ### 5633 5634Signed saturating accumulate of unsigned value. 5635 5636 void suqadd(const VRegister& vd, const VRegister& vn) 5637 5638 5639### SXTL ### 5640 5641Signed extend long. 5642 5643 void sxtl(const VRegister& vd, const VRegister& vn) 5644 5645 5646### SXTL2 ### 5647 5648Signed extend long (second part). 5649 5650 void sxtl2(const VRegister& vd, const VRegister& vn) 5651 5652 5653<a id="float-t"> 5654 5655### TBL ### 5656 5657Table lookup from four registers. 5658 5659 void tbl(const VRegister& vd, 5660 const VRegister& vn, 5661 const VRegister& vn2, 5662 const VRegister& vn3, 5663 const VRegister& vn4, 5664 const VRegister& vm) 5665 5666 5667### TBL ### 5668 5669Table lookup from one register. 5670 5671 void tbl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5672 5673 5674### TBL ### 5675 5676Table lookup from three registers. 5677 5678 void tbl(const VRegister& vd, 5679 const VRegister& vn, 5680 const VRegister& vn2, 5681 const VRegister& vn3, 5682 const VRegister& vm) 5683 5684 5685### TBL ### 5686 5687Table lookup from two registers. 5688 5689 void tbl(const VRegister& vd, 5690 const VRegister& vn, 5691 const VRegister& vn2, 5692 const VRegister& vm) 5693 5694 5695### TBX ### 5696 5697Table lookup extension from four registers. 5698 5699 void tbx(const VRegister& vd, 5700 const VRegister& vn, 5701 const VRegister& vn2, 5702 const VRegister& vn3, 5703 const VRegister& vn4, 5704 const VRegister& vm) 5705 5706 5707### TBX ### 5708 5709Table lookup extension from one register. 5710 5711 void tbx(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5712 5713 5714### TBX ### 5715 5716Table lookup extension from three registers. 5717 5718 void tbx(const VRegister& vd, 5719 const VRegister& vn, 5720 const VRegister& vn2, 5721 const VRegister& vn3, 5722 const VRegister& vm) 5723 5724 5725### TBX ### 5726 5727Table lookup extension from two registers. 5728 5729 void tbx(const VRegister& vd, 5730 const VRegister& vn, 5731 const VRegister& vn2, 5732 const VRegister& vm) 5733 5734 5735### TRN1 ### 5736 5737Transpose vectors (primary). 5738 5739 void trn1(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5740 5741 5742### TRN2 ### 5743 5744Transpose vectors (secondary). 5745 5746 void trn2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5747 5748 5749<a id="float-u"> 5750 5751### UABA ### 5752 5753Unsigned absolute difference and accumulate. 5754 5755 void uaba(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5756 5757 5758### UABAL ### 5759 5760Unsigned absolute difference and accumulate long. 5761 5762 void uabal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5763 5764 5765### UABAL2 ### 5766 5767Unsigned absolute difference and accumulate long (second part). 5768 5769 void uabal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5770 5771 5772### UABD ### 5773 5774Unsigned absolute difference. 5775 5776 void uabd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5777 5778 5779### UABDL ### 5780 5781Unsigned absolute difference long. 5782 5783 void uabdl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5784 5785 5786### UABDL2 ### 5787 5788Unsigned absolute difference long (second part). 5789 5790 void uabdl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5791 5792 5793### UADALP ### 5794 5795Unsigned pairwise long add and accumulate. 5796 5797 void uadalp(const VRegister& vd, const VRegister& vn) 5798 5799 5800### UADDL ### 5801 5802Unsigned add long. 5803 5804 void uaddl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5805 5806 5807### UADDL2 ### 5808 5809Unsigned add long (second part). 5810 5811 void uaddl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5812 5813 5814### UADDLP ### 5815 5816Unsigned pairwise long add. 5817 5818 void uaddlp(const VRegister& vd, const VRegister& vn) 5819 5820 5821### UADDLV ### 5822 5823Unsigned add long across vector. 5824 5825 void uaddlv(const VRegister& vd, const VRegister& vn) 5826 5827 5828### UADDW ### 5829 5830Unsigned add wide. 5831 5832 void uaddw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5833 5834 5835### UADDW2 ### 5836 5837Unsigned add wide (second part). 5838 5839 void uaddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5840 5841 5842### UCVTF ### 5843 5844Convert unsigned integer or fixed point to FP. 5845 5846 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0) 5847 5848 5849### UCVTF ### 5850 5851Convert unsigned integer or fixed-point to FP. 5852 5853 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0) 5854 5855 5856### UDOT ### 5857 5858Unsigned dot product _(Armv8.2)_. 5859 5860 void udot(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5861 5862 5863### UDOT ### 5864 5865Unsigned dot product by element _(Armv8.2)_. 5866 5867 void udot(const VRegister& vd, 5868 const VRegister& vn, 5869 const VRegister& vm, 5870 int vm_index) 5871 5872 5873### UHADD ### 5874 5875Unsigned halving add. 5876 5877 void uhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5878 5879 5880### UHSUB ### 5881 5882Unsigned halving sub. 5883 5884 void uhsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5885 5886 5887### UMAX ### 5888 5889Unsigned maximum. 5890 5891 void umax(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5892 5893 5894### UMAXP ### 5895 5896Unsigned pairwise maximum. 5897 5898 void umaxp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5899 5900 5901### UMAXV ### 5902 5903Unsigned maximum across vector. 5904 5905 void umaxv(const VRegister& vd, const VRegister& vn) 5906 5907 5908### UMIN ### 5909 5910Unsigned minimum. 5911 5912 void umin(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5913 5914 5915### UMINP ### 5916 5917Unsigned pairwise minimum. 5918 5919 void uminp(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5920 5921 5922### UMINV ### 5923 5924Unsigned minimum across vector. 5925 5926 void uminv(const VRegister& vd, const VRegister& vn) 5927 5928 5929### UMLAL ### 5930 5931Unsigned long multiply-add by scalar element. 5932 5933 void umlal(const VRegister& vd, 5934 const VRegister& vn, 5935 const VRegister& vm, 5936 int vm_index) 5937 5938 5939### UMLAL ### 5940 5941Unsigned long multiply-add. 5942 5943 void umlal(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5944 5945 5946### UMLAL2 ### 5947 5948Unsigned long multiply-add (second part). 5949 5950 void umlal2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5951 5952 5953### UMLAL2 ### 5954 5955Unsigned long multiply-add by scalar element (second part). 5956 5957 void umlal2(const VRegister& vd, 5958 const VRegister& vn, 5959 const VRegister& vm, 5960 int vm_index) 5961 5962 5963### UMLSL ### 5964 5965Unsigned long multiply-sub by scalar element. 5966 5967 void umlsl(const VRegister& vd, 5968 const VRegister& vn, 5969 const VRegister& vm, 5970 int vm_index) 5971 5972 5973### UMLSL ### 5974 5975Unsigned long multiply-sub. 5976 5977 void umlsl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5978 5979 5980### UMLSL2 ### 5981 5982Unsigned long multiply-sub (second part). 5983 5984 void umlsl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 5985 5986 5987### UMLSL2 ### 5988 5989Unsigned long multiply-sub by scalar element (second part). 5990 5991 void umlsl2(const VRegister& vd, 5992 const VRegister& vn, 5993 const VRegister& vm, 5994 int vm_index) 5995 5996 5997### UMMLA ### 5998 5999Unsigned 8-bit integer matrix multiply-accumulate (vector). 6000 6001 void ummla(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6002 6003 6004### UMOV ### 6005 6006Unsigned move vector element to general-purpose register. 6007 6008 void umov(const Register& rd, const VRegister& vn, int vn_index) 6009 6010 6011### UMULL ### 6012 6013Unsigned long multiply by scalar element. 6014 6015 void umull(const VRegister& vd, 6016 const VRegister& vn, 6017 const VRegister& vm, 6018 int vm_index) 6019 6020 6021### UMULL ### 6022 6023Unsigned long multiply long. 6024 6025 void umull(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6026 6027 6028### UMULL2 ### 6029 6030Unsigned long multiply (second part). 6031 6032 void umull2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6033 6034 6035### UMULL2 ### 6036 6037Unsigned long multiply by scalar element (second part). 6038 6039 void umull2(const VRegister& vd, 6040 const VRegister& vn, 6041 const VRegister& vm, 6042 int vm_index) 6043 6044 6045### UQADD ### 6046 6047Unsigned saturating add. 6048 6049 void uqadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6050 6051 6052### UQRSHL ### 6053 6054Unsigned saturating rounding shift left by register. 6055 6056 void uqrshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6057 6058 6059### UQRSHRN ### 6060 6061Unsigned saturating rounding shift right narrow by immediate. 6062 6063 void uqrshrn(const VRegister& vd, const VRegister& vn, int shift) 6064 6065 6066### UQRSHRN2 ### 6067 6068Unsigned saturating rounding shift right narrow by immediate (second part). 6069 6070 void uqrshrn2(const VRegister& vd, const VRegister& vn, int shift) 6071 6072 6073### UQSHL ### 6074 6075Unsigned saturating shift left by immediate. 6076 6077 void uqshl(const VRegister& vd, const VRegister& vn, int shift) 6078 6079 6080### UQSHL ### 6081 6082Unsigned saturating shift left by register. 6083 6084 void uqshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6085 6086 6087### UQSHRN ### 6088 6089Unsigned saturating shift right narrow by immediate. 6090 6091 void uqshrn(const VRegister& vd, const VRegister& vn, int shift) 6092 6093 6094### UQSHRN2 ### 6095 6096Unsigned saturating shift right narrow by immediate (second part). 6097 6098 void uqshrn2(const VRegister& vd, const VRegister& vn, int shift) 6099 6100 6101### UQSUB ### 6102 6103Unsigned saturating subtract. 6104 6105 void uqsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6106 6107 6108### UQXTN ### 6109 6110Unsigned saturating extract narrow. 6111 6112 void uqxtn(const VRegister& vd, const VRegister& vn) 6113 6114 6115### UQXTN2 ### 6116 6117Unsigned saturating extract narrow (second part). 6118 6119 void uqxtn2(const VRegister& vd, const VRegister& vn) 6120 6121 6122### URECPE ### 6123 6124Unsigned reciprocal estimate. 6125 6126 void urecpe(const VRegister& vd, const VRegister& vn) 6127 6128 6129### URHADD ### 6130 6131Unsigned rounding halving add. 6132 6133 void urhadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6134 6135 6136### URSHL ### 6137 6138Unsigned rounding shift left by register. 6139 6140 void urshl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6141 6142 6143### URSHR ### 6144 6145Unsigned rounding shift right by immediate. 6146 6147 void urshr(const VRegister& vd, const VRegister& vn, int shift) 6148 6149 6150### URSQRTE ### 6151 6152Unsigned reciprocal square root estimate. 6153 6154 void ursqrte(const VRegister& vd, const VRegister& vn) 6155 6156 6157### URSRA ### 6158 6159Unsigned rounding shift right by immediate and accumulate. 6160 6161 void ursra(const VRegister& vd, const VRegister& vn, int shift) 6162 6163 6164### USDOT ### 6165 6166Dot Product with unsigned and signed integers (vector). 6167 6168 void usdot(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6169 6170 6171### USDOT ### 6172 6173Dot product with unsigned and signed integers (vector, by element). 6174 6175 void usdot(const VRegister& vd, 6176 const VRegister& vn, 6177 const VRegister& vm, 6178 int vm_index) 6179 6180 6181### USHL ### 6182 6183Unsigned shift left by register. 6184 6185 void ushl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6186 6187 6188### USHLL ### 6189 6190Unsigned shift left long by immediate. 6191 6192 void ushll(const VRegister& vd, const VRegister& vn, int shift) 6193 6194 6195### USHLL2 ### 6196 6197Unsigned shift left long by immediate (second part). 6198 6199 void ushll2(const VRegister& vd, const VRegister& vn, int shift) 6200 6201 6202### USHR ### 6203 6204Unsigned shift right by immediate. 6205 6206 void ushr(const VRegister& vd, const VRegister& vn, int shift) 6207 6208 6209### USMMLA ### 6210 6211Unsigned and signed 8-bit integer matrix multiply-accumulate (vector). 6212 6213 void usmmla(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6214 6215 6216### USQADD ### 6217 6218Unsigned saturating accumulate of signed value. 6219 6220 void usqadd(const VRegister& vd, const VRegister& vn) 6221 6222 6223### USRA ### 6224 6225Unsigned shift right by immediate and accumulate. 6226 6227 void usra(const VRegister& vd, const VRegister& vn, int shift) 6228 6229 6230### USUBL ### 6231 6232Unsigned subtract long. 6233 6234 void usubl(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6235 6236 6237### USUBL2 ### 6238 6239Unsigned subtract long (second part). 6240 6241 void usubl2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6242 6243 6244### USUBW ### 6245 6246Unsigned subtract wide. 6247 6248 void usubw(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6249 6250 6251### USUBW2 ### 6252 6253Unsigned subtract wide (second part). 6254 6255 void usubw2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6256 6257 6258### UXTL ### 6259 6260Unsigned extend long. 6261 6262 void uxtl(const VRegister& vd, const VRegister& vn) 6263 6264 6265### UXTL2 ### 6266 6267Unsigned extend long (second part). 6268 6269 void uxtl2(const VRegister& vd, const VRegister& vn) 6270 6271 6272### UZP1 ### 6273 6274Unzip vectors (primary). 6275 6276 void uzp1(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6277 6278 6279### UZP2 ### 6280 6281Unzip vectors (secondary). 6282 6283 void uzp2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6284 6285 6286<a id="float-x"> 6287 6288### XTN ### 6289 6290Extract narrow. 6291 6292 void xtn(const VRegister& vd, const VRegister& vn) 6293 6294 6295### XTN2 ### 6296 6297Extract narrow (second part). 6298 6299 void xtn2(const VRegister& vd, const VRegister& vn) 6300 6301 6302<a id="float-z"> 6303 6304### ZIP1 ### 6305 6306Zip vectors (primary). 6307 6308 void zip1(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6309 6310 6311### ZIP2 ### 6312 6313Zip vectors (secondary). 6314 6315 void zip2(const VRegister& vd, const VRegister& vn, const VRegister& vm) 6316 6317 6318 6319AArch64 Scalable Vector Extension (SVE) instructions 6320---------------------------------------------------- 6321 6322<a id="sve-a"> 6323 6324### ABS ### 6325 6326Absolute value (predicated). 6327 6328 void abs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 6329 6330 6331### ADCLB ### 6332 6333Add with carry long (bottom). 6334 6335 void adclb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 6336 6337 6338### ADCLT ### 6339 6340Add with carry long (top). 6341 6342 void adclt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 6343 6344 6345### ADD ### 6346 6347Add immediate (unpredicated). 6348 6349 void add(const ZRegister& zd, const ZRegister& zn, int imm8, int shift = -1) 6350 6351 6352### ADD ### 6353 6354Add vectors (predicated). 6355 6356 void add(const ZRegister& zd, 6357 const PRegisterM& pg, 6358 const ZRegister& zn, 6359 const ZRegister& zm) 6360 6361 6362### ADD ### 6363 6364Add vectors (unpredicated). 6365 6366 void add(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 6367 6368 6369### ADDHNB ### 6370 6371Add narrow high part (bottom). 6372 6373 void addhnb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 6374 6375 6376### ADDHNT ### 6377 6378Add narrow high part (top). 6379 6380 void addhnt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 6381 6382 6383### ADDP ### 6384 6385Add pairwise. 6386 6387 void addp(const ZRegister& zd, 6388 const PRegisterM& pg, 6389 const ZRegister& zn, 6390 const ZRegister& zm) 6391 6392 6393### ADDPL ### 6394 6395Add multiple of predicate register size to scalar register. 6396 6397 void addpl(const Register& xd, const Register& xn, int imm6) 6398 6399 6400### ADDVL ### 6401 6402Add multiple of vector register size to scalar register. 6403 6404 void addvl(const Register& xd, const Register& xn, int imm6) 6405 6406 6407### ADR ### 6408 6409Compute vector address. 6410 6411 void adr(const ZRegister& zd, const SVEMemOperand& addr) 6412 6413 6414### AND ### 6415 6416Bitwise AND predicates. 6417 6418 void and_(const PRegisterWithLaneSize& pd, 6419 const PRegisterZ& pg, 6420 const PRegisterWithLaneSize& pn, 6421 const PRegisterWithLaneSize& pm) 6422 6423 6424### AND ### 6425 6426Bitwise AND vectors (predicated). 6427 6428 void and_(const ZRegister& zd, 6429 const PRegisterM& pg, 6430 const ZRegister& zn, 6431 const ZRegister& zm) 6432 6433 6434### AND ### 6435 6436Bitwise AND vectors (unpredicated). 6437 6438 void and_(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 6439 6440 6441### AND ### 6442 6443Bitwise AND with immediate (unpredicated). 6444 6445 void and_(const ZRegister& zd, const ZRegister& zn, uint64_t imm) 6446 6447 6448### ANDS ### 6449 6450Bitwise AND predicates. 6451 6452 void ands(const PRegisterWithLaneSize& pd, 6453 const PRegisterZ& pg, 6454 const PRegisterWithLaneSize& pn, 6455 const PRegisterWithLaneSize& pm) 6456 6457 6458### ANDV ### 6459 6460Bitwise AND reduction to scalar. 6461 6462 void andv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 6463 6464 6465### ASR ### 6466 6467Arithmetic shift right by 64-bit wide elements (predicated). 6468 6469 void asr(const ZRegister& zd, 6470 const PRegisterM& pg, 6471 const ZRegister& zn, 6472 const ZRegister& zm) 6473 6474 6475### ASR ### 6476 6477Arithmetic shift right by 64-bit wide elements (unpredicated). 6478 6479 void asr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 6480 6481 6482### ASR ### 6483 6484Arithmetic shift right by immediate (predicated). 6485 6486 void asr(const ZRegister& zd, 6487 const PRegisterM& pg, 6488 const ZRegister& zn, 6489 int shift) 6490 6491 6492### ASR ### 6493 6494Arithmetic shift right by immediate (unpredicated). 6495 6496 void asr(const ZRegister& zd, const ZRegister& zn, int shift) 6497 6498 6499### ASRD ### 6500 6501Arithmetic shift right for divide by immediate (predicated). 6502 6503 void asrd(const ZRegister& zd, 6504 const PRegisterM& pg, 6505 const ZRegister& zn, 6506 int shift) 6507 6508 6509### ASRR ### 6510 6511Reversed arithmetic shift right by vector (predicated). 6512 6513 void asrr(const ZRegister& zd, 6514 const PRegisterM& pg, 6515 const ZRegister& zn, 6516 const ZRegister& zm) 6517 6518 6519<a id="sve-b"> 6520 6521### BCAX ### 6522 6523Bitwise clear and exclusive OR. 6524 6525 void bcax(const ZRegister& zd, 6526 const ZRegister& zn, 6527 const ZRegister& zm, 6528 const ZRegister& zk) 6529 6530 6531### BDEP ### 6532 6533Scatter lower bits into positions selected by bitmask. 6534 6535 void bdep(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 6536 6537 6538### BEXT ### 6539 6540Gather lower bits from positions selected by bitmask. 6541 6542 void bext(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 6543 6544 6545### BGRP ### 6546 6547Group bits to right or left as selected by bitmask. 6548 6549 void bgrp(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 6550 6551 6552### BIC ### 6553 6554Bitwise clear bits using immediate (unpredicated). 6555 6556 void bic(const ZRegister& zd, const ZRegister& zn, uint64_t imm) 6557 6558 6559### BIC ### 6560 6561Bitwise clear predicates. 6562 6563 void bic(const PRegisterWithLaneSize& pd, 6564 const PRegisterZ& pg, 6565 const PRegisterWithLaneSize& pn, 6566 const PRegisterWithLaneSize& pm) 6567 6568 6569### BIC ### 6570 6571Bitwise clear vectors (predicated). 6572 6573 void bic(const ZRegister& zd, 6574 const PRegisterM& pg, 6575 const ZRegister& zn, 6576 const ZRegister& zm) 6577 6578 6579### BIC ### 6580 6581Bitwise clear vectors (unpredicated). 6582 6583 void bic(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 6584 6585 6586### BICS ### 6587 6588Bitwise clear predicates. 6589 6590 void bics(const PRegisterWithLaneSize& pd, 6591 const PRegisterZ& pg, 6592 const PRegisterWithLaneSize& pn, 6593 const PRegisterWithLaneSize& pm) 6594 6595 6596### BRKA ### 6597 6598Break after first true condition. 6599 6600 void brka(const PRegisterWithLaneSize& pd, 6601 const PRegister& pg, 6602 const PRegisterWithLaneSize& pn) 6603 6604 6605### BRKAS ### 6606 6607Break after first true condition. 6608 6609 void brkas(const PRegisterWithLaneSize& pd, 6610 const PRegisterZ& pg, 6611 const PRegisterWithLaneSize& pn) 6612 6613 6614### BRKB ### 6615 6616Break before first true condition. 6617 6618 void brkb(const PRegisterWithLaneSize& pd, 6619 const PRegister& pg, 6620 const PRegisterWithLaneSize& pn) 6621 6622 6623### BRKBS ### 6624 6625Break before first true condition. 6626 6627 void brkbs(const PRegisterWithLaneSize& pd, 6628 const PRegisterZ& pg, 6629 const PRegisterWithLaneSize& pn) 6630 6631 6632### BRKN ### 6633 6634Propagate break to next partition. 6635 6636 void brkn(const PRegisterWithLaneSize& pd, 6637 const PRegisterZ& pg, 6638 const PRegisterWithLaneSize& pn, 6639 const PRegisterWithLaneSize& pm) 6640 6641 6642### BRKNS ### 6643 6644Propagate break to next partition. 6645 6646 void brkns(const PRegisterWithLaneSize& pd, 6647 const PRegisterZ& pg, 6648 const PRegisterWithLaneSize& pn, 6649 const PRegisterWithLaneSize& pm) 6650 6651 6652### BRKPA ### 6653 6654Break after first true condition, propagating from previous partition. 6655 6656 void brkpa(const PRegisterWithLaneSize& pd, 6657 const PRegisterZ& pg, 6658 const PRegisterWithLaneSize& pn, 6659 const PRegisterWithLaneSize& pm) 6660 6661 6662### BRKPAS ### 6663 6664Break after first true condition, propagating from previous partition. 6665 6666 void brkpas(const PRegisterWithLaneSize& pd, 6667 const PRegisterZ& pg, 6668 const PRegisterWithLaneSize& pn, 6669 const PRegisterWithLaneSize& pm) 6670 6671 6672### BRKPB ### 6673 6674Break before first true condition, propagating from previous partition. 6675 6676 void brkpb(const PRegisterWithLaneSize& pd, 6677 const PRegisterZ& pg, 6678 const PRegisterWithLaneSize& pn, 6679 const PRegisterWithLaneSize& pm) 6680 6681 6682### BRKPBS ### 6683 6684Break before first true condition, propagating from previous partition. 6685 6686 void brkpbs(const PRegisterWithLaneSize& pd, 6687 const PRegisterZ& pg, 6688 const PRegisterWithLaneSize& pn, 6689 const PRegisterWithLaneSize& pm) 6690 6691 6692### BSL ### 6693 6694Bitwise select. 6695 6696 void bsl(const ZRegister& zd, 6697 const ZRegister& zn, 6698 const ZRegister& zm, 6699 const ZRegister& zk) 6700 6701 6702### BSL1N ### 6703 6704Bitwise select with first input inverted. 6705 6706 void bsl1n(const ZRegister& zd, 6707 const ZRegister& zn, 6708 const ZRegister& zm, 6709 const ZRegister& zk) 6710 6711 6712### BSL2N ### 6713 6714Bitwise select with second input inverted. 6715 6716 void bsl2n(const ZRegister& zd, 6717 const ZRegister& zn, 6718 const ZRegister& zm, 6719 const ZRegister& zk) 6720 6721 6722<a id="sve-c"> 6723 6724### CADD ### 6725 6726Complex integer add with rotate. 6727 6728 void cadd(const ZRegister& zd, 6729 const ZRegister& zn, 6730 const ZRegister& zm, 6731 int rot) 6732 6733 6734### CDOT ### 6735 6736Complex integer dot product (indexed). 6737 6738 void cdot(const ZRegister& zda, 6739 const ZRegister& zn, 6740 const ZRegister& zm, 6741 int index, 6742 int rot) 6743 6744 6745### CDOT ### 6746 6747Complex integer dot product. 6748 6749 void cdot(const ZRegister& zda, 6750 const ZRegister& zn, 6751 const ZRegister& zm, 6752 int rot) 6753 6754 6755### CLASTA ### 6756 6757Conditionally extract element after last to SIMD&FP scalar register. 6758 6759 void clasta(const VRegister& vd, 6760 const PRegister& pg, 6761 const VRegister& vn, 6762 const ZRegister& zm) 6763 6764 6765### CLASTA ### 6766 6767Conditionally extract element after last to general-purpose register. 6768 6769 void clasta(const Register& rd, 6770 const PRegister& pg, 6771 const Register& rn, 6772 const ZRegister& zm) 6773 6774 6775### CLASTA ### 6776 6777Conditionally extract element after last to vector register. 6778 6779 void clasta(const ZRegister& zd, 6780 const PRegister& pg, 6781 const ZRegister& zn, 6782 const ZRegister& zm) 6783 6784 6785### CLASTB ### 6786 6787Conditionally extract last element to SIMD&FP scalar register. 6788 6789 void clastb(const VRegister& vd, 6790 const PRegister& pg, 6791 const VRegister& vn, 6792 const ZRegister& zm) 6793 6794 6795### CLASTB ### 6796 6797Conditionally extract last element to general-purpose register. 6798 6799 void clastb(const Register& rd, 6800 const PRegister& pg, 6801 const Register& rn, 6802 const ZRegister& zm) 6803 6804 6805### CLASTB ### 6806 6807Conditionally extract last element to vector register. 6808 6809 void clastb(const ZRegister& zd, 6810 const PRegister& pg, 6811 const ZRegister& zn, 6812 const ZRegister& zm) 6813 6814 6815### CLS ### 6816 6817Count leading sign bits (predicated). 6818 6819 void cls(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 6820 6821 6822### CLZ ### 6823 6824Count leading zero bits (predicated). 6825 6826 void clz(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 6827 6828 6829### CMLA ### 6830 6831Complex integer multiply-add with rotate (indexed). 6832 6833 void cmla(const ZRegister& zda, 6834 const ZRegister& zn, 6835 const ZRegister& zm, 6836 int index, 6837 int rot) 6838 6839 6840### CMLA ### 6841 6842Complex integer multiply-add with rotate. 6843 6844 void cmla(const ZRegister& zda, 6845 const ZRegister& zn, 6846 const ZRegister& zm, 6847 int rot) 6848 6849 6850### CMP ### 6851 6852 6853 6854 void cmp(Condition cond, 6855 const PRegisterWithLaneSize& pd, 6856 const PRegisterZ& pg, 6857 const ZRegister& zn, 6858 const ZRegister& zm) 6859 6860 6861### CMPEQ ### 6862 6863Compare vector to 64-bit wide elements. 6864 6865 void cmpeq(const PRegisterWithLaneSize& pd, 6866 const PRegisterZ& pg, 6867 const ZRegister& zn, 6868 const ZRegister& zm) 6869 6870 6871### CMPEQ ### 6872 6873Compare vector to immediate. 6874 6875 void cmpeq(const PRegisterWithLaneSize& pd, 6876 const PRegisterZ& pg, 6877 const ZRegister& zn, 6878 int imm5) 6879 6880 6881### CMPGE ### 6882 6883Compare vector to 64-bit wide elements. 6884 6885 void cmpge(const PRegisterWithLaneSize& pd, 6886 const PRegisterZ& pg, 6887 const ZRegister& zn, 6888 const ZRegister& zm) 6889 6890 6891### CMPGE ### 6892 6893Compare vector to immediate. 6894 6895 void cmpge(const PRegisterWithLaneSize& pd, 6896 const PRegisterZ& pg, 6897 const ZRegister& zn, 6898 int imm5) 6899 6900 6901### CMPGT ### 6902 6903Compare vector to 64-bit wide elements. 6904 6905 void cmpgt(const PRegisterWithLaneSize& pd, 6906 const PRegisterZ& pg, 6907 const ZRegister& zn, 6908 const ZRegister& zm) 6909 6910 6911### CMPGT ### 6912 6913Compare vector to immediate. 6914 6915 void cmpgt(const PRegisterWithLaneSize& pd, 6916 const PRegisterZ& pg, 6917 const ZRegister& zn, 6918 int imm5) 6919 6920 6921### CMPHI ### 6922 6923Compare vector to 64-bit wide elements. 6924 6925 void cmphi(const PRegisterWithLaneSize& pd, 6926 const PRegisterZ& pg, 6927 const ZRegister& zn, 6928 const ZRegister& zm) 6929 6930 6931### CMPHI ### 6932 6933Compare vector to immediate. 6934 6935 void cmphi(const PRegisterWithLaneSize& pd, 6936 const PRegisterZ& pg, 6937 const ZRegister& zn, 6938 unsigned imm7) 6939 6940 6941### CMPHS ### 6942 6943Compare vector to 64-bit wide elements. 6944 6945 void cmphs(const PRegisterWithLaneSize& pd, 6946 const PRegisterZ& pg, 6947 const ZRegister& zn, 6948 const ZRegister& zm) 6949 6950 6951### CMPHS ### 6952 6953Compare vector to immediate. 6954 6955 void cmphs(const PRegisterWithLaneSize& pd, 6956 const PRegisterZ& pg, 6957 const ZRegister& zn, 6958 unsigned imm7) 6959 6960 6961### CMPLE ### 6962 6963Compare vector to 64-bit wide elements. 6964 6965 void cmple(const PRegisterWithLaneSize& pd, 6966 const PRegisterZ& pg, 6967 const ZRegister& zn, 6968 const ZRegister& zm) 6969 6970 6971### CMPLE ### 6972 6973Compare vector to immediate. 6974 6975 void cmple(const PRegisterWithLaneSize& pd, 6976 const PRegisterZ& pg, 6977 const ZRegister& zn, 6978 int imm5) 6979 6980 6981### CMPLO ### 6982 6983Compare vector to 64-bit wide elements. 6984 6985 void cmplo(const PRegisterWithLaneSize& pd, 6986 const PRegisterZ& pg, 6987 const ZRegister& zn, 6988 const ZRegister& zm) 6989 6990 6991### CMPLO ### 6992 6993Compare vector to immediate. 6994 6995 void cmplo(const PRegisterWithLaneSize& pd, 6996 const PRegisterZ& pg, 6997 const ZRegister& zn, 6998 unsigned imm7) 6999 7000 7001### CMPLS ### 7002 7003Compare vector to 64-bit wide elements. 7004 7005 void cmpls(const PRegisterWithLaneSize& pd, 7006 const PRegisterZ& pg, 7007 const ZRegister& zn, 7008 const ZRegister& zm) 7009 7010 7011### CMPLS ### 7012 7013Compare vector to immediate. 7014 7015 void cmpls(const PRegisterWithLaneSize& pd, 7016 const PRegisterZ& pg, 7017 const ZRegister& zn, 7018 unsigned imm7) 7019 7020 7021### CMPLT ### 7022 7023Compare vector to 64-bit wide elements. 7024 7025 void cmplt(const PRegisterWithLaneSize& pd, 7026 const PRegisterZ& pg, 7027 const ZRegister& zn, 7028 const ZRegister& zm) 7029 7030 7031### CMPLT ### 7032 7033Compare vector to immediate. 7034 7035 void cmplt(const PRegisterWithLaneSize& pd, 7036 const PRegisterZ& pg, 7037 const ZRegister& zn, 7038 int imm5) 7039 7040 7041### CMPNE ### 7042 7043Compare vector to 64-bit wide elements. 7044 7045 void cmpne(const PRegisterWithLaneSize& pd, 7046 const PRegisterZ& pg, 7047 const ZRegister& zn, 7048 const ZRegister& zm) 7049 7050 7051### CMPNE ### 7052 7053Compare vector to immediate. 7054 7055 void cmpne(const PRegisterWithLaneSize& pd, 7056 const PRegisterZ& pg, 7057 const ZRegister& zn, 7058 int imm5) 7059 7060 7061### CNOT ### 7062 7063Logically invert boolean condition in vector (predicated). 7064 7065 void cnot(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7066 7067 7068### CNT ### 7069 7070Count non-zero bits (predicated). 7071 7072 void cnt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7073 7074 7075### CNTB ### 7076 7077Set scalar to multiple of predicate constraint element count. 7078 7079 void cntb(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) 7080 7081 7082### CNTD ### 7083 7084Set scalar to multiple of predicate constraint element count. 7085 7086 void cntd(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) 7087 7088 7089### CNTH ### 7090 7091Set scalar to multiple of predicate constraint element count. 7092 7093 void cnth(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) 7094 7095 7096### CNTP ### 7097 7098Set scalar to active predicate element count. 7099 7100 void cntp(const Register& xd, 7101 const PRegister& pg, 7102 const PRegisterWithLaneSize& pn) 7103 7104 7105### CNTW ### 7106 7107Set scalar to multiple of predicate constraint element count. 7108 7109 void cntw(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) 7110 7111 7112### COMPACT ### 7113 7114Shuffle active elements of vector to the right and fill with zero. 7115 7116 void compact(const ZRegister& zd, const PRegister& pg, const ZRegister& zn) 7117 7118 7119### CPY ### 7120 7121Copy SIMD&FP scalar register to vector elements (predicated). 7122 7123 void cpy(const ZRegister& zd, const PRegisterM& pg, const VRegister& vn) 7124 7125 7126### CPY ### 7127 7128Copy general-purpose register to vector elements (predicated). 7129 7130 void cpy(const ZRegister& zd, const PRegisterM& pg, const Register& rn) 7131 7132 7133### CPY ### 7134 7135Copy signed integer immediate to vector elements (predicated). 7136 7137 void cpy(const ZRegister& zd, const PRegister& pg, int imm8, int shift = -1) 7138 7139 7140### CTERMEQ ### 7141 7142Compare and terminate loop. 7143 7144 void ctermeq(const Register& rn, const Register& rm) 7145 7146 7147### CTERMNE ### 7148 7149Compare and terminate loop. 7150 7151 void ctermne(const Register& rn, const Register& rm) 7152 7153 7154<a id="sve-d"> 7155 7156### DECB ### 7157 7158Decrement scalar by multiple of predicate constraint element count. 7159 7160 void decb(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1) 7161 7162 7163### DECD ### 7164 7165Decrement scalar by multiple of predicate constraint element count. 7166 7167 void decd(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1) 7168 7169 7170### DECD ### 7171 7172Decrement vector by multiple of predicate constraint element count. 7173 7174 void decd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 7175 7176 7177### DECH ### 7178 7179Decrement scalar by multiple of predicate constraint element count. 7180 7181 void dech(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1) 7182 7183 7184### DECH ### 7185 7186Decrement vector by multiple of predicate constraint element count. 7187 7188 void dech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 7189 7190 7191### DECP ### 7192 7193Decrement scalar by active predicate element count. 7194 7195 void decp(const Register& rdn, const PRegisterWithLaneSize& pg) 7196 7197 7198### DECP ### 7199 7200Decrement vector by active predicate element count. 7201 7202 void decp(const ZRegister& zdn, const PRegister& pg) 7203 7204 7205### DECW ### 7206 7207Decrement scalar by multiple of predicate constraint element count. 7208 7209 void decw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1) 7210 7211 7212### DECW ### 7213 7214Decrement vector by multiple of predicate constraint element count. 7215 7216 void decw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 7217 7218 7219### DUP ### 7220 7221Broadcast general-purpose register to vector elements (unpredicated). 7222 7223 void dup(const ZRegister& zd, const Register& xn) 7224 7225 7226### DUP ### 7227 7228Broadcast indexed element to vector (unpredicated). 7229 7230 void dup(const ZRegister& zd, const ZRegister& zn, unsigned index) 7231 7232 7233### DUP ### 7234 7235Broadcast signed immediate to vector elements (unpredicated). 7236 7237 void dup(const ZRegister& zd, int imm8, int shift = -1) 7238 7239 7240### DUPM ### 7241 7242Broadcast logical bitmask immediate to vector (unpredicated). 7243 7244 void dupm(const ZRegister& zd, uint64_t imm) 7245 7246 7247<a id="sve-e"> 7248 7249### EON ### 7250 7251Bitwise exclusive OR with inverted immediate (unpredicated). 7252 7253 void eon(const ZRegister& zd, const ZRegister& zn, uint64_t imm) 7254 7255 7256### EOR ### 7257 7258Bitwise exclusive OR predicates. 7259 7260 void eor(const PRegisterWithLaneSize& pd, 7261 const PRegisterZ& pg, 7262 const PRegisterWithLaneSize& pn, 7263 const PRegisterWithLaneSize& pm) 7264 7265 7266### EOR ### 7267 7268Bitwise exclusive OR vectors (predicated). 7269 7270 void eor(const ZRegister& zd, 7271 const PRegisterM& pg, 7272 const ZRegister& zn, 7273 const ZRegister& zm) 7274 7275 7276### EOR ### 7277 7278Bitwise exclusive OR vectors (unpredicated). 7279 7280 void eor(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 7281 7282 7283### EOR ### 7284 7285Bitwise exclusive OR with immediate (unpredicated). 7286 7287 void eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) 7288 7289 7290### EOR3 ### 7291 7292Bitwise exclusive OR of three vectors. 7293 7294 void eor3(const ZRegister& zd, 7295 const ZRegister& zn, 7296 const ZRegister& zm, 7297 const ZRegister& zk) 7298 7299 7300### EORBT ### 7301 7302Interleaving exclusive OR (bottom, top). 7303 7304 void eorbt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 7305 7306 7307### EORS ### 7308 7309Bitwise exclusive OR predicates. 7310 7311 void eors(const PRegisterWithLaneSize& pd, 7312 const PRegisterZ& pg, 7313 const PRegisterWithLaneSize& pn, 7314 const PRegisterWithLaneSize& pm) 7315 7316 7317### EORTB ### 7318 7319Interleaving exclusive OR (top, bottom). 7320 7321 void eortb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 7322 7323 7324### EORV ### 7325 7326Bitwise XOR reduction to scalar. 7327 7328 void eorv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 7329 7330 7331### EXT ### 7332 7333Extract vector from pair of vectors. 7334 7335 void ext(const ZRegister& zd, 7336 const ZRegister& zn, 7337 const ZRegister& zm, 7338 unsigned offset) 7339 7340 7341<a id="sve-f"> 7342 7343### FABD ### 7344 7345Floating-point absolute difference (predicated). 7346 7347 void fabd(const ZRegister& zd, 7348 const PRegisterM& pg, 7349 const ZRegister& zn, 7350 const ZRegister& zm) 7351 7352 7353### FABS ### 7354 7355Floating-point absolute value (predicated). 7356 7357 void fabs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7358 7359 7360### FACGE ### 7361 7362Floating-point absolute compare vectors. 7363 7364 void facge(const PRegisterWithLaneSize& pd, 7365 const PRegisterZ& pg, 7366 const ZRegister& zn, 7367 const ZRegister& zm) 7368 7369 7370### FACGT ### 7371 7372Floating-point absolute compare vectors. 7373 7374 void facgt(const PRegisterWithLaneSize& pd, 7375 const PRegisterZ& pg, 7376 const ZRegister& zn, 7377 const ZRegister& zm) 7378 7379 7380### FADD ### 7381 7382Floating-point add immediate (predicated). 7383 7384 void fadd(const ZRegister& zd, 7385 const PRegisterM& pg, 7386 const ZRegister& zn, 7387 double imm) 7388 7389 7390### FADD ### 7391 7392Floating-point add vector (predicated). 7393 7394 void fadd(const ZRegister& zd, 7395 const PRegisterM& pg, 7396 const ZRegister& zn, 7397 const ZRegister& zm) 7398 7399 7400### FADD ### 7401 7402Floating-point add vector (unpredicated). 7403 7404 void fadd(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 7405 7406 7407### FADDA ### 7408 7409Floating-point add strictly-ordered reduction, accumulating in scalar. 7410 7411 void fadda(const VRegister& vd, 7412 const PRegister& pg, 7413 const VRegister& vn, 7414 const ZRegister& zm) 7415 7416 7417### FADDP ### 7418 7419Floating-point add pairwise. 7420 7421 void faddp(const ZRegister& zd, 7422 const PRegisterM& pg, 7423 const ZRegister& zn, 7424 const ZRegister& zm) 7425 7426 7427### FADDV ### 7428 7429Floating-point add recursive reduction to scalar. 7430 7431 void faddv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 7432 7433 7434### FCADD ### 7435 7436Floating-point complex add with rotate (predicated). 7437 7438 void fcadd(const ZRegister& zd, 7439 const PRegisterM& pg, 7440 const ZRegister& zn, 7441 const ZRegister& zm, 7442 int rot) 7443 7444 7445### FCMEQ ### 7446 7447Floating-point compare vector with zero. 7448 7449 void fcmeq(const PRegisterWithLaneSize& pd, 7450 const PRegisterZ& pg, 7451 const ZRegister& zn, 7452 double zero) 7453 7454 7455### FCMEQ ### 7456 7457Floating-point compare vectors. 7458 7459 void fcmeq(const PRegisterWithLaneSize& pd, 7460 const PRegisterZ& pg, 7461 const ZRegister& zn, 7462 const ZRegister& zm) 7463 7464 7465### FCMGE ### 7466 7467Floating-point compare vector with zero. 7468 7469 void fcmge(const PRegisterWithLaneSize& pd, 7470 const PRegisterZ& pg, 7471 const ZRegister& zn, 7472 double zero) 7473 7474 7475### FCMGE ### 7476 7477Floating-point compare vectors. 7478 7479 void fcmge(const PRegisterWithLaneSize& pd, 7480 const PRegisterZ& pg, 7481 const ZRegister& zn, 7482 const ZRegister& zm) 7483 7484 7485### FCMGT ### 7486 7487Floating-point compare vector with zero. 7488 7489 void fcmgt(const PRegisterWithLaneSize& pd, 7490 const PRegisterZ& pg, 7491 const ZRegister& zn, 7492 double zero) 7493 7494 7495### FCMGT ### 7496 7497Floating-point compare vectors. 7498 7499 void fcmgt(const PRegisterWithLaneSize& pd, 7500 const PRegisterZ& pg, 7501 const ZRegister& zn, 7502 const ZRegister& zm) 7503 7504 7505### FCMLA ### 7506 7507Floating-point complex multiply-add by indexed values with rotate. 7508 7509 void fcmla(const ZRegister& zda, 7510 const ZRegister& zn, 7511 const ZRegister& zm, 7512 int index, 7513 int rot) 7514 7515 7516### FCMLA ### 7517 7518Floating-point complex multiply-add with rotate (predicated). 7519 7520 void fcmla(const ZRegister& zda, 7521 const PRegisterM& pg, 7522 const ZRegister& zn, 7523 const ZRegister& zm, 7524 int rot) 7525 7526 7527### FCMLE ### 7528 7529Floating-point compare vector with zero. 7530 7531 void fcmle(const PRegisterWithLaneSize& pd, 7532 const PRegisterZ& pg, 7533 const ZRegister& zn, 7534 double zero) 7535 7536 7537### FCMLT ### 7538 7539Floating-point compare vector with zero. 7540 7541 void fcmlt(const PRegisterWithLaneSize& pd, 7542 const PRegisterZ& pg, 7543 const ZRegister& zn, 7544 double zero) 7545 7546 7547### FCMNE ### 7548 7549Floating-point compare vector with zero. 7550 7551 void fcmne(const PRegisterWithLaneSize& pd, 7552 const PRegisterZ& pg, 7553 const ZRegister& zn, 7554 double zero) 7555 7556 7557### FCMNE ### 7558 7559Floating-point compare vectors. 7560 7561 void fcmne(const PRegisterWithLaneSize& pd, 7562 const PRegisterZ& pg, 7563 const ZRegister& zn, 7564 const ZRegister& zm) 7565 7566 7567### FCMUO ### 7568 7569Floating-point compare vectors. 7570 7571 void fcmuo(const PRegisterWithLaneSize& pd, 7572 const PRegisterZ& pg, 7573 const ZRegister& zn, 7574 const ZRegister& zm) 7575 7576 7577### FCPY ### 7578 7579Copy floating-point immediate to vector elements (predicated). 7580 7581 void fcpy(const ZRegister& zd, const PRegisterM& pg, double imm) 7582 7583 7584### FCPY ### 7585 7586Copy half-precision floating-point immediate to vector elements (predicated). 7587 7588 void fcpy(const ZRegister& zd, const PRegisterM& pg, Float16 imm) 7589 7590 7591### FCVT ### 7592 7593Floating-point convert precision (predicated). 7594 7595 void fcvt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7596 7597 7598### FCVTLT ### 7599 7600Floating-point up convert long (top, predicated). 7601 7602 void fcvtlt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7603 7604 7605### FCVTNT ### 7606 7607Floating-point down convert and narrow (top, predicated). 7608 7609 void fcvtnt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7610 7611 7612### FCVTX ### 7613 7614Floating-point down convert, rounding to odd (predicated). 7615 7616 void fcvtx(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7617 7618 7619### FCVTXNT ### 7620 7621Floating-point down convert, rounding to odd (top, predicated). 7622 7623 void fcvtxnt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7624 7625 7626### FCVTZS ### 7627 7628Floating-point convert to signed integer, rounding toward zero (predicated). 7629 7630 void fcvtzs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7631 7632 7633### FCVTZU ### 7634 7635Floating-point convert to unsigned integer, rounding toward zero (predicated). 7636 7637 void fcvtzu(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7638 7639 7640### FDIV ### 7641 7642Floating-point divide by vector (predicated). 7643 7644 void fdiv(const ZRegister& zd, 7645 const PRegisterM& pg, 7646 const ZRegister& zn, 7647 const ZRegister& zm) 7648 7649 7650### FDIVR ### 7651 7652Floating-point reversed divide by vector (predicated). 7653 7654 void fdivr(const ZRegister& zd, 7655 const PRegisterM& pg, 7656 const ZRegister& zn, 7657 const ZRegister& zm) 7658 7659 7660### FDUP ### 7661 7662Broadcast floating-point immediate to vector elements. 7663 7664 void fdup(const ZRegister& zd, double imm) 7665 7666 7667### FDUP ### 7668 7669Broadcast half-precision floating-point immediate to vector elements. 7670 7671 void fdup(const ZRegister& zd, Float16 imm) 7672 7673 7674### FEXPA ### 7675 7676Floating-point exponential accelerator. 7677 7678 void fexpa(const ZRegister& zd, const ZRegister& zn) 7679 7680 7681### FLOGB ### 7682 7683Floating-point base 2 logarithm as integer. 7684 7685 void flogb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 7686 7687 7688### FMAD ### 7689 7690Floating-point fused multiply-add vectors (predicated), writing multiplicand [Zdn = Za + Zdn * Zm]. 7691 7692 void fmad(const ZRegister& zdn, 7693 const PRegisterM& pg, 7694 const ZRegister& zm, 7695 const ZRegister& za) 7696 7697 7698### FMAX ### 7699 7700Floating-point maximum (predicated). 7701 7702 void fmax(const ZRegister& zd, 7703 const PRegisterM& pg, 7704 const ZRegister& zn, 7705 const ZRegister& zm) 7706 7707 7708### FMAX ### 7709 7710Floating-point maximum with immediate (predicated). 7711 7712 void fmax(const ZRegister& zd, 7713 const PRegisterM& pg, 7714 const ZRegister& zn, 7715 double imm) 7716 7717 7718### FMAXNM ### 7719 7720Floating-point maximum number (predicated). 7721 7722 void fmaxnm(const ZRegister& zd, 7723 const PRegisterM& pg, 7724 const ZRegister& zn, 7725 const ZRegister& zm) 7726 7727 7728### FMAXNM ### 7729 7730Floating-point maximum number with immediate (predicated). 7731 7732 void fmaxnm(const ZRegister& zd, 7733 const PRegisterM& pg, 7734 const ZRegister& zn, 7735 double imm) 7736 7737 7738### FMAXNMP ### 7739 7740Floating-point maximum number pairwise. 7741 7742 void fmaxnmp(const ZRegister& zd, 7743 const PRegisterM& pg, 7744 const ZRegister& zn, 7745 const ZRegister& zm) 7746 7747 7748### FMAXNMV ### 7749 7750Floating-point maximum number recursive reduction to scalar. 7751 7752 void fmaxnmv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 7753 7754 7755### FMAXP ### 7756 7757Floating-point maximum pairwise. 7758 7759 void fmaxp(const ZRegister& zd, 7760 const PRegisterM& pg, 7761 const ZRegister& zn, 7762 const ZRegister& zm) 7763 7764 7765### FMAXV ### 7766 7767Floating-point maximum recursive reduction to scalar. 7768 7769 void fmaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 7770 7771 7772### FMIN ### 7773 7774Floating-point minimum (predicated). 7775 7776 void fmin(const ZRegister& zd, 7777 const PRegisterM& pg, 7778 const ZRegister& zn, 7779 const ZRegister& zm) 7780 7781 7782### FMIN ### 7783 7784Floating-point minimum with immediate (predicated). 7785 7786 void fmin(const ZRegister& zd, 7787 const PRegisterM& pg, 7788 const ZRegister& zn, 7789 double imm) 7790 7791 7792### FMINNM ### 7793 7794Floating-point minimum number (predicated). 7795 7796 void fminnm(const ZRegister& zd, 7797 const PRegisterM& pg, 7798 const ZRegister& zn, 7799 const ZRegister& zm) 7800 7801 7802### FMINNM ### 7803 7804Floating-point minimum number with immediate (predicated). 7805 7806 void fminnm(const ZRegister& zd, 7807 const PRegisterM& pg, 7808 const ZRegister& zn, 7809 double imm) 7810 7811 7812### FMINNMP ### 7813 7814Floating-point minimum number pairwise. 7815 7816 void fminnmp(const ZRegister& zd, 7817 const PRegisterM& pg, 7818 const ZRegister& zn, 7819 const ZRegister& zm) 7820 7821 7822### FMINNMV ### 7823 7824Floating-point minimum number recursive reduction to scalar. 7825 7826 void fminnmv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 7827 7828 7829### FMINP ### 7830 7831Floating-point minimum pairwise. 7832 7833 void fminp(const ZRegister& zd, 7834 const PRegisterM& pg, 7835 const ZRegister& zn, 7836 const ZRegister& zm) 7837 7838 7839### FMINV ### 7840 7841Floating-point minimum recursive reduction to scalar. 7842 7843 void fminv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 7844 7845 7846### FMLA ### 7847 7848Floating-point fused multiply-add by indexed elements (Zda = Zda + Zn * Zm[indexed]). 7849 7850 void fmla(const ZRegister& zda, 7851 const ZRegister& zn, 7852 const ZRegister& zm, 7853 int index) 7854 7855 7856### FMLA ### 7857 7858Floating-point fused multiply-add vectors (predicated), writing addend [Zda = Zda + Zn * Zm]. 7859 7860 void fmla(const ZRegister& zda, 7861 const PRegisterM& pg, 7862 const ZRegister& zn, 7863 const ZRegister& zm) 7864 7865 7866### FMLALB ### 7867 7868Half-precision floating-point multiply-add long to single-precision (bottom). 7869 7870 void fmlalb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 7871 7872 7873### FMLALB ### 7874 7875Half-precision floating-point multiply-add long to single-precision (bottom, indexed). 7876 7877 void fmlalb(const ZRegister& zda, 7878 const ZRegister& zn, 7879 const ZRegister& zm, 7880 int index) 7881 7882 7883### FMLALT ### 7884 7885Half-precision floating-point multiply-add long to single-precision (top). 7886 7887 void fmlalt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 7888 7889 7890### FMLALT ### 7891 7892Half-precision floating-point multiply-add long to single-precision (top, indexed). 7893 7894 void fmlalt(const ZRegister& zda, 7895 const ZRegister& zn, 7896 const ZRegister& zm, 7897 int index) 7898 7899 7900### FMLS ### 7901 7902Floating-point fused multiply-subtract by indexed elements (Zda = Zda + -Zn * Zm[indexed]). 7903 7904 void fmls(const ZRegister& zda, 7905 const ZRegister& zn, 7906 const ZRegister& zm, 7907 int index) 7908 7909 7910### FMLS ### 7911 7912Floating-point fused multiply-subtract vectors (predicated), writing addend [Zda = Zda + -Zn * Zm]. 7913 7914 void fmls(const ZRegister& zda, 7915 const PRegisterM& pg, 7916 const ZRegister& zn, 7917 const ZRegister& zm) 7918 7919 7920### FMLSLB ### 7921 7922Half-precision floating-point multiply-subtract long from single-precision (bottom). 7923 7924 void fmlslb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 7925 7926 7927### FMLSLB ### 7928 7929Half-precision floating-point multiply-subtract long from single-precision (bottom, indexed). 7930 7931 void fmlslb(const ZRegister& zda, 7932 const ZRegister& zn, 7933 const ZRegister& zm, 7934 int index) 7935 7936 7937### FMLSLT ### 7938 7939Half-precision floating-point multiply-subtract long from single-precision (top). 7940 7941 void fmlslt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 7942 7943 7944### FMLSLT ### 7945 7946Half-precision floating-point multiply-subtract long from single-precision (top, indexed). 7947 7948 void fmlslt(const ZRegister& zda, 7949 const ZRegister& zn, 7950 const ZRegister& zm, 7951 int index) 7952 7953 7954### FMMLA ### 7955 7956Floating-point matrix multiply-accumulate. 7957 7958 void fmmla(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 7959 7960 7961### FMOV ### 7962 7963Move 8-bit floating-point immediate to vector elements (predicated). 7964 7965 void fmov(const ZRegister& zd, const PRegisterM& pg, double imm) 7966 7967 7968### FMOV ### 7969 7970Move 8-bit floating-point immediate to vector elements (unpredicated). 7971 7972 void fmov(const ZRegister& zd, double imm) 7973 7974 7975### FMSB ### 7976 7977Floating-point fused multiply-subtract vectors (predicated), writing multiplicand [Zdn = Za + -Zdn * Zm]. 7978 7979 void fmsb(const ZRegister& zdn, 7980 const PRegisterM& pg, 7981 const ZRegister& zm, 7982 const ZRegister& za) 7983 7984 7985### FMUL ### 7986 7987Floating-point multiply by immediate (predicated). 7988 7989 void fmul(const ZRegister& zd, 7990 const PRegisterM& pg, 7991 const ZRegister& zn, 7992 double imm) 7993 7994 7995### FMUL ### 7996 7997Floating-point multiply by indexed elements. 7998 7999 void fmul(const ZRegister& zd, 8000 const ZRegister& zn, 8001 const ZRegister& zm, 8002 unsigned index) 8003 8004 8005### FMUL ### 8006 8007Floating-point multiply vectors (predicated). 8008 8009 void fmul(const ZRegister& zd, 8010 const PRegisterM& pg, 8011 const ZRegister& zn, 8012 const ZRegister& zm) 8013 8014 8015### FMUL ### 8016 8017Floating-point multiply vectors (unpredicated). 8018 8019 void fmul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 8020 8021 8022### FMULX ### 8023 8024Floating-point multiply-extended vectors (predicated). 8025 8026 void fmulx(const ZRegister& zd, 8027 const PRegisterM& pg, 8028 const ZRegister& zn, 8029 const ZRegister& zm) 8030 8031 8032### FNEG ### 8033 8034Floating-point negate (predicated). 8035 8036 void fneg(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 8037 8038 8039### FNMAD ### 8040 8041Floating-point negated fused multiply-add vectors (predicated), writing multiplicand [Zdn = -Za + -Zdn * Zm]. 8042 8043 void fnmad(const ZRegister& zdn, 8044 const PRegisterM& pg, 8045 const ZRegister& zm, 8046 const ZRegister& za) 8047 8048 8049### FNMLA ### 8050 8051Floating-point negated fused multiply-add vectors (predicated), writing addend [Zda = -Zda + -Zn * Zm]. 8052 8053 void fnmla(const ZRegister& zda, 8054 const PRegisterM& pg, 8055 const ZRegister& zn, 8056 const ZRegister& zm) 8057 8058 8059### FNMLS ### 8060 8061Floating-point negated fused multiply-subtract vectors (predicated), writing addend [Zda = -Zda + Zn * Zm]. 8062 8063 void fnmls(const ZRegister& zda, 8064 const PRegisterM& pg, 8065 const ZRegister& zn, 8066 const ZRegister& zm) 8067 8068 8069### FNMSB ### 8070 8071Floating-point negated fused multiply-subtract vectors (predicated), writing multiplicand [Zdn = -Za + Zdn * Zm]. 8072 8073 void fnmsb(const ZRegister& zdn, 8074 const PRegisterM& pg, 8075 const ZRegister& zm, 8076 const ZRegister& za) 8077 8078 8079### FRECPE ### 8080 8081Floating-point reciprocal estimate (unpredicated). 8082 8083 void frecpe(const ZRegister& zd, const ZRegister& zn) 8084 8085 8086### FRECPS ### 8087 8088Floating-point reciprocal step (unpredicated). 8089 8090 void frecps(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 8091 8092 8093### FRECPX ### 8094 8095Floating-point reciprocal exponent (predicated). 8096 8097 void frecpx(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 8098 8099 8100### FRINTA ### 8101 8102Floating-point round to integral value (predicated). 8103 8104 void frinta(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 8105 8106 8107### FRINTI ### 8108 8109Floating-point round to integral value (predicated). 8110 8111 void frinti(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 8112 8113 8114### FRINTM ### 8115 8116Floating-point round to integral value (predicated). 8117 8118 void frintm(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 8119 8120 8121### FRINTN ### 8122 8123Floating-point round to integral value (predicated). 8124 8125 void frintn(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 8126 8127 8128### FRINTP ### 8129 8130Floating-point round to integral value (predicated). 8131 8132 void frintp(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 8133 8134 8135### FRINTX ### 8136 8137Floating-point round to integral value (predicated). 8138 8139 void frintx(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 8140 8141 8142### FRINTZ ### 8143 8144Floating-point round to integral value (predicated). 8145 8146 void frintz(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 8147 8148 8149### FRSQRTE ### 8150 8151Floating-point reciprocal square root estimate (unpredicated). 8152 8153 void frsqrte(const ZRegister& zd, const ZRegister& zn) 8154 8155 8156### FRSQRTS ### 8157 8158Floating-point reciprocal square root step (unpredicated). 8159 8160 void frsqrts(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 8161 8162 8163### FSCALE ### 8164 8165Floating-point adjust exponent by vector (predicated). 8166 8167 void fscale(const ZRegister& zd, 8168 const PRegisterM& pg, 8169 const ZRegister& zn, 8170 const ZRegister& zm) 8171 8172 8173### FSQRT ### 8174 8175Floating-point square root (predicated). 8176 8177 void fsqrt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 8178 8179 8180### FSUB ### 8181 8182Floating-point subtract immediate (predicated). 8183 8184 void fsub(const ZRegister& zd, 8185 const PRegisterM& pg, 8186 const ZRegister& zn, 8187 double imm) 8188 8189 8190### FSUB ### 8191 8192Floating-point subtract vectors (predicated). 8193 8194 void fsub(const ZRegister& zd, 8195 const PRegisterM& pg, 8196 const ZRegister& zn, 8197 const ZRegister& zm) 8198 8199 8200### FSUB ### 8201 8202Floating-point subtract vectors (unpredicated). 8203 8204 void fsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 8205 8206 8207### FSUBR ### 8208 8209Floating-point reversed subtract from immediate (predicated). 8210 8211 void fsubr(const ZRegister& zd, 8212 const PRegisterM& pg, 8213 const ZRegister& zn, 8214 double imm) 8215 8216 8217### FSUBR ### 8218 8219Floating-point reversed subtract vectors (predicated). 8220 8221 void fsubr(const ZRegister& zd, 8222 const PRegisterM& pg, 8223 const ZRegister& zn, 8224 const ZRegister& zm) 8225 8226 8227### FTMAD ### 8228 8229Floating-point trigonometric multiply-add coefficient. 8230 8231 void ftmad(const ZRegister& zd, 8232 const ZRegister& zn, 8233 const ZRegister& zm, 8234 int imm3) 8235 8236 8237### FTSMUL ### 8238 8239Floating-point trigonometric starting value. 8240 8241 void ftsmul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 8242 8243 8244### FTSSEL ### 8245 8246Floating-point trigonometric select coefficient. 8247 8248 void ftssel(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 8249 8250 8251<a id="sve-h"> 8252 8253### HISTCNT ### 8254 8255Count matching elements in vector. 8256 8257 void histcnt(const ZRegister& zd, 8258 const PRegisterZ& pg, 8259 const ZRegister& zn, 8260 const ZRegister& zm) 8261 8262 8263### HISTSEG ### 8264 8265Count matching elements in vector segments. 8266 8267 void histseg(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 8268 8269 8270<a id="sve-i"> 8271 8272### INCB ### 8273 8274Increment scalar by multiple of predicate constraint element count. 8275 8276 void incb(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1) 8277 8278 8279### INCD ### 8280 8281Increment scalar by multiple of predicate constraint element count. 8282 8283 void incd(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1) 8284 8285 8286### INCD ### 8287 8288Increment vector by multiple of predicate constraint element count. 8289 8290 void incd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 8291 8292 8293### INCH ### 8294 8295Increment scalar by multiple of predicate constraint element count. 8296 8297 void inch(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1) 8298 8299 8300### INCH ### 8301 8302Increment vector by multiple of predicate constraint element count. 8303 8304 void inch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 8305 8306 8307### INCP ### 8308 8309Increment scalar by active predicate element count. 8310 8311 void incp(const Register& rdn, const PRegisterWithLaneSize& pg) 8312 8313 8314### INCP ### 8315 8316Increment vector by active predicate element count. 8317 8318 void incp(const ZRegister& zdn, const PRegister& pg) 8319 8320 8321### INCW ### 8322 8323Increment scalar by multiple of predicate constraint element count. 8324 8325 void incw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1) 8326 8327 8328### INCW ### 8329 8330Increment vector by multiple of predicate constraint element count. 8331 8332 void incw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 8333 8334 8335### INDEX ### 8336 8337Create index starting from and incremented by general-purpose register. 8338 8339 void index(const ZRegister& zd, const Register& rn, const Register& rm) 8340 8341 8342### INDEX ### 8343 8344Create index starting from and incremented by immediate. 8345 8346 void index(const ZRegister& zd, int start, int step) 8347 8348 8349### INDEX ### 8350 8351Create index starting from general-purpose register and incremented by immediate. 8352 8353 void index(const ZRegister& zd, const Register& rn, int imm5) 8354 8355 8356### INDEX ### 8357 8358Create index starting from immediate and incremented by general-purpose register. 8359 8360 void index(const ZRegister& zd, int imm5, const Register& rm) 8361 8362 8363### INSR ### 8364 8365Insert SIMD&FP scalar register in shifted vector. 8366 8367 void insr(const ZRegister& zdn, const VRegister& vm) 8368 8369 8370### INSR ### 8371 8372Insert general-purpose register in shifted vector. 8373 8374 void insr(const ZRegister& zdn, const Register& rm) 8375 8376 8377<a id="sve-l"> 8378 8379### LASTA ### 8380 8381Extract element after last to SIMD&FP scalar register. 8382 8383 void lasta(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 8384 8385 8386### LASTA ### 8387 8388Extract element after last to general-purpose register. 8389 8390 void lasta(const Register& rd, const PRegister& pg, const ZRegister& zn) 8391 8392 8393### LASTB ### 8394 8395Extract last element to SIMD&FP scalar register. 8396 8397 void lastb(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 8398 8399 8400### LASTB ### 8401 8402Extract last element to general-purpose register. 8403 8404 void lastb(const Register& rd, const PRegister& pg, const ZRegister& zn) 8405 8406 8407### LD1B ### 8408 8409Contiguous/gather load bytes to vector. 8410 8411 void ld1b(const ZRegister& zt, 8412 const PRegisterZ& pg, 8413 const SVEMemOperand& addr) 8414 8415 8416### LD1D ### 8417 8418Contiguous/gather load doublewords to vector. 8419 8420 void ld1d(const ZRegister& zt, 8421 const PRegisterZ& pg, 8422 const SVEMemOperand& addr) 8423 8424 8425### LD1H ### 8426 8427Contiguous/gather load halfwords to vector. 8428 8429 void ld1h(const ZRegister& zt, 8430 const PRegisterZ& pg, 8431 const SVEMemOperand& addr) 8432 8433 8434### LD1RB ### 8435 8436Load and broadcast unsigned byte to vector. 8437 8438 void ld1rb(const ZRegister& zt, 8439 const PRegisterZ& pg, 8440 const SVEMemOperand& addr) 8441 8442 8443### LD1RD ### 8444 8445Load and broadcast doubleword to vector. 8446 8447 void ld1rd(const ZRegister& zt, 8448 const PRegisterZ& pg, 8449 const SVEMemOperand& addr) 8450 8451 8452### LD1RH ### 8453 8454Load and broadcast unsigned halfword to vector. 8455 8456 void ld1rh(const ZRegister& zt, 8457 const PRegisterZ& pg, 8458 const SVEMemOperand& addr) 8459 8460 8461### LD1ROB ### 8462 8463Contiguous load and replicate thirty-two bytes. 8464 8465 void ld1rob(const ZRegister& zt, 8466 const PRegisterZ& pg, 8467 const SVEMemOperand& addr) 8468 8469 8470### LD1ROD ### 8471 8472Contiguous load and replicate four doublewords. 8473 8474 void ld1rod(const ZRegister& zt, 8475 const PRegisterZ& pg, 8476 const SVEMemOperand& addr) 8477 8478 8479### LD1ROH ### 8480 8481Contiguous load and replicate sixteen halfwords. 8482 8483 void ld1roh(const ZRegister& zt, 8484 const PRegisterZ& pg, 8485 const SVEMemOperand& addr) 8486 8487 8488### LD1ROW ### 8489 8490Contiguous load and replicate eight words. 8491 8492 void ld1row(const ZRegister& zt, 8493 const PRegisterZ& pg, 8494 const SVEMemOperand& addr) 8495 8496 8497### LD1RQB ### 8498 8499Contiguous load and replicate sixteen bytes. 8500 8501 void ld1rqb(const ZRegister& zt, 8502 const PRegisterZ& pg, 8503 const SVEMemOperand& addr) 8504 8505 8506### LD1RQD ### 8507 8508Contiguous load and replicate two doublewords. 8509 8510 void ld1rqd(const ZRegister& zt, 8511 const PRegisterZ& pg, 8512 const SVEMemOperand& addr) 8513 8514 8515### LD1RQH ### 8516 8517Contiguous load and replicate eight halfwords. 8518 8519 void ld1rqh(const ZRegister& zt, 8520 const PRegisterZ& pg, 8521 const SVEMemOperand& addr) 8522 8523 8524### LD1RQW ### 8525 8526Contiguous load and replicate four words. 8527 8528 void ld1rqw(const ZRegister& zt, 8529 const PRegisterZ& pg, 8530 const SVEMemOperand& addr) 8531 8532 8533### LD1RSB ### 8534 8535Load and broadcast signed byte to vector. 8536 8537 void ld1rsb(const ZRegister& zt, 8538 const PRegisterZ& pg, 8539 const SVEMemOperand& addr) 8540 8541 8542### LD1RSH ### 8543 8544Load and broadcast signed halfword to vector. 8545 8546 void ld1rsh(const ZRegister& zt, 8547 const PRegisterZ& pg, 8548 const SVEMemOperand& addr) 8549 8550 8551### LD1RSW ### 8552 8553Load and broadcast signed word to vector. 8554 8555 void ld1rsw(const ZRegister& zt, 8556 const PRegisterZ& pg, 8557 const SVEMemOperand& addr) 8558 8559 8560### LD1RW ### 8561 8562Load and broadcast unsigned word to vector. 8563 8564 void ld1rw(const ZRegister& zt, 8565 const PRegisterZ& pg, 8566 const SVEMemOperand& addr) 8567 8568 8569### LD1SB ### 8570 8571Contiguous/gather load signed bytes to vector. 8572 8573 void ld1sb(const ZRegister& zt, 8574 const PRegisterZ& pg, 8575 const SVEMemOperand& addr) 8576 8577 8578### LD1SH ### 8579 8580Contiguous/gather load signed halfwords to vector. 8581 8582 void ld1sh(const ZRegister& zt, 8583 const PRegisterZ& pg, 8584 const SVEMemOperand& addr) 8585 8586 8587### LD1SW ### 8588 8589Contiguous/gather load signed words to vector. 8590 8591 void ld1sw(const ZRegister& zt, 8592 const PRegisterZ& pg, 8593 const SVEMemOperand& addr) 8594 8595 8596### LD1W ### 8597 8598Contiguous/gather load words to vector. 8599 8600 void ld1w(const ZRegister& zt, 8601 const PRegisterZ& pg, 8602 const SVEMemOperand& addr) 8603 8604 8605### LD2B ### 8606 8607Contiguous load two-byte structures to two vectors. 8608 8609 void ld2b(const ZRegister& zt1, 8610 const ZRegister& zt2, 8611 const PRegisterZ& pg, 8612 const SVEMemOperand& addr) 8613 8614 8615### LD2D ### 8616 8617Contiguous load two-doubleword structures to two vectors. 8618 8619 void ld2d(const ZRegister& zt1, 8620 const ZRegister& zt2, 8621 const PRegisterZ& pg, 8622 const SVEMemOperand& addr) 8623 8624 8625### LD2H ### 8626 8627Contiguous load two-halfword structures to two vectors. 8628 8629 void ld2h(const ZRegister& zt1, 8630 const ZRegister& zt2, 8631 const PRegisterZ& pg, 8632 const SVEMemOperand& addr) 8633 8634 8635### LD2W ### 8636 8637Contiguous load two-word structures to two vectors. 8638 8639 void ld2w(const ZRegister& zt1, 8640 const ZRegister& zt2, 8641 const PRegisterZ& pg, 8642 const SVEMemOperand& addr) 8643 8644 8645### LD3B ### 8646 8647Contiguous load three-byte structures to three vectors. 8648 8649 void ld3b(const ZRegister& zt1, 8650 const ZRegister& zt2, 8651 const ZRegister& zt3, 8652 const PRegisterZ& pg, 8653 const SVEMemOperand& addr) 8654 8655 8656### LD3D ### 8657 8658Contiguous load three-doubleword structures to three vectors. 8659 8660 void ld3d(const ZRegister& zt1, 8661 const ZRegister& zt2, 8662 const ZRegister& zt3, 8663 const PRegisterZ& pg, 8664 const SVEMemOperand& addr) 8665 8666 8667### LD3H ### 8668 8669Contiguous load three-halfword structures to three vectors. 8670 8671 void ld3h(const ZRegister& zt1, 8672 const ZRegister& zt2, 8673 const ZRegister& zt3, 8674 const PRegisterZ& pg, 8675 const SVEMemOperand& addr) 8676 8677 8678### LD3W ### 8679 8680Contiguous load three-word structures to three vectors. 8681 8682 void ld3w(const ZRegister& zt1, 8683 const ZRegister& zt2, 8684 const ZRegister& zt3, 8685 const PRegisterZ& pg, 8686 const SVEMemOperand& addr) 8687 8688 8689### LD4B ### 8690 8691Contiguous load four-byte structures to four vectors. 8692 8693 void ld4b(const ZRegister& zt1, 8694 const ZRegister& zt2, 8695 const ZRegister& zt3, 8696 const ZRegister& zt4, 8697 const PRegisterZ& pg, 8698 const SVEMemOperand& addr) 8699 8700 8701### LD4D ### 8702 8703Contiguous load four-doubleword structures to four vectors. 8704 8705 void ld4d(const ZRegister& zt1, 8706 const ZRegister& zt2, 8707 const ZRegister& zt3, 8708 const ZRegister& zt4, 8709 const PRegisterZ& pg, 8710 const SVEMemOperand& addr) 8711 8712 8713### LD4H ### 8714 8715Contiguous load four-halfword structures to four vectors. 8716 8717 void ld4h(const ZRegister& zt1, 8718 const ZRegister& zt2, 8719 const ZRegister& zt3, 8720 const ZRegister& zt4, 8721 const PRegisterZ& pg, 8722 const SVEMemOperand& addr) 8723 8724 8725### LD4W ### 8726 8727Contiguous load four-word structures to four vectors. 8728 8729 void ld4w(const ZRegister& zt1, 8730 const ZRegister& zt2, 8731 const ZRegister& zt3, 8732 const ZRegister& zt4, 8733 const PRegisterZ& pg, 8734 const SVEMemOperand& addr) 8735 8736 8737### LDFF1B ### 8738 8739Contiguous load first-fault unsigned bytes to vector. 8740 8741 void ldff1b(const ZRegister& zt, 8742 const PRegisterZ& pg, 8743 const SVEMemOperand& addr) 8744 8745 8746### LDFF1B ### 8747 8748Gather load first-fault unsigned bytes to vector (immediate index). 8749 8750 void ldff1b(const ZRegister& zt, 8751 const PRegisterZ& pg, 8752 const ZRegister& zn, 8753 int imm5) 8754 8755 8756### LDFF1B ### 8757 8758Gather load first-fault unsigned bytes to vector. 8759 8760 void ldff1b(const ZRegister& zt, 8761 const PRegisterZ& pg, 8762 const Register& xn, 8763 const ZRegister& zm) 8764 8765 8766### LDFF1D ### 8767 8768Contiguous load first-fault doublewords to vector. 8769 8770 void ldff1d(const ZRegister& zt, 8771 const PRegisterZ& pg, 8772 const SVEMemOperand& addr) 8773 8774 8775### LDFF1D ### 8776 8777Gather load first-fault doublewords to vector (immediate index). 8778 8779 void ldff1d(const ZRegister& zt, 8780 const PRegisterZ& pg, 8781 const ZRegister& zn, 8782 int imm5) 8783 8784 8785### LDFF1D ### 8786 8787Gather load first-fault doublewords to vector (vector index). 8788 8789 void ldff1d(const ZRegister& zt, 8790 const PRegisterZ& pg, 8791 const Register& xn, 8792 const ZRegister& zm) 8793 8794 8795### LDFF1H ### 8796 8797Contiguous load first-fault unsigned halfwords to vector. 8798 8799 void ldff1h(const ZRegister& zt, 8800 const PRegisterZ& pg, 8801 const SVEMemOperand& addr) 8802 8803 8804### LDFF1H ### 8805 8806Gather load first-fault unsigned halfwords to vector (immediate index). 8807 8808 void ldff1h(const ZRegister& zt, 8809 const PRegisterZ& pg, 8810 const ZRegister& zn, 8811 int imm5) 8812 8813 8814### LDFF1H ### 8815 8816Gather load first-fault unsigned halfwords to vector (vector index). 8817 8818 void ldff1h(const ZRegister& zt, 8819 const PRegisterZ& pg, 8820 const Register& xn, 8821 const ZRegister& zm) 8822 8823 8824### LDFF1SB ### 8825 8826Contiguous load first-fault signed bytes to vector. 8827 8828 void ldff1sb(const ZRegister& zt, 8829 const PRegisterZ& pg, 8830 const SVEMemOperand& addr) 8831 8832 8833### LDFF1SB ### 8834 8835Gather load first-fault signed bytes to vector (immediate index). 8836 8837 void ldff1sb(const ZRegister& zt, 8838 const PRegisterZ& pg, 8839 const ZRegister& zn, 8840 int imm5) 8841 8842 8843### LDFF1SB ### 8844 8845Gather load first-fault signed bytes to vector (vector index). 8846 8847 void ldff1sb(const ZRegister& zt, 8848 const PRegisterZ& pg, 8849 const Register& xn, 8850 const ZRegister& zm) 8851 8852 8853### LDFF1SH ### 8854 8855Contiguous load first-fault signed halfwords to vector. 8856 8857 void ldff1sh(const ZRegister& zt, 8858 const PRegisterZ& pg, 8859 const SVEMemOperand& addr) 8860 8861 8862### LDFF1SH ### 8863 8864Gather load first-fault signed halfwords to vector (immediate index). 8865 8866 void ldff1sh(const ZRegister& zt, 8867 const PRegisterZ& pg, 8868 const ZRegister& zn, 8869 int imm5) 8870 8871 8872### LDFF1SH ### 8873 8874Gather load first-fault signed halfwords to vector (vector index). 8875 8876 void ldff1sh(const ZRegister& zt, 8877 const PRegisterZ& pg, 8878 const Register& xn, 8879 const ZRegister& zm) 8880 8881 8882### LDFF1SW ### 8883 8884Contiguous load first-fault signed words to vector. 8885 8886 void ldff1sw(const ZRegister& zt, 8887 const PRegisterZ& pg, 8888 const SVEMemOperand& addr) 8889 8890 8891### LDFF1SW ### 8892 8893Gather load first-fault signed words to vector (immediate index). 8894 8895 void ldff1sw(const ZRegister& zt, 8896 const PRegisterZ& pg, 8897 const ZRegister& zn, 8898 int imm5) 8899 8900 8901### LDFF1SW ### 8902 8903Gather load first-fault signed words to vector (vector index). 8904 8905 void ldff1sw(const ZRegister& zt, 8906 const PRegisterZ& pg, 8907 const Register& xn, 8908 const ZRegister& zm) 8909 8910 8911### LDFF1W ### 8912 8913Contiguous load first-fault unsigned words to vector. 8914 8915 void ldff1w(const ZRegister& zt, 8916 const PRegisterZ& pg, 8917 const SVEMemOperand& addr) 8918 8919 8920### LDFF1W ### 8921 8922Gather load first-fault unsigned words to vector (immediate index). 8923 8924 void ldff1w(const ZRegister& zt, 8925 const PRegisterZ& pg, 8926 const ZRegister& zn, 8927 int imm5) 8928 8929 8930### LDFF1W ### 8931 8932Gather load first-fault unsigned words to vector (vector index). 8933 8934 void ldff1w(const ZRegister& zt, 8935 const PRegisterZ& pg, 8936 const Register& xn, 8937 const ZRegister& zm) 8938 8939 8940### LDNF1B ### 8941 8942Contiguous load non-fault unsigned bytes to vector (immediate index). 8943 8944 void ldnf1b(const ZRegister& zt, 8945 const PRegisterZ& pg, 8946 const SVEMemOperand& addr) 8947 8948 8949### LDNF1D ### 8950 8951Contiguous load non-fault doublewords to vector (immediate index). 8952 8953 void ldnf1d(const ZRegister& zt, 8954 const PRegisterZ& pg, 8955 const SVEMemOperand& addr) 8956 8957 8958### LDNF1H ### 8959 8960Contiguous load non-fault unsigned halfwords to vector (immediate index). 8961 8962 void ldnf1h(const ZRegister& zt, 8963 const PRegisterZ& pg, 8964 const SVEMemOperand& addr) 8965 8966 8967### LDNF1SB ### 8968 8969Contiguous load non-fault signed bytes to vector (immediate index). 8970 8971 void ldnf1sb(const ZRegister& zt, 8972 const PRegisterZ& pg, 8973 const SVEMemOperand& addr) 8974 8975 8976### LDNF1SH ### 8977 8978Contiguous load non-fault signed halfwords to vector (immediate index). 8979 8980 void ldnf1sh(const ZRegister& zt, 8981 const PRegisterZ& pg, 8982 const SVEMemOperand& addr) 8983 8984 8985### LDNF1SW ### 8986 8987Contiguous load non-fault signed words to vector (immediate index). 8988 8989 void ldnf1sw(const ZRegister& zt, 8990 const PRegisterZ& pg, 8991 const SVEMemOperand& addr) 8992 8993 8994### LDNF1W ### 8995 8996Contiguous load non-fault unsigned words to vector (immediate index). 8997 8998 void ldnf1w(const ZRegister& zt, 8999 const PRegisterZ& pg, 9000 const SVEMemOperand& addr) 9001 9002 9003### LDNT1B ### 9004 9005Contiguous load non-temporal bytes to vector. 9006 9007 void ldnt1b(const ZRegister& zt, 9008 const PRegisterZ& pg, 9009 const SVEMemOperand& addr) 9010 9011 9012### LDNT1D ### 9013 9014Contiguous load non-temporal doublewords to vector. 9015 9016 void ldnt1d(const ZRegister& zt, 9017 const PRegisterZ& pg, 9018 const SVEMemOperand& addr) 9019 9020 9021### LDNT1H ### 9022 9023Contiguous load non-temporal halfwords to vector. 9024 9025 void ldnt1h(const ZRegister& zt, 9026 const PRegisterZ& pg, 9027 const SVEMemOperand& addr) 9028 9029 9030### LDNT1SB ### 9031 9032Gather load non-temporal signed bytes. 9033 9034 void ldnt1sb(const ZRegister& zt, 9035 const PRegisterZ& pg, 9036 const SVEMemOperand& addr) 9037 9038 9039### LDNT1SH ### 9040 9041Gather load non-temporal signed halfwords. 9042 9043 void ldnt1sh(const ZRegister& zt, 9044 const PRegisterZ& pg, 9045 const SVEMemOperand& addr) 9046 9047 9048### LDNT1SW ### 9049 9050Gather load non-temporal signed words. 9051 9052 void ldnt1sw(const ZRegister& zt, 9053 const PRegisterZ& pg, 9054 const SVEMemOperand& addr) 9055 9056 9057### LDNT1W ### 9058 9059Contiguous load non-temporal words to vector. 9060 9061 void ldnt1w(const ZRegister& zt, 9062 const PRegisterZ& pg, 9063 const SVEMemOperand& addr) 9064 9065 9066### LDR ### 9067 9068Load SVE predicate/vector register. 9069 9070 void ldr(const CPURegister& rt, const SVEMemOperand& addr) 9071 9072 9073### LSL ### 9074 9075Logical shift left by 64-bit wide elements (predicated). 9076 9077 void lsl(const ZRegister& zd, 9078 const PRegisterM& pg, 9079 const ZRegister& zn, 9080 const ZRegister& zm) 9081 9082 9083### LSL ### 9084 9085Logical shift left by 64-bit wide elements (unpredicated). 9086 9087 void lsl(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9088 9089 9090### LSL ### 9091 9092Logical shift left by immediate (predicated). 9093 9094 void lsl(const ZRegister& zd, 9095 const PRegisterM& pg, 9096 const ZRegister& zn, 9097 int shift) 9098 9099 9100### LSL ### 9101 9102Logical shift left by immediate (unpredicated). 9103 9104 void lsl(const ZRegister& zd, const ZRegister& zn, int shift) 9105 9106 9107### LSLR ### 9108 9109Reversed logical shift left by vector (predicated). 9110 9111 void lslr(const ZRegister& zd, 9112 const PRegisterM& pg, 9113 const ZRegister& zn, 9114 const ZRegister& zm) 9115 9116 9117### LSR ### 9118 9119Logical shift right by 64-bit wide elements (predicated). 9120 9121 void lsr(const ZRegister& zd, 9122 const PRegisterM& pg, 9123 const ZRegister& zn, 9124 const ZRegister& zm) 9125 9126 9127### LSR ### 9128 9129Logical shift right by 64-bit wide elements (unpredicated). 9130 9131 void lsr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9132 9133 9134### LSR ### 9135 9136Logical shift right by immediate (predicated). 9137 9138 void lsr(const ZRegister& zd, 9139 const PRegisterM& pg, 9140 const ZRegister& zn, 9141 int shift) 9142 9143 9144### LSR ### 9145 9146Logical shift right by immediate (unpredicated). 9147 9148 void lsr(const ZRegister& zd, const ZRegister& zn, int shift) 9149 9150 9151### LSRR ### 9152 9153Reversed logical shift right by vector (predicated). 9154 9155 void lsrr(const ZRegister& zd, 9156 const PRegisterM& pg, 9157 const ZRegister& zn, 9158 const ZRegister& zm) 9159 9160 9161<a id="sve-m"> 9162 9163### MAD ### 9164 9165Multiply-add vectors (predicated), writing multiplicand [Zdn = Za + Zdn * Zm]. 9166 9167 void mad(const ZRegister& zdn, 9168 const PRegisterM& pg, 9169 const ZRegister& zm, 9170 const ZRegister& za) 9171 9172 9173### MATCH ### 9174 9175Detect any matching elements, setting the condition flags. 9176 9177 void match(const PRegisterWithLaneSize& pd, 9178 const PRegisterZ& pg, 9179 const ZRegister& zn, 9180 const ZRegister& zm) 9181 9182 9183### MLA ### 9184 9185Multiply-add to accumulator (indexed). 9186 9187 void mla(const ZRegister& zda, 9188 const ZRegister& zn, 9189 const ZRegister& zm, 9190 int index) 9191 9192 9193### MLA ### 9194 9195Multiply-add vectors (predicated), writing addend [Zda = Zda + Zn * Zm]. 9196 9197 void mla(const ZRegister& zda, 9198 const PRegisterM& pg, 9199 const ZRegister& zn, 9200 const ZRegister& zm) 9201 9202 9203### MLS ### 9204 9205Multiply-subtract from accumulator (indexed). 9206 9207 void mls(const ZRegister& zda, 9208 const ZRegister& zn, 9209 const ZRegister& zm, 9210 int index) 9211 9212 9213### MLS ### 9214 9215Multiply-subtract vectors (predicated), writing addend [Zda = Zda - Zn * Zm]. 9216 9217 void mls(const ZRegister& zda, 9218 const PRegisterM& pg, 9219 const ZRegister& zn, 9220 const ZRegister& zm) 9221 9222 9223### MOV ### 9224 9225Move SIMD&FP scalar register to vector elements (predicated) 9226 9227 void mov(const ZRegister& zd, const PRegisterM& pg, const VRegister& vn) 9228 9229 9230### MOV ### 9231 9232Move SIMD&FP scalar register to vector elements (unpredicated) 9233 9234 void mov(const ZRegister& zd, const VRegister& vn) 9235 9236 9237### MOV ### 9238 9239Move general-purpose register to vector elements (predicated) 9240 9241 void mov(const ZRegister& zd, const PRegisterM& pg, const Register& rn) 9242 9243 9244### MOV ### 9245 9246Move general-purpose register to vector elements (unpredicated) 9247 9248 void mov(const ZRegister& zd, const Register& xn) 9249 9250 9251### MOV ### 9252 9253Move indexed element to vector elements (unpredicated) 9254 9255 void mov(const ZRegister& zd, const ZRegister& zn, unsigned index) 9256 9257 9258### MOV ### 9259 9260Move logical bitmask immediate to vector (unpredicated). 9261 9262 void mov(const ZRegister& zd, uint64_t imm) 9263 9264 9265### MOV ### 9266 9267Move predicates (merging) 9268 9269 void mov(const PRegisterWithLaneSize& pd, 9270 const PRegisterM& pg, 9271 const PRegisterWithLaneSize& pn) 9272 9273 9274### MOV ### 9275 9276Move predicates (unpredicated) 9277 9278 void mov(const PRegister& pd, const PRegister& pn) 9279 9280 9281### MOV ### 9282 9283Move predicates (zeroing) 9284 9285 void mov(const PRegisterWithLaneSize& pd, 9286 const PRegisterZ& pg, 9287 const PRegisterWithLaneSize& pn) 9288 9289 9290### MOV ### 9291 9292Move signed immediate to vector elements (unpredicated). 9293 9294 void mov(const ZRegister& zd, int imm8, int shift) 9295 9296 9297### MOV ### 9298 9299Move signed integer immediate to vector elements (predicated) 9300 9301 void mov(const ZRegister& zd, const PRegister& pg, int imm8, int shift = -1) 9302 9303 9304### MOV ### 9305 9306Move vector elements (predicated) 9307 9308 void mov(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 9309 9310 9311### MOV ### 9312 9313Move vector register (unpredicated) 9314 9315 void mov(const ZRegister& zd, const ZRegister& zn) 9316 9317 9318### MOVPRFX ### 9319 9320Move prefix (predicated). 9321 9322 void movprfx(const ZRegister& zd, const PRegister& pg, const ZRegister& zn) 9323 9324 9325### MOVPRFX ### 9326 9327Move prefix (unpredicated). 9328 9329 void movprfx(const ZRegister& zd, const ZRegister& zn) 9330 9331 9332### MOVS ### 9333 9334Move predicate (unpredicated), setting the condition flags 9335 9336 void movs(const PRegister& pd, const PRegister& pn) 9337 9338 9339### MOVS ### 9340 9341Move predicates (zeroing), setting the condition flags 9342 9343 void movs(const PRegisterWithLaneSize& pd, 9344 const PRegisterZ& pg, 9345 const PRegisterWithLaneSize& pn) 9346 9347 9348### MSB ### 9349 9350Multiply-subtract vectors (predicated), writing multiplicand [Zdn = Za - Zdn * Zm]. 9351 9352 void msb(const ZRegister& zdn, 9353 const PRegisterM& pg, 9354 const ZRegister& zm, 9355 const ZRegister& za) 9356 9357 9358### MUL ### 9359 9360Multiply (indexed). 9361 9362 void mul(const ZRegister& zd, 9363 const ZRegister& zn, 9364 const ZRegister& zm, 9365 int index) 9366 9367 9368### MUL ### 9369 9370Multiply by immediate (unpredicated). 9371 9372 void mul(const ZRegister& zd, const ZRegister& zn, int imm8) 9373 9374 9375### MUL ### 9376 9377Multiply vectors (predicated). 9378 9379 void mul(const ZRegister& zd, 9380 const PRegisterM& pg, 9381 const ZRegister& zn, 9382 const ZRegister& zm) 9383 9384 9385### MUL ### 9386 9387Multiply vectors (unpredicated). 9388 9389 void mul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9390 9391 9392<a id="sve-n"> 9393 9394### NAND ### 9395 9396Bitwise NAND predicates. 9397 9398 void nand(const PRegisterWithLaneSize& pd, 9399 const PRegisterZ& pg, 9400 const PRegisterWithLaneSize& pn, 9401 const PRegisterWithLaneSize& pm) 9402 9403 9404### NANDS ### 9405 9406Bitwise NAND predicates. 9407 9408 void nands(const PRegisterWithLaneSize& pd, 9409 const PRegisterZ& pg, 9410 const PRegisterWithLaneSize& pn, 9411 const PRegisterWithLaneSize& pm) 9412 9413 9414### NBSL ### 9415 9416Bitwise inverted select. 9417 9418 void nbsl(const ZRegister& zd, 9419 const ZRegister& zn, 9420 const ZRegister& zm, 9421 const ZRegister& zk) 9422 9423 9424### NEG ### 9425 9426Negate (predicated). 9427 9428 void neg(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 9429 9430 9431### NMATCH ### 9432 9433Detect no matching elements, setting the condition flags. 9434 9435 void nmatch(const PRegisterWithLaneSize& pd, 9436 const PRegisterZ& pg, 9437 const ZRegister& zn, 9438 const ZRegister& zm) 9439 9440 9441### NOR ### 9442 9443Bitwise NOR predicates. 9444 9445 void nor(const PRegisterWithLaneSize& pd, 9446 const PRegisterZ& pg, 9447 const PRegisterWithLaneSize& pn, 9448 const PRegisterWithLaneSize& pm) 9449 9450 9451### NORS ### 9452 9453Bitwise NOR predicates. 9454 9455 void nors(const PRegisterWithLaneSize& pd, 9456 const PRegisterZ& pg, 9457 const PRegisterWithLaneSize& pn, 9458 const PRegisterWithLaneSize& pm) 9459 9460 9461### NOT ### 9462 9463Bitwise invert predicate. 9464 9465 void not_(const PRegisterWithLaneSize& pd, 9466 const PRegisterZ& pg, 9467 const PRegisterWithLaneSize& pn) 9468 9469 9470### NOT ### 9471 9472Bitwise invert vector (predicated). 9473 9474 void not_(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 9475 9476 9477### NOTS ### 9478 9479Bitwise invert predicate, setting the condition flags. 9480 9481 void nots(const PRegisterWithLaneSize& pd, 9482 const PRegisterZ& pg, 9483 const PRegisterWithLaneSize& pn) 9484 9485 9486<a id="sve-o"> 9487 9488### ORN ### 9489 9490Bitwise OR inverted predicate. 9491 9492 void orn(const PRegisterWithLaneSize& pd, 9493 const PRegisterZ& pg, 9494 const PRegisterWithLaneSize& pn, 9495 const PRegisterWithLaneSize& pm) 9496 9497 9498### ORN ### 9499 9500Bitwise OR with inverted immediate (unpredicated). 9501 9502 void orn(const ZRegister& zd, const ZRegister& zn, uint64_t imm) 9503 9504 9505### ORNS ### 9506 9507Bitwise OR inverted predicate. 9508 9509 void orns(const PRegisterWithLaneSize& pd, 9510 const PRegisterZ& pg, 9511 const PRegisterWithLaneSize& pn, 9512 const PRegisterWithLaneSize& pm) 9513 9514 9515### ORR ### 9516 9517Bitwise OR predicate. 9518 9519 void orr(const PRegisterWithLaneSize& pd, 9520 const PRegisterZ& pg, 9521 const PRegisterWithLaneSize& pn, 9522 const PRegisterWithLaneSize& pm) 9523 9524 9525### ORR ### 9526 9527Bitwise OR vectors (predicated). 9528 9529 void orr(const ZRegister& zd, 9530 const PRegisterM& pg, 9531 const ZRegister& zn, 9532 const ZRegister& zm) 9533 9534 9535### ORR ### 9536 9537Bitwise OR vectors (unpredicated). 9538 9539 void orr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9540 9541 9542### ORR ### 9543 9544Bitwise OR with immediate (unpredicated). 9545 9546 void orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm) 9547 9548 9549### ORRS ### 9550 9551Bitwise OR predicate. 9552 9553 void orrs(const PRegisterWithLaneSize& pd, 9554 const PRegisterZ& pg, 9555 const PRegisterWithLaneSize& pn, 9556 const PRegisterWithLaneSize& pm) 9557 9558 9559### ORV ### 9560 9561Bitwise OR reduction to scalar. 9562 9563 void orv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 9564 9565 9566<a id="sve-p"> 9567 9568### PFALSE ### 9569 9570Set all predicate elements to false. 9571 9572 void pfalse(const PRegisterWithLaneSize& pd) 9573 9574 9575### PFIRST ### 9576 9577Set the first active predicate element to true. 9578 9579 void pfirst(const PRegisterWithLaneSize& pd, 9580 const PRegister& pg, 9581 const PRegisterWithLaneSize& pn) 9582 9583 9584### PMUL ### 9585 9586Polynomial multiply vectors (unpredicated). 9587 9588 void pmul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9589 9590 9591### PMULLB ### 9592 9593Polynomial multiply long (bottom). 9594 9595 void pmullb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9596 9597 9598### PMULLT ### 9599 9600Polynomial multiply long (top). 9601 9602 void pmullt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9603 9604 9605### PNEXT ### 9606 9607Find next active predicate. 9608 9609 void pnext(const PRegisterWithLaneSize& pd, 9610 const PRegister& pg, 9611 const PRegisterWithLaneSize& pn) 9612 9613 9614### PRFB ### 9615 9616Prefetch bytes. 9617 9618 void prfb(PrefetchOperation prfop, 9619 const PRegister& pg, 9620 const SVEMemOperand& addr) 9621 9622 9623### PRFD ### 9624 9625Prefetch doublewords. 9626 9627 void prfd(PrefetchOperation prfop, 9628 const PRegister& pg, 9629 const SVEMemOperand& addr) 9630 9631 9632### PRFH ### 9633 9634Prefetch halfwords. 9635 9636 void prfh(PrefetchOperation prfop, 9637 const PRegister& pg, 9638 const SVEMemOperand& addr) 9639 9640 9641### PRFW ### 9642 9643Prefetch words. 9644 9645 void prfw(PrefetchOperation prfop, 9646 const PRegister& pg, 9647 const SVEMemOperand& addr) 9648 9649 9650### PTEST ### 9651 9652Set condition flags for predicate. 9653 9654 void ptest(const PRegister& pg, const PRegisterWithLaneSize& pn) 9655 9656 9657### PTRUE ### 9658 9659Initialise predicate from named constraint. 9660 9661 void ptrue(const PRegisterWithLaneSize& pd, int pattern = SVE_ALL) 9662 9663 9664### PTRUES ### 9665 9666Initialise predicate from named constraint. 9667 9668 void ptrues(const PRegisterWithLaneSize& pd, int pattern = SVE_ALL) 9669 9670 9671### PUNPKHI ### 9672 9673Unpack and widen half of predicate. 9674 9675 void punpkhi(const PRegisterWithLaneSize& pd, 9676 const PRegisterWithLaneSize& pn) 9677 9678 9679### PUNPKLO ### 9680 9681Unpack and widen half of predicate. 9682 9683 void punpklo(const PRegisterWithLaneSize& pd, 9684 const PRegisterWithLaneSize& pn) 9685 9686 9687<a id="sve-r"> 9688 9689### RADDHNB ### 9690 9691Rounding add narrow high part (bottom). 9692 9693 void raddhnb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9694 9695 9696### RADDHNT ### 9697 9698Rounding add narrow high part (top). 9699 9700 void raddhnt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9701 9702 9703### RBIT ### 9704 9705Reverse bits (predicated). 9706 9707 void rbit(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 9708 9709 9710### RDFFR ### 9711 9712Read the first-fault register. 9713 9714 void rdffr(const PRegisterWithLaneSize& pd) 9715 9716 9717### RDFFR ### 9718 9719Return predicate of succesfully loaded elements. 9720 9721 void rdffr(const PRegisterWithLaneSize& pd, const PRegisterZ& pg) 9722 9723 9724### RDFFRS ### 9725 9726Return predicate of succesfully loaded elements. 9727 9728 void rdffrs(const PRegisterWithLaneSize& pd, const PRegisterZ& pg) 9729 9730 9731### RDVL ### 9732 9733Read multiple of vector register size to scalar register. 9734 9735 void rdvl(const Register& xd, int imm6) 9736 9737 9738### REV ### 9739 9740Reverse all elements in a predicate. 9741 9742 void rev(const PRegisterWithLaneSize& pd, const PRegisterWithLaneSize& pn) 9743 9744 9745### REV ### 9746 9747Reverse all elements in a vector (unpredicated). 9748 9749 void rev(const ZRegister& zd, const ZRegister& zn) 9750 9751 9752### REVB ### 9753 9754Reverse bytes / halfwords / words within elements (predicated). 9755 9756 void revb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 9757 9758 9759### REVH ### 9760 9761Reverse bytes / halfwords / words within elements (predicated). 9762 9763 void revh(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 9764 9765 9766### REVW ### 9767 9768Reverse bytes / halfwords / words within elements (predicated). 9769 9770 void revw(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 9771 9772 9773### RSHRNB ### 9774 9775Rounding shift right narrow by immediate (bottom). 9776 9777 void rshrnb(const ZRegister& zd, const ZRegister& zn, int shift) 9778 9779 9780### RSHRNT ### 9781 9782Rounding shift right narrow by immediate (top). 9783 9784 void rshrnt(const ZRegister& zd, const ZRegister& zn, int shift) 9785 9786 9787### RSUBHNB ### 9788 9789Rounding subtract narrow high part (bottom). 9790 9791 void rsubhnb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9792 9793 9794### RSUBHNT ### 9795 9796Rounding subtract narrow high part (top). 9797 9798 void rsubhnt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9799 9800 9801<a id="sve-s"> 9802 9803### SABA ### 9804 9805Signed absolute difference and accumulate. 9806 9807 void saba(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 9808 9809 9810### SABALB ### 9811 9812Signed absolute difference and accumulate long (bottom). 9813 9814 void sabalb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 9815 9816 9817### SABALT ### 9818 9819Signed absolute difference and accumulate long (top). 9820 9821 void sabalt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 9822 9823 9824### SABD ### 9825 9826Signed absolute difference (predicated). 9827 9828 void sabd(const ZRegister& zd, 9829 const PRegisterM& pg, 9830 const ZRegister& zn, 9831 const ZRegister& zm) 9832 9833 9834### SABDLB ### 9835 9836Signed absolute difference long (bottom). 9837 9838 void sabdlb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9839 9840 9841### SABDLT ### 9842 9843Signed absolute difference long (top). 9844 9845 void sabdlt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9846 9847 9848### SADALP ### 9849 9850Signed add and accumulate long pairwise. 9851 9852 void sadalp(const ZRegister& zda, const PRegisterM& pg, const ZRegister& zn) 9853 9854 9855### SADDLB ### 9856 9857Signed add long (bottom). 9858 9859 void saddlb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9860 9861 9862### SADDLBT ### 9863 9864Signed add long (bottom + top). 9865 9866 void saddlbt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9867 9868 9869### SADDLT ### 9870 9871Signed add long (top). 9872 9873 void saddlt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9874 9875 9876### SADDV ### 9877 9878Signed add reduction to scalar. 9879 9880 void saddv(const VRegister& dd, const PRegister& pg, const ZRegister& zn) 9881 9882 9883### SADDWB ### 9884 9885Signed add wide (bottom). 9886 9887 void saddwb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9888 9889 9890### SADDWT ### 9891 9892Signed add wide (top). 9893 9894 void saddwt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 9895 9896 9897### SBCLB ### 9898 9899Subtract with carry long (bottom). 9900 9901 void sbclb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 9902 9903 9904### SBCLT ### 9905 9906Subtract with carry long (top). 9907 9908 void sbclt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 9909 9910 9911### SCVTF ### 9912 9913Signed integer convert to floating-point (predicated). 9914 9915 void scvtf(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 9916 9917 9918### SDIV ### 9919 9920Signed divide (predicated). 9921 9922 void sdiv(const ZRegister& zd, 9923 const PRegisterM& pg, 9924 const ZRegister& zn, 9925 const ZRegister& zm) 9926 9927 9928### SDIVR ### 9929 9930Signed reversed divide (predicated). 9931 9932 void sdivr(const ZRegister& zd, 9933 const PRegisterM& pg, 9934 const ZRegister& zn, 9935 const ZRegister& zm) 9936 9937 9938### SDOT ### 9939 9940Signed dot product by indexed quadtuplet. 9941 9942 void sdot(const ZRegister& zda, 9943 const ZRegister& zn, 9944 const ZRegister& zm, 9945 int index) 9946 9947 9948### SDOT ### 9949 9950Signed dot product. 9951 9952 void sdot(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 9953 9954 9955### SEL ### 9956 9957Conditionally select elements from two predicates. 9958 9959 void sel(const PRegisterWithLaneSize& pd, 9960 const PRegister& pg, 9961 const PRegisterWithLaneSize& pn, 9962 const PRegisterWithLaneSize& pm) 9963 9964 9965### SEL ### 9966 9967Conditionally select elements from two vectors. 9968 9969 void sel(const ZRegister& zd, 9970 const PRegister& pg, 9971 const ZRegister& zn, 9972 const ZRegister& zm) 9973 9974 9975### SETFFR ### 9976 9977Initialise the first-fault register to all true. 9978 9979 void setffr() 9980 9981 9982### SHADD ### 9983 9984Signed halving addition. 9985 9986 void shadd(const ZRegister& zd, 9987 const PRegisterM& pg, 9988 const ZRegister& zn, 9989 const ZRegister& zm) 9990 9991 9992### SHRNB ### 9993 9994Shift right narrow by immediate (bottom). 9995 9996 void shrnb(const ZRegister& zd, const ZRegister& zn, int shift) 9997 9998 9999### SHRNT ### 10000 10001Shift right narrow by immediate (top). 10002 10003 void shrnt(const ZRegister& zd, const ZRegister& zn, int shift) 10004 10005 10006### SHSUB ### 10007 10008Signed halving subtract. 10009 10010 void shsub(const ZRegister& zd, 10011 const PRegisterM& pg, 10012 const ZRegister& zn, 10013 const ZRegister& zm) 10014 10015 10016### SHSUBR ### 10017 10018Signed halving subtract reversed vectors. 10019 10020 void shsubr(const ZRegister& zd, 10021 const PRegisterM& pg, 10022 const ZRegister& zn, 10023 const ZRegister& zm) 10024 10025 10026### SLI ### 10027 10028Shift left and insert (immediate). 10029 10030 void sli(const ZRegister& zd, const ZRegister& zn, int shift) 10031 10032 10033### SMAX ### 10034 10035Signed maximum vectors (predicated). 10036 10037 void smax(const ZRegister& zd, 10038 const PRegisterM& pg, 10039 const ZRegister& zn, 10040 const ZRegister& zm) 10041 10042 10043### SMAX ### 10044 10045Signed maximum with immediate (unpredicated). 10046 10047 void smax(const ZRegister& zd, const ZRegister& zn, int imm8) 10048 10049 10050### SMAXP ### 10051 10052Signed maximum pairwise. 10053 10054 void smaxp(const ZRegister& zd, 10055 const PRegisterM& pg, 10056 const ZRegister& zn, 10057 const ZRegister& zm) 10058 10059 10060### SMAXV ### 10061 10062Signed maximum reduction to scalar. 10063 10064 void smaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 10065 10066 10067### SMIN ### 10068 10069Signed minimum vectors (predicated). 10070 10071 void smin(const ZRegister& zd, 10072 const PRegisterM& pg, 10073 const ZRegister& zn, 10074 const ZRegister& zm) 10075 10076 10077### SMIN ### 10078 10079Signed minimum with immediate (unpredicated). 10080 10081 void smin(const ZRegister& zd, const ZRegister& zn, int imm8) 10082 10083 10084### SMINP ### 10085 10086Signed minimum pairwise. 10087 10088 void sminp(const ZRegister& zd, 10089 const PRegisterM& pg, 10090 const ZRegister& zn, 10091 const ZRegister& zm) 10092 10093 10094### SMINV ### 10095 10096Signed minimum reduction to scalar. 10097 10098 void sminv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 10099 10100 10101### SMLALB ### 10102 10103Signed multiply-add long to accumulator (bottom). 10104 10105 void smlalb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10106 10107 10108### SMLALB ### 10109 10110Signed multiply-add long to accumulator (bottom, indexed). 10111 10112 void smlalb(const ZRegister& zda, 10113 const ZRegister& zn, 10114 const ZRegister& zm, 10115 int index) 10116 10117 10118### SMLALT ### 10119 10120Signed multiply-add long to accumulator (top). 10121 10122 void smlalt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10123 10124 10125### SMLALT ### 10126 10127Signed multiply-add long to accumulator (top, indexed). 10128 10129 void smlalt(const ZRegister& zda, 10130 const ZRegister& zn, 10131 const ZRegister& zm, 10132 int index) 10133 10134 10135### SMLSLB ### 10136 10137Signed multiply-subtract long from accumulator (bottom). 10138 10139 void smlslb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10140 10141 10142### SMLSLB ### 10143 10144Signed multiply-subtract long from accumulator (bottom, indexed). 10145 10146 void smlslb(const ZRegister& zda, 10147 const ZRegister& zn, 10148 const ZRegister& zm, 10149 int index) 10150 10151 10152### SMLSLT ### 10153 10154Signed multiply-subtract long from accumulator (top). 10155 10156 void smlslt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10157 10158 10159### SMLSLT ### 10160 10161Signed multiply-subtract long from accumulator (top, indexed). 10162 10163 void smlslt(const ZRegister& zda, 10164 const ZRegister& zn, 10165 const ZRegister& zm, 10166 int index) 10167 10168 10169### SMMLA ### 10170 10171Signed integer matrix multiply-accumulate. 10172 10173 void smmla(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10174 10175 10176### SMULH ### 10177 10178Signed multiply returning high half (predicated). 10179 10180 void smulh(const ZRegister& zd, 10181 const PRegisterM& pg, 10182 const ZRegister& zn, 10183 const ZRegister& zm) 10184 10185 10186### SMULH ### 10187 10188Signed multiply returning high half (unpredicated). 10189 10190 void smulh(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10191 10192 10193### SMULLB ### 10194 10195Signed multiply long (bottom). 10196 10197 void smullb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10198 10199 10200### SMULLB ### 10201 10202Signed multiply long (bottom, indexed). 10203 10204 void smullb(const ZRegister& zd, 10205 const ZRegister& zn, 10206 const ZRegister& zm, 10207 int index) 10208 10209 10210### SMULLT ### 10211 10212Signed multiply long (top). 10213 10214 void smullt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10215 10216 10217### SMULLT ### 10218 10219Signed multiply long (top, indexed). 10220 10221 void smullt(const ZRegister& zd, 10222 const ZRegister& zn, 10223 const ZRegister& zm, 10224 int index) 10225 10226 10227### SPLICE ### 10228 10229Splice two vectors under predicate control. 10230 10231 void splice(const ZRegister& zd, 10232 const PRegister& pg, 10233 const ZRegister& zn, 10234 const ZRegister& zm) 10235 10236 10237### SQABS ### 10238 10239Signed saturating absolute value. 10240 10241 void sqabs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 10242 10243 10244### SQADD ### 10245 10246Signed saturating add immediate (unpredicated). 10247 10248 void sqadd(const ZRegister& zd, 10249 const ZRegister& zn, 10250 int imm8, 10251 int shift = -1) 10252 10253 10254### SQADD ### 10255 10256Signed saturating add vectors (unpredicated). 10257 10258 void sqadd(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10259 10260 10261### SQADD ### 10262 10263Signed saturating addition (predicated). 10264 10265 void sqadd(const ZRegister& zd, 10266 const PRegisterM& pg, 10267 const ZRegister& zn, 10268 const ZRegister& zm) 10269 10270 10271### SQCADD ### 10272 10273Saturating complex integer add with rotate. 10274 10275 void sqcadd(const ZRegister& zd, 10276 const ZRegister& zn, 10277 const ZRegister& zm, 10278 int rot) 10279 10280 10281### SQDECB ### 10282 10283Signed saturating decrement scalar by multiple of 8-bit predicate constraint element count. 10284 10285 void sqdecb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 10286 10287 10288### SQDECB ### 10289 10290Signed saturating decrement scalar by multiple of 8-bit predicate constraint element count. 10291 10292 void sqdecb(const Register& xd, 10293 const Register& wn, 10294 int pattern, 10295 int multiplier) 10296 10297 10298### SQDECD ### 10299 10300Signed saturating decrement scalar by multiple of 64-bit predicate constraint element count. 10301 10302 void sqdecd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 10303 10304 10305### SQDECD ### 10306 10307Signed saturating decrement scalar by multiple of 64-bit predicate constraint element count. 10308 10309 void sqdecd(const Register& xd, 10310 const Register& wn, 10311 int pattern = SVE_ALL, 10312 int multiplier = 1) 10313 10314 10315### SQDECD ### 10316 10317Signed saturating decrement vector by multiple of 64-bit predicate constraint element count. 10318 10319 void sqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 10320 10321 10322### SQDECH ### 10323 10324Signed saturating decrement scalar by multiple of 16-bit predicate constraint element count. 10325 10326 void sqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 10327 10328 10329### SQDECH ### 10330 10331Signed saturating decrement scalar by multiple of 16-bit predicate constraint element count. 10332 10333 void sqdech(const Register& xd, 10334 const Register& wn, 10335 int pattern = SVE_ALL, 10336 int multiplier = 1) 10337 10338 10339### SQDECH ### 10340 10341Signed saturating decrement vector by multiple of 16-bit predicate constraint element count. 10342 10343 void sqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 10344 10345 10346### SQDECP ### 10347 10348Signed saturating decrement scalar by active predicate element count. 10349 10350 void sqdecp(const Register& xd, 10351 const PRegisterWithLaneSize& pg, 10352 const Register& wn) 10353 10354 10355### SQDECP ### 10356 10357Signed saturating decrement scalar by active predicate element count. 10358 10359 void sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg) 10360 10361 10362### SQDECP ### 10363 10364Signed saturating decrement vector by active predicate element count. 10365 10366 void sqdecp(const ZRegister& zdn, const PRegister& pg) 10367 10368 10369### SQDECW ### 10370 10371Signed saturating decrement scalar by multiple of 32-bit predicate constraint element count. 10372 10373 void sqdecw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 10374 10375 10376### SQDECW ### 10377 10378Signed saturating decrement scalar by multiple of 32-bit predicate constraint element count. 10379 10380 void sqdecw(const Register& xd, 10381 const Register& wn, 10382 int pattern = SVE_ALL, 10383 int multiplier = 1) 10384 10385 10386### SQDECW ### 10387 10388Signed saturating decrement vector by multiple of 32-bit predicate constraint element count. 10389 10390 void sqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 10391 10392 10393### SQDMLALB ### 10394 10395Signed saturating doubling multiply-add long to accumulator (bottom). 10396 10397 void sqdmlalb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10398 10399 10400### SQDMLALB ### 10401 10402Signed saturating doubling multiply-add long to accumulator (bottom, indexed). 10403 10404 void sqdmlalb(const ZRegister& zda, 10405 const ZRegister& zn, 10406 const ZRegister& zm, 10407 int index) 10408 10409 10410### SQDMLALBT ### 10411 10412Signed saturating doubling multiply-add long to accumulator (bottom x top). 10413 10414 void sqdmlalbt(const ZRegister& zda, 10415 const ZRegister& zn, 10416 const ZRegister& zm) 10417 10418 10419### SQDMLALT ### 10420 10421Signed saturating doubling multiply-add long to accumulator (top). 10422 10423 void sqdmlalt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10424 10425 10426### SQDMLALT ### 10427 10428Signed saturating doubling multiply-add long to accumulator (top, indexed). 10429 10430 void sqdmlalt(const ZRegister& zda, 10431 const ZRegister& zn, 10432 const ZRegister& zm, 10433 int index) 10434 10435 10436### SQDMLSLB ### 10437 10438Signed saturating doubling multiply-subtract long from accumulator (bottom). 10439 10440 void sqdmlslb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10441 10442 10443### SQDMLSLB ### 10444 10445Signed saturating doubling multiply-subtract long from accumulator (bottom, indexed). 10446 10447 void sqdmlslb(const ZRegister& zda, 10448 const ZRegister& zn, 10449 const ZRegister& zm, 10450 int index) 10451 10452 10453### SQDMLSLBT ### 10454 10455Signed saturating doubling multiply-subtract long from accumulator (bottom x top). 10456 10457 void sqdmlslbt(const ZRegister& zda, 10458 const ZRegister& zn, 10459 const ZRegister& zm) 10460 10461 10462### SQDMLSLT ### 10463 10464Signed saturating doubling multiply-subtract long from accumulator (top). 10465 10466 void sqdmlslt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10467 10468 10469### SQDMLSLT ### 10470 10471Signed saturating doubling multiply-subtract long from accumulator (top, indexed). 10472 10473 void sqdmlslt(const ZRegister& zda, 10474 const ZRegister& zn, 10475 const ZRegister& zm, 10476 int index) 10477 10478 10479### SQDMULH ### 10480 10481Signed saturating doubling multiply high (indexed). 10482 10483 void sqdmulh(const ZRegister& zd, 10484 const ZRegister& zn, 10485 const ZRegister& zm, 10486 int index) 10487 10488 10489### SQDMULH ### 10490 10491Signed saturating doubling multiply high (unpredicated). 10492 10493 void sqdmulh(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10494 10495 10496### SQDMULLB ### 10497 10498Signed saturating doubling multiply long (bottom). 10499 10500 void sqdmullb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10501 10502 10503### SQDMULLB ### 10504 10505Signed saturating doubling multiply long (bottom, indexed). 10506 10507 void sqdmullb(const ZRegister& zd, 10508 const ZRegister& zn, 10509 const ZRegister& zm, 10510 int index) 10511 10512 10513### SQDMULLT ### 10514 10515Signed saturating doubling multiply long (top). 10516 10517 void sqdmullt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10518 10519 10520### SQDMULLT ### 10521 10522Signed saturating doubling multiply long (top, indexed). 10523 10524 void sqdmullt(const ZRegister& zd, 10525 const ZRegister& zn, 10526 const ZRegister& zm, 10527 int index) 10528 10529 10530### SQINCB ### 10531 10532Signed saturating increment scalar by multiple of 8-bit predicate constraint element count. 10533 10534 void sqincb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 10535 10536 10537### SQINCB ### 10538 10539Signed saturating increment scalar by multiple of 8-bit predicate constraint element count. 10540 10541 void sqincb(const Register& xd, 10542 const Register& wn, 10543 int pattern = SVE_ALL, 10544 int multiplier = 1) 10545 10546 10547### SQINCD ### 10548 10549Signed saturating increment scalar by multiple of 64-bit predicate constraint element count. 10550 10551 void sqincd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 10552 10553 10554### SQINCD ### 10555 10556Signed saturating increment scalar by multiple of 64-bit predicate constraint element count. 10557 10558 void sqincd(const Register& xd, 10559 const Register& wn, 10560 int pattern, 10561 int multiplier) 10562 10563 10564### SQINCD ### 10565 10566Signed saturating increment vector by multiple of 64-bit predicate constraint element count. 10567 10568 void sqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 10569 10570 10571### SQINCH ### 10572 10573Signed saturating increment scalar by multiple of 16-bit predicate constraint element count. 10574 10575 void sqinch(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 10576 10577 10578### SQINCH ### 10579 10580Signed saturating increment scalar by multiple of 16-bit predicate constraint element count. 10581 10582 void sqinch(const Register& xd, 10583 const Register& wn, 10584 int pattern = SVE_ALL, 10585 int multiplier = 1) 10586 10587 10588### SQINCH ### 10589 10590Signed saturating increment vector by multiple of 16-bit predicate constraint element count. 10591 10592 void sqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 10593 10594 10595### SQINCP ### 10596 10597Signed saturating increment scalar by active predicate element count. 10598 10599 void sqincp(const Register& xd, 10600 const PRegisterWithLaneSize& pg, 10601 const Register& wn) 10602 10603 10604### SQINCP ### 10605 10606Signed saturating increment scalar by active predicate element count. 10607 10608 void sqincp(const Register& xdn, const PRegisterWithLaneSize& pg) 10609 10610 10611### SQINCP ### 10612 10613Signed saturating increment vector by active predicate element count. 10614 10615 void sqincp(const ZRegister& zdn, const PRegister& pg) 10616 10617 10618### SQINCW ### 10619 10620Signed saturating increment scalar by multiple of 32-bit predicate constraint element count. 10621 10622 void sqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 10623 10624 10625### SQINCW ### 10626 10627Signed saturating increment scalar by multiple of 32-bit predicate constraint element count. 10628 10629 void sqincw(const Register& xd, 10630 const Register& wn, 10631 int pattern = SVE_ALL, 10632 int multiplier = 1) 10633 10634 10635### SQINCW ### 10636 10637Signed saturating increment vector by multiple of 32-bit predicate constraint element count. 10638 10639 void sqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 10640 10641 10642### SQNEG ### 10643 10644Signed saturating negate. 10645 10646 void sqneg(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 10647 10648 10649### SQRDCMLAH ### 10650 10651Saturating rounding doubling complex integer multiply-add high with rotate (indexed). 10652 10653 void sqrdcmlah(const ZRegister& zda, 10654 const ZRegister& zn, 10655 const ZRegister& zm, 10656 int index, 10657 int rot) 10658 10659 10660### SQRDCMLAH ### 10661 10662Saturating rounding doubling complex integer multiply-add high with rotate. 10663 10664 void sqrdcmlah(const ZRegister& zda, 10665 const ZRegister& zn, 10666 const ZRegister& zm, 10667 int rot) 10668 10669 10670### SQRDMLAH ### 10671 10672Signed saturating rounding doubling multiply-add high to accumulator (indexed). 10673 10674 void sqrdmlah(const ZRegister& zda, 10675 const ZRegister& zn, 10676 const ZRegister& zm, 10677 int index) 10678 10679 10680### SQRDMLAH ### 10681 10682Signed saturating rounding doubling multiply-add high to accumulator (unpredicated). 10683 10684 void sqrdmlah(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10685 10686 10687### SQRDMLSH ### 10688 10689Signed saturating rounding doubling multiply-subtract high from accumulator (indexed). 10690 10691 void sqrdmlsh(const ZRegister& zda, 10692 const ZRegister& zn, 10693 const ZRegister& zm, 10694 int index) 10695 10696 10697### SQRDMLSH ### 10698 10699Signed saturating rounding doubling multiply-subtract high from accumulator (unpredicated). 10700 10701 void sqrdmlsh(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 10702 10703 10704### SQRDMULH ### 10705 10706Signed saturating rounding doubling multiply high (indexed). 10707 10708 void sqrdmulh(const ZRegister& zd, 10709 const ZRegister& zn, 10710 const ZRegister& zm, 10711 int index) 10712 10713 10714### SQRDMULH ### 10715 10716Signed saturating rounding doubling multiply high (unpredicated). 10717 10718 void sqrdmulh(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10719 10720 10721### SQRSHL ### 10722 10723Signed saturating rounding shift left by vector (predicated). 10724 10725 void sqrshl(const ZRegister& zd, 10726 const PRegisterM& pg, 10727 const ZRegister& zn, 10728 const ZRegister& zm) 10729 10730 10731### SQRSHLR ### 10732 10733Signed saturating rounding shift left reversed vectors (predicated). 10734 10735 void sqrshlr(const ZRegister& zd, 10736 const PRegisterM& pg, 10737 const ZRegister& zn, 10738 const ZRegister& zm) 10739 10740 10741### SQRSHRNB ### 10742 10743Signed saturating rounding shift right narrow by immediate (bottom). 10744 10745 void sqrshrnb(const ZRegister& zd, const ZRegister& zn, int shift) 10746 10747 10748### SQRSHRNT ### 10749 10750Signed saturating rounding shift right narrow by immediate (top). 10751 10752 void sqrshrnt(const ZRegister& zd, const ZRegister& zn, int shift) 10753 10754 10755### SQRSHRUNB ### 10756 10757Signed saturating rounding shift right unsigned narrow by immediate (bottom). 10758 10759 void sqrshrunb(const ZRegister& zd, const ZRegister& zn, int shift) 10760 10761 10762### SQRSHRUNT ### 10763 10764Signed saturating rounding shift right unsigned narrow by immediate (top). 10765 10766 void sqrshrunt(const ZRegister& zd, const ZRegister& zn, int shift) 10767 10768 10769### SQSHL ### 10770 10771Signed saturating shift left by immediate. 10772 10773 void sqshl(const ZRegister& zd, 10774 const PRegisterM& pg, 10775 const ZRegister& zn, 10776 int shift) 10777 10778 10779### SQSHL ### 10780 10781Signed saturating shift left by vector (predicated). 10782 10783 void sqshl(const ZRegister& zd, 10784 const PRegisterM& pg, 10785 const ZRegister& zn, 10786 const ZRegister& zm) 10787 10788 10789### SQSHLR ### 10790 10791Signed saturating shift left reversed vectors (predicated). 10792 10793 void sqshlr(const ZRegister& zd, 10794 const PRegisterM& pg, 10795 const ZRegister& zn, 10796 const ZRegister& zm) 10797 10798 10799### SQSHLU ### 10800 10801Signed saturating shift left unsigned by immediate. 10802 10803 void sqshlu(const ZRegister& zd, 10804 const PRegisterM& pg, 10805 const ZRegister& zn, 10806 int shift) 10807 10808 10809### SQSHRNB ### 10810 10811Signed saturating shift right narrow by immediate (bottom). 10812 10813 void sqshrnb(const ZRegister& zd, const ZRegister& zn, int shift) 10814 10815 10816### SQSHRNT ### 10817 10818Signed saturating shift right narrow by immediate (top). 10819 10820 void sqshrnt(const ZRegister& zd, const ZRegister& zn, int shift) 10821 10822 10823### SQSHRUNB ### 10824 10825Signed saturating shift right unsigned narrow by immediate (bottom). 10826 10827 void sqshrunb(const ZRegister& zd, const ZRegister& zn, int shift) 10828 10829 10830### SQSHRUNT ### 10831 10832Signed saturating shift right unsigned narrow by immediate (top). 10833 10834 void sqshrunt(const ZRegister& zd, const ZRegister& zn, int shift) 10835 10836 10837### SQSUB ### 10838 10839Signed saturating subtract immediate (unpredicated). 10840 10841 void sqsub(const ZRegister& zd, 10842 const ZRegister& zn, 10843 int imm8, 10844 int shift = -1) 10845 10846 10847### SQSUB ### 10848 10849Signed saturating subtract vectors (unpredicated). 10850 10851 void sqsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10852 10853 10854### SQSUB ### 10855 10856Signed saturating subtraction (predicated). 10857 10858 void sqsub(const ZRegister& zd, 10859 const PRegisterM& pg, 10860 const ZRegister& zn, 10861 const ZRegister& zm) 10862 10863 10864### SQSUBR ### 10865 10866Signed saturating subtraction reversed vectors (predicated). 10867 10868 void sqsubr(const ZRegister& zd, 10869 const PRegisterM& pg, 10870 const ZRegister& zn, 10871 const ZRegister& zm) 10872 10873 10874### SQXTNB ### 10875 10876Signed saturating extract narrow (bottom). 10877 10878 void sqxtnb(const ZRegister& zd, const ZRegister& zn) 10879 10880 10881### SQXTNT ### 10882 10883Signed saturating extract narrow (top). 10884 10885 void sqxtnt(const ZRegister& zd, const ZRegister& zn) 10886 10887 10888### SQXTUNB ### 10889 10890Signed saturating unsigned extract narrow (bottom). 10891 10892 void sqxtunb(const ZRegister& zd, const ZRegister& zn) 10893 10894 10895### SQXTUNT ### 10896 10897Signed saturating unsigned extract narrow (top). 10898 10899 void sqxtunt(const ZRegister& zd, const ZRegister& zn) 10900 10901 10902### SRHADD ### 10903 10904Signed rounding halving addition. 10905 10906 void srhadd(const ZRegister& zd, 10907 const PRegisterM& pg, 10908 const ZRegister& zn, 10909 const ZRegister& zm) 10910 10911 10912### SRI ### 10913 10914Shift right and insert (immediate). 10915 10916 void sri(const ZRegister& zd, const ZRegister& zn, int shift) 10917 10918 10919### SRSHL ### 10920 10921Signed rounding shift left by vector (predicated). 10922 10923 void srshl(const ZRegister& zd, 10924 const PRegisterM& pg, 10925 const ZRegister& zn, 10926 const ZRegister& zm) 10927 10928 10929### SRSHLR ### 10930 10931Signed rounding shift left reversed vectors (predicated). 10932 10933 void srshlr(const ZRegister& zd, 10934 const PRegisterM& pg, 10935 const ZRegister& zn, 10936 const ZRegister& zm) 10937 10938 10939### SRSHR ### 10940 10941Signed rounding shift right by immediate. 10942 10943 void srshr(const ZRegister& zd, 10944 const PRegisterM& pg, 10945 const ZRegister& zn, 10946 int shift) 10947 10948 10949### SRSRA ### 10950 10951Signed rounding shift right and accumulate (immediate). 10952 10953 void srsra(const ZRegister& zda, const ZRegister& zn, int shift) 10954 10955 10956### SSHLLB ### 10957 10958Signed shift left long by immediate (bottom). 10959 10960 void sshllb(const ZRegister& zd, const ZRegister& zn, int shift) 10961 10962 10963### SSHLLT ### 10964 10965Signed shift left long by immediate (top). 10966 10967 void sshllt(const ZRegister& zd, const ZRegister& zn, int shift) 10968 10969 10970### SSRA ### 10971 10972Signed shift right and accumulate (immediate). 10973 10974 void ssra(const ZRegister& zda, const ZRegister& zn, int shift) 10975 10976 10977### SSUBLB ### 10978 10979Signed subtract long (bottom). 10980 10981 void ssublb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10982 10983 10984### SSUBLBT ### 10985 10986Signed subtract long (bottom - top). 10987 10988 void ssublbt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10989 10990 10991### SSUBLT ### 10992 10993Signed subtract long (top). 10994 10995 void ssublt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 10996 10997 10998### SSUBLTB ### 10999 11000Signed subtract long (top - bottom). 11001 11002 void ssubltb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11003 11004 11005### SSUBWB ### 11006 11007Signed subtract wide (bottom). 11008 11009 void ssubwb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11010 11011 11012### SSUBWT ### 11013 11014Signed subtract wide (top). 11015 11016 void ssubwt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11017 11018 11019### ST1B ### 11020 11021Contiguous/scatter store bytes from vector. 11022 11023 void st1b(const ZRegister& zt, 11024 const PRegister& pg, 11025 const SVEMemOperand& addr) 11026 11027 11028### ST1D ### 11029 11030Contiguous/scatter store doublewords from vector. 11031 11032 void st1d(const ZRegister& zt, 11033 const PRegister& pg, 11034 const SVEMemOperand& addr) 11035 11036 11037### ST1H ### 11038 11039Contiguous/scatter store halfwords from vector. 11040 11041 void st1h(const ZRegister& zt, 11042 const PRegister& pg, 11043 const SVEMemOperand& addr) 11044 11045 11046### ST1W ### 11047 11048Contiguous/scatter store words from vector. 11049 11050 void st1w(const ZRegister& zt, 11051 const PRegister& pg, 11052 const SVEMemOperand& addr) 11053 11054 11055### ST2B ### 11056 11057Contiguous store two-byte structures from two vectors. 11058 11059 void st2b(const ZRegister& zt1, 11060 const ZRegister& zt2, 11061 const PRegister& pg, 11062 const SVEMemOperand& addr) 11063 11064 11065### ST2D ### 11066 11067Contiguous store two-doubleword structures from two vectors, 11068 11069 void st2d(const ZRegister& zt1, 11070 const ZRegister& zt2, 11071 const PRegister& pg, 11072 const SVEMemOperand& addr) 11073 11074 11075### ST2H ### 11076 11077Contiguous store two-halfword structures from two vectors. 11078 11079 void st2h(const ZRegister& zt1, 11080 const ZRegister& zt2, 11081 const PRegister& pg, 11082 const SVEMemOperand& addr) 11083 11084 11085### ST2W ### 11086 11087Contiguous store two-word structures from two vectors. 11088 11089 void st2w(const ZRegister& zt1, 11090 const ZRegister& zt2, 11091 const PRegister& pg, 11092 const SVEMemOperand& addr) 11093 11094 11095### ST3B ### 11096 11097Contiguous store three-byte structures from three vectors. 11098 11099 void st3b(const ZRegister& zt1, 11100 const ZRegister& zt2, 11101 const ZRegister& zt3, 11102 const PRegister& pg, 11103 const SVEMemOperand& addr) 11104 11105 11106### ST3D ### 11107 11108Contiguous store three-doubleword structures from three vectors. 11109 11110 void st3d(const ZRegister& zt1, 11111 const ZRegister& zt2, 11112 const ZRegister& zt3, 11113 const PRegister& pg, 11114 const SVEMemOperand& addr) 11115 11116 11117### ST3H ### 11118 11119Contiguous store three-halfword structures from three vectors. 11120 11121 void st3h(const ZRegister& zt1, 11122 const ZRegister& zt2, 11123 const ZRegister& zt3, 11124 const PRegister& pg, 11125 const SVEMemOperand& addr) 11126 11127 11128### ST3W ### 11129 11130Contiguous store three-word structures from three vectors. 11131 11132 void st3w(const ZRegister& zt1, 11133 const ZRegister& zt2, 11134 const ZRegister& zt3, 11135 const PRegister& pg, 11136 const SVEMemOperand& addr) 11137 11138 11139### ST4B ### 11140 11141Contiguous store four-byte structures from four vectors. 11142 11143 void st4b(const ZRegister& zt1, 11144 const ZRegister& zt2, 11145 const ZRegister& zt3, 11146 const ZRegister& zt4, 11147 const PRegister& pg, 11148 const SVEMemOperand& addr) 11149 11150 11151### ST4D ### 11152 11153Contiguous store four-doubleword structures from four vectors. 11154 11155 void st4d(const ZRegister& zt1, 11156 const ZRegister& zt2, 11157 const ZRegister& zt3, 11158 const ZRegister& zt4, 11159 const PRegister& pg, 11160 const SVEMemOperand& addr) 11161 11162 11163### ST4H ### 11164 11165Contiguous store four-halfword structures from four vectors. 11166 11167 void st4h(const ZRegister& zt1, 11168 const ZRegister& zt2, 11169 const ZRegister& zt3, 11170 const ZRegister& zt4, 11171 const PRegister& pg, 11172 const SVEMemOperand& addr) 11173 11174 11175### ST4W ### 11176 11177Contiguous store four-word structures from four vectors. 11178 11179 void st4w(const ZRegister& zt1, 11180 const ZRegister& zt2, 11181 const ZRegister& zt3, 11182 const ZRegister& zt4, 11183 const PRegister& pg, 11184 const SVEMemOperand& addr) 11185 11186 11187### STNT1B ### 11188 11189Contiguous store non-temporal bytes from vector. 11190 11191 void stnt1b(const ZRegister& zt, 11192 const PRegister& pg, 11193 const SVEMemOperand& addr) 11194 11195 11196### STNT1D ### 11197 11198Contiguous store non-temporal doublewords from vector. 11199 11200 void stnt1d(const ZRegister& zt, 11201 const PRegister& pg, 11202 const SVEMemOperand& addr) 11203 11204 11205### STNT1H ### 11206 11207Contiguous store non-temporal halfwords from vector. 11208 11209 void stnt1h(const ZRegister& zt, 11210 const PRegister& pg, 11211 const SVEMemOperand& addr) 11212 11213 11214### STNT1W ### 11215 11216Contiguous store non-temporal words from vector. 11217 11218 void stnt1w(const ZRegister& zt, 11219 const PRegister& pg, 11220 const SVEMemOperand& addr) 11221 11222 11223### STR ### 11224 11225Store SVE predicate/vector register. 11226 11227 void str(const CPURegister& rt, const SVEMemOperand& addr) 11228 11229 11230### SUB ### 11231 11232Subtract immediate (unpredicated). 11233 11234 void sub(const ZRegister& zd, const ZRegister& zn, int imm8, int shift = -1) 11235 11236 11237### SUB ### 11238 11239Subtract vectors (predicated). 11240 11241 void sub(const ZRegister& zd, 11242 const PRegisterM& pg, 11243 const ZRegister& zn, 11244 const ZRegister& zm) 11245 11246 11247### SUB ### 11248 11249Subtract vectors (unpredicated). 11250 11251 void sub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11252 11253 11254### SUBHNB ### 11255 11256Subtract narrow high part (bottom). 11257 11258 void subhnb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11259 11260 11261### SUBHNT ### 11262 11263Subtract narrow high part (top). 11264 11265 void subhnt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11266 11267 11268### SUBR ### 11269 11270Reversed subtract from immediate (unpredicated). 11271 11272 void subr(const ZRegister& zd, const ZRegister& zn, int imm8, int shift = -1) 11273 11274 11275### SUBR ### 11276 11277Reversed subtract vectors (predicated). 11278 11279 void subr(const ZRegister& zd, 11280 const PRegisterM& pg, 11281 const ZRegister& zn, 11282 const ZRegister& zm) 11283 11284 11285### SUDOT ### 11286 11287Signed by unsigned integer indexed dot product. 11288 11289 void sudot(const ZRegister& zda, 11290 const ZRegister& zn, 11291 const ZRegister& zm, 11292 int index) 11293 11294 11295### SUNPKHI ### 11296 11297Signed unpack and extend half of vector. 11298 11299 void sunpkhi(const ZRegister& zd, const ZRegister& zn) 11300 11301 11302### SUNPKLO ### 11303 11304Signed unpack and extend half of vector. 11305 11306 void sunpklo(const ZRegister& zd, const ZRegister& zn) 11307 11308 11309### SUQADD ### 11310 11311Signed saturating addition of unsigned value. 11312 11313 void suqadd(const ZRegister& zd, 11314 const PRegisterM& pg, 11315 const ZRegister& zn, 11316 const ZRegister& zm) 11317 11318 11319### SXTB ### 11320 11321Signed byte extend (predicated). 11322 11323 void sxtb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 11324 11325 11326### SXTH ### 11327 11328Signed halfword extend (predicated). 11329 11330 void sxth(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 11331 11332 11333### SXTW ### 11334 11335Signed word extend (predicated). 11336 11337 void sxtw(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 11338 11339 11340<a id="sve-t"> 11341 11342### TBL ### 11343 11344Programmable table lookup in one or two vector table (zeroing). 11345 11346 void tbl(const ZRegister& zd, 11347 const ZRegister& zn1, 11348 const ZRegister& zn2, 11349 const ZRegister& zm) 11350 11351 11352### TBL ### 11353 11354Programmable table lookup/permute using vector of indices into a vector. 11355 11356 void tbl(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11357 11358 11359### TBX ### 11360 11361Programmable table lookup in single vector table (merging). 11362 11363 void tbx(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11364 11365 11366### TRN1 ### 11367 11368Interleave even or odd elements from two predicates. 11369 11370 void trn1(const PRegisterWithLaneSize& pd, 11371 const PRegisterWithLaneSize& pn, 11372 const PRegisterWithLaneSize& pm) 11373 11374 11375### TRN1 ### 11376 11377Interleave even or odd elements from two vectors. 11378 11379 void trn1(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11380 11381 11382### TRN2 ### 11383 11384Interleave even or odd elements from two predicates. 11385 11386 void trn2(const PRegisterWithLaneSize& pd, 11387 const PRegisterWithLaneSize& pn, 11388 const PRegisterWithLaneSize& pm) 11389 11390 11391### TRN2 ### 11392 11393Interleave even or odd elements from two vectors. 11394 11395 void trn2(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11396 11397 11398<a id="sve-u"> 11399 11400### UABA ### 11401 11402Unsigned absolute difference and accumulate. 11403 11404 void uaba(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 11405 11406 11407### UABALB ### 11408 11409Unsigned absolute difference and accumulate long (bottom). 11410 11411 void uabalb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 11412 11413 11414### UABALT ### 11415 11416Unsigned absolute difference and accumulate long (top). 11417 11418 void uabalt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 11419 11420 11421### UABD ### 11422 11423Unsigned absolute difference (predicated). 11424 11425 void uabd(const ZRegister& zd, 11426 const PRegisterM& pg, 11427 const ZRegister& zn, 11428 const ZRegister& zm) 11429 11430 11431### UABDLB ### 11432 11433Unsigned absolute difference long (bottom). 11434 11435 void uabdlb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11436 11437 11438### UABDLT ### 11439 11440Unsigned absolute difference long (top). 11441 11442 void uabdlt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11443 11444 11445### UADALP ### 11446 11447Unsigned add and accumulate long pairwise. 11448 11449 void uadalp(const ZRegister& zda, const PRegisterM& pg, const ZRegister& zn) 11450 11451 11452### UADDLB ### 11453 11454Unsigned add long (bottom). 11455 11456 void uaddlb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11457 11458 11459### UADDLT ### 11460 11461Unsigned add long (top). 11462 11463 void uaddlt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11464 11465 11466### UADDV ### 11467 11468Unsigned add reduction to scalar. 11469 11470 void uaddv(const VRegister& dd, const PRegister& pg, const ZRegister& zn) 11471 11472 11473### UADDWB ### 11474 11475Unsigned add wide (bottom). 11476 11477 void uaddwb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11478 11479 11480### UADDWT ### 11481 11482Unsigned add wide (top). 11483 11484 void uaddwt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11485 11486 11487### UCVTF ### 11488 11489Unsigned integer convert to floating-point (predicated). 11490 11491 void ucvtf(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 11492 11493 11494### UDIV ### 11495 11496Unsigned divide (predicated). 11497 11498 void udiv(const ZRegister& zd, 11499 const PRegisterM& pg, 11500 const ZRegister& zn, 11501 const ZRegister& zm) 11502 11503 11504### UDIVR ### 11505 11506Unsigned reversed divide (predicated). 11507 11508 void udivr(const ZRegister& zd, 11509 const PRegisterM& pg, 11510 const ZRegister& zn, 11511 const ZRegister& zm) 11512 11513 11514### UDOT ### 11515 11516Unsigned dot product by indexed quadtuplet. 11517 11518 void udot(const ZRegister& zda, 11519 const ZRegister& zn, 11520 const ZRegister& zm, 11521 int index) 11522 11523 11524### UDOT ### 11525 11526Unsigned dot product. 11527 11528 void udot(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 11529 11530 11531### UHADD ### 11532 11533Unsigned halving addition. 11534 11535 void uhadd(const ZRegister& zd, 11536 const PRegisterM& pg, 11537 const ZRegister& zn, 11538 const ZRegister& zm) 11539 11540 11541### UHSUB ### 11542 11543Unsigned halving subtract. 11544 11545 void uhsub(const ZRegister& zd, 11546 const PRegisterM& pg, 11547 const ZRegister& zn, 11548 const ZRegister& zm) 11549 11550 11551### UHSUBR ### 11552 11553Unsigned halving subtract reversed vectors. 11554 11555 void uhsubr(const ZRegister& zd, 11556 const PRegisterM& pg, 11557 const ZRegister& zn, 11558 const ZRegister& zm) 11559 11560 11561### UMAX ### 11562 11563Unsigned maximum vectors (predicated). 11564 11565 void umax(const ZRegister& zd, 11566 const PRegisterM& pg, 11567 const ZRegister& zn, 11568 const ZRegister& zm) 11569 11570 11571### UMAX ### 11572 11573Unsigned maximum with immediate (unpredicated). 11574 11575 void umax(const ZRegister& zd, const ZRegister& zn, int imm8) 11576 11577 11578### UMAXP ### 11579 11580Unsigned maximum pairwise. 11581 11582 void umaxp(const ZRegister& zd, 11583 const PRegisterM& pg, 11584 const ZRegister& zn, 11585 const ZRegister& zm) 11586 11587 11588### UMAXV ### 11589 11590Unsigned maximum reduction to scalar. 11591 11592 void umaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 11593 11594 11595### UMIN ### 11596 11597Unsigned minimum vectors (predicated). 11598 11599 void umin(const ZRegister& zd, 11600 const PRegisterM& pg, 11601 const ZRegister& zn, 11602 const ZRegister& zm) 11603 11604 11605### UMIN ### 11606 11607Unsigned minimum with immediate (unpredicated). 11608 11609 void umin(const ZRegister& zd, const ZRegister& zn, int imm8) 11610 11611 11612### UMINP ### 11613 11614Unsigned minimum pairwise. 11615 11616 void uminp(const ZRegister& zd, 11617 const PRegisterM& pg, 11618 const ZRegister& zn, 11619 const ZRegister& zm) 11620 11621 11622### UMINV ### 11623 11624Unsigned minimum reduction to scalar. 11625 11626 void uminv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) 11627 11628 11629### UMLALB ### 11630 11631Unsigned multiply-add long to accumulator (bottom). 11632 11633 void umlalb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 11634 11635 11636### UMLALB ### 11637 11638Unsigned multiply-add long to accumulator (bottom, indexed). 11639 11640 void umlalb(const ZRegister& zda, 11641 const ZRegister& zn, 11642 const ZRegister& zm, 11643 int index) 11644 11645 11646### UMLALT ### 11647 11648Unsigned multiply-add long to accumulator (top). 11649 11650 void umlalt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 11651 11652 11653### UMLALT ### 11654 11655Unsigned multiply-add long to accumulator (top, indexed). 11656 11657 void umlalt(const ZRegister& zda, 11658 const ZRegister& zn, 11659 const ZRegister& zm, 11660 int index) 11661 11662 11663### UMLSLB ### 11664 11665Unsigned multiply-subtract long from accumulator (bottom). 11666 11667 void umlslb(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 11668 11669 11670### UMLSLB ### 11671 11672Unsigned multiply-subtract long from accumulator (bottom, indexed). 11673 11674 void umlslb(const ZRegister& zda, 11675 const ZRegister& zn, 11676 const ZRegister& zm, 11677 int index) 11678 11679 11680### UMLSLT ### 11681 11682Unsigned multiply-subtract long from accumulator (top). 11683 11684 void umlslt(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 11685 11686 11687### UMLSLT ### 11688 11689Unsigned multiply-subtract long from accumulator (top, indexed). 11690 11691 void umlslt(const ZRegister& zda, 11692 const ZRegister& zn, 11693 const ZRegister& zm, 11694 int index) 11695 11696 11697### UMMLA ### 11698 11699Unsigned integer matrix multiply-accumulate. 11700 11701 void ummla(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 11702 11703 11704### UMULH ### 11705 11706Unsigned multiply returning high half (predicated). 11707 11708 void umulh(const ZRegister& zd, 11709 const PRegisterM& pg, 11710 const ZRegister& zn, 11711 const ZRegister& zm) 11712 11713 11714### UMULH ### 11715 11716Unsigned multiply returning high half (unpredicated). 11717 11718 void umulh(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11719 11720 11721### UMULLB ### 11722 11723Unsigned multiply long (bottom). 11724 11725 void umullb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11726 11727 11728### UMULLB ### 11729 11730Unsigned multiply long (bottom, indexed). 11731 11732 void umullb(const ZRegister& zd, 11733 const ZRegister& zn, 11734 const ZRegister& zm, 11735 int index) 11736 11737 11738### UMULLT ### 11739 11740Unsigned multiply long (top). 11741 11742 void umullt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11743 11744 11745### UMULLT ### 11746 11747Unsigned multiply long (top, indexed). 11748 11749 void umullt(const ZRegister& zd, 11750 const ZRegister& zn, 11751 const ZRegister& zm, 11752 int index) 11753 11754 11755### UQADD ### 11756 11757Unsigned saturating add immediate (unpredicated). 11758 11759 void uqadd(const ZRegister& zd, 11760 const ZRegister& zn, 11761 int imm8, 11762 int shift = -1) 11763 11764 11765### UQADD ### 11766 11767Unsigned saturating add vectors (unpredicated). 11768 11769 void uqadd(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 11770 11771 11772### UQADD ### 11773 11774Unsigned saturating addition (predicated). 11775 11776 void uqadd(const ZRegister& zd, 11777 const PRegisterM& pg, 11778 const ZRegister& zn, 11779 const ZRegister& zm) 11780 11781 11782### UQDECB ### 11783 11784Unsigned saturating decrement scalar by multiple of 8-bit predicate constraint element count. 11785 11786 void uqdecb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 11787 11788 11789### UQDECD ### 11790 11791Unsigned saturating decrement scalar by multiple of 64-bit predicate constraint element count. 11792 11793 void uqdecd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 11794 11795 11796### UQDECD ### 11797 11798Unsigned saturating decrement vector by multiple of 64-bit predicate constraint element count. 11799 11800 void uqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 11801 11802 11803### UQDECH ### 11804 11805Unsigned saturating decrement scalar by multiple of 16-bit predicate constraint element count. 11806 11807 void uqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 11808 11809 11810### UQDECH ### 11811 11812Unsigned saturating decrement vector by multiple of 16-bit predicate constraint element count. 11813 11814 void uqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 11815 11816 11817### UQDECP ### 11818 11819Unsigned saturating decrement scalar by active predicate element count. 11820 11821 void uqdecp(const Register& rdn, const PRegisterWithLaneSize& pg) 11822 11823 11824### UQDECP ### 11825 11826Unsigned saturating decrement vector by active predicate element count. 11827 11828 void uqdecp(const ZRegister& zdn, const PRegister& pg) 11829 11830 11831### UQDECW ### 11832 11833Unsigned saturating decrement scalar by multiple of 32-bit predicate constraint element count. 11834 11835 void uqdecw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 11836 11837 11838### UQDECW ### 11839 11840Unsigned saturating decrement vector by multiple of 32-bit predicate constraint element count. 11841 11842 void uqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 11843 11844 11845### UQINCB ### 11846 11847Unsigned saturating increment scalar by multiple of 8-bit predicate constraint element count. 11848 11849 void uqincb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 11850 11851 11852### UQINCD ### 11853 11854Unsigned saturating increment scalar by multiple of 64-bit predicate constraint element count. 11855 11856 void uqincd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 11857 11858 11859### UQINCD ### 11860 11861Unsigned saturating increment vector by multiple of 64-bit predicate constraint element count. 11862 11863 void uqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 11864 11865 11866### UQINCH ### 11867 11868Unsigned saturating increment scalar by multiple of 16-bit predicate constraint element count. 11869 11870 void uqinch(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 11871 11872 11873### UQINCH ### 11874 11875Unsigned saturating increment vector by multiple of 16-bit predicate constraint element count. 11876 11877 void uqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 11878 11879 11880### UQINCP ### 11881 11882Unsigned saturating increment scalar by active predicate element count. 11883 11884 void uqincp(const Register& rdn, const PRegisterWithLaneSize& pg) 11885 11886 11887### UQINCP ### 11888 11889Unsigned saturating increment vector by active predicate element count. 11890 11891 void uqincp(const ZRegister& zdn, const PRegister& pg) 11892 11893 11894### UQINCW ### 11895 11896Unsigned saturating increment scalar by multiple of 32-bit predicate constraint element count. 11897 11898 void uqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) 11899 11900 11901### UQINCW ### 11902 11903Unsigned saturating increment vector by multiple of 32-bit predicate constraint element count. 11904 11905 void uqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) 11906 11907 11908### UQRSHL ### 11909 11910Unsigned saturating rounding shift left by vector (predicated). 11911 11912 void uqrshl(const ZRegister& zd, 11913 const PRegisterM& pg, 11914 const ZRegister& zn, 11915 const ZRegister& zm) 11916 11917 11918### UQRSHLR ### 11919 11920Unsigned saturating rounding shift left reversed vectors (predicated). 11921 11922 void uqrshlr(const ZRegister& zd, 11923 const PRegisterM& pg, 11924 const ZRegister& zn, 11925 const ZRegister& zm) 11926 11927 11928### UQRSHRNB ### 11929 11930Unsigned saturating rounding shift right narrow by immediate (bottom). 11931 11932 void uqrshrnb(const ZRegister& zd, const ZRegister& zn, int shift) 11933 11934 11935### UQRSHRNT ### 11936 11937Unsigned saturating rounding shift right narrow by immediate (top). 11938 11939 void uqrshrnt(const ZRegister& zd, const ZRegister& zn, int shift) 11940 11941 11942### UQSHL ### 11943 11944Unsigned saturating shift left by immediate. 11945 11946 void uqshl(const ZRegister& zd, 11947 const PRegisterM& pg, 11948 const ZRegister& zn, 11949 int shift) 11950 11951 11952### UQSHL ### 11953 11954Unsigned saturating shift left by vector (predicated). 11955 11956 void uqshl(const ZRegister& zd, 11957 const PRegisterM& pg, 11958 const ZRegister& zn, 11959 const ZRegister& zm) 11960 11961 11962### UQSHLR ### 11963 11964Unsigned saturating shift left reversed vectors (predicated). 11965 11966 void uqshlr(const ZRegister& zd, 11967 const PRegisterM& pg, 11968 const ZRegister& zn, 11969 const ZRegister& zm) 11970 11971 11972### UQSHRNB ### 11973 11974Unsigned saturating shift right narrow by immediate (bottom). 11975 11976 void uqshrnb(const ZRegister& zd, const ZRegister& zn, int shift) 11977 11978 11979### UQSHRNT ### 11980 11981Unsigned saturating shift right narrow by immediate (top). 11982 11983 void uqshrnt(const ZRegister& zd, const ZRegister& zn, int shift) 11984 11985 11986### UQSUB ### 11987 11988Unsigned saturating subtract immediate (unpredicated). 11989 11990 void uqsub(const ZRegister& zd, 11991 const ZRegister& zn, 11992 int imm8, 11993 int shift = -1) 11994 11995 11996### UQSUB ### 11997 11998Unsigned saturating subtract vectors (unpredicated). 11999 12000 void uqsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 12001 12002 12003### UQSUB ### 12004 12005Unsigned saturating subtraction (predicated). 12006 12007 void uqsub(const ZRegister& zd, 12008 const PRegisterM& pg, 12009 const ZRegister& zn, 12010 const ZRegister& zm) 12011 12012 12013### UQSUBR ### 12014 12015Unsigned saturating subtraction reversed vectors (predicated). 12016 12017 void uqsubr(const ZRegister& zd, 12018 const PRegisterM& pg, 12019 const ZRegister& zn, 12020 const ZRegister& zm) 12021 12022 12023### UQXTNB ### 12024 12025Unsigned saturating extract narrow (bottom). 12026 12027 void uqxtnb(const ZRegister& zd, const ZRegister& zn) 12028 12029 12030### UQXTNT ### 12031 12032Unsigned saturating extract narrow (top). 12033 12034 void uqxtnt(const ZRegister& zd, const ZRegister& zn) 12035 12036 12037### URECPE ### 12038 12039Unsigned reciprocal estimate (predicated). 12040 12041 void urecpe(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 12042 12043 12044### URHADD ### 12045 12046Unsigned rounding halving addition. 12047 12048 void urhadd(const ZRegister& zd, 12049 const PRegisterM& pg, 12050 const ZRegister& zn, 12051 const ZRegister& zm) 12052 12053 12054### URSHL ### 12055 12056Unsigned rounding shift left by vector (predicated). 12057 12058 void urshl(const ZRegister& zd, 12059 const PRegisterM& pg, 12060 const ZRegister& zn, 12061 const ZRegister& zm) 12062 12063 12064### URSHLR ### 12065 12066Unsigned rounding shift left reversed vectors (predicated). 12067 12068 void urshlr(const ZRegister& zd, 12069 const PRegisterM& pg, 12070 const ZRegister& zn, 12071 const ZRegister& zm) 12072 12073 12074### URSHR ### 12075 12076Unsigned rounding shift right by immediate. 12077 12078 void urshr(const ZRegister& zd, 12079 const PRegisterM& pg, 12080 const ZRegister& zn, 12081 int shift) 12082 12083 12084### URSQRTE ### 12085 12086Unsigned reciprocal square root estimate (predicated). 12087 12088 void ursqrte(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 12089 12090 12091### URSRA ### 12092 12093Unsigned rounding shift right and accumulate (immediate). 12094 12095 void ursra(const ZRegister& zda, const ZRegister& zn, int shift) 12096 12097 12098### USDOT ### 12099 12100Unsigned by signed integer dot product. 12101 12102 void usdot(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 12103 12104 12105### USDOT ### 12106 12107Unsigned by signed integer indexed dot product. 12108 12109 void usdot(const ZRegister& zda, 12110 const ZRegister& zn, 12111 const ZRegister& zm, 12112 int index) 12113 12114 12115### USHLLB ### 12116 12117Unsigned shift left long by immediate (bottom). 12118 12119 void ushllb(const ZRegister& zd, const ZRegister& zn, int shift) 12120 12121 12122### USHLLT ### 12123 12124Unsigned shift left long by immediate (top). 12125 12126 void ushllt(const ZRegister& zd, const ZRegister& zn, int shift) 12127 12128 12129### USMMLA ### 12130 12131Unsigned by signed integer matrix multiply-accumulate. 12132 12133 void usmmla(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm) 12134 12135 12136### USQADD ### 12137 12138Unsigned saturating addition of signed value. 12139 12140 void usqadd(const ZRegister& zd, 12141 const PRegisterM& pg, 12142 const ZRegister& zn, 12143 const ZRegister& zm) 12144 12145 12146### USRA ### 12147 12148Unsigned shift right and accumulate (immediate). 12149 12150 void usra(const ZRegister& zda, const ZRegister& zn, int shift) 12151 12152 12153### USUBLB ### 12154 12155Unsigned subtract long (bottom). 12156 12157 void usublb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 12158 12159 12160### USUBLT ### 12161 12162Unsigned subtract long (top). 12163 12164 void usublt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 12165 12166 12167### USUBWB ### 12168 12169Unsigned subtract wide (bottom). 12170 12171 void usubwb(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 12172 12173 12174### USUBWT ### 12175 12176Unsigned subtract wide (top). 12177 12178 void usubwt(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 12179 12180 12181### UUNPKHI ### 12182 12183Unsigned unpack and extend half of vector. 12184 12185 void uunpkhi(const ZRegister& zd, const ZRegister& zn) 12186 12187 12188### UUNPKLO ### 12189 12190Unsigned unpack and extend half of vector. 12191 12192 void uunpklo(const ZRegister& zd, const ZRegister& zn) 12193 12194 12195### UXTB ### 12196 12197Unsigned byte extend (predicated). 12198 12199 void uxtb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 12200 12201 12202### UXTH ### 12203 12204Unsigned halfword extend (predicated). 12205 12206 void uxth(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 12207 12208 12209### UXTW ### 12210 12211Unsigned word extend (predicated). 12212 12213 void uxtw(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) 12214 12215 12216### UZP1 ### 12217 12218Concatenate even or odd elements from two predicates. 12219 12220 void uzp1(const PRegisterWithLaneSize& pd, 12221 const PRegisterWithLaneSize& pn, 12222 const PRegisterWithLaneSize& pm) 12223 12224 12225### UZP1 ### 12226 12227Concatenate even or odd elements from two vectors. 12228 12229 void uzp1(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 12230 12231 12232### UZP2 ### 12233 12234Concatenate even or odd elements from two predicates. 12235 12236 void uzp2(const PRegisterWithLaneSize& pd, 12237 const PRegisterWithLaneSize& pn, 12238 const PRegisterWithLaneSize& pm) 12239 12240 12241### UZP2 ### 12242 12243Concatenate even or odd elements from two vectors. 12244 12245 void uzp2(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 12246 12247 12248<a id="sve-w"> 12249 12250### WHILEGE ### 12251 12252While decrementing signed scalar greater than or equal to scalar. 12253 12254 void whilege(const PRegisterWithLaneSize& pd, 12255 const Register& rn, 12256 const Register& rm) 12257 12258 12259### WHILEGT ### 12260 12261While decrementing signed scalar greater than scalar. 12262 12263 void whilegt(const PRegisterWithLaneSize& pd, 12264 const Register& rn, 12265 const Register& rm) 12266 12267 12268### WHILEHI ### 12269 12270While decrementing unsigned scalar higher than scalar. 12271 12272 void whilehi(const PRegisterWithLaneSize& pd, 12273 const Register& rn, 12274 const Register& rm) 12275 12276 12277### WHILEHS ### 12278 12279While decrementing unsigned scalar higher or same as scalar. 12280 12281 void whilehs(const PRegisterWithLaneSize& pd, 12282 const Register& rn, 12283 const Register& rm) 12284 12285 12286### WHILELE ### 12287 12288While incrementing signed scalar less than or equal to scalar. 12289 12290 void whilele(const PRegisterWithLaneSize& pd, 12291 const Register& rn, 12292 const Register& rm) 12293 12294 12295### WHILELO ### 12296 12297While incrementing unsigned scalar lower than scalar. 12298 12299 void whilelo(const PRegisterWithLaneSize& pd, 12300 const Register& rn, 12301 const Register& rm) 12302 12303 12304### WHILELS ### 12305 12306While incrementing unsigned scalar lower or same as scalar. 12307 12308 void whilels(const PRegisterWithLaneSize& pd, 12309 const Register& rn, 12310 const Register& rm) 12311 12312 12313### WHILELT ### 12314 12315While incrementing signed scalar less than scalar. 12316 12317 void whilelt(const PRegisterWithLaneSize& pd, 12318 const Register& rn, 12319 const Register& rm) 12320 12321 12322### WHILERW ### 12323 12324While free of read-after-write conflicts. 12325 12326 void whilerw(const PRegisterWithLaneSize& pd, 12327 const Register& rn, 12328 const Register& rm) 12329 12330 12331### WHILEWR ### 12332 12333While free of write-after-read/write conflicts. 12334 12335 void whilewr(const PRegisterWithLaneSize& pd, 12336 const Register& rn, 12337 const Register& rm) 12338 12339 12340### WRFFR ### 12341 12342Write the first-fault register. 12343 12344 void wrffr(const PRegisterWithLaneSize& pn) 12345 12346 12347<a id="sve-x"> 12348 12349### XAR ### 12350 12351Bitwise exclusive OR and rotate right by immediate. 12352 12353 void xar(const ZRegister& zd, 12354 const ZRegister& zn, 12355 const ZRegister& zm, 12356 int shift) 12357 12358 12359<a id="sve-z"> 12360 12361### ZIP1 ### 12362 12363Interleave elements from two half predicates. 12364 12365 void zip1(const PRegisterWithLaneSize& pd, 12366 const PRegisterWithLaneSize& pn, 12367 const PRegisterWithLaneSize& pm) 12368 12369 12370### ZIP1 ### 12371 12372Interleave elements from two half vectors. 12373 12374 void zip1(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 12375 12376 12377### ZIP2 ### 12378 12379Interleave elements from two half predicates. 12380 12381 void zip2(const PRegisterWithLaneSize& pd, 12382 const PRegisterWithLaneSize& pn, 12383 const PRegisterWithLaneSize& pm) 12384 12385 12386### ZIP2 ### 12387 12388Interleave elements from two half vectors. 12389 12390 void zip2(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) 12391 12392 12393 12394Additional or pseudo instructions 12395--------------------------------- 12396 12397<a id="pseudo-b"> 12398 12399### BIND ### 12400 12401Bind a label to the current PC. 12402 12403 void bind(Label* label) 12404 12405 12406<a id="pseudo-d"> 12407 12408### DC ### 12409 12410Emit data in the instruction stream. 12411 12412 void dc(T data) 12413 12414 12415### DC32 ### 12416 12417Emit 32 bits of data into the instruction stream. 12418 12419 void dc32(uint32_t data) 12420 12421 12422### DC64 ### 12423 12424Emit 64 bits of data into the instruction stream. 12425 12426 void dc64(uint64_t data) 12427 12428 12429### DCI ### 12430 12431Emit raw instructions into the instruction stream. 12432 12433 void dci(Instr raw_inst) 12434 12435 12436<a id="pseudo-p"> 12437 12438### PLACE ### 12439 12440Place a literal at the current PC. 12441 12442 void place(RawLiteral* literal) 12443 12444 12445 12446