| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FixupLEAs.cpp | 577 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
615 unsigned NewOpc = in processInstrForSlow3OpLEA() local
621 unsigned NewOpc = getADDriFromLEA(MI.getOpcode(), Offset); in processInstrForSlow3OpLEA() local
648 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
670 unsigned NewOpc = getADDrrFromLEA(MI.getOpcode()); in processInstrForSlow3OpLEA() local
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| D | X86EvexToVex.cpp | 147 static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) { in performCustomAdjustments()
259 unsigned NewOpc = I->VexOpcode; in CompressEvexToVexImpl() local
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| D | X86MCInstLower.cpp | 502 unsigned NewOpc; in Lower() local
527 unsigned NewOpc; in Lower() local
570 unsigned NewOpc; in Lower() local
642 unsigned NewOpc; in Lower() local
806 unsigned NewOpc; in Lower() local
831 unsigned NewOpc; in Lower() local
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| D | X86ISelDAGToDAG.cpp | 830 unsigned NewOpc; in PreprocessISelDAG() local
863 unsigned NewOpc; in PreprocessISelDAG() local
886 unsigned NewOpc = N->getOpcode() == ISD::ANY_EXTEND in PreprocessISelDAG() local
1260 unsigned NewOpc; in PostprocessISelDAG() local
1301 unsigned NewOpc; in PostprocessISelDAG() local
3076 unsigned NewOpc = SelectOpcode(X86::NEG64m, X86::NEG32m, X86::NEG16m, in foldLoadStoreIntoMemOperand() local
3091 unsigned NewOpc = in foldLoadStoreIntoMemOperand() local
3181 unsigned NewOpc = SelectRegOpcode(Opc); in foldLoadStoreIntoMemOperand() local
3586 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; in matchBEXTRFromAndImm() local
3602 unsigned NewOpc = NVT == MVT::i64 ? X86::MOV32ri64 : X86::MOV32ri; in matchBEXTRFromAndImm() local
[all …]
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| D | X86InstructionSelector.cpp | 529 unsigned NewOpc = getLoadStoreOp(Ty, RB, Opc, MemOp.getAlignment()); in selectLoadStoreOp() local
571 unsigned NewOpc = getLeaOP(Ty, STI); in selectFrameIndexOrGep() local
622 unsigned NewOpc = getLeaOP(Ty, STI); in selectGlobalValue() local
654 unsigned NewOpc; in selectConstant() local
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| /external/capstone/arch/X86/ |
| D | X86Disassembler.c | 204 unsigned NewOpc = 0; in translateImmediate() local
243 unsigned NewOpc = 0; in translateImmediate() local
279 unsigned NewOpc = 0; in translateImmediate() local
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| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 418 unsigned NewOpc; in translateImmediate() local
452 unsigned NewOpc; in translateImmediate() local
483 unsigned NewOpc; in translateImmediate() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1261 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1361 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1457 unsigned NewOpc; in MergeBaseUpdateLSDouble() local
1551 bool isDef, const DebugLoc &DL, unsigned NewOpc, in InsertLDR_STR()
1616 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
1638 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
1875 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM() local
2056 DebugLoc &dl, unsigned &NewOpc, in CanFormLdStDWord()
2221 unsigned NewOpc = 0; in RescheduleOps() local
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| D | Thumb2InstrInfo.cpp | 504 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in rewriteT2FrameIndex() local
538 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
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| D | ARMExpandPseudoInsts.cpp | 1097 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI() local
1136 unsigned NewOpc; in ExpandMI() local
1380 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local
1411 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1323 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); in MergeBaseUpdateLSMultiple() local
1423 unsigned NewOpc; in MergeBaseUpdateLoadStore() local
1535 unsigned NewOpc; in MergeBaseUpdateLSDouble() local
1629 bool isDef, unsigned NewOpc, unsigned Reg, in InsertLDR_STR()
1701 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
1725 unsigned NewOpc = (isLd) in FixInvalidRegPairOp() local
1953 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); in MergeReturnIntoLDM() local
2148 DebugLoc &dl, unsigned &NewOpc, in CanFormLdStDWord()
2320 unsigned NewOpc = 0; in RescheduleOps() local
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| D | Thumb2InstrInfo.cpp | 531 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex() local
564 unsigned NewOpc = Opcode; in rewriteT2FrameIndex() local
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| D | ARMExpandPseudoInsts.cpp | 1273 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI() local
1315 unsigned NewOpc; in ExpandMI() local
1588 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI() local
1619 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI() local
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| D | ARMConstantIslandPass.cpp | 1773 unsigned NewOpc = 0; in optimizeThumb2Instructions() local
1824 unsigned NewOpc = 0; in optimizeThumb2Branches() local
1858 unsigned NewOpc = 0; in optimizeThumb2Branches() member
1872 unsigned NewOpc = 0; in optimizeThumb2Branches() local
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 427 unsigned NewOpc; in Lower() local
452 unsigned NewOpc; in Lower() local
615 unsigned NewOpc; in Lower() local
640 unsigned NewOpc; in Lower() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CondBrTuning.cpp | 100 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit); in convertToFlagSetting() local
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| D | AArch64AdvSIMDScalarPass.cpp | 292 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiMemAluCombiner.cpp | 252 unsigned NewOpc = mergedOpcode(MemInstr->getOpcode(), AluOffset.isImm()); in insertMergedInstruction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 224 unsigned OpNum, NewOpc; in rewrite() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 300 unsigned NewOpc = getTransformOpcode(OldOpc); in transformInstruction() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 210 unsigned OpNum, NewOpc; in rewrite() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 397 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc()
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| D | MipsLongBranch.cpp | 222 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 594 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, in genInstrWithNewOpc()
|