| /external/llvm/utils/TableGen/ |
| D | X86RecognizableInstr.cpp | 483 uint8_t OpSize)) { in handleOperand()
914 uint8_t OpSize) { in typeFromString()
1048 uint8_t OpSize) { in immediateEncodingFromString()
1086 uint8_t OpSize) { in rmRegisterEncodingFromString()
1118 uint8_t OpSize) { in roRegisterEncodingFromString()
1159 uint8_t OpSize) { in vvvvRegisterEncodingFromString()
1185 uint8_t OpSize) { in writemaskRegisterEncodingFromString()
1199 uint8_t OpSize) { in memoryEncodingFromString()
1240 uint8_t OpSize) { in relocationEncodingFromString()
1287 uint8_t OpSize) { in opcodeModifierEncodingFromString()
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| D | X86RecognizableInstr.h | 51 uint8_t OpSize; variable
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMLegalizerInfo.cpp | 400 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in legalizeCustom() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 317 unsigned OpSize = TII->getOpSize(MI, 1); in runOnMachineFunction() local
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| D | SIInstrInfo.cpp | 1548 unsigned OpSize = RI.getRegClass(OpInfo.RegClass)->getSize(); in isImmOperandLegal() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterBankInfo.cpp | 616 SmallVector<unsigned, 4> OpSize(NumOperands); in getInstrMapping() local
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| D | AArch64InstructionSelector.cpp | 477 unsigned OpSize) { in selectBinaryOp()
548 unsigned OpSize) { in selectLoadStoreUIOp()
878 unsigned OpSize = MRI.getType(I.getOperand(2).getReg()).getSizeInBits(); in selectFCMPOpc() local
1965 const unsigned OpSize = Ty.getSizeInBits(); in select() local
1991 unsigned OpSize = Ty.getSizeInBits(); in select() local
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| D | AArch64ISelLowering.cpp | 4147 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8 in LowerCall() local
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| /external/llvm/lib/IR/ |
| D | Metadata.cpp | 445 size_t OpSize = NumOps * sizeof(MDOperand); in operator new() local
458 size_t OpSize = N->NumOperands * sizeof(MDOperand); in operator delete() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | Metadata.cpp | 481 size_t OpSize = NumOps * sizeof(MDOperand); in operator new() local
496 size_t OpSize = N->NumOperands * sizeof(MDOperand); in operator delete() local
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| /external/llvm/include/llvm/Analysis/ |
| D | TargetTransformInfoImpl.h | 76 unsigned OpSize = OpTy->getScalarSizeInBits(); in getOperationCost() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 556 int64_t OpSize = MFI.getObjectSize(FI); in foldMemoryOperand() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 844 unsigned OpSize = OpTy.getSizeInBits(); in executeInWaterfallLoop() local
3011 unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in getInstrMapping() local
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| D | SIISelLowering.cpp | 2834 unsigned OpSize = Flags.isByVal() ? in LowerCall() local
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| /external/llvm/lib/Analysis/ |
| D | ConstantFolding.cpp | 676 unsigned OpSize = DL.getTypeSizeInBits(Op0->getType()); in SymbolicallyEvaluateBinop() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 542 unsigned OpSize = OpTy.getSizeInBits(); in buildSequence() local
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| D | LegalizerHelper.cpp | 3517 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarExtract() local
3584 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarInsert() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/ |
| D | TargetTransformInfoImpl.h | 76 unsigned OpSize = OpTy->getScalarSizeInBits(); in getOperationCost() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | ConstantFolding.cpp | 751 unsigned OpSize = DL.getTypeSizeInBits(Op0->getType()); in SymbolicallyEvaluateBinop() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2752 auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx); in isInlineConstant() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 4884 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8; in CalculateTailCallArgDest() local
12310 auto OpSize = N->getOperand(0).getValueSizeInBits(); in ConvertSETCCToSubtract() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 4222 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; in CalculateTailCallArgDest() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3102 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8 in LowerCall() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 13262 int OpSize = OpVT.getVectorNumElements(); in simplifyShuffleOperandRecursively() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4125 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; in LowerCall() local
43723 unsigned OpSize = OpVT.getSizeInBits(); in combineVectorSizedSetCCEquality() local
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