| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 68 struct Operands { struct
69 Condition cond;
70 Register rd;
71 Register rn;
72 Sign sign;
73 Register rm;
74 ShiftType shift;
75 uint32_t amount;
76 AddrMode addr_mode;
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| D | test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 68 struct Operands { struct
69 Condition cond;
70 Register rd;
71 Register rn;
72 Sign sign;
73 Register rm;
74 ShiftType shift;
75 uint32_t amount;
76 AddrMode addr_mode;
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| D | test-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc | 84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 Register rs;
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| D | test-assembler-cond-rd-memop-immediate-512-a32.cc | 68 struct Operands { struct
69 Condition cond;
70 Register rd;
71 Register rn;
72 Sign sign;
73 int32_t offset;
74 AddrMode addr_mode;
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| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc | 70 struct Operands { struct
71 Condition cond;
72 Register rd;
73 Register rn;
74 Register rm;
75 ShiftType ror;
76 uint32_t amount;
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| D | test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc | 84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 Register rs;
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| D | test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc | 70 struct Operands { struct
71 Condition cond;
72 Register rd;
73 Register rn;
74 Register rm;
75 ShiftType ror;
76 uint32_t amount;
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| D | test-assembler-cond-rd-memop-immediate-8192-a32.cc | 68 struct Operands { struct
69 Condition cond;
70 Register rd;
71 Register rn;
72 Sign sign;
73 int32_t offset;
74 AddrMode addr_mode;
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| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 uint32_t amount;
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| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 uint32_t amount;
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| D | test-assembler-cond-rd-memop-rs-a32.cc | 72 struct Operands { struct
73 Condition cond;
74 Register rd;
75 Register rn;
76 Sign sign;
77 Register rm;
78 AddrMode addr_mode;
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| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 uint32_t amount;
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| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 84 struct Operands { struct
85 Condition cond;
86 Register rd;
87 Register rn;
88 Register rm;
89 ShiftType shift;
90 uint32_t amount;
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| D | test-assembler-cond-rd-operand-rn-shift-rs-t32.cc | 66 struct Operands { struct
67 Condition cond;
68 Register rd;
69 Register rn;
70 ShiftType shift;
71 Register rs;
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 72 struct Operands { struct
73 Condition cond;
74 Register rd;
75 Register rn;
76 ShiftType shift;
77 uint32_t amount;
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 72 struct Operands { struct
73 Condition cond;
74 Register rd;
75 Register rn;
76 ShiftType shift;
77 uint32_t amount;
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| D | test-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc | 64 struct Operands { struct
65 Condition cond;
66 Register rd;
67 Register rn;
68 ShiftType shift;
69 Register rs;
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 72 struct Operands { struct
73 Condition cond;
74 Register rd;
75 Register rn;
76 ShiftType shift;
77 uint32_t amount;
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| D | test-assembler-cond-rd-operand-rn-ror-amount-a32.cc | 70 struct Operands { struct
71 Condition cond;
72 Register rd;
73 Register rn;
74 ShiftType ror;
75 uint32_t amount;
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| D | test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc | 64 struct Operands { struct
65 Condition cond;
66 Register rd;
67 Register rn;
68 ShiftType shift;
69 Register rs;
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| D | test-assembler-cond-rd-operand-rn-shift-rs-a32.cc | 72 struct Operands { struct
73 Condition cond;
74 Register rd;
75 Register rn;
76 ShiftType shift;
77 Register rs;
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc | 64 struct Operands { struct
65 Condition cond;
66 Register rd;
67 Register rn;
68 ShiftType shift;
69 uint32_t amount;
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| /external/llvm/docs/ |
| D | MIRLangRef.rst | 362 Immediate Operands
375 .. _register-operands:
377 Register Operands
398 .. _register-flags:
400 Register Flags
441 Subregister Indices
456 Global Value Operands
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 412 OperandMatchResultTy parseGR32(OperandVector &Operands) { in parseGR32()
415 OperandMatchResultTy parseGRH32(OperandVector &Operands) { in parseGRH32()
418 OperandMatchResultTy parseGRX32(OperandVector &Operands) { in parseGRX32()
421 OperandMatchResultTy parseGR64(OperandVector &Operands) { in parseGR64()
424 OperandMatchResultTy parseGR128(OperandVector &Operands) { in parseGR128()
427 OperandMatchResultTy parseADDR32(OperandVector &Operands) { in parseADDR32()
430 OperandMatchResultTy parseADDR64(OperandVector &Operands) { in parseADDR64()
433 OperandMatchResultTy parseADDR128(OperandVector &Operands) { in parseADDR128()
436 OperandMatchResultTy parseFP32(OperandVector &Operands) { in parseFP32()
439 OperandMatchResultTy parseFP64(OperandVector &Operands) { in parseFP64()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 460 OperandMatchResultTy parseGR32(OperandVector &Operands) { in parseGR32()
463 OperandMatchResultTy parseGRH32(OperandVector &Operands) { in parseGRH32()
466 OperandMatchResultTy parseGRX32(OperandVector &Operands) { in parseGRX32()
469 OperandMatchResultTy parseGR64(OperandVector &Operands) { in parseGR64()
472 OperandMatchResultTy parseGR128(OperandVector &Operands) { in parseGR128()
475 OperandMatchResultTy parseADDR32(OperandVector &Operands) { in parseADDR32()
478 OperandMatchResultTy parseADDR64(OperandVector &Operands) { in parseADDR64()
481 OperandMatchResultTy parseADDR128(OperandVector &Operands) { in parseADDR128()
484 OperandMatchResultTy parseFP32(OperandVector &Operands) { in parseFP32()
487 OperandMatchResultTy parseFP64(OperandVector &Operands) { in parseFP64()
[all …]
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