1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "ARMCallLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMISelLowering.h"
18 #include "ARMSubtarget.h"
19 #include "Utils/ARMBaseInfo.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
24 #include "llvm/CodeGen/GlobalISel/Utils.h"
25 #include "llvm/CodeGen/LowLevelType.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/TargetRegisterInfo.h"
34 #include "llvm/CodeGen/TargetSubtargetInfo.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/Support/Casting.h"
43 #include "llvm/Support/LowLevelTypeImpl.h"
44 #include "llvm/Support/MachineValueType.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <utility>
49
50 using namespace llvm;
51
ARMCallLowering(const ARMTargetLowering & TLI)52 ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
53 : CallLowering(&TLI) {}
54
isSupportedType(const DataLayout & DL,const ARMTargetLowering & TLI,Type * T)55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
56 Type *T) {
57 if (T->isArrayTy())
58 return isSupportedType(DL, TLI, T->getArrayElementType());
59
60 if (T->isStructTy()) {
61 // For now we only allow homogeneous structs that we can manipulate with
62 // G_MERGE_VALUES and G_UNMERGE_VALUES
63 auto StructT = cast<StructType>(T);
64 for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
65 if (StructT->getElementType(i) != StructT->getElementType(0))
66 return false;
67 return isSupportedType(DL, TLI, StructT->getElementType(0));
68 }
69
70 EVT VT = TLI.getValueType(DL, T, true);
71 if (!VT.isSimple() || VT.isVector() ||
72 !(VT.isInteger() || VT.isFloatingPoint()))
73 return false;
74
75 unsigned VTSize = VT.getSimpleVT().getSizeInBits();
76
77 if (VTSize == 64)
78 // FIXME: Support i64 too
79 return VT.isFloatingPoint();
80
81 return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
82 }
83
84 namespace {
85
86 /// Helper class for values going out through an ABI boundary (used for handling
87 /// function return values and call parameters).
88 struct OutgoingValueHandler : public CallLowering::ValueHandler {
OutgoingValueHandler__anonb3f185610111::OutgoingValueHandler89 OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
90 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
91 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
92
isIncomingArgumentHandler__anonb3f185610111::OutgoingValueHandler93 bool isIncomingArgumentHandler() const override { return false; }
94
getStackAddress__anonb3f185610111::OutgoingValueHandler95 Register getStackAddress(uint64_t Size, int64_t Offset,
96 MachinePointerInfo &MPO) override {
97 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
98 "Unsupported size");
99
100 LLT p0 = LLT::pointer(0, 32);
101 LLT s32 = LLT::scalar(32);
102 Register SPReg = MRI.createGenericVirtualRegister(p0);
103 MIRBuilder.buildCopy(SPReg, Register(ARM::SP));
104
105 Register OffsetReg = MRI.createGenericVirtualRegister(s32);
106 MIRBuilder.buildConstant(OffsetReg, Offset);
107
108 Register AddrReg = MRI.createGenericVirtualRegister(p0);
109 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg);
110
111 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
112 return AddrReg;
113 }
114
assignValueToReg__anonb3f185610111::OutgoingValueHandler115 void assignValueToReg(Register ValVReg, Register PhysReg,
116 CCValAssign &VA) override {
117 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
118 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
119
120 assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
121 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
122
123 Register ExtReg = extendRegister(ValVReg, VA);
124 MIRBuilder.buildCopy(PhysReg, ExtReg);
125 MIB.addUse(PhysReg, RegState::Implicit);
126 }
127
assignValueToAddress__anonb3f185610111::OutgoingValueHandler128 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
129 MachinePointerInfo &MPO, CCValAssign &VA) override {
130 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
131 "Unsupported size");
132
133 Register ExtReg = extendRegister(ValVReg, VA);
134 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
135 MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
136 /* Alignment */ 1);
137 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
138 }
139
assignCustomValue__anonb3f185610111::OutgoingValueHandler140 unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
141 ArrayRef<CCValAssign> VAs) override {
142 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
143
144 CCValAssign VA = VAs[0];
145 assert(VA.needsCustom() && "Value doesn't need custom handling");
146 assert(VA.getValVT() == MVT::f64 && "Unsupported type");
147
148 CCValAssign NextVA = VAs[1];
149 assert(NextVA.needsCustom() && "Value doesn't need custom handling");
150 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
151
152 assert(VA.getValNo() == NextVA.getValNo() &&
153 "Values belong to different arguments");
154
155 assert(VA.isRegLoc() && "Value should be in reg");
156 assert(NextVA.isRegLoc() && "Value should be in reg");
157
158 Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
159 MRI.createGenericVirtualRegister(LLT::scalar(32))};
160 MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
161
162 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
163 if (!IsLittle)
164 std::swap(NewRegs[0], NewRegs[1]);
165
166 assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
167 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
168
169 return 1;
170 }
171
assignArg__anonb3f185610111::OutgoingValueHandler172 bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
173 CCValAssign::LocInfo LocInfo,
174 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
175 CCState &State) override {
176 if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State))
177 return true;
178
179 StackSize =
180 std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
181 return false;
182 }
183
184 MachineInstrBuilder &MIB;
185 uint64_t StackSize = 0;
186 };
187
188 } // end anonymous namespace
189
splitToValueTypes(const ArgInfo & OrigArg,SmallVectorImpl<ArgInfo> & SplitArgs,MachineFunction & MF) const190 void ARMCallLowering::splitToValueTypes(const ArgInfo &OrigArg,
191 SmallVectorImpl<ArgInfo> &SplitArgs,
192 MachineFunction &MF) const {
193 const ARMTargetLowering &TLI = *getTLI<ARMTargetLowering>();
194 LLVMContext &Ctx = OrigArg.Ty->getContext();
195 const DataLayout &DL = MF.getDataLayout();
196 const Function &F = MF.getFunction();
197
198 SmallVector<EVT, 4> SplitVTs;
199 ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, nullptr, nullptr, 0);
200 assert(OrigArg.Regs.size() == SplitVTs.size() && "Regs / types mismatch");
201
202 if (SplitVTs.size() == 1) {
203 // Even if there is no splitting to do, we still want to replace the
204 // original type (e.g. pointer type -> integer).
205 auto Flags = OrigArg.Flags[0];
206 Flags.setOrigAlign(Align(DL.getABITypeAlignment(OrigArg.Ty)));
207 SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
208 Flags, OrigArg.IsFixed);
209 return;
210 }
211
212 // Create one ArgInfo for each virtual register.
213 for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
214 EVT SplitVT = SplitVTs[i];
215 Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
216 auto Flags = OrigArg.Flags[0];
217
218 Flags.setOrigAlign(Align(DL.getABITypeAlignment(SplitTy)));
219
220 bool NeedsConsecutiveRegisters =
221 TLI.functionArgumentNeedsConsecutiveRegisters(
222 SplitTy, F.getCallingConv(), F.isVarArg());
223 if (NeedsConsecutiveRegisters) {
224 Flags.setInConsecutiveRegs();
225 if (i == e - 1)
226 Flags.setInConsecutiveRegsLast();
227 }
228
229 // FIXME: We also want to split SplitTy further.
230 Register PartReg = OrigArg.Regs[i];
231 SplitArgs.emplace_back(PartReg, SplitTy, Flags, OrigArg.IsFixed);
232 }
233 }
234
235 /// Lower the return value for the already existing \p Ret. This assumes that
236 /// \p MIRBuilder's insertion point is correct.
lowerReturnVal(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,MachineInstrBuilder & Ret) const237 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
238 const Value *Val, ArrayRef<Register> VRegs,
239 MachineInstrBuilder &Ret) const {
240 if (!Val)
241 // Nothing to do here.
242 return true;
243
244 auto &MF = MIRBuilder.getMF();
245 const auto &F = MF.getFunction();
246
247 auto DL = MF.getDataLayout();
248 auto &TLI = *getTLI<ARMTargetLowering>();
249 if (!isSupportedType(DL, TLI, Val->getType()))
250 return false;
251
252 ArgInfo OrigRetInfo(VRegs, Val->getType());
253 setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
254
255 SmallVector<ArgInfo, 4> SplitRetInfos;
256 splitToValueTypes(OrigRetInfo, SplitRetInfos, MF);
257
258 CCAssignFn *AssignFn =
259 TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
260
261 OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
262 return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler);
263 }
264
lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs) const265 bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
266 const Value *Val,
267 ArrayRef<Register> VRegs) const {
268 assert(!Val == VRegs.empty() && "Return value without a vreg");
269
270 auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
271 unsigned Opcode = ST.getReturnOpcode();
272 auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
273
274 if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
275 return false;
276
277 MIRBuilder.insertInstr(Ret);
278 return true;
279 }
280
281 namespace {
282
283 /// Helper class for values coming in through an ABI boundary (used for handling
284 /// formal arguments and call return values).
285 struct IncomingValueHandler : public CallLowering::ValueHandler {
IncomingValueHandler__anonb3f185610211::IncomingValueHandler286 IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
287 CCAssignFn AssignFn)
288 : ValueHandler(MIRBuilder, MRI, AssignFn) {}
289
isIncomingArgumentHandler__anonb3f185610211::IncomingValueHandler290 bool isIncomingArgumentHandler() const override { return true; }
291
getStackAddress__anonb3f185610211::IncomingValueHandler292 Register getStackAddress(uint64_t Size, int64_t Offset,
293 MachinePointerInfo &MPO) override {
294 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
295 "Unsupported size");
296
297 auto &MFI = MIRBuilder.getMF().getFrameInfo();
298
299 int FI = MFI.CreateFixedObject(Size, Offset, true);
300 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
301
302 Register AddrReg =
303 MRI.createGenericVirtualRegister(LLT::pointer(MPO.getAddrSpace(), 32));
304 MIRBuilder.buildFrameIndex(AddrReg, FI);
305
306 return AddrReg;
307 }
308
assignValueToAddress__anonb3f185610211::IncomingValueHandler309 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
310 MachinePointerInfo &MPO, CCValAssign &VA) override {
311 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
312 "Unsupported size");
313
314 if (VA.getLocInfo() == CCValAssign::SExt ||
315 VA.getLocInfo() == CCValAssign::ZExt) {
316 // If the value is zero- or sign-extended, its size becomes 4 bytes, so
317 // that's what we should load.
318 Size = 4;
319 assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
320
321 auto LoadVReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
322 buildLoad(LoadVReg, Addr, Size, /* Alignment */ 1, MPO);
323 MIRBuilder.buildTrunc(ValVReg, LoadVReg);
324 } else {
325 // If the value is not extended, a simple load will suffice.
326 buildLoad(ValVReg, Addr, Size, /* Alignment */ 1, MPO);
327 }
328 }
329
buildLoad__anonb3f185610211::IncomingValueHandler330 void buildLoad(Register Val, Register Addr, uint64_t Size, unsigned Alignment,
331 MachinePointerInfo &MPO) {
332 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
333 MPO, MachineMemOperand::MOLoad, Size, Alignment);
334 MIRBuilder.buildLoad(Val, Addr, *MMO);
335 }
336
assignValueToReg__anonb3f185610211::IncomingValueHandler337 void assignValueToReg(Register ValVReg, Register PhysReg,
338 CCValAssign &VA) override {
339 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
340 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
341
342 auto ValSize = VA.getValVT().getSizeInBits();
343 auto LocSize = VA.getLocVT().getSizeInBits();
344
345 assert(ValSize <= 64 && "Unsupported value size");
346 assert(LocSize <= 64 && "Unsupported location size");
347
348 markPhysRegUsed(PhysReg);
349 if (ValSize == LocSize) {
350 MIRBuilder.buildCopy(ValVReg, PhysReg);
351 } else {
352 assert(ValSize < LocSize && "Extensions not supported");
353
354 // We cannot create a truncating copy, nor a trunc of a physical register.
355 // Therefore, we need to copy the content of the physical register into a
356 // virtual one and then truncate that.
357 auto PhysRegToVReg =
358 MRI.createGenericVirtualRegister(LLT::scalar(LocSize));
359 MIRBuilder.buildCopy(PhysRegToVReg, PhysReg);
360 MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
361 }
362 }
363
assignCustomValue__anonb3f185610211::IncomingValueHandler364 unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
365 ArrayRef<CCValAssign> VAs) override {
366 assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
367
368 CCValAssign VA = VAs[0];
369 assert(VA.needsCustom() && "Value doesn't need custom handling");
370 assert(VA.getValVT() == MVT::f64 && "Unsupported type");
371
372 CCValAssign NextVA = VAs[1];
373 assert(NextVA.needsCustom() && "Value doesn't need custom handling");
374 assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
375
376 assert(VA.getValNo() == NextVA.getValNo() &&
377 "Values belong to different arguments");
378
379 assert(VA.isRegLoc() && "Value should be in reg");
380 assert(NextVA.isRegLoc() && "Value should be in reg");
381
382 Register NewRegs[] = {MRI.createGenericVirtualRegister(LLT::scalar(32)),
383 MRI.createGenericVirtualRegister(LLT::scalar(32))};
384
385 assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
386 assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
387
388 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
389 if (!IsLittle)
390 std::swap(NewRegs[0], NewRegs[1]);
391
392 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
393
394 return 1;
395 }
396
397 /// Marking a physical register as used is different between formal
398 /// parameters, where it's a basic block live-in, and call returns, where it's
399 /// an implicit-def of the call instruction.
400 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
401 };
402
403 struct FormalArgHandler : public IncomingValueHandler {
FormalArgHandler__anonb3f185610211::FormalArgHandler404 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
405 CCAssignFn AssignFn)
406 : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
407
markPhysRegUsed__anonb3f185610211::FormalArgHandler408 void markPhysRegUsed(unsigned PhysReg) override {
409 MIRBuilder.getMRI()->addLiveIn(PhysReg);
410 MIRBuilder.getMBB().addLiveIn(PhysReg);
411 }
412 };
413
414 } // end anonymous namespace
415
lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<ArrayRef<Register>> VRegs) const416 bool ARMCallLowering::lowerFormalArguments(
417 MachineIRBuilder &MIRBuilder, const Function &F,
418 ArrayRef<ArrayRef<Register>> VRegs) const {
419 auto &TLI = *getTLI<ARMTargetLowering>();
420 auto Subtarget = TLI.getSubtarget();
421
422 if (Subtarget->isThumb1Only())
423 return false;
424
425 // Quick exit if there aren't any args
426 if (F.arg_empty())
427 return true;
428
429 if (F.isVarArg())
430 return false;
431
432 auto &MF = MIRBuilder.getMF();
433 auto &MBB = MIRBuilder.getMBB();
434 auto DL = MF.getDataLayout();
435
436 for (auto &Arg : F.args()) {
437 if (!isSupportedType(DL, TLI, Arg.getType()))
438 return false;
439 if (Arg.hasByValOrInAllocaAttr())
440 return false;
441 }
442
443 CCAssignFn *AssignFn =
444 TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
445
446 FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
447 AssignFn);
448
449 SmallVector<ArgInfo, 8> SplitArgInfos;
450 unsigned Idx = 0;
451 for (auto &Arg : F.args()) {
452 ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
453
454 setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
455 splitToValueTypes(OrigArgInfo, SplitArgInfos, MF);
456
457 Idx++;
458 }
459
460 if (!MBB.empty())
461 MIRBuilder.setInstr(*MBB.begin());
462
463 if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler))
464 return false;
465
466 // Move back to the end of the basic block.
467 MIRBuilder.setMBB(MBB);
468 return true;
469 }
470
471 namespace {
472
473 struct CallReturnHandler : public IncomingValueHandler {
CallReturnHandler__anonb3f185610311::CallReturnHandler474 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
475 MachineInstrBuilder MIB, CCAssignFn *AssignFn)
476 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
477
markPhysRegUsed__anonb3f185610311::CallReturnHandler478 void markPhysRegUsed(unsigned PhysReg) override {
479 MIB.addDef(PhysReg, RegState::Implicit);
480 }
481
482 MachineInstrBuilder MIB;
483 };
484
485 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
getCallOpcode(const ARMSubtarget & STI,bool isDirect)486 unsigned getCallOpcode(const ARMSubtarget &STI, bool isDirect) {
487 if (isDirect)
488 return STI.isThumb() ? ARM::tBL : ARM::BL;
489
490 if (STI.isThumb())
491 return ARM::tBLXr;
492
493 if (STI.hasV5TOps())
494 return ARM::BLX;
495
496 if (STI.hasV4TOps())
497 return ARM::BX_CALL;
498
499 return ARM::BMOVPCRX_CALL;
500 }
501 } // end anonymous namespace
502
lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const503 bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const {
504 MachineFunction &MF = MIRBuilder.getMF();
505 const auto &TLI = *getTLI<ARMTargetLowering>();
506 const auto &DL = MF.getDataLayout();
507 const auto &STI = MF.getSubtarget<ARMSubtarget>();
508 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
509 MachineRegisterInfo &MRI = MF.getRegInfo();
510
511 if (STI.genLongCalls())
512 return false;
513
514 if (STI.isThumb1Only())
515 return false;
516
517 auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
518
519 // Create the call instruction so we can add the implicit uses of arg
520 // registers, but don't insert it yet.
521 bool IsDirect = !Info.Callee.isReg();
522 auto CallOpcode = getCallOpcode(STI, IsDirect);
523 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
524
525 bool IsThumb = STI.isThumb();
526 if (IsThumb)
527 MIB.add(predOps(ARMCC::AL));
528
529 MIB.add(Info.Callee);
530 if (!IsDirect) {
531 auto CalleeReg = Info.Callee.getReg();
532 if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
533 unsigned CalleeIdx = IsThumb ? 2 : 0;
534 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
535 MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
536 *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));
537 }
538 }
539
540 MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
541
542 bool IsVarArg = false;
543 SmallVector<ArgInfo, 8> ArgInfos;
544 for (auto Arg : Info.OrigArgs) {
545 if (!isSupportedType(DL, TLI, Arg.Ty))
546 return false;
547
548 if (!Arg.IsFixed)
549 IsVarArg = true;
550
551 if (Arg.Flags[0].isByVal())
552 return false;
553
554 splitToValueTypes(Arg, ArgInfos, MF);
555 }
556
557 auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, IsVarArg);
558 OutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
559 if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler))
560 return false;
561
562 // Now we can add the actual call instruction to the correct basic block.
563 MIRBuilder.insertInstr(MIB);
564
565 if (!Info.OrigRet.Ty->isVoidTy()) {
566 if (!isSupportedType(DL, TLI, Info.OrigRet.Ty))
567 return false;
568
569 ArgInfos.clear();
570 splitToValueTypes(Info.OrigRet, ArgInfos, MF);
571 auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, IsVarArg);
572 CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
573 if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler))
574 return false;
575 }
576
577 // We now know the size of the stack - update the ADJCALLSTACKDOWN
578 // accordingly.
579 CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
580
581 MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
582 .addImm(ArgHandler.StackSize)
583 .addImm(0)
584 .add(predOps(ARMCC::AL));
585
586 return true;
587 }
588