Searched defs:OrigRegs (Results 1 – 11 of 11) sorted by relevance
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTLSDynamicCall.cpp | 83 const unsigned OrigRegs[] = {OutReg, InReg, GPR3}; in processBlock() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTLSDynamicCall.cpp | 76 const unsigned OrigRegs[] = {OutReg, InReg, GPR3}; in processBlock() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUPALMetadata.cpp | 571 auto OrigRegs = RegsObj.getMap(); in toString() local
632 auto OrigRegs = RegsObj; in setFromString() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 51 SmallVector<Register, 2> OrigRegs; member
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNNSAReassign.cpp | 276 SmallVector<unsigned, 16> OrigRegs; in runOnMachineFunction() local
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| D | AMDGPUCallLowering.cpp | 490 ArrayRef<Register> OrigRegs, in packSplitRegsToOrigType()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 345 unsigned OrigRegs[] = { Data0->getReg(), Data1->getReg(), Addr->getReg() }; in mergeWrite2Pair() local
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| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 1366 SmallVector<unsigned, 4> OrigRegs; in tryInstructionTransform() local
1740 SmallVector<unsigned, 4> OrigRegs; in eliminateRegSequence() local
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| D | LiveIntervalAnalysis.cpp | 1483 ArrayRef<unsigned> OrigRegs) { in repairIntervalsInRange()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 1425 SmallVector<unsigned, 4> OrigRegs; in tryInstructionTransform() local
1808 SmallVector<unsigned, 4> OrigRegs; in eliminateRegSequence() local
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| D | LiveIntervals.cpp | 1590 ArrayRef<unsigned> OrigRegs) { in repairIntervalsInRange()
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