1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef _SOC_H 9 #define _SOC_H 10 11 /* Chassis specific defines - common across SoC's of a particular platform */ 12 #include <dcfg_lsch3.h> 13 #include <soc_default_base_addr.h> 14 #include <soc_default_helper_macros.h> 15 16 17 #define NUM_DRAM_REGIONS 3 18 #define NXP_DRAM0_ADDR 0x80000000 19 #define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */ 20 21 #define NXP_DRAM1_ADDR 0x2080000000 22 #define NXP_DRAM1_MAX_SIZE 0x1F80000000 /* 126 G */ 23 24 #define NXP_DRAM2_ADDR 0x6000000000 25 #define NXP_DRAM2_MAX_SIZE 0x2000000000 /* 128G */ 26 27 /*DRAM0 Size defined in platform_def.h */ 28 #define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE 29 30 #define DDR_PLL_FIX 31 #define NXP_DDR_PHY1_ADDR 0x01400000 32 #define NXP_DDR_PHY2_ADDR 0x01600000 33 34 #if defined(IMAGE_BL31) 35 #define LS_SYS_TIMCTL_BASE 0x2890000 36 37 #ifdef LS_SYS_TIMCTL_BASE 38 #define PLAT_LS_NSTIMER_FRAME_ID 0 39 #define LS_CONFIG_CNTACR 1 40 #endif 41 #endif 42 43 /* Start: Macros used by soc.c: get_boot_dev */ 44 #define PORSR1_RCW_MASK 0x07800000 45 #define PORSR1_RCW_SHIFT 23 46 47 #define SDHC1_VAL 0x8 48 #define SDHC2_VAL 0x9 49 #define I2C1_VAL 0xa 50 #define FLEXSPI_NAND2K_VAL 0xc 51 #define FLEXSPI_NAND4K_VAL 0xd 52 #define FLEXSPI_NOR 0xf 53 /* End: Macros used by soc.c: get_boot_dev */ 54 55 /* SVR Definition (not include major and minor rev) */ 56 #define SVR_LX2160A 0x873601 57 #define SVR_LX2120A 0x873621 58 #define SVR_LX2080A 0x873603 59 60 /* Number of cores in platform */ 61 /* Used by common code for array initialization */ 62 #define NUMBER_OF_CLUSTERS 8 63 #define CORES_PER_CLUSTER 2 64 #define PLATFORM_CORE_COUNT NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER 65 66 /* 67 * Required LS standard platform porting definitions 68 * for CCN-508 69 */ 70 #define PLAT_CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28, 16, 0 71 #define PLAT_6CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28 72 73 74 /* Defines required for using XLAT tables from ARM common code */ 75 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40) 76 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40) 77 78 /* Clock Divisors */ 79 #define NXP_PLATFORM_CLK_DIVIDER 2 80 #define NXP_UART_CLK_DIVIDER 4 81 82 /* Start: Macros used by lx2160a.S */ 83 #define MPIDR_AFFINITY0_MASK 0x00FF 84 #define MPIDR_AFFINITY1_MASK 0xFF00 85 #define CPUECTLR_DISABLE_TWALK_PREFETCH 0x4000000000 86 #define CPUECTLR_INS_PREFETCH_MASK 0x1800000000 87 #define CPUECTLR_DAT_PREFETCH_MASK 0x0300000000 88 #define CPUECTLR_RET_8CLK 0x2 89 #define OSDLR_EL1_DLK_LOCK 0x1 90 #define CNTP_CTL_EL0_EN 0x1 91 #define CNTP_CTL_EL0_IMASK 0x2 92 /* set to 0 if the clusters are not symmetrical */ 93 #define SYMMETRICAL_CLUSTERS 1 94 /* End: Macros used by lx2160a.S */ 95 96 /* Start: Macros used by lib/psci files */ 97 #define SYSTEM_PWR_DOMAINS 1 98 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 99 NUMBER_OF_CLUSTERS + \ 100 SYSTEM_PWR_DOMAINS) 101 102 /* Power state coordination occurs at the system level */ 103 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 104 105 /* define retention state */ 106 #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) 107 108 /* define power-down state */ 109 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) 110 /* End: Macros used by lib/psci files */ 111 112 /* Some data must be aligned on the biggest cache line size in the platform. 113 * This is known only to the platform as it might have a combination of 114 * integrated and external caches. 115 * 116 * CACHE_WRITEBACK_GRANULE is defined in soc.def 117 * 118 * One cache line needed for bakery locks on ARM platforms 119 */ 120 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 121 122 #ifndef WDOG_RESET_FLAG 123 #define WDOG_RESET_FLAG DEFAULT_SET_VALUE 124 #endif 125 126 #ifndef WARM_BOOT_SUCCESS 127 #define WARM_BOOT_SUCCESS DEFAULT_SET_VALUE 128 #endif 129 130 #ifndef __ASSEMBLER__ 131 132 void set_base_freq_CNTFID0(void); 133 void soc_init_start(void); 134 void soc_init_finish(void); 135 void soc_init_percpu(void); 136 void _soc_set_start_addr(unsigned long addr); 137 void _set_platform_security(void); 138 139 #endif 140 141 #endif /* _SOC_H */ 142