| /external/python/cpython2/Tools/framer/framer/ |
| D | member.py | 19 RO = READONLY = "READONLY" variable
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| /external/python/cpython2/Include/ |
| D | structmember.h | 81 #define RO READONLY /* Shorthand */ macro
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| /external/llvm/lib/Analysis/ |
| D | ScalarEvolutionNormalization.cpp | 215 const SCEV *RO = X->getRHS(); in TransformImpl() local
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| /external/autotest/client/common_lib/cros/ |
| D | cr50_utils.py | 19 RO = 'ro' variable
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| /external/llvm/include/llvm/ExecutionEngine/Orc/ |
| D | CompileOnDemandLayer.h | 87 typedef ResourceOwnerImpl<ResourceT, ResourcePtrT> RO; in wrapOwnership() typedef
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| /external/igt-gpu-tools/tests/i915/ |
| D | gem_exec_reloc.c | 101 #define RO 0x100 macro
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86WinCOFFTargetStreamer.cpp | 351 for (RegSaveOffset RO : RegSaveOffsets) in emitFrameDataRecord() local
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| /external/llvm/tools/llvm-diff/ |
| D | DifferenceEngine.cpp | 354 Value *LO = L->getOperand(I), *RO = R->getOperand(I); in diff() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ExecutionEngine/Orc/ |
| D | CompileOnDemandLayer.h | 193 using RO = ResourceOwnerImpl<ResourceT, ResourcePtrT>; in wrapOwnership() local
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| /external/rust/crates/virtio-drivers/src/device/ |
| D | blk.rs | 430 const RO = 1 << 5; constant
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| /external/llvm/utils/TableGen/ |
| D | AsmWriterEmitter.cpp | 826 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; in EmitPrintAliasInstruction() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 783 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1); in updatePhiNodes() local
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| D | HexagonExpandCondsets.cpp | 916 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, in renameInRange()
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| D | HexagonInstrInfo.cpp | 628 const MachineOperand &RO = Cond[1]; in InsertBranch() local
651 const MachineOperand &RO = Cond[1]; in InsertBranch() local
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| D | HexagonGenInsert.cpp | 361 OrderedRegisterList(const RegisterOrdering &RO) : Ord(RO) {} in OrderedRegisterList()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonEarlyIfConv.cpp | 820 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1); in updatePhiNodes() local
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| D | HexagonExpandCondsets.cpp | 908 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, in renameInRange()
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| D | HexagonInstrInfo.cpp | 644 const MachineOperand &RO = Cond[1]; in insertBranch() local
668 const MachineOperand &RO = Cond[1]; in insertBranch() local
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| D | HexagonGenInsert.cpp | 387 OrderedRegisterList(const RegisterOrdering &RO) in OrderedRegisterList()
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| /external/clang/lib/StaticAnalyzer/Core/ |
| D | RegionStore.cpp | 114 const RegionOffset &RO = R->getAsOffset(); in Make() local
1102 const RegionOffset &RO = baseR->getAsOffset(); in VisitCluster() local
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| /external/deqp/external/vulkancts/modules/vulkan/image/ |
| D | vktImageDepthStencilDescriptorTests.cpp | 108 RO = 1, // Different subtypes, see below. enumerator
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| /external/swiftshader/src/Device/ |
| D | ETC_Decoder.cpp | 281 unsigned char RO : 6; member
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| /external/deqp/framework/common/ |
| D | tcuCompressedTexture.cpp | 772 const deUint8 RO = extend6To8((deUint8)getBits(src, 57, 62)); in decompressETC2Block() local
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| /external/python/cpython3/Lib/test/ |
| D | test_enum.py | 2227 RO = 0 variable in TestFlag.Open
2676 RO = 0 variable in TestIntFlag.Open
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| /external/angle/src/image_util/ |
| D | loadimage_etc.cpp | 300 unsigned char RO : 6; member
|