| /external/rust/crates/tokio/tests/ |
| D | io_read_buf.rs | 13 struct Rd { in read_buf() struct
14 cnt: usize, in read_buf()
17 impl AsyncRead for Rd { in read_buf() implementation
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| D | io_read.rs | 19 struct Rd { in read() struct
20 poll_cnt: usize, in read()
23 impl AsyncRead for Rd { in read() implementation
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| D | io_copy.rs | 14 struct Rd(bool); in copy() struct
16 impl AsyncRead for Rd { in copy() implementation
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint()
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint()
363 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
373 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint()
242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint()
362 Register Rd = MI.getOperand(0).getReg(); in apply() local
372 Register Rd = MI.getOperand(0).getReg(); in apply() local
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| /external/capstone/arch/AArch64/ |
| D | AArch64Disassembler.c | 730 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
835 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
899 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1390 unsigned Rd, Rn, Rm; in DecodeAddSubERegInstruction() local
1450 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1483 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1523 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1541 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1559 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeBaseAddSubImm() local
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 652 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
743 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
805 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1296 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1353 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1384 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1423 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1440 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1459 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeBaseAddSubImm() local
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| /external/capstone/arch/ARM/ |
| D | ARMDisassembler.c | 1898 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeQADDInstruction() local
2103 unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2127 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2154 unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); in DecodeSMLAInstruction() local
2296 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLDInstruction() local
2630 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVSTInstruction() local
2902 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD1DupInstruction() local
2950 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD2DupInstruction() local
2999 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3035 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2070 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2094 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2121 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2334 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local
2659 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local
2930 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local
2977 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local
3025 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3060 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 845 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
936 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
998 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1507 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1564 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1595 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1634 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1651 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1670 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubImmShift() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 2196 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2422 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2446 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2473 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2685 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local
3012 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local
3282 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local
3329 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local
3377 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3412 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 271 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); in emitRdRtSa() local
284 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); in emitRdRsRt() local
527 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "clz"); in clz() local
657 const IValueT Rd = in jalr() local
774 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mfhi"); in mfhi() local
781 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mflo"); in mflo() local
821 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "pseudo-move"); in move() local
840 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movf"); in movf() local
875 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movt"); in movt() local
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| D | IceAssemblerARM32.cpp | 797 IValueT Rd, IValueT Imm12, in emitType01()
819 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitType01() local
825 IValueT Rd, IValueT Rn, const Operand *OpSrc1, in emitType01()
929 constexpr IValueT Rd = RegARM32::Encoded_Reg_r0; in emitCompareOp() local
1061 void AssemblerARM32::emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitDivOp()
1128 void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitMulOp()
1158 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitSignExtend() local
1464 IValueT Rd = encodeGPRegister(OpRd, RdName, ClzName); in clz() local
1624 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitMemExOp() local
1692 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitShift() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/ |
| D | RISCVDisassembler.cpp | 296 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2() local
306 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/ |
| D | MSP430Disassembler.cpp | 194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1680 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1713 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1723 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1911 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1903 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1942 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1952 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
2150 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
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| /external/mesa3d/src/mesa/swrast/ |
| D | s_blend.c | 486 const GLfloat Rd = dest[i][RCOMP]; in blend_general_float() local
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| /external/XNNPACK/src/jit/ |
| D | aarch32-assembler.cc | 198 void Assembler::mov(Condition c, CoreRegister Rd, CoreRegister Rm) { in mov()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonConstExtenders.cpp | 325 Register Rd; member
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| D | HexagonFrameLowering.cpp | 2407 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
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| D | HexagonInstrInfo.cpp | 1234 Register Rd = Op0.getReg(); in expandPostRAPseudo() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 2203 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
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| D | HexagonInstrInfo.cpp | 1238 unsigned Rd = Op0.getReg(); in expandPostRAPseudo() local
|