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Searched defs:Reg0 (Results 1 – 25 of 38) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp166 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
175 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
185 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX()
236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
242 void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, in emitRRIII()
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DLocked.cpp89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DLocked.cpp86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp129 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR()
138 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX()
148 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI()
153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
180 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
186 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1861 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
1991 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2156 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
2254 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
2356 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2403 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2424 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2444 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2776 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
2795 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
DThumb2SizeReduction.cpp706 unsigned Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
DARMAsmPrinter.cpp298 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp243 unsigned Reg0 = Op0.getReg(); in runOnMachineFunction() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp240 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
DHexagonBitTracker.cpp316 unsigned Reg0 = Reg[0].Reg; in evaluate() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp2063 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2195 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2365 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDSTLane() local
2749 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLDDup() local
2851 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2899 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2921 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
2942 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in tryV6T2BitfieldExtractOp() local
3262 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
3281 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in Select() local
[all …]
DThumb2SizeReduction.cpp746 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
DARMAsmPrinter.cpp312 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp225 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
/external/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp438 unsigned Reg0 = in emitPrologue() local
456 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp463 unsigned Reg0 = in emitPrologue() local
481 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp505 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
518 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
556 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
567 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
/external/capstone/arch/ARM/
DARMInstPrinter.c2467 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwo() local
2508 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwoSpaced() local
2680 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwoAllLanes() local
2827 unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0); in printVectorListTwoSpacedAllLanes() local
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp1476 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1489 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1544 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1591 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp1437 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1450 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1505 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1552 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp348 unsigned Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
378 unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86MCInstLower.cpp2055 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0); in EmitInstruction() local
2086 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0); in EmitInstruction() local
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h613 uint16_t Reg0; variable
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCRegisterInfo.h739 uint16_t Reg0 = 0; variable

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