| /external/oboe/samples/RhythmGame/third_party/glm/simd/ |
| D | integer.h | 16 glm_uvec4 Reg1; in glm_i128_interleave() local
70 glm_uvec4 Reg1; in glm_i128_interleave2() local
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| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| D | Locked.cpp | 89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
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| /external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| D | Locked.cpp | 86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 506 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg()); in InsertSEH() local
519 Register Reg1 = MBBI->getOperand(2).getReg(); in InsertSEH() local
557 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
568 Register Reg1 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1867 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing()
1890 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing()
1906 unsigned Reg1 = AArch64::NoRegister; member
2131 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
2239 unsigned Reg1 = RPI.Reg1; in restoreCalleeSavedRegisters() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
217 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
223 void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRRX()
236 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
243 unsigned Reg1, int16_t Imm0, int16_t Imm1, in emitRRIII()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 769 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg()
789 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg()
800 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair()
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| D | MipsSEFrameLowering.cpp | 440 unsigned Reg1 = in emitPrologue() local
457 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr() local
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP() local
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| D | MipsAsmPrinter.cpp | 875 unsigned Opcode, unsigned Reg1, in EmitInstrRegReg()
895 unsigned Opcode, unsigned Reg1, in EmitInstrRegRegReg()
906 unsigned MovOpc, unsigned Reg1, in EmitMovFPIntPair()
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| D | MipsSEFrameLowering.cpp | 465 unsigned Reg1 = in emitPrologue() local
482 unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; in emitPrologue() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 875 unsigned Reg1; member
974 unsigned Reg1 = RPI.Reg1; in spillCalleeSavedRegisters() local
1037 unsigned Reg1 = RPI.Reg1; in restoreCalleeSavedRegisters() local
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 515 unsigned Reg1 = Reg; in lowerCRSpilling() local
560 unsigned Reg1 = Reg; in lowerCRRestore() local
604 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 144 unsigned Reg1, bool isKill1, in addRegReg()
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR()
168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX()
180 void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRR()
186 void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRI()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 668 unsigned Reg1 = Reg; in lowerCRSpilling() local
713 unsigned Reg1 = Reg; in lowerCRRestore() local
817 unsigned Reg1 = Reg; in lowerCRBitSpilling() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 165 unsigned Reg1, bool isKill1, in addRegReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 225 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 226 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg(); in tryInlineAsm() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 402 unsigned Reg1, in getOperandGatherWeight()
540 unsigned Reg1 = OperandMasks[I].Reg; in collectCandidates() local
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { in contains()
614 uint16_t Reg1; variable
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 77 bool contains(MCRegister Reg1, MCRegister Reg2) const { in contains()
740 uint16_t Reg1 = 0; variable
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1382 StringRef Reg1(R1); in processInstruction() local
1397 StringRef Reg1(R1); in processInstruction() local
1413 StringRef Reg1(R1); in processInstruction() local
1745 StringRef Reg1(R1); in processInstruction() local
1889 StringRef Reg1(R1); in processInstruction() local
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| /external/capstone/arch/ARM/ |
| D | ARMInstPrinter.c | 2468 unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1); in printVectorListTwo() local
2509 unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2); in printVectorListTwoSpaced() local
2681 unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1); in printVectorListTwoAllLanes() local
2828 unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2); in printVectorListTwoSpacedAllLanes() local
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1603 StringRef Reg1(R1); in processInstruction() local
1618 StringRef Reg1(R1); in processInstruction() local
1634 StringRef Reg1(R1); in processInstruction() local
1974 StringRef Reg1(R1); in processInstruction() local
2128 StringRef Reg1(R1); in processInstruction() local
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 447 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true); in generateCompactUnwindEncoding() local
|