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Searched defs:RegClass (Results 1 – 25 of 51) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp33 const TargetRegisterClass &RegClass) { in constrainRegToClass()
44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO, in constrainOperandRegClass()
79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
/external/mesa3d/src/amd/compiler/
Daco_ir.h253 struct RegClass { struct
255 enum RC : uint8_t {
284 constexpr RegClass(RC rc) in RegClass() argument
286 constexpr RegClass(RegType type, unsigned size) in RegClass() function
298 constexpr RegClass as_linear() const { return RegClass((RC) (rc | (1 << 6))); } in as_linear() argument
299 constexpr RegClass as_subdword() const { return RegClass((RC) (rc | 1 << 7)); } in as_subdword() argument
301 static constexpr RegClass get(RegType type, unsigned bytes) { in get() argument
/external/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp51 #define DECODE_OPERAND2(RegClass, DecName) \ argument
60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) argument
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h47 std::unique_ptr<RCInfo[]> RegClass; variable
/external/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h45 std::unique_ptr<RCInfo[]> RegClass; variable
DRegisterScavenging.h145 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyPeephole.cpp97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
DWebAssemblyRegStackify.cpp105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
609 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
/external/swiftshader/third_party/subzero/src/
DIceTypes.h36 enum RegClass : uint8_t { enum
/external/capstone/
DMCInstrDesc.h60 int16_t RegClass; member
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DRDFRegisters.h136 const TargetRegisterClass *RegClass = nullptr; member
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1598 SDValue RegClass = in createGPRPairNode() local
1609 SDValue RegClass = in createSRegPairNode() local
1620 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1631 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1643 SDValue RegClass = in createQuadSRegsNode() local
1658 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1673 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
DMachineRegisterInfo.cpp158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister()
/external/llvm/lib/CodeGen/
DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
DMachineRegisterInfo.cpp95 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUMachineCFGStructurizer.cpp1934 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
2001 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2061 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2176 const TargetRegisterClass *RegClass = in createEntryPHI() local
2314 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2451 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumb2InstrInfo.cpp483 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
DARMISelDAGToDAG.cpp1778 SDValue RegClass = in createGPRPairNode() local
1789 SDValue RegClass = in createSRegPairNode() local
1800 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1811 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1823 SDValue RegClass = in createQuadSRegsNode() local
1838 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1853 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
DARMBaseRegisterInfo.cpp814 const TargetRegisterClass *RegClass = in eliminateFrameIndex() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64LoadStoreOptimizer.cpp1286 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef() local
1416 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in tryToFindRegisterToRename() local
DAArch64AsmPrinter.cpp706 const TargetRegisterClass *RegClass; in PrintAsmOperand() local
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyRegStackify.cpp547 const auto *RegClass = MRI.getRegClass(Reg); in MoveAndTeeForMultiUse() local
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp200 int RegClass = Desc.OpInfo[OpIdx].RegClass; in getOperandRegClass() local
315 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select() local
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp1274 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
1334 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets() local

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