1 /* 2 * Copyright (C) 2009 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 18 #define ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 19 20 #include <stdint.h> 21 22 #include <iosfwd> 23 24 #include <android-base/logging.h> 25 26 #include "arch/arm/registers_arm.h" 27 #include "base/casts.h" 28 #include "base/globals.h" 29 #include "base/macros.h" 30 31 namespace art HIDDEN { 32 namespace arm { 33 34 // Defines constants and accessor classes to assemble, disassemble and 35 // simulate ARM instructions. 36 // 37 // Section references in the code refer to the "ARM Architecture 38 // Reference Manual ARMv7-A and ARMv7-R edition", issue C.b (24 July 39 // 2012). 40 // 41 // Constants for specific fields are defined in their respective named enums. 42 // General constants are in an anonymous enum in class Instr. 43 44 // 4 bits option for the dmb instruction. 45 // Order and values follows those of the ARM Architecture Reference Manual. 46 enum DmbOptions { 47 SY = 0xf, 48 ST = 0xe, 49 ISH = 0xb, 50 ISHST = 0xa, 51 NSH = 0x7, 52 NSHST = 0x6 53 }; 54 55 // Values for double-precision floating point registers. 56 enum DRegister { // private marker to avoid generate-operator-out.py from processing. 57 D0 = 0, 58 D1 = 1, 59 D2 = 2, 60 D3 = 3, 61 D4 = 4, 62 D5 = 5, 63 D6 = 6, 64 D7 = 7, 65 D8 = 8, 66 D9 = 9, 67 D10 = 10, 68 D11 = 11, 69 D12 = 12, 70 D13 = 13, 71 D14 = 14, 72 D15 = 15, 73 D16 = 16, 74 D17 = 17, 75 D18 = 18, 76 D19 = 19, 77 D20 = 20, 78 D21 = 21, 79 D22 = 22, 80 D23 = 23, 81 D24 = 24, 82 D25 = 25, 83 D26 = 26, 84 D27 = 27, 85 D28 = 28, 86 D29 = 29, 87 D30 = 30, 88 D31 = 31, 89 kNumberOfDRegisters = 32, 90 kNumberOfOverlappingDRegisters = 16, 91 kNoDRegister = -1, 92 }; 93 std::ostream& operator<<(std::ostream& os, const DRegister& rhs); 94 95 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) 96 // as defined in section A3.4 97 enum Opcode { 98 kNoOperand = -1, 99 AND = 0, // Logical AND 100 EOR = 1, // Logical Exclusive OR 101 SUB = 2, // Subtract 102 RSB = 3, // Reverse Subtract 103 ADD = 4, // Add 104 ADC = 5, // Add with Carry 105 SBC = 6, // Subtract with Carry 106 RSC = 7, // Reverse Subtract with Carry 107 TST = 8, // Test 108 TEQ = 9, // Test Equivalence 109 CMP = 10, // Compare 110 CMN = 11, // Compare Negated 111 ORR = 12, // Logical (inclusive) OR 112 MOV = 13, // Move 113 BIC = 14, // Bit Clear 114 MVN = 15, // Move Not 115 ORN = 16, // Logical OR NOT. 116 kMaxOperand = 17 117 }; 118 119 // Size (in bytes) of registers. 120 const int kRegisterSize = 4; 121 122 // List of registers used in load/store multiple. 123 using RegList = uint16_t; 124 125 } // namespace arm 126 } // namespace art 127 128 #endif // ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_ 129