| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallingConv.cpp | 33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs() local
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister() local
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
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| /external/llvm/utils/TableGen/ |
| D | CallingConvEmitter.cpp | 113 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
134 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.h | 31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
206 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
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| D | ARMBaseRegisterInfo.cpp | 64 const MCPhysReg *RegList = in getCalleeSavedRegs() local
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| D | ARMAsmPrinter.cpp | 1161 SmallVector<unsigned, 4> RegList; in EmitUnwindingInstruction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.cpp | 24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
199 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
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| D | Thumb2ITBlockPass.cpp | 83 using RegList = SmallVector<unsigned, 4>; in INITIALIZE_PASS() typedef
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| D | ARMBaseRegisterInfo.cpp | 68 const MCPhysReg *RegList = in getCalleeSavedRegs() local
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| D | ARMAsmPrinter.cpp | 1097 SmallVector<unsigned, 4> RegList; in EmitUnwindingInstruction() local
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| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.h | 53 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.h | 89 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.cpp | 90 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMTargetStreamer.cpp | 56 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
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| D | ARMELFStreamer.cpp | 137 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
649 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
1328 void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMTargetStreamer.cpp | 98 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
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| D | ARMELFStreamer.cpp | 157 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
749 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
1452 void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
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| /external/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 35 typedef SmallVector<unsigned, 4> RegList; typedef
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| /external/vixl/src/aarch64/ |
| D | registers-aarch64.h | 39 typedef uint64_t RegList; typedef
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 278 static const MCPhysReg RegList[] = { in AnalyzeArguments() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 469 ArrayRef<MCPhysReg> RegList; in AnalyzeArguments() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 979 const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8; in analyzeStandardArguments() local
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 56 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Split_64() local
84 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Ret_Split_64() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 58 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Split_64() local
86 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Ret_Split_64() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 2442 const SmallVectorImpl<unsigned> &RegList = getRegList(); in addRegListOperands() local
2450 const SmallVectorImpl<unsigned> &RegList = getRegList(); in addRegListWithAPSROperands() local
3840 const SmallVectorImpl<unsigned> &RegList = getRegList(); in print() local
7911 auto &RegList = Op.getRegList(); in validateInstruction() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 276 static const MCPhysReg RegList[] = { in CC_Hexagon32() local
|