| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
|
| D | MipsSEFrameLowering.cpp | 198 unsigned RegSize) { in expandLoadACC()
223 unsigned RegSize) { in expandStoreACC()
|
| D | MipsCallLowering.cpp | 505 unsigned RegSize = 4; in lowerFormalArguments() local
|
| /external/capstone/ |
| D | MCRegisterInfo.h | 36 uint16_t RegSize, Alignment; // Size & Alignment of register in bytes member
|
| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 222 unsigned RegSize = 0; in getInstrMappingImpl() local
372 unsigned RegSize = MRI.getSize(Reg); in getSizeInBits() local
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 133 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8; in AddMachineRegPiece() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 137 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 179 unsigned RegSize) { in expandLoadACC()
204 unsigned RegSize) { in expandStoreACC()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 482 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0; in getRegSizeInBits() local
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes variable
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1616 unsigned RegSize; in emitLogicalOp_ri() local
3946 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4053 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4174 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1703 unsigned RegSize; in emitLogicalOp_ri() local
4124 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4231 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4352 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
|
| D | AArch64FrameLowering.cpp | 2405 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 233 unsigned RegSize, SpillSize, SpillAlignment; member
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 746 unsigned RegSize, ImmLSB, ImmSize; member
|
| /external/clang/include/clang/Basic/ |
| D | TargetInfo.h | 692 unsigned RegSize, in validateGlobalRegisterVariable()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 146 int RegSize; in sizeOfSPAdjustment() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 918 unsigned RegSize = 0; member
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 3184 unsigned RegSize = PVT.getStoreSize(); in emitEHSjLjLongJmp() local
3237 unsigned RegSize = PVT.getStoreSize(); in emitEHSjLjSetJmp() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 190 int RegSize; in sizeOfSPAdjustment() local
|
| /external/clang/lib/Basic/ |
| D | Targets.cpp | 2641 unsigned RegSize, in validateGlobalRegisterVariable()
4386 unsigned RegSize, in validateGlobalRegisterVariable()
|
| /external/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 3764 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8); in EmitVAArg() local
4729 int RegSize = IsIndirect ? 8 : TyInfo.first.getQuantity(); in EmitAAPCSVAArg() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 807 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments() local
|