| /external/crosvm/hypervisor/src/ |
| D | x86_64.rs | 69 fn get_regs(&self) -> Result<Regs>; in get_regs()
670 pub struct Regs { struct
691 impl Default for Regs { argument
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 83 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
292 const unsigned *Regs) { in decodeBDAddr12Operand()
302 const unsigned *Regs) { in decodeBDAddr20Operand()
312 const unsigned *Regs) { in decodeBDXAddr12Operand()
324 const unsigned *Regs) { in decodeBDXAddr20Operand()
336 const unsigned *Regs) { in decodeBDLAddr12Len4Operand()
348 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
360 const unsigned *Regs) { in decodeBDRAddr12Operand()
372 const unsigned *Regs) { in decodeBDVAddr12Operand()
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| /external/capstone/arch/SystemZ/ |
| D | SystemZDisassembler.c | 39 static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsigned *Regs) in decodeRegisterClass()
258 const unsigned *Regs) in decodeBDAddr12Operand()
271 const unsigned *Regs) in decodeBDAddr20Operand()
283 const unsigned *Regs) in decodeBDXAddr12Operand()
298 const unsigned *Regs) in decodeBDXAddr20Operand()
313 const unsigned *Regs) in decodeBDLAddr12Len8Operand()
328 const unsigned *Regs) in decodeBDRAddr12Operand()
343 const unsigned *Regs) in decodeBDVAddr12Operand()
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| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 78 const unsigned *Regs, unsigned Size) { in decodeRegisterClass()
269 const unsigned *Regs) { in decodeBDAddr12Operand()
279 const unsigned *Regs) { in decodeBDAddr20Operand()
289 const unsigned *Regs) { in decodeBDXAddr12Operand()
301 const unsigned *Regs) { in decodeBDXAddr20Operand()
313 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
325 const unsigned *Regs) { in decodeBDVAddr12Operand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 212 [&](ArrayRef<Register> Regs) { in lowerReturn()
357 [&](ArrayRef<Register> Regs) { in lowerFormalArguments()
418 [&](ArrayRef<Register> Regs) { in lowerCall()
468 [&](ArrayRef<Register> Regs) { in lowerCall()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 332 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
359 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
373 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
400 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 344 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
371 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
385 unsigned AllocateRegBlock(ArrayRef<MCPhysReg> Regs, unsigned RegsRequired) { in AllocateRegBlock()
412 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MCA/ |
| D | HWEventListener.h | 74 HWInstructionDispatchedEvent(const InstRef &IR, ArrayRef<unsigned> Regs, in HWInstructionDispatchedEvent()
95 HWInstructionRetiredEvent(const InstRef &IR, ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
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| /external/llvm/utils/TableGen/ |
| D | RegisterInfoEmitter.cpp | 200 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
338 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
461 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
822 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1361 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1459 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
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| D | CodeGenRegisters.cpp | 160 RegUnitIterator(const CodeGenRegister::Vec &Regs): in RegUnitIterator()
939 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
1309 CodeGenRegister::Vec Regs; member
1338 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets() local
2101 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { in computeCoveredRegisters()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 127 static const unsigned Regs[2][2] = { in getFrameRegister() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUPALMetadata.cpp | 161 auto Regs = getRegisters(); in getRegister() local
555 auto Regs = getRegisters(); in toString() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 135 static const unsigned Regs[2][2] = { in getFrameRegister() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 972 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
981 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
990 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1028 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1194 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1212 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1266 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1305 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1360 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1390 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.cpp | 324 auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) { in makeRegRef()
334 BitVector Regs(PRI.getTRI().getNumRegs()); in makeRegRef() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1117 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
1135 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
1173 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1344 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1366 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1420 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1459 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1514 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1543 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 281 [&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { in lowerReturnVal()
491 ArrayRef<Register> Regs, in packSplitRegsToOrigType()
653 [&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) { in lowerFormalArguments()
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| D | SILoadStoreOptimizer.cpp | 520 const unsigned Regs = getRegs(I->getOpcode(), TII); in setMI() local
1236 const unsigned Regs = getRegs(Opcode, *TII); in mergeBufferLoadPair() local
1298 const unsigned Regs = getRegs(Opcode, *TII); in mergeTBufferLoadPair() local
1377 const unsigned Regs = getRegs(Opcode, *TII); in mergeTBufferStorePair() local
1539 const unsigned Regs = getRegs(Opcode, *TII); in mergeBufferStorePair() local
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| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 544 const unsigned *Regs, bool IsAddress) { in parseRegister()
561 const unsigned *Regs, RegisterKind Kind) { in parseRegister()
580 const MCExpr *&Length, const unsigned *Regs, in parseAddress()
641 const unsigned *Regs, RegisterKind RegKind) { in parseAddress()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 99 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { in INITIALIZE_PASS()
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DbgValueHistoryCalculator.cpp | 153 BitVector &Regs) { in collectChangingRegs()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | CallLowering.h | 47 SmallVector<Register, 4> Regs; member
|
| /external/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 86 static void removeRegsFromMap(Reg2MIMap &Map, const RegList &Regs, in removeRegsFromMap()
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| /external/crosvm/hypervisor/src/haxm/ |
| D | vcpu.rs | 407 fn get_regs(&self) -> Result<Regs> { in get_regs()
631 fn get_regs(&self) -> Regs { in get_regs()
696 fn set_regs(&mut self, regs: &Regs) { in set_regs()
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| /external/mesa3d/include/android_stub/backtrace/ |
| D | Backtrace.h | 103 class Regs; variable
|