| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 636 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
705 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
748 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
778 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
819 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP65GroupBranchMMR6() local
858 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP75GroupBranchMMR6() local
900 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
945 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/ |
| D | MSP430Disassembler.cpp | 154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode()
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRsRt() local
222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16() local
237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16Rel() local
259 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitFtRsImm16() local
285 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRdRsRt() local
528 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "clz"); in clz() local
656 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr"); in jalr() local
822 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "pseudo-move"); in move() local
841 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf"); in movf() local
876 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movt"); in movt() local
[all …]
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| D | IceAssemblerARM32.cpp | 344 IValueT Rs) { in encodeShiftRotateReg()
393 IValueT Rs; in encodeOperand() local
1129 IValueT Rn, IValueT Rm, IValueT Rs, in emitMulOp()
1718 IValueT Rs = encodeGPRegister(OpSrc1, "Rs", InstName); in emitShift() local
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 602 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
632 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
672 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
702 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
743 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
788 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
830 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzGroupBranch() local
879 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezGroupBranch() local
2287 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranchMMR6() local
2333 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranchMMR6() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1618 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1638 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1658 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1681 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1714 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1724 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1766 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1783 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1912 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1844 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1863 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1882 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1904 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1943 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1953 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1995 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
2014 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
2151 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 147 const USet &Rs = I.second; in isInduction() local
375 Register Rs = MI->getOperand(1).getReg(); in profit() local
477 USet &Rs) { in collectIndRegsForLoop()
584 USet Rs; in collectIndRegs() local
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| D | HexagonConstExtenders.cpp | 293 Register Rs; member
446 HCE::Register Rs; member
1504 Register Rs = ExtI.second.Rs; // Only one reg allowed now. in calculatePlacement() local
1783 Register Rs = MI.getOperand(IsSub ? 3 : 2); in replaceInstrExpr() local
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| D | HexagonAsmPrinter.cpp | 409 MCOperand &Rs = Inst.getOperand(1); in HexagonProcessInstruction() local
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| D | HexagonBitTracker.cpp | 297 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
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| D | HexagonBitSimplify.cpp | 1884 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
2018 BitTracker::RegisterRef Rs, Rt; in genPackhl() local
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| /external/capstone/arch/Mips/ |
| D | MipsDisassembler.c | 589 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch_4() local
625 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch_4() local
662 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch_4() local
704 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch_4() local
742 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzGroupBranch_4() local
788 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezGroupBranch_4() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVMergeBaseOffset.cpp | 138 Register Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 200 MCOperand Rs, Rt; in getCompoundInsn() local
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 207 MCOperand Rs, Rt; in getCompoundInsn() local
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| /external/eigen/Eigen/src/UmfPackSupport/ |
| D | UmfPackSupport.h | 218 … int P[], int Q[], double Dx[], int *do_recip, double Rs[], void *Numeric) in umfpack_get_numeric()
224 … int P[], int Q[], std::complex<double> Dx[], int *do_recip, double Rs[], void *Numeric) in umfpack_get_numeric()
233 …ong P[], SuiteSparse_long Q[], double Dx[], SuiteSparse_long *do_recip, double Rs[], void *Numeric) in umfpack_get_numeric()
239 …Sparse_long Q[], std::complex<double> Dx[], SuiteSparse_long *do_recip, double Rs[], void *Numeric) in umfpack_get_numeric()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSplitDouble.cpp | 122 const USet &Rs = I.second; in isInduction() local
431 USet &Rs) { in collectIndRegsForLoop()
537 USet Rs; in collectIndRegs() local
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| D | HexagonAsmPrinter.cpp | 365 MCOperand &Rs = Inst.getOperand(1); in HexagonProcessInstruction() local
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| D | HexagonBitTracker.cpp | 225 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate()
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| D | HexagonBitSimplify.cpp | 1782 const BitTracker::RegisterCell &RC, BitTracker::RegisterRef &Rs, in matchPackhl()
1914 BitTracker::RegisterRef Rs, Rt; in genPackhl() local
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| /external/cronet/buildtools/third_party/libc++/trunk/test/libcxx/ |
| D | nasty_macros.compile.pass.cpp | 125 #define Rs NASTY_MACRO macro
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| /external/mesa3d/src/mesa/swrast/ |
| D | s_blend.c | 480 const GLfloat Rs = rgba[i][RCOMP]; in blend_general_float() local
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| /external/capstone/arch/AArch64/ |
| D | AArch64Disassembler.c | 1188 unsigned Rs = fieldFromInstruction(insn, 16, 5); in DecodeExclusiveLdStInstruction() local
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1087 unsigned Rs = fieldFromInstruction(insn, 16, 5); in DecodeExclusiveLdStInstruction() local
|