1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 # 9 #ifndef NXP_TIMER_H 10 #define NXP_TIMER_H 11 12 /* System Counter Offset and Bit Mask */ 13 #define SYS_COUNTER_CNTCR_OFFSET 0x0 14 #define SYS_COUNTER_CNTCR_EN 0x00000001 15 #define CNTCR_EN_MASK 0x1 16 17 #ifndef __ASSEMBLER__ 18 uint64_t get_timer_val(uint64_t start); 19 20 #ifdef IMAGE_BL31 21 void ls_configure_sys_timer(uintptr_t ls_sys_timctl_base, 22 uint8_t ls_config_cntacr, 23 uint8_t plat_ls_ns_timer_frame_id); 24 void enable_init_timer(void); 25 #endif 26 27 /* 28 * Initialise the nxp on-chip free rolling usec counter as the delay 29 * timer. 30 */ 31 void delay_timer_init(uintptr_t nxp_timer_addr); 32 void ls_bl31_timer_init(uintptr_t nxp_timer_addr); 33 #endif /* __ASSEMBLER__ */ 34 35 #endif /* NXP_TIMER_H */ 36