1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __MTK_APUSYS_H__ 8 #define __MTK_APUSYS_H__ 9 10 #include <stdint.h> 11 12 /* setup the SMC command ops */ 13 #define MTK_SIP_APU_START_MCU 0x00U 14 #define MTK_SIP_APU_STOP_MCU 0x01U 15 16 /* AO Register */ 17 #define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00) 18 #define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04) 19 #define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08) 20 #define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10) 21 22 #define PRE_DEFINE_CACHE_TCM 0x3U 23 #define PRE_DEFINE_CACHE 0x2U 24 #define PRE_DEFINE_SHIFT_0G 0U 25 #define PRE_DEFINE_SHIFT_1G 2U 26 #define PRE_DEFINE_SHIFT_2G 4U 27 #define PRE_DEFINE_SHIFT_3G 6U 28 29 #define SEC_FW_NON_SECURE 1U 30 #define SEC_FW_SHIFT_NS 4U 31 #define SEC_FW_DOMAIN_SHIFT 0U 32 33 #define SYS_CTRL_RUN 0U 34 #define SYS_CTRL_STALL 1U 35 36 /* Reviser Register */ 37 #define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x300) 38 #define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x304) 39 40 uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, 41 uint32_t *ret1); 42 #endif /* __MTK_APUSYS_H__ */ 43