| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = in expandAtomicCmpSwapSubword() local
557 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
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| D | MipsISelLowering.cpp | 1638 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 516 unsigned ShiftImm; // shift for OffsetReg. member
526 unsigned ShiftImm; member
538 unsigned ShiftImm; member
544 unsigned ShiftImm; member
2650 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister()
2664 unsigned ShiftImm, SMLoc S, SMLoc E) { in CreateShiftedImmediate()
2805 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, in CreateMem()
2823 unsigned ShiftImm, SMLoc S, SMLoc E) { in CreatePostIdxReg()
4667 unsigned ShiftImm = 0; in parsePostIdxReg() local
4993 unsigned ShiftImm = 0; in parseMemory() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1277 unsigned ShiftImm; in emitAddSub_ri() local
1318 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs()
1359 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rx()
1514 uint64_t ShiftImm, bool WantResult) { in emitSubs_rs()
1653 uint64_t ShiftImm) { in emitLogicalOp_rs()
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| D | AArch64ISelDAGToDAG.cpp | 1526 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local
1662 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1360 unsigned ShiftImm; in emitAddSub_ri() local
1401 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs()
1444 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rx()
1601 uint64_t ShiftImm, bool WantResult) { in emitSubs_rs()
1740 uint64_t ShiftImm) { in emitLogicalOp_rs()
|
| D | AArch64ISelDAGToDAG.cpp | 1679 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local
1816 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local
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| D | AArch64InstructionSelector.cpp | 1066 Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); in getVectorSHLImm() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 787 unsigned ShiftImm; // shift for OffsetReg. member
797 unsigned ShiftImm; member
809 unsigned ShiftImm; member
815 unsigned ShiftImm; member
3461 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister()
3475 unsigned ShiftImm, SMLoc S, SMLoc E) { in CreateShiftedImmediate()
3627 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, in CreateMem()
3645 unsigned ShiftImm, SMLoc S, SMLoc E) { in CreatePostIdxReg()
5461 unsigned ShiftImm = 0; in parsePostIdxReg() local
5806 unsigned ShiftImm = 0; in parseMemory() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 501 unsigned ShiftImm = DefMI->getOperand(3).getImm(); in simplifyCode() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2780 unsigned ShiftImm; in SelectShift() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 957 unsigned Size, ShiftImm; in getMVEShiftImmOpValue() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2759 unsigned ShiftImm; in SelectShift() local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1218 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
|