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Searched defs:Src0 (Results 1 – 25 of 74) sorted by relevance

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/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringX8632.h444 void _adc(Variable *Dest, Operand *Src0) { in _adc()
450 void _add(Variable *Dest, Operand *Src0) { in _add()
456 void _addps(Variable *Dest, Operand *Src0) { in _addps()
459 void _addss(Variable *Dest, Operand *Src0) { in _addss()
463 void _and(Variable *Dest, Operand *Src0) { in _and()
466 void _andnps(Variable *Dest, Operand *Src0) { in _andnps()
469 void _andps(Variable *Dest, Operand *Src0) { in _andps()
475 void _blendvps(Variable *Dest, Operand *Src0, Operand *Src1) { in _blendvps()
492 void _bsf(Variable *Dest, Operand *Src0) { in _bsf()
495 void _bsr(Variable *Dest, Operand *Src0) { in _bsr()
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DIceTargetLoweringX8664.h440 void _adc(Variable *Dest, Operand *Src0) { in _adc()
446 void _add(Variable *Dest, Operand *Src0) { in _add()
452 void _addps(Variable *Dest, Operand *Src0) { in _addps()
455 void _addss(Variable *Dest, Operand *Src0) { in _addss()
459 void _and(Variable *Dest, Operand *Src0) { in _and()
462 void _andnps(Variable *Dest, Operand *Src0) { in _andnps()
465 void _andps(Variable *Dest, Operand *Src0) { in _andps()
471 void _blendvps(Variable *Dest, Operand *Src0, Operand *Src1) { in _blendvps()
488 void _bsf(Variable *Dest, Operand *Src0) { in _bsf()
491 void _bsr(Variable *Dest, Operand *Src0) { in _bsr()
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DIceTargetLoweringMIPS32.h166 void _add(Variable *Dest, Variable *Src0, Variable *Src1) { in _add()
170 void _addu(Variable *Dest, Variable *Src0, Variable *Src1) { in _addu()
174 void _and(Variable *Dest, Variable *Src0, Variable *Src1) { in _and()
188 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, in _br()
194 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, in _br()
199 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, in _br()
222 void _add_d(Variable *Dest, Variable *Src0, Variable *Src1) { in _add_d()
226 void _add_s(Variable *Dest, Variable *Src0, Variable *Src1) { in _add_s()
234 void _addiu(Variable *Dest, Variable *Src0, Operand *Src1, RelocOp Reloc) { in _addiu()
238 void _c_eq_d(Variable *Src0, Variable *Src1) { in _c_eq_d()
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DIceTargetLoweringARM32.h847 void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) { in _vadd()
850 void _vand(Variable *Dest, Variable *Src0, Variable *Src1) { in _vand()
853 InstARM32Vbsl *_vbsl(Variable *Dest, Variable *Src0, Variable *Src1) { in _vbsl()
856 void _vceq(Variable *Dest, Variable *Src0, Variable *Src1) { in _vceq()
859 InstARM32Vcge *_vcge(Variable *Dest, Variable *Src0, Variable *Src1) { in _vcge()
862 InstARM32Vcgt *_vcgt(Variable *Dest, Variable *Src0, Variable *Src1) { in _vcgt()
869 void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) { in _vdiv()
883 void _veor(Variable *Dest, Variable *Src0, Variable *Src1) { in _veor()
897 void _vmla(Variable *Dest, Variable *Src0, Variable *Src1) { in _vmla()
900 void _vmlap(Variable *Dest, Variable *Src0, Variable *Src1) { in _vmlap()
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DIceInstMIPS32.h409 Variable *Src0) { in create()
436 InstMIPS32TwoAddrFPR(Cfg *Func, Variable *Dest, Variable *Src0) in InstMIPS32TwoAddrFPR()
453 Variable *Src0) { in create()
480 InstMIPS32TwoAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0) in InstMIPS32TwoAddrGPR()
500 Variable *Src0, Variable *Src1) { in create()
527 InstMIPS32ThreeAddrFPR(Cfg *Func, Variable *Dest, Variable *Src0, in InstMIPS32ThreeAddrFPR()
549 Variable *Src0, Variable *Src1) { in create()
576 InstMIPS32ThreeAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, in InstMIPS32ThreeAddrGPR()
820 CfgNode *TargetFalse, Operand *Src0, in create()
828 CfgNode *TargetFalse, Operand *Src0, in create()
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DIceInstARM32.h770 InstARM32ThreeAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, in InstARM32ThreeAddrGPR()
795 static InstARM32ThreeAddrFP *create(Cfg *Func, Variable *Dest, Variable *Src0, in create()
821 InstARM32ThreeAddrFP(Cfg *Func, Variable *Dest, Variable *Src0, Operand *Src1) in InstARM32ThreeAddrFP()
846 Variable *Src0, Variable *Src1) { in create()
852 create(Cfg *Func, Variable *Dest, Variable *Src0, ConstantInteger32 *Src1) { in create()
861 InstARM32ThreeAddrSignAwareFP(Cfg *Func, Variable *Dest, Variable *Src0, in InstARM32ThreeAddrSignAwareFP()
875 static InstARM32FourAddrGPR *create(Cfg *Func, Variable *Dest, Variable *Src0, in create()
900 InstARM32FourAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, in InstARM32FourAddrGPR()
925 static InstARM32FourAddrFP *create(Cfg *Func, Variable *Dest, Variable *Src0, in create()
950 InstARM32FourAddrFP(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1) in InstARM32FourAddrFP()
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DIceTargetLoweringX8664.cpp666 Operand *&Src0, Operand *&Src1) { in canFoldLoadIntoBinaryInst()
720 Operand *Src0 = Arith->getSrc(0); in doLoadOpt() local
727 Operand *Src0 = Icmp->getSrc(0); in doLoadOpt() local
734 Operand *Src0 = Fcmp->getSrc(0); in doLoadOpt() local
741 Operand *Src0 = Select->getTrueOperand(); in doLoadOpt() local
749 auto *Src0 = llvm::dyn_cast<Variable>(Cast->getSrc(0)); in doLoadOpt() local
1349 bool TargetX8664::optimizeScalarMul(Variable *Dest, Operand *Src0, in optimizeScalarMul()
1661 Operand *Src0 = legalize(Instr->getSrc(0)); in lowerArithmetic() local
2200 Operand *Src0 = legalize(Cond, Legal_Reg | Legal_Mem); in lowerBr() local
2487 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerCast() local
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DIceTargetLoweringX8632.cpp657 Operand *&Src0, Operand *&Src1) { in canFoldLoadIntoBinaryInst()
710 Operand *Src0 = Arith->getSrc(0); in doLoadOpt() local
717 Operand *Src0 = Icmp->getSrc(0); in doLoadOpt() local
724 Operand *Src0 = Fcmp->getSrc(0); in doLoadOpt() local
731 Operand *Src0 = Select->getTrueOperand(); in doLoadOpt() local
739 auto *Src0 = llvm::dyn_cast<Variable>(Cast->getSrc(0)); in doLoadOpt() local
1426 bool TargetX8632::optimizeScalarMul(Variable *Dest, Operand *Src0, in optimizeScalarMul()
1738 Operand *Src0 = legalize(Instr->getSrc(0)); in lowerArithmetic() local
2384 Operand *Src0 = legalize(Cond, Legal_Reg | Legal_Mem); in lowerBr() local
2739 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerCast() local
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DIceTargetLowering.h523 auto *Src0 = thunk0(); in applyToThunkedArgs() local
532 auto *Src0 = thunk0(); in applyToThunkedArgs() local
542 auto *Src0 = thunk0(); in applyToThunkedArgs() local
DIceTargetLoweringARM32.cpp531 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
592 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
722 Operand *Src0 = Intrinsic->getArg(0); in genTargetHelperCallFor() local
2168 Variable *Src0 = Func->makeVariable(IceType_i1); in lowerInt1Arithmetic() local
2258 Operand *const Src0; member in Ice::ARM32::__anon63a690470a11::NumericOperandsBase
2398 Variable *Dest, Operand *Src0, in lowerInt64Arithmetic()
2902 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerArithmetic() local
3342 Operand *Src0 = Instr->getSrc(0); in lowerAssign() local
3710 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerCast() local
3959 Operand *Src0 = Instr->getSrc(0); in lowerCast() local
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DIceTargetLoweringMIPS32.cpp304 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
331 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
419 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
585 Operand *Src0 = Intrinsic->getArg(0); in genTargetHelperCallFor() local
737 Operand *Src0 = Intrinsic->getArg(0); in genTargetHelperCallFor() local
2137 Operand *Src0 = NumSrcs < 1 ? nullptr : CurInstr->getSrc(0); in postLowerLegalization() local
2418 Variable *Dest, Operand *Src0, in lowerInt64Arithmetic()
2714 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerArithmetic() local
3011 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerAssign() local
3023 Operand *Src0 = Instr->getSrc(0); in lowerAssign() local
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h1312 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, in buildAnd()
1327 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, in buildOr()
1333 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, in buildXor()
1341 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) { in buildNot()
1347 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) { in buildCTPOP()
1352 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) { in buildCTLZ()
1357 MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { in buildCTLZ_ZERO_UNDEF()
1362 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) { in buildCTTZ()
1367 MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { in buildCTTZ_ZERO_UNDEF()
1379 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, in buildFSub()
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DConstantFoldingMIRBuilder.h50 const SrcOp &Src0 = SrcOps[0]; variable
61 const SrcOp &Src0 = SrcOps[0]; variable
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DControlFlow.cpp17 #define TestJ(C, Near, Dest, Src0, Value0, Src1, Value1) \ in TEST_F() argument
39 #define TestImpl(Dst, Src0, Src1) \ in TEST_F() argument
DGPRArith.cpp33 #define TestSetCC(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \ in TEST_F() argument
57 #define TestImpl(Dest, Src0, Src1) \ in TEST_F() argument
709 #define TestImplRegReg(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, \ in TEST_F() argument
800 #define TestImplAddrReg(Inst0, Inst1, Value0, Src0, Src1, Value1, Op, Size) \ in TEST_F() argument
862 #define TestImplOp(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, Op, \ in TEST_F() argument
873 #define TestImplValues(Dst0, Dst1, Value0, Src0, Src1, Value1, Size) \ in TEST_F() argument
879 #define TestImplSize(Dst0, Dst1, Src0, Src1, Size) \ in TEST_F() argument
885 #define TestImpl(Dst0, Dst1, Src0, Src1) \ in TEST_F() argument
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp158 Register Src0 = in runOnMachineFunction() local
210 Register Src0 = in runOnMachineFunction() local
DSIPeepholeSDWA.cpp563 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
604 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
673 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
690 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
1031 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA() local
DSIShrinkInstructions.cpp78 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
321 MachineOperand *Src0 = &MI.getOperand(1); in shrinkScalarLogicOp() local
635 MachineOperand *Src0 = &MI.getOperand(1); in runOnMachineFunction() local
DSIFoldOperands.cpp1004 MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx)); in tryConstantFoldOp() local
1108 const MachineOperand *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in tryFoldInst() local
1274 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isClamp() local
1390 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod() local
1419 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isOMod() local
DSIInstrInfo.cpp1631 MachineOperand &Src0, in swapSourceModifiers()
1690 MachineOperand &Src0 = MI.getOperand(Src0Idx); in commuteInstructionImpl() local
2367 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0); in FoldImmediate() local
2640 const MachineOperand *Src0 = &MI.getOperand(Src0Idx); in convertToThreeAddress() local
2652 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); in convertToThreeAddress() local
3525 const MachineOperand &Src0 = MI.getOperand(Src0Idx); in verifyInstruction() local
3538 const MachineOperand &Src0 = MI.getOperand(Src0Idx); in verifyInstruction() local
3612 const MachineOperand &Src0 = MI.getOperand(Src0Idx); in verifyInstruction() local
4027 MachineOperand &Src0 = MI.getOperand(Src0Idx); in legalizeOperandsVOP2() local
4633 Register Src0 = MI.getOperand(1).getReg(); in legalizeOperands() local
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/external/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp222 unsigned Src0 = BMI->getOperand( in runOnMachineFunction() local
274 unsigned Src0 = MI.getOperand( in runOnMachineFunction() local
DSIShrinkInstructions.cpp139 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
276 const MachineOperand &Src0 = MI.getOperand(1); in runOnMachineFunction() local
DSIInstrInfo.cpp889 unsigned Src0 = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
954 MachineOperand &Src0 = MI.getOperand(Src0Idx); in commuteInstructionImpl() local
1239 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0); in FoldImmediate() local
1425 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); in convertToThreeAddress() local
1433 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); in convertToThreeAddress() local
1760 const MachineOperand &Src0 = MI.getOperand(Src0Idx); in verifyInstruction() local
2066 MachineOperand &Src0 = MI.getOperand(Src0Idx); in legalizeOperandsVOP2() local
2087 MachineOperand &Src0 = MI.getOperand(Src0Idx); in legalizeOperandsVOP2() local
2312 unsigned Src0 = MI.getOperand(1).getReg(); in legalizeOperands() local
2703 MachineOperand &Src0 = Inst.getOperand(1); in splitScalar64BitUnaryOp() local
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/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DControlFlow.cpp18 #define TestJ(C, Near, Src0, Value0, Src1, Value1, Dest) \ in TEST_F() argument
DGPRArith.cpp48 #define TestSetCC(C, Src0, Value0, Src1, Value1, Dest, IsTrue) \ in TEST_F() argument
678 #define TestImplRegReg(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, \ in TEST_F() argument
773 #define TestImplAddrReg(Inst0, Inst1, Value0, Src0, Src1, Value1, Op, Size) \ in TEST_F() argument
837 #define TestImplOp(Inst0, Inst1, Dst0, Dst1, Value0, Src0, Src1, Value1, Op, \ in TEST_F() argument
848 #define TestImplValues(Dst0, Dst1, Value0, Src0, Src1, Value1, Size) \ in TEST_F() argument
854 #define TestImplSize(Dst0, Dst1, Src0, Src1, Size) \ in TEST_F() argument
860 #define TestImpl(Dst0, Dst1, Src0, Src1) \ in TEST_F() argument

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