| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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| D | HexagonMCCompound.cpp | 84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCompound.cpp | 80 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
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| D | HexagonMCDuplexInfo.cpp | 191 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZPostRewrite.cpp | 111 Register Src1Reg = MBBI->getOperand(1).getReg(); in selectSELRMux() local
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 278 unsigned Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 275 Register Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1139 unsigned Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1163 unsigned Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1193 unsigned Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
3304 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
3638 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1177 Register Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1201 Register Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
3294 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
3726 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 415 Register Src1Reg = I.getOperand(3).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
590 Register Src1Reg = I.getOperand(2).getReg(); in selectG_INSERT() local
653 Register Src1Reg = I.getOperand(3).getReg(); in selectG_INTRINSIC() local
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| D | AMDGPURegisterBankInfo.cpp | 2995 Register Src1Reg = MI.getOperand(3).getReg(); in getInstrMapping() local
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| D | SIInstrInfo.cpp | 2408 Register Src1Reg = Src1->getReg(); in FoldImmediate() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1047 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
1942 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectDivRem() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 994 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
1685 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectDivRem() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 1102 Register Src1Reg = I.getOperand(1).getReg(); in selectVectorSHL() local
1140 Register Src1Reg = I.getOperand(1).getReg(); in selectVectorASHR() local
2822 Register Src1Reg = I.getOperand(1).getReg(); in selectMergeValues() local
3777 Register Src1Reg = I.getOperand(1).getReg(); in selectShuffleVector() local
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| D | AArch64FastISel.cpp | 2689 unsigned Src1Reg = getRegForValue(Src1Val); in optimizeSelect() local
2819 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
4666 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectRem() local
4744 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectMul() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2558 unsigned Src1Reg = getRegForValue(Src1Val); in optimizeSelect() local
2688 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
4487 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectRem() local
4565 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectMul() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1265 unsigned Src1Reg = Src1->getReg(); in FoldImmediate() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 4200 Register Src1Reg = MI.getOperand(2).getReg(); in lowerShuffleVector() local
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