| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ | 
| D | RDFCopy.cpp | 47       RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());  in interpretAsCopy()  local
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| D | HexagonRDFOpt.cpp | 113   auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void {  in INITIALIZE_PASS_DEPENDENCY()
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| D | HexagonFrameLowering.cpp | 1608   Register SrcR = MI->getOperand(1).getReg();  in expandCopy()  local1632   Register SrcR = MI->getOperand(2).getReg();  in expandStoreInt()  local
 1695   Register SrcR = MI->getOperand(2).getReg();  in expandStoreVecPred()  local
 1782   Register SrcR = MI->getOperand(2).getReg();  in expandStoreVec2()  local
 1882   Register SrcR = MI->getOperand(2).getReg();  in expandStoreVec()  local
 
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| D | HexagonGenInsert.cpp | 471     unsigned SrcR, InsR;  member487     unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR;  in operator <<()  local
 684 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR,  in isValidInsertForm()
 881     unsigned SrcR = *I;  in findRecordInsertForms()  local
 
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| D | HexagonBitSimplify.cpp | 2210   unsigned SrcR = B0.RefI.Reg;  in genBitSplit()  local
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| D | HexagonConstPropagation.cpp | 1944     RegisterSubReg SrcR(MI.getOperand(1));  in evaluate()  local
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| /external/llvm/lib/Target/Hexagon/ | 
| D | RDFCopy.cpp | 36       RegisterRef SrcR = { Src.getReg(), Src.getSubReg() };  in interpretAsCopy()  local
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| D | HexagonRDFOpt.cpp | 98   auto mapRegs = [MI,&EM] (RegisterRef DstR, RegisterRef SrcR) -> void {  in interpretAsCopy()
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| D | HexagonFrameLowering.cpp | 1381   unsigned SrcR = MI->getOperand(1).getReg();  in expandCopy()  local1403   unsigned SrcR = MI->getOperand(2).getReg();  in expandStoreInt()  local
 1466   unsigned SrcR = MI->getOperand(2).getReg();  in expandStoreVecPred()  local
 1549   unsigned SrcR = MI->getOperand(2).getReg();  in expandStoreVec2()  local
 1653   unsigned SrcR = MI->getOperand(2).getReg();  in expandStoreVec()  local
 
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| D | HexagonGenInsert.cpp | 433     unsigned SrcR, InsR;  member447     unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR;  in operator <<()  local
 637 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR,  in isValidInsertForm()
 839     unsigned SrcR = *I;  in findRecordInsertForms()  local
 
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| /external/llvm/lib/Target/X86/ | 
| D | X86FixupLEAs.cpp | 388     const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3);  in processInstructionForSLM()  local
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| /external/swiftshader/third_party/subzero/src/ | 
| D | IceTargetLoweringMIPS32.cpp | 1812     Variable *SrcR;  in legalizeMovFp()  local1843   auto *SrcR = llvm::cast<Variable>(Src);  in legalizeMov()  local
 1933     auto *SrcR = llvm::cast<Variable>(Src);  in legalizeMov()  local
 3038   Operand *SrcR;  in lowerAssign()  local
 4886       auto *SrcR = legalizeToReg(Src);  in lowerIntrinsic()  local
 4902       auto *SrcR = legalizeToReg(Src);  in lowerIntrinsic()  local
 4979       auto *SrcR = legalizeToReg(Src);  in lowerIntrinsic()  local
 5019       auto *SrcR = legalizeToReg(Src);  in lowerIntrinsic()  local
 
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| D | IceTargetLoweringARM32.cpp | 1692     auto *SrcR = llvm::cast<Variable>(Src);  in legalizeMov()  local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ | 
| D | X86FixupLEAs.cpp | 517     const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index;  in processInstructionForSlowLEA()  local
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