| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 180 unsigned &SrcReg2, int &CmpMask, in analyzeCompare()
208 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr()
286 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 178 unsigned &SrcReg2, int &CmpMask, in analyzeCompare()
206 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr()
284 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int /*CmpMask*/, in optimizeCompareInstr()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 407 unsigned SrcReg2 = in fuseCompareOperations() local
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| D | SystemZInstrInfo.cpp | 433 unsigned &SrcReg2, int &Mask, in analyzeCompare()
515 MachineInstr &Compare, unsigned SrcReg, unsigned SrcReg2, int Mask, in optimizeCompareInstr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SIMDInstrOpt.cpp | 438 Register SrcReg2 = MI.getOperand(3).getReg(); in optimizeVectElement() local
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| D | AArch64InstrInfo.cpp | 988 unsigned &SrcReg2, int &CmpMask, in analyzeCompare()
1183 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr()
4184 unsigned SrcReg2; in genFusedMultiply() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1166 unsigned &SrcReg2, int &Mask, int &Value) const { in analyzeCompare()
1174 unsigned SrcReg2, int Mask, int Value, in optimizeCompareInstr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 631 Register SrcReg2 = in fuseCompareOperations() local
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| D | SystemZInstrInfo.cpp | 517 unsigned &SrcReg2, int &Mask, in analyzeCompare()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 1500 unsigned &SrcReg2, int &Mask, in analyzeCompare()
1528 unsigned SrcReg2, int Mask, int Value, in optimizeCompareInstr()
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| D | PPCFastISel.cpp | 876 unsigned SrcReg2 = 0; in PPCEmitCmp() local
1262 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 693 unsigned &SrcReg2, int &CmpMask, in analyzeCompare()
883 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr()
3294 unsigned SrcReg2 = Root.getOperand(IdxOtherOpd).getReg(); in genFusedMultiply() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1398 unsigned &SrcReg2, int &Mask, int &Value) const { in analyzeCompare()
1406 unsigned SrcReg2, int Mask, int Value, in optimizeCompareInstr()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 857 unsigned SrcReg2 = 0; in PPCEmitCmp() local
1359 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
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| D | PPCInstrInfo.cpp | 1591 unsigned &SrcReg2, int &Mask, in analyzeCompare()
1621 unsigned SrcReg2, int Mask, int Value, in optimizeCompareInstr()
4125 Register SrcReg2 = MI.getOperand(2).getReg(); in isSignOrZeroExtended() local
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 2928 unsigned SrcReg2; in convertToThreeAddress() local
4828 unsigned &SrcReg2, int &CmpMask, in analyzeCompare()
4907 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr()
5045 unsigned SrcReg2, int CmpMask, in optimizeCompareInstr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 2675 unsigned &SrcReg2, int &CmpMask, in analyzeCompare()
2746 unsigned SrcReg, unsigned SrcReg2, in isRedundantFlagInstr()
2882 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr()
3169 unsigned SrcReg, SrcReg2; in shouldSink() local
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| D | ARMFastISel.cpp | 1428 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1776 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 2288 unsigned &SrcReg2, int &CmpMask, in analyzeCompare()
2362 unsigned SrcReg2, int ImmValue, in isRedundantFlagInstr()
2392 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, in optimizeCompareInstr()
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| D | ARMFastISel.cpp | 1425 unsigned SrcReg2 = 0; in ARMEmitCmp() local
1763 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); in SelectBinaryIntOp() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 1053 Register SrcReg2; in convertToThreeAddress() local
3274 unsigned &SrcReg2, int &CmpMask, in analyzeCompare()
3361 unsigned SrcReg, unsigned SrcReg2, in isRedundantFlagInstr()
3551 unsigned SrcReg2, int CmpMask, in optimizeCompareInstr()
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_program_alu.c | 83 struct rc_src_register SrcReg2) in emit3()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 565 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 610 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1524 unsigned &SrcReg2, int &Mask, in analyzeCompare()
|