| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 239 void addSource(unsigned SrcReg, unsigned SrcSubReg) { in addSource()
243 void setSource(int Idx, unsigned SrcReg, unsigned SrcSubReg) { in setSource()
778 virtual bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg, in getNextRewritableSource()
900 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg, in getNextRewritableSource()
982 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg, in getNextRewritableSource()
1030 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg, in getNextRewritableSource()
1102 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg, in getNextRewritableSource()
1200 unsigned SrcReg, SrcSubReg, TrackReg, TrackSubReg; in optimizeCoalescableCopy() local
1397 unsigned SrcSubReg = MI->getOperand(1).getSubReg(); in foldRedundantCopy() local
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| D | PHIElimination.cpp | 361 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg(); in LowerPHINode() local
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| D | TargetRegisterInfo.cpp | 293 unsigned SrcSubReg) { in shareSameRegisterFile()
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| D | TailDuplicator.cpp | 312 unsigned SrcSubReg = MI->getOperand(SrcOpIdx).getSubReg(); in processPHI() local
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| D | RegisterCoalescer.cpp | 2836 unsigned DstReg, DstSubReg, SrcReg, SrcSubReg; in applyTerminalRule() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 218 unsigned SrcSubReg = MI.getOperand(I).getSubReg(); in foldVGPRCopyIntoRegSequence() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 308 void addSource(unsigned SrcReg, unsigned SrcSubReg) { in addSource()
312 void setSource(int Idx, unsigned SrcReg, unsigned SrcSubReg) { in setSource()
1412 unsigned SrcSubReg = MI.getOperand(1).getSubReg(); in foldRedundantCopy() local
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| D | PHIElimination.cpp | 377 unsigned SrcSubReg = MPhi->getOperand(i*2+1).getSubReg(); in LowerPHINode() local
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| D | TargetRegisterInfo.cpp | 346 unsigned SrcSubReg) { in shareSameRegisterFile()
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| D | TailDuplicator.cpp | 354 unsigned SrcSubReg = MI->getOperand(SrcOpIdx).getSubReg(); in processPHI() local
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| D | RegisterCoalescer.cpp | 3704 unsigned DstReg, DstSubReg, SrcReg, SrcSubReg; in applyTerminalRule() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 290 unsigned SrcSubReg = MI.getOperand(I).getSubReg(); in foldVGPRCopyIntoRegSequence() local
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| D | SIInstrInfo.cpp | 6578 const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const { in createPHISourceCopy()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1744 unsigned SrcSubReg, in createPHISourceCopy()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 6579 Register SrcSubReg = TRI->getSubReg(SrcReg, AArch64::sub_32); in describeORRLoadedValue() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 7577 unsigned SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx); in describeMOVrrLoadedValue() local
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