1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _ASM_X86_KVM_H 20 #define _ASM_X86_KVM_H 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #define KVM_PIO_PAGE_OFFSET 1 24 #define KVM_COALESCED_MMIO_PAGE_OFFSET 2 25 #define KVM_DIRTY_LOG_PAGE_OFFSET 64 26 #define DE_VECTOR 0 27 #define DB_VECTOR 1 28 #define BP_VECTOR 3 29 #define OF_VECTOR 4 30 #define BR_VECTOR 5 31 #define UD_VECTOR 6 32 #define NM_VECTOR 7 33 #define DF_VECTOR 8 34 #define TS_VECTOR 10 35 #define NP_VECTOR 11 36 #define SS_VECTOR 12 37 #define GP_VECTOR 13 38 #define PF_VECTOR 14 39 #define MF_VECTOR 16 40 #define AC_VECTOR 17 41 #define MC_VECTOR 18 42 #define XM_VECTOR 19 43 #define VE_VECTOR 20 44 #define __KVM_HAVE_PIT 45 #define __KVM_HAVE_IOAPIC 46 #define __KVM_HAVE_IRQ_LINE 47 #define __KVM_HAVE_MSI 48 #define __KVM_HAVE_USER_NMI 49 #define __KVM_HAVE_GUEST_DEBUG 50 #define __KVM_HAVE_MSIX 51 #define __KVM_HAVE_MCE 52 #define __KVM_HAVE_PIT_STATE2 53 #define __KVM_HAVE_XEN_HVM 54 #define __KVM_HAVE_VCPU_EVENTS 55 #define __KVM_HAVE_DEBUGREGS 56 #define __KVM_HAVE_XSAVE 57 #define __KVM_HAVE_XCRS 58 #define __KVM_HAVE_READONLY_MEM 59 #define KVM_NR_INTERRUPTS 256 60 struct kvm_pic_state { 61 __u8 last_irr; 62 __u8 irr; 63 __u8 imr; 64 __u8 isr; 65 __u8 priority_add; 66 __u8 irq_base; 67 __u8 read_reg_select; 68 __u8 poll; 69 __u8 special_mask; 70 __u8 init_state; 71 __u8 auto_eoi; 72 __u8 rotate_on_auto_eoi; 73 __u8 special_fully_nested_mode; 74 __u8 init4; 75 __u8 elcr; 76 __u8 elcr_mask; 77 }; 78 #define KVM_IOAPIC_NUM_PINS 24 79 struct kvm_ioapic_state { 80 __u64 base_address; 81 __u32 ioregsel; 82 __u32 id; 83 __u32 irr; 84 __u32 pad; 85 union { 86 __u64 bits; 87 struct { 88 __u8 vector; 89 __u8 delivery_mode : 3; 90 __u8 dest_mode : 1; 91 __u8 delivery_status : 1; 92 __u8 polarity : 1; 93 __u8 remote_irr : 1; 94 __u8 trig_mode : 1; 95 __u8 mask : 1; 96 __u8 reserve : 7; 97 __u8 reserved[4]; 98 __u8 dest_id; 99 } fields; 100 } redirtbl[KVM_IOAPIC_NUM_PINS]; 101 }; 102 #define KVM_IRQCHIP_PIC_MASTER 0 103 #define KVM_IRQCHIP_PIC_SLAVE 1 104 #define KVM_IRQCHIP_IOAPIC 2 105 #define KVM_NR_IRQCHIPS 3 106 #define KVM_RUN_X86_SMM (1 << 0) 107 #define KVM_RUN_X86_BUS_LOCK (1 << 1) 108 struct kvm_regs { 109 __u64 rax, rbx, rcx, rdx; 110 __u64 rsi, rdi, rsp, rbp; 111 __u64 r8, r9, r10, r11; 112 __u64 r12, r13, r14, r15; 113 __u64 rip, rflags; 114 }; 115 #define KVM_APIC_REG_SIZE 0x400 116 struct kvm_lapic_state { 117 char regs[KVM_APIC_REG_SIZE]; 118 }; 119 struct kvm_segment { 120 __u64 base; 121 __u32 limit; 122 __u16 selector; 123 __u8 type; 124 __u8 present, dpl, db, s, l, g, avl; 125 __u8 unusable; 126 __u8 padding; 127 }; 128 struct kvm_dtable { 129 __u64 base; 130 __u16 limit; 131 __u16 padding[3]; 132 }; 133 struct kvm_sregs { 134 struct kvm_segment cs, ds, es, fs, gs, ss; 135 struct kvm_segment tr, ldt; 136 struct kvm_dtable gdt, idt; 137 __u64 cr0, cr2, cr3, cr4, cr8; 138 __u64 efer; 139 __u64 apic_base; 140 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; 141 }; 142 struct kvm_sregs2 { 143 struct kvm_segment cs, ds, es, fs, gs, ss; 144 struct kvm_segment tr, ldt; 145 struct kvm_dtable gdt, idt; 146 __u64 cr0, cr2, cr3, cr4, cr8; 147 __u64 efer; 148 __u64 apic_base; 149 __u64 flags; 150 __u64 pdptrs[4]; 151 }; 152 #define KVM_SREGS2_FLAGS_PDPTRS_VALID 1 153 struct kvm_fpu { 154 __u8 fpr[8][16]; 155 __u16 fcw; 156 __u16 fsw; 157 __u8 ftwx; 158 __u8 pad1; 159 __u16 last_opcode; 160 __u64 last_ip; 161 __u64 last_dp; 162 __u8 xmm[16][16]; 163 __u32 mxcsr; 164 __u32 pad2; 165 }; 166 struct kvm_msr_entry { 167 __u32 index; 168 __u32 reserved; 169 __u64 data; 170 }; 171 struct kvm_msrs { 172 __u32 nmsrs; 173 __u32 pad; 174 struct kvm_msr_entry entries[]; 175 }; 176 struct kvm_msr_list { 177 __u32 nmsrs; 178 __u32 indices[]; 179 }; 180 #define KVM_MSR_FILTER_MAX_BITMAP_SIZE 0x600 181 struct kvm_msr_filter_range { 182 #define KVM_MSR_FILTER_READ (1 << 0) 183 #define KVM_MSR_FILTER_WRITE (1 << 1) 184 #define KVM_MSR_FILTER_RANGE_VALID_MASK (KVM_MSR_FILTER_READ | KVM_MSR_FILTER_WRITE) 185 __u32 flags; 186 __u32 nmsrs; 187 __u32 base; 188 __u8 * bitmap; 189 }; 190 #define KVM_MSR_FILTER_MAX_RANGES 16 191 struct kvm_msr_filter { 192 #define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0) 193 #define KVM_MSR_FILTER_DEFAULT_DENY (1 << 0) 194 #define KVM_MSR_FILTER_VALID_MASK (KVM_MSR_FILTER_DEFAULT_DENY) 195 __u32 flags; 196 struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES]; 197 }; 198 struct kvm_cpuid_entry { 199 __u32 function; 200 __u32 eax; 201 __u32 ebx; 202 __u32 ecx; 203 __u32 edx; 204 __u32 padding; 205 }; 206 struct kvm_cpuid { 207 __u32 nent; 208 __u32 padding; 209 struct kvm_cpuid_entry entries[]; 210 }; 211 struct kvm_cpuid_entry2 { 212 __u32 function; 213 __u32 index; 214 __u32 flags; 215 __u32 eax; 216 __u32 ebx; 217 __u32 ecx; 218 __u32 edx; 219 __u32 padding[3]; 220 }; 221 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0) 222 #define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1) 223 #define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2) 224 struct kvm_cpuid2 { 225 __u32 nent; 226 __u32 padding; 227 struct kvm_cpuid_entry2 entries[]; 228 }; 229 struct kvm_pit_channel_state { 230 __u32 count; 231 __u16 latched_count; 232 __u8 count_latched; 233 __u8 status_latched; 234 __u8 status; 235 __u8 read_state; 236 __u8 write_state; 237 __u8 write_latch; 238 __u8 rw_mode; 239 __u8 mode; 240 __u8 bcd; 241 __u8 gate; 242 __s64 count_load_time; 243 }; 244 struct kvm_debug_exit_arch { 245 __u32 exception; 246 __u32 pad; 247 __u64 pc; 248 __u64 dr6; 249 __u64 dr7; 250 }; 251 #define KVM_GUESTDBG_USE_SW_BP 0x00010000 252 #define KVM_GUESTDBG_USE_HW_BP 0x00020000 253 #define KVM_GUESTDBG_INJECT_DB 0x00040000 254 #define KVM_GUESTDBG_INJECT_BP 0x00080000 255 #define KVM_GUESTDBG_BLOCKIRQ 0x00100000 256 struct kvm_guest_debug_arch { 257 __u64 debugreg[8]; 258 }; 259 struct kvm_pit_state { 260 struct kvm_pit_channel_state channels[3]; 261 }; 262 #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001 263 #define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002 264 struct kvm_pit_state2 { 265 struct kvm_pit_channel_state channels[3]; 266 __u32 flags; 267 __u32 reserved[9]; 268 }; 269 struct kvm_reinject_control { 270 __u8 pit_reinject; 271 __u8 reserved[31]; 272 }; 273 #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001 274 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002 275 #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004 276 #define KVM_VCPUEVENT_VALID_SMM 0x00000008 277 #define KVM_VCPUEVENT_VALID_PAYLOAD 0x00000010 278 #define KVM_VCPUEVENT_VALID_TRIPLE_FAULT 0x00000020 279 #define KVM_X86_SHADOW_INT_MOV_SS 0x01 280 #define KVM_X86_SHADOW_INT_STI 0x02 281 struct kvm_vcpu_events { 282 struct { 283 __u8 injected; 284 __u8 nr; 285 __u8 has_error_code; 286 __u8 pending; 287 __u32 error_code; 288 } exception; 289 struct { 290 __u8 injected; 291 __u8 nr; 292 __u8 soft; 293 __u8 shadow; 294 } interrupt; 295 struct { 296 __u8 injected; 297 __u8 pending; 298 __u8 masked; 299 __u8 pad; 300 } nmi; 301 __u32 sipi_vector; 302 __u32 flags; 303 struct { 304 __u8 smm; 305 __u8 pending; 306 __u8 smm_inside_nmi; 307 __u8 latched_init; 308 } smi; 309 struct { 310 __u8 pending; 311 } triple_fault; 312 __u8 reserved[26]; 313 __u8 exception_has_payload; 314 __u64 exception_payload; 315 }; 316 struct kvm_debugregs { 317 __u64 db[4]; 318 __u64 dr6; 319 __u64 dr7; 320 __u64 flags; 321 __u64 reserved[9]; 322 }; 323 struct kvm_xsave { 324 __u32 region[1024]; 325 __u32 extra[]; 326 }; 327 #define KVM_MAX_XCRS 16 328 struct kvm_xcr { 329 __u32 xcr; 330 __u32 reserved; 331 __u64 value; 332 }; 333 struct kvm_xcrs { 334 __u32 nr_xcrs; 335 __u32 flags; 336 struct kvm_xcr xcrs[KVM_MAX_XCRS]; 337 __u64 padding[16]; 338 }; 339 #define KVM_SYNC_X86_REGS (1UL << 0) 340 #define KVM_SYNC_X86_SREGS (1UL << 1) 341 #define KVM_SYNC_X86_EVENTS (1UL << 2) 342 #define KVM_SYNC_X86_VALID_FIELDS (KVM_SYNC_X86_REGS | KVM_SYNC_X86_SREGS | KVM_SYNC_X86_EVENTS) 343 struct kvm_sync_regs { 344 struct kvm_regs regs; 345 struct kvm_sregs sregs; 346 struct kvm_vcpu_events events; 347 }; 348 #define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0) 349 #define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1) 350 #define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2) 351 #define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3) 352 #define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4) 353 #define KVM_X86_QUIRK_FIX_HYPERCALL_INSN (1 << 5) 354 #define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS (1 << 6) 355 #define KVM_STATE_NESTED_FORMAT_VMX 0 356 #define KVM_STATE_NESTED_FORMAT_SVM 1 357 #define KVM_STATE_NESTED_GUEST_MODE 0x00000001 358 #define KVM_STATE_NESTED_RUN_PENDING 0x00000002 359 #define KVM_STATE_NESTED_EVMCS 0x00000004 360 #define KVM_STATE_NESTED_MTF_PENDING 0x00000008 361 #define KVM_STATE_NESTED_GIF_SET 0x00000100 362 #define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001 363 #define KVM_STATE_NESTED_SMM_VMXON 0x00000002 364 #define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000 365 #define KVM_STATE_NESTED_SVM_VMCB_SIZE 0x1000 366 #define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001 367 #define KVM_X86_XCOMP_GUEST_SUPP 0 368 struct kvm_vmx_nested_state_data { 369 __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; 370 __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; 371 }; 372 struct kvm_vmx_nested_state_hdr { 373 __u64 vmxon_pa; 374 __u64 vmcs12_pa; 375 struct { 376 __u16 flags; 377 } smm; 378 __u16 pad; 379 __u32 flags; 380 __u64 preemption_timer_deadline; 381 }; 382 struct kvm_svm_nested_state_data { 383 __u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE]; 384 }; 385 struct kvm_svm_nested_state_hdr { 386 __u64 vmcb_pa; 387 }; 388 struct kvm_nested_state { 389 __u16 flags; 390 __u16 format; 391 __u32 size; 392 union { 393 struct kvm_vmx_nested_state_hdr vmx; 394 struct kvm_svm_nested_state_hdr svm; 395 __u8 pad[120]; 396 } hdr; 397 union { 398 struct kvm_vmx_nested_state_data vmx[0]; 399 struct kvm_svm_nested_state_data svm[0]; 400 } data; 401 }; 402 struct kvm_pmu_event_filter { 403 __u32 action; 404 __u32 nevents; 405 __u32 fixed_counter_bitmap; 406 __u32 flags; 407 __u32 pad[4]; 408 __u64 events[]; 409 }; 410 #define KVM_PMU_EVENT_ALLOW 0 411 #define KVM_PMU_EVENT_DENY 1 412 #define KVM_VCPU_TSC_CTRL 0 413 #define KVM_VCPU_TSC_OFFSET 0 414 #endif 415