1 /*
2 * Copyright (c) 2021 Arm Limited.
3 *
4 * SPDX-License-Identifier: MIT
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in all
14 * copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25 #if defined(__aarch64__)
26 #include <cstddef>
27 #include <cstdint>
28
29 namespace arm_conv {
30 namespace depthwise {
31
a64_fp32_nhwc_generic_output9_mla_depthfirst_impl(const float * const * const inptrs,float * const * const outptrs,const void * params,const void * bias,const unsigned int n_points,const unsigned int n_channels,const float activation_min,const float activation_max)32 void a64_fp32_nhwc_generic_output9_mla_depthfirst_impl(
33 const float *const *const inptrs,
34 float *const *const outptrs,
35 const void *params,
36 const void *bias,
37 const unsigned int n_points,
38 const unsigned int n_channels,
39 const float activation_min,
40 const float activation_max
41 )
42 {
43 const float minmax_vals[2] = { activation_min, activation_max };
44
45 __asm__ __volatile__(
46 "ld1r { v4.4s }, [%x[minmax_vals]]\n"
47 "add x19, %x[minmax_vals], #0x4\n"
48 "mov x11, #0x0\n"
49 "ld1r { v3.4s }, [x19]\n"
50 "lsr x10, %x[n_channels], #0x2\n"
51 "cbz x10, 5f\n"
52 "1:" // Channel loop
53 "movi v25.16b, #0x0\n"
54 "cbz %x[bias], 2f\n"
55 "ldr q25, [%x[bias], x11]\n"
56 "2:" // Channel loop: Load bias: Done
57 "mov v24.16b, v25.16b\n"
58 "ldr q23, [%x[params], #0x0]\n"
59 "mov x20, %x[inptrs]\n"
60 "mov v22.16b, v25.16b\n"
61 "ldp x9, x28, [x20], #0x10\n"
62 "subs x19, %x[n_points], #0x1\n"
63 "mov v21.16b, v25.16b\n"
64 "ldr q2, [x9, x11]\n"
65 "mov v20.16b, v25.16b\n"
66 "add %x[params], %x[params], #0x10\n"
67 "mov v19.16b, v25.16b\n"
68 "ldr q1, [x28, x11]\n"
69 "mov v18.16b, v25.16b\n"
70 "ldp x27, x26, [x20], #0x10\n"
71 "mov v17.16b, v25.16b\n"
72 "ldr q0, [x27, x11]\n"
73 "mov v16.16b, v25.16b\n"
74 "ldr q31, [x26, x11]\n"
75 "ldp x25, x24, [x20], #0x10\n"
76 "ldr q30, [x25, x11]\n"
77 "ldr q29, [x24, x11]\n"
78 "ldp x23, x22, [x20], #0x10\n"
79 "ldr q28, [x23, x11]\n"
80 "ldr q27, [x22, x11]\n"
81 "ldr x21, [x20], #0x8\n"
82 "ldr q26, [x21, x11]\n"
83 "ble 4f\n"
84 "3:" // Channel loop: Planar loop
85 "fmla v25.4s, v2.4s, v23.4s\n"
86 "ldp x9, x28, [x20], #0x10\n"
87 "subs x19, x19, #0x1\n"
88 "fmla v24.4s, v1.4s, v23.4s\n"
89 "ldr q2, [x9, x11]\n"
90 "fmla v22.4s, v0.4s, v23.4s\n"
91 "fmla v21.4s, v31.4s, v23.4s\n"
92 "ldr q1, [x28, x11]\n"
93 "fmla v20.4s, v30.4s, v23.4s\n"
94 "ldp x27, x26, [x20], #0x10\n"
95 "fmla v19.4s, v29.4s, v23.4s\n"
96 "fmla v18.4s, v28.4s, v23.4s\n"
97 "ldr q0, [x27, x11]\n"
98 "fmla v17.4s, v27.4s, v23.4s\n"
99 "fmla v16.4s, v26.4s, v23.4s\n"
100 "ldr q23, [%x[params], #0x0]\n"
101 "add %x[params], %x[params], #0x10\n"
102 "ldr q31, [x26, x11]\n"
103 "ldp x25, x24, [x20], #0x10\n"
104 "ldr q30, [x25, x11]\n"
105 "ldr q29, [x24, x11]\n"
106 "ldp x23, x22, [x20], #0x10\n"
107 "ldr q28, [x23, x11]\n"
108 "ldr q27, [x22, x11]\n"
109 "ldr x21, [x20], #0x8\n"
110 "ldr q26, [x21, x11]\n"
111 "bgt 3b\n"
112 "4:" // Channel loop: Planar tail
113 "fmla v25.4s, v2.4s, v23.4s\n"
114 "ldp x27, x26, [%x[outptrs], #0x0]\n"
115 "fmla v24.4s, v1.4s, v23.4s\n"
116 "ldp x25, x24, [%x[outptrs], #0x10]\n"
117 "fmla v22.4s, v0.4s, v23.4s\n"
118 "ldp x23, x22, [%x[outptrs], #0x20]\n"
119 "fmla v21.4s, v31.4s, v23.4s\n"
120 "ldp x21, x20, [%x[outptrs], #0x30]\n"
121 "fmla v20.4s, v30.4s, v23.4s\n"
122 "ldr x19, [%x[outptrs], #0x40]\n"
123 "fmla v19.4s, v29.4s, v23.4s\n"
124 "fmla v18.4s, v28.4s, v23.4s\n"
125 "fmla v17.4s, v27.4s, v23.4s\n"
126 "fmla v16.4s, v26.4s, v23.4s\n"
127 "fmax v25.4s, v25.4s, v4.4s\n"
128 "fmax v24.4s, v24.4s, v4.4s\n"
129 "fmax v22.4s, v22.4s, v4.4s\n"
130 "fmin v25.4s, v25.4s, v3.4s\n"
131 "str q25, [x27, x11]\n"
132 "fmin v24.4s, v24.4s, v3.4s\n"
133 "fmin v22.4s, v22.4s, v3.4s\n"
134 "str q24, [x26, x11]\n"
135 "fmax v21.4s, v21.4s, v4.4s\n"
136 "fmax v20.4s, v20.4s, v4.4s\n"
137 "str q22, [x25, x11]\n"
138 "fmax v19.4s, v19.4s, v4.4s\n"
139 "fmax v18.4s, v18.4s, v4.4s\n"
140 "fmin v21.4s, v21.4s, v3.4s\n"
141 "str q21, [x24, x11]\n"
142 "fmin v20.4s, v20.4s, v3.4s\n"
143 "fmin v19.4s, v19.4s, v3.4s\n"
144 "str q20, [x23, x11]\n"
145 "fmin v18.4s, v18.4s, v3.4s\n"
146 "fmax v17.4s, v17.4s, v4.4s\n"
147 "str q19, [x22, x11]\n"
148 "fmax v16.4s, v16.4s, v4.4s\n"
149 "str q18, [x21, x11]\n"
150 "fmin v17.4s, v17.4s, v3.4s\n"
151 "fmin v16.4s, v16.4s, v3.4s\n"
152 "str q17, [x20, x11]\n"
153 "str q16, [x19, x11]\n"
154 "add x11, x11, #0x10\n"
155 "cmp x11, x10, LSL #4\n"
156 "blt 1b\n"
157 "5:" // Oddments
158 "tst %x[n_channels], #0x3\n"
159 "beq 17f\n"
160 "movi v25.16b, #0x0\n"
161 "cbz %x[bias], 8f\n"
162 "add x19, %x[bias], x11\n"
163 "tbz %x[n_channels], #1, 6f\n"
164 "ld1 { v25.d }[0], [x19], #0x8\n"
165 "tbz %x[n_channels], #0, 7f\n"
166 "ld1 { v25.s }[2], [x19], #0x4\n"
167 "b 7f\n"
168 "6:" // Oddments: Load bias: Bit 1: Unset
169 "tbz %x[n_channels], #0, 7f\n"
170 "ld1 { v25.s }[0], [x19], #0x4\n"
171 "7:" // Oddments: Load bias: Bit 1: End
172
173 "8:" // Oddments: Load bias: Done
174 "mov v24.16b, v25.16b\n"
175 "ldr q23, [%x[params], #0x0]\n"
176 "mov x20, %x[inptrs]\n"
177 "mov v22.16b, v25.16b\n"
178 "ldp x9, x28, [x20], #0x10\n"
179 "add %x[params], %x[params], #0x10\n"
180 "mov v21.16b, v25.16b\n"
181 "ldp x27, x26, [x20], #0x10\n"
182 "mov v20.16b, v25.16b\n"
183 "add x9, x9, x11\n"
184 "mov v19.16b, v25.16b\n"
185 "ldp x25, x24, [x20], #0x10\n"
186 "mov v18.16b, v25.16b\n"
187 "add x28, x28, x11\n"
188 "mov v17.16b, v25.16b\n"
189 "ldp x23, x22, [x20], #0x10\n"
190 "mov v16.16b, v25.16b\n"
191 "add x27, x27, x11\n"
192 "ldr x21, [x20], #0x8\n"
193 "add x26, x26, x11\n"
194 "add x25, x25, x11\n"
195 "add x24, x24, x11\n"
196 "add x23, x23, x11\n"
197 "add x22, x22, x11\n"
198 "add x21, x21, x11\n"
199 "tbz %x[n_channels], #1, 9f\n"
200 "ldr d2, [x9], #0x8\n"
201 "ldr d1, [x28], #0x8\n"
202 "ldr d0, [x27], #0x8\n"
203 "ldr d31, [x26], #0x8\n"
204 "ldr d30, [x25], #0x8\n"
205 "ldr d29, [x24], #0x8\n"
206 "ldr d28, [x23], #0x8\n"
207 "ldr d27, [x22], #0x8\n"
208 "ldr d26, [x21], #0x8\n"
209 "tbz %x[n_channels], #0, 10f\n"
210 "ld1 { v2.s }[2], [x9], #0x4\n"
211 "ld1 { v1.s }[2], [x28], #0x4\n"
212 "ld1 { v0.s }[2], [x27], #0x4\n"
213 "ld1 { v31.s }[2], [x26], #0x4\n"
214 "ld1 { v30.s }[2], [x25], #0x4\n"
215 "ld1 { v29.s }[2], [x24], #0x4\n"
216 "ld1 { v28.s }[2], [x23], #0x4\n"
217 "ld1 { v27.s }[2], [x22], #0x4\n"
218 "ld1 { v26.s }[2], [x21], #0x4\n"
219 "b 10f\n"
220 "9:" // Oddments: Load: Bit 1: Unset
221 "tbz %x[n_channels], #0, 10f\n"
222 "ldr s2, [x9], #0x4\n"
223 "ldr s1, [x28], #0x4\n"
224 "ldr s0, [x27], #0x4\n"
225 "ldr s31, [x26], #0x4\n"
226 "ldr s30, [x25], #0x4\n"
227 "ldr s29, [x24], #0x4\n"
228 "ldr s28, [x23], #0x4\n"
229 "ldr s27, [x22], #0x4\n"
230 "ldr s26, [x21], #0x4\n"
231 "10:" // Oddments: Load: Bit 1: End
232 "subs x19, %x[n_points], #0x1\n"
233 "ble 14f\n"
234 "11:" // Oddments: Planar loop
235 "fmla v25.4s, v2.4s, v23.4s\n"
236 "ldp x9, x28, [x20], #0x10\n"
237 "add x9, x9, x11\n"
238 "fmla v24.4s, v1.4s, v23.4s\n"
239 "ldp x27, x26, [x20], #0x10\n"
240 "fmla v22.4s, v0.4s, v23.4s\n"
241 "ldp x25, x24, [x20], #0x10\n"
242 "fmla v21.4s, v31.4s, v23.4s\n"
243 "add x28, x28, x11\n"
244 "fmla v20.4s, v30.4s, v23.4s\n"
245 "ldp x23, x22, [x20], #0x10\n"
246 "fmla v19.4s, v29.4s, v23.4s\n"
247 "add x27, x27, x11\n"
248 "fmla v18.4s, v28.4s, v23.4s\n"
249 "ldr x21, [x20], #0x8\n"
250 "fmla v17.4s, v27.4s, v23.4s\n"
251 "add x26, x26, x11\n"
252 "fmla v16.4s, v26.4s, v23.4s\n"
253 "ldr q23, [%x[params], #0x0]\n"
254 "add x25, x25, x11\n"
255 "add x24, x24, x11\n"
256 "add x23, x23, x11\n"
257 "add x22, x22, x11\n"
258 "add x21, x21, x11\n"
259 "add %x[params], %x[params], #0x10\n"
260 "tbz %x[n_channels], #1, 12f\n"
261 "ldr d2, [x9], #0x8\n"
262 "ldr d1, [x28], #0x8\n"
263 "ldr d0, [x27], #0x8\n"
264 "ldr d31, [x26], #0x8\n"
265 "ldr d30, [x25], #0x8\n"
266 "ldr d29, [x24], #0x8\n"
267 "ldr d28, [x23], #0x8\n"
268 "ldr d27, [x22], #0x8\n"
269 "ldr d26, [x21], #0x8\n"
270 "tbz %x[n_channels], #0, 13f\n"
271 "ld1 { v2.s }[2], [x9], #0x4\n"
272 "ld1 { v1.s }[2], [x28], #0x4\n"
273 "ld1 { v0.s }[2], [x27], #0x4\n"
274 "ld1 { v31.s }[2], [x26], #0x4\n"
275 "ld1 { v30.s }[2], [x25], #0x4\n"
276 "ld1 { v29.s }[2], [x24], #0x4\n"
277 "ld1 { v28.s }[2], [x23], #0x4\n"
278 "ld1 { v27.s }[2], [x22], #0x4\n"
279 "ld1 { v26.s }[2], [x21], #0x4\n"
280 "b 13f\n"
281 "12:" // Oddments: Planar loop: Load: Bit 1: Unset
282 "tbz %x[n_channels], #0, 13f\n"
283 "ldr s2, [x9], #0x4\n"
284 "ldr s1, [x28], #0x4\n"
285 "ldr s0, [x27], #0x4\n"
286 "ldr s31, [x26], #0x4\n"
287 "ldr s30, [x25], #0x4\n"
288 "ldr s29, [x24], #0x4\n"
289 "ldr s28, [x23], #0x4\n"
290 "ldr s27, [x22], #0x4\n"
291 "ldr s26, [x21], #0x4\n"
292 "13:" // Oddments: Planar loop: Load: Bit 1: End
293 "subs x19, x19, #0x1\n"
294 "bgt 11b\n"
295 "14:" // Oddments: Planar tail
296 "fmla v25.4s, v2.4s, v23.4s\n"
297 "ldp x27, x26, [%x[outptrs], #0x0]\n"
298 "add x27, x27, x11\n"
299 "fmla v24.4s, v1.4s, v23.4s\n"
300 "ldp x25, x24, [%x[outptrs], #0x10]\n"
301 "fmla v22.4s, v0.4s, v23.4s\n"
302 "ldp x23, x22, [%x[outptrs], #0x20]\n"
303 "add x26, x26, x11\n"
304 "fmla v21.4s, v31.4s, v23.4s\n"
305 "ldp x21, x20, [%x[outptrs], #0x30]\n"
306 "fmla v20.4s, v30.4s, v23.4s\n"
307 "ldr x19, [%x[outptrs], #0x40]\n"
308 "add x25, x25, x11\n"
309 "fmla v19.4s, v29.4s, v23.4s\n"
310 "add x24, x24, x11\n"
311 "fmla v18.4s, v28.4s, v23.4s\n"
312 "add x23, x23, x11\n"
313 "fmla v17.4s, v27.4s, v23.4s\n"
314 "add x22, x22, x11\n"
315 "fmla v16.4s, v26.4s, v23.4s\n"
316 "add x21, x21, x11\n"
317 "fmax v25.4s, v25.4s, v4.4s\n"
318 "add x20, x20, x11\n"
319 "fmax v24.4s, v24.4s, v4.4s\n"
320 "add x19, x19, x11\n"
321 "fmax v22.4s, v22.4s, v4.4s\n"
322 "fmin v25.4s, v25.4s, v3.4s\n"
323 "fmin v24.4s, v24.4s, v3.4s\n"
324 "fmin v22.4s, v22.4s, v3.4s\n"
325 "fmax v21.4s, v21.4s, v4.4s\n"
326 "fmax v20.4s, v20.4s, v4.4s\n"
327 "fmax v19.4s, v19.4s, v4.4s\n"
328 "fmin v21.4s, v21.4s, v3.4s\n"
329 "fmin v20.4s, v20.4s, v3.4s\n"
330 "fmin v19.4s, v19.4s, v3.4s\n"
331 "fmax v18.4s, v18.4s, v4.4s\n"
332 "fmax v17.4s, v17.4s, v4.4s\n"
333 "fmax v16.4s, v16.4s, v4.4s\n"
334 "fmin v18.4s, v18.4s, v3.4s\n"
335 "fmin v17.4s, v17.4s, v3.4s\n"
336 "fmin v16.4s, v16.4s, v3.4s\n"
337 "tbz %x[n_channels], #1, 15f\n"
338 "st1 { v25.d }[0], [x27], #0x8\n"
339 "st1 { v24.d }[0], [x26], #0x8\n"
340 "st1 { v22.d }[0], [x25], #0x8\n"
341 "st1 { v21.d }[0], [x24], #0x8\n"
342 "st1 { v20.d }[0], [x23], #0x8\n"
343 "st1 { v19.d }[0], [x22], #0x8\n"
344 "st1 { v18.d }[0], [x21], #0x8\n"
345 "st1 { v17.d }[0], [x20], #0x8\n"
346 "st1 { v16.d }[0], [x19], #0x8\n"
347 "tbz %x[n_channels], #0, 16f\n"
348 "st1 { v25.s }[2], [x27], #0x4\n"
349 "st1 { v24.s }[2], [x26], #0x4\n"
350 "st1 { v22.s }[2], [x25], #0x4\n"
351 "st1 { v21.s }[2], [x24], #0x4\n"
352 "st1 { v20.s }[2], [x23], #0x4\n"
353 "st1 { v19.s }[2], [x22], #0x4\n"
354 "st1 { v18.s }[2], [x21], #0x4\n"
355 "st1 { v17.s }[2], [x20], #0x4\n"
356 "st1 { v16.s }[2], [x19], #0x4\n"
357 "b 16f\n"
358 "15:" // Oddments: Store: Bit 1: Unset
359 "tbz %x[n_channels], #0, 16f\n"
360 "st1 { v25.s }[0], [x27], #0x4\n"
361 "st1 { v24.s }[0], [x26], #0x4\n"
362 "st1 { v22.s }[0], [x25], #0x4\n"
363 "st1 { v21.s }[0], [x24], #0x4\n"
364 "st1 { v20.s }[0], [x23], #0x4\n"
365 "st1 { v19.s }[0], [x22], #0x4\n"
366 "st1 { v18.s }[0], [x21], #0x4\n"
367 "st1 { v17.s }[0], [x20], #0x4\n"
368 "st1 { v16.s }[0], [x19], #0x4\n"
369 "16:" // Oddments: Store: Bit 1: End
370
371 "17:" // End
372
373 : [params] "+&r" (params)
374 : [bias] "r" (bias), [inptrs] "r" (inptrs), [minmax_vals] "r" (minmax_vals), [n_channels] "r" ((uint64_t) n_channels), [n_points] "r" ((uint64_t) n_points), [outptrs] "r" (outptrs)
375 : "cc", "memory", "v0", "v1", "v2", "v3", "v4", "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", "x9", "x10", "x11", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28"
376 );
377 }
378
379 } // namespace depthwise
380 } // namespace arm_conv
381 #endif // defined(__aarch64__)
382